2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_gtt_reg_addr.h"
13 #include "ecore_chain.h"
14 #include "ecore_status.h"
16 #include "ecore_rt_defs.h"
17 #include "ecore_init_ops.h"
18 #include "ecore_int.h"
19 #include "ecore_cxt.h"
20 #include "ecore_spq.h"
21 #include "ecore_init_fw_funcs.h"
22 #include "ecore_sp_commands.h"
23 #include "ecore_dev_api.h"
24 #include "ecore_sriov.h"
26 #include "ecore_mcp.h"
27 #include "ecore_hw_defs.h"
28 #include "mcp_public.h"
29 #include "ecore_iro.h"
31 #include "ecore_dcbx.h"
34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
35 * registers involved are not split and thus configuration is a race where
36 * some of the PFs configuration might be lost.
37 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
38 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
39 * there's more than a single compiled ecore component in system].
41 static osal_spinlock_t qm_lock;
42 static bool qm_lock_init;
44 /******************** Doorbell Recovery *******************/
45 /* The doorbell recovery mechanism consists of a list of entries which represent
46 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
47 * entity needs to register with the mechanism and provide the parameters
48 * describing it's doorbell, including a location where last used doorbell data
49 * can be found. The doorbell execute function will traverse the list and
50 * doorbell all of the registered entries.
52 struct ecore_db_recovery_entry {
53 osal_list_entry_t list_entry;
54 void OSAL_IOMEM *db_addr;
56 enum ecore_db_rec_width db_width;
57 enum ecore_db_rec_space db_space;
61 /* display a single doorbell recovery entry */
62 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
63 struct ecore_db_recovery_entry *db_entry,
66 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
67 action, db_entry, db_entry->db_addr, db_entry->db_data,
68 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
69 db_entry->db_space == DB_REC_USER ? "user" : "kernel",
73 /* doorbell address sanity (address within doorbell bar range) */
74 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
77 /* make sure doorbell address is within the doorbell bar */
78 if (db_addr < p_dev->doorbells || (u8 *)db_addr >
79 (u8 *)p_dev->doorbells + p_dev->db_size) {
81 "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
82 db_addr, p_dev->doorbells,
83 (u8 *)p_dev->doorbells + p_dev->db_size);
87 /* make sure doorbell data pointer is not null */
89 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
96 /* find hwfn according to the doorbell address */
97 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
98 void OSAL_IOMEM *db_addr)
100 struct ecore_hwfn *p_hwfn;
102 /* In CMT doorbell bar is split down the middle between engine 0 and
105 if (ECORE_IS_CMT(p_dev))
106 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
107 &p_dev->hwfns[0] : &p_dev->hwfns[1];
109 p_hwfn = ECORE_LEADING_HWFN(p_dev);
114 /* add a new entry to the doorbell recovery mechanism */
115 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
116 void OSAL_IOMEM *db_addr,
118 enum ecore_db_rec_width db_width,
119 enum ecore_db_rec_space db_space)
121 struct ecore_db_recovery_entry *db_entry;
122 struct ecore_hwfn *p_hwfn;
124 /* shortcircuit VFs, for now */
126 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
127 return ECORE_SUCCESS;
130 /* sanitize doorbell address */
131 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
134 /* obtain hwfn from doorbell address */
135 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
138 db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
140 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
145 db_entry->db_addr = db_addr;
146 db_entry->db_data = db_data;
147 db_entry->db_width = db_width;
148 db_entry->db_space = db_space;
149 db_entry->hwfn_idx = p_hwfn->my_id;
152 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
154 /* protect the list */
155 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
156 OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
157 &p_hwfn->db_recovery_info.list);
158 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
160 return ECORE_SUCCESS;
163 /* remove an entry from the doorbell recovery mechanism */
164 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
165 void OSAL_IOMEM *db_addr,
168 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
169 enum _ecore_status_t rc = ECORE_INVAL;
170 struct ecore_hwfn *p_hwfn;
172 /* shortcircuit VFs, for now */
174 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
175 return ECORE_SUCCESS;
178 /* sanitize doorbell address */
179 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
182 /* obtain hwfn from doorbell address */
183 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
185 /* protect the list */
186 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
187 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
188 &p_hwfn->db_recovery_info.list,
190 struct ecore_db_recovery_entry) {
191 /* search according to db_data addr since db_addr is not unique
194 if (db_entry->db_data == db_data) {
195 ecore_db_recovery_dp_entry(p_hwfn, db_entry,
197 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
198 &p_hwfn->db_recovery_info.list);
204 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
206 if (rc == ECORE_INVAL)
208 DP_NOTICE(p_hwfn, false,
209 "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
212 OSAL_FREE(p_dev, db_entry);
217 /* initialize the doorbell recovery mechanism */
218 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
220 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
222 /* make sure db_size was set in p_dev */
223 if (!p_hwfn->p_dev->db_size) {
224 DP_ERR(p_hwfn->p_dev, "db_size not set\n");
228 OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
229 #ifdef CONFIG_ECORE_LOCK_ALLOC
230 OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock);
232 OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
233 p_hwfn->db_recovery_info.db_recovery_counter = 0;
235 return ECORE_SUCCESS;
238 /* destroy the doorbell recovery mechanism */
239 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
241 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
243 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
244 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
245 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
246 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
247 db_entry = OSAL_LIST_FIRST_ENTRY(
248 &p_hwfn->db_recovery_info.list,
249 struct ecore_db_recovery_entry,
251 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
252 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
253 &p_hwfn->db_recovery_info.list);
254 OSAL_FREE(p_hwfn->p_dev, db_entry);
257 #ifdef CONFIG_ECORE_LOCK_ALLOC
258 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
260 p_hwfn->db_recovery_info.db_recovery_counter = 0;
263 /* print the content of the doorbell recovery mechanism */
264 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
266 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
268 DP_NOTICE(p_hwfn, false,
269 "Dispalying doorbell recovery database. Counter was %d\n",
270 p_hwfn->db_recovery_info.db_recovery_counter);
272 /* protect the list */
273 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
274 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
275 &p_hwfn->db_recovery_info.list,
277 struct ecore_db_recovery_entry) {
278 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
281 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
284 /* ring the doorbell of a single doorbell recovery entry */
285 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
286 struct ecore_db_recovery_entry *db_entry,
287 enum ecore_db_rec_exec db_exec)
289 /* Print according to width */
290 if (db_entry->db_width == DB_REC_WIDTH_32B)
291 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
292 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
293 db_entry->db_addr, *(u32 *)db_entry->db_data);
295 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n",
296 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
298 *(unsigned long *)(db_entry->db_data));
301 if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
305 /* Flush the write combined buffer. Since there are multiple doorbelling
306 * entities using the same address, if we don't flush, a transaction
309 OSAL_WMB(p_hwfn->p_dev);
311 /* Ring the doorbell */
312 if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
313 if (db_entry->db_width == DB_REC_WIDTH_32B)
314 DIRECT_REG_WR(p_hwfn, db_entry->db_addr,
315 *(u32 *)(db_entry->db_data));
317 DIRECT_REG_WR64(p_hwfn, db_entry->db_addr,
318 *(u64 *)(db_entry->db_data));
321 /* Flush the write combined buffer. Next doorbell may come from a
322 * different entity to the same address...
324 OSAL_WMB(p_hwfn->p_dev);
327 /* traverse the doorbell recovery entry list and ring all the doorbells */
328 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
329 enum ecore_db_rec_exec db_exec)
331 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
333 if (db_exec != DB_REC_ONCE) {
334 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
335 p_hwfn->db_recovery_info.db_recovery_counter);
337 /* track amount of times recovery was executed */
338 p_hwfn->db_recovery_info.db_recovery_counter++;
341 /* protect the list */
342 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
343 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
344 &p_hwfn->db_recovery_info.list,
346 struct ecore_db_recovery_entry) {
347 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
348 if (db_exec == DB_REC_ONCE)
352 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
354 /******************** Doorbell Recovery end ****************/
357 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to
358 * load the driver. The number was
363 #define ECORE_MIN_PWM_REGION (ECORE_WID_SIZE * ECORE_MIN_DPIS)
365 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
366 struct ecore_ptt *p_ptt,
369 u32 bar_reg = (bar_id == BAR_ID_0 ?
370 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
373 if (IS_VF(p_hwfn->p_dev))
374 return ecore_vf_hw_bar_size(p_hwfn, bar_id);
376 val = ecore_rd(p_hwfn, p_ptt, bar_reg);
378 return 1 << (val + 15);
380 /* The above registers were updated in the past only in CMT mode. Since
381 * they were found to be useful MFW started updating them from 8.7.7.0.
382 * In older MFW versions they are set to 0 which means disabled.
384 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
386 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
387 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
390 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
397 void ecore_init_dp(struct ecore_dev *p_dev,
398 u32 dp_module, u8 dp_level, void *dp_ctx)
402 p_dev->dp_level = dp_level;
403 p_dev->dp_module = dp_module;
404 p_dev->dp_ctx = dp_ctx;
405 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
406 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
408 p_hwfn->dp_level = dp_level;
409 p_hwfn->dp_module = dp_module;
410 p_hwfn->dp_ctx = dp_ctx;
414 void ecore_init_struct(struct ecore_dev *p_dev)
418 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
419 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
421 p_hwfn->p_dev = p_dev;
423 p_hwfn->b_active = false;
425 #ifdef CONFIG_ECORE_LOCK_ALLOC
426 OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->dmae_info.lock);
428 OSAL_SPIN_LOCK_INIT(&p_hwfn->dmae_info.lock);
431 /* hwfn 0 is always active */
432 p_dev->hwfns[0].b_active = true;
434 /* set the default cache alignment to 128 (may be overridden later) */
435 p_dev->cache_shift = 7;
438 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
440 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
442 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
443 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
444 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
445 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
448 void ecore_resc_free(struct ecore_dev *p_dev)
453 for_each_hwfn(p_dev, i)
454 ecore_l2_free(&p_dev->hwfns[i]);
458 OSAL_FREE(p_dev, p_dev->fw_data);
460 OSAL_FREE(p_dev, p_dev->reset_stats);
462 for_each_hwfn(p_dev, i) {
463 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
465 ecore_cxt_mngr_free(p_hwfn);
466 ecore_qm_info_free(p_hwfn);
467 ecore_spq_free(p_hwfn);
468 ecore_eq_free(p_hwfn);
469 ecore_consq_free(p_hwfn);
470 ecore_int_free(p_hwfn);
471 ecore_iov_free(p_hwfn);
472 ecore_l2_free(p_hwfn);
473 ecore_dmae_info_free(p_hwfn);
474 ecore_dcbx_info_free(p_hwfn);
475 /* @@@TBD Flush work-queue ? */
477 /* destroy doorbell recovery mechanism */
478 ecore_db_recovery_teardown(p_hwfn);
482 /******************** QM initialization *******************/
484 /* bitmaps for indicating active traffic classes.
485 * Special case for Arrowhead 4 port
487 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
488 #define ACTIVE_TCS_BMAP 0x9f
489 /* 0..3 actually used, OOO and high priority stuff all use 3 */
490 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
492 /* determines the physical queue flags for a given PF. */
493 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
501 if (IS_ECORE_SRIOV(p_hwfn->p_dev))
502 flags |= PQ_FLAGS_VFS;
505 switch (p_hwfn->hw_info.personality) {
507 flags |= PQ_FLAGS_MCOS;
510 flags |= PQ_FLAGS_OFLD;
512 case ECORE_PCI_ISCSI:
513 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
515 case ECORE_PCI_ETH_ROCE:
516 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
518 case ECORE_PCI_ETH_IWARP:
519 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
523 DP_ERR(p_hwfn, "unknown personality %d\n",
524 p_hwfn->hw_info.personality);
530 /* Getters for resource amounts necessary for qm initialization */
531 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
533 return p_hwfn->hw_info.num_hw_tc;
536 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
538 return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
539 p_hwfn->p_dev->p_iov_info->total_vfs : 0;
542 #define NUM_DEFAULT_RLS 1
544 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
546 u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
549 /* num RLs can't exceed resource amount of rls or vports or the
552 num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
553 (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
555 /* make sure after we reserve the default and VF rls we'll have
558 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
559 DP_NOTICE(p_hwfn, false,
560 "no rate limiters left for PF rate limiting"
561 " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
565 /* subtract rls necessary for VFs and one default one for the PF */
566 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
571 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
573 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
575 /* all pqs share the same vport (hence the 1 below), except for vfs
578 return (!!(PQ_FLAGS_RLS & pq_flags)) *
579 ecore_init_qm_get_num_pf_rls(p_hwfn) +
580 (!!(PQ_FLAGS_VFS & pq_flags)) *
581 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
584 /* calc amount of PQs according to the requested flags */
585 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
587 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
589 return (!!(PQ_FLAGS_RLS & pq_flags)) *
590 ecore_init_qm_get_num_pf_rls(p_hwfn) +
591 (!!(PQ_FLAGS_MCOS & pq_flags)) *
592 ecore_init_qm_get_num_tcs(p_hwfn) +
593 (!!(PQ_FLAGS_LB & pq_flags)) +
594 (!!(PQ_FLAGS_OOO & pq_flags)) +
595 (!!(PQ_FLAGS_ACK & pq_flags)) +
596 (!!(PQ_FLAGS_OFLD & pq_flags)) +
597 (!!(PQ_FLAGS_VFS & pq_flags)) *
598 ecore_init_qm_get_num_vfs(p_hwfn);
601 /* initialize the top level QM params */
602 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
604 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
607 /* pq and vport bases for this PF */
608 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
609 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
611 /* rate limiting and weighted fair queueing are always enabled */
612 qm_info->vport_rl_en = 1;
613 qm_info->vport_wfq_en = 1;
615 /* TC config is different for AH 4 port */
616 four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;
618 /* in AH 4 port we have fewer TCs per port */
619 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
622 /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
625 if (!qm_info->ooo_tc)
626 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
630 /* initialize qm vport params */
631 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
633 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
636 /* all vports participate in weighted fair queueing */
637 for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
638 qm_info->qm_vport_params[i].vport_wfq = 1;
641 /* initialize qm port params */
642 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
644 /* Initialize qm port parameters */
645 u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
647 /* indicate how ooo and high pri traffic is dealt with */
648 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
649 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
651 for (i = 0; i < num_ports; i++) {
652 struct init_qm_port_params *p_qm_port =
653 &p_hwfn->qm_info.qm_port_params[i];
655 p_qm_port->active = 1;
656 p_qm_port->active_phys_tcs = active_phys_tcs;
657 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES_E4 / num_ports;
658 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
662 /* Reset the params which must be reset for qm init. QM init may be called as
663 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
664 * params may be affected by the init but would simply recalculate to the same
665 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
666 * affected as these amounts stay the same.
668 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
670 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
672 qm_info->num_pqs = 0;
673 qm_info->num_vports = 0;
674 qm_info->num_pf_rls = 0;
675 qm_info->num_vf_pqs = 0;
676 qm_info->first_vf_pq = 0;
677 qm_info->first_mcos_pq = 0;
678 qm_info->first_rl_pq = 0;
681 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
683 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
685 qm_info->num_vports++;
687 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
689 "vport overflow! qm_info->num_vports %d,"
690 " qm_init_get_num_vports() %d\n",
692 ecore_init_qm_get_num_vports(p_hwfn));
695 /* initialize a single pq and manage qm_info resources accounting.
696 * The pq_init_flags param determines whether the PQ is rate limited
698 * and whether a new vport is allocated to the pq or not (i.e. vport will be
702 /* flags for pq init */
703 #define PQ_INIT_SHARE_VPORT (1 << 0)
704 #define PQ_INIT_PF_RL (1 << 1)
705 #define PQ_INIT_VF_RL (1 << 2)
707 /* defines for pq init */
708 #define PQ_INIT_DEFAULT_WRR_GROUP 1
709 #define PQ_INIT_DEFAULT_TC 0
710 #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc)
712 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
713 struct ecore_qm_info *qm_info,
714 u8 tc, u32 pq_init_flags)
716 u16 pq_idx = qm_info->num_pqs, max_pq =
717 ecore_init_qm_get_num_pqs(p_hwfn);
721 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
724 qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
725 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
727 qm_info->qm_pq_params[pq_idx].tc_id = tc;
728 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
729 qm_info->qm_pq_params[pq_idx].rl_valid =
730 (pq_init_flags & PQ_INIT_PF_RL ||
731 pq_init_flags & PQ_INIT_VF_RL);
733 /* qm params accounting */
735 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
736 qm_info->num_vports++;
738 if (pq_init_flags & PQ_INIT_PF_RL)
739 qm_info->num_pf_rls++;
741 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
743 "vport overflow! qm_info->num_vports %d,"
744 " qm_init_get_num_vports() %d\n",
746 ecore_init_qm_get_num_vports(p_hwfn));
748 if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
749 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
750 " qm_init_get_num_pf_rls() %d\n",
752 ecore_init_qm_get_num_pf_rls(p_hwfn));
755 /* get pq index according to PQ_FLAGS */
756 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
759 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
761 /* Can't have multiple flags set here */
762 if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
763 sizeof(pq_flags)) > 1)
768 return &qm_info->first_rl_pq;
770 return &qm_info->first_mcos_pq;
772 return &qm_info->pure_lb_pq;
774 return &qm_info->ooo_pq;
776 return &qm_info->pure_ack_pq;
778 return &qm_info->offload_pq;
780 return &qm_info->first_vf_pq;
786 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
790 /* save pq index in qm info */
791 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
792 u32 pq_flags, u16 pq_val)
794 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
796 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
799 /* get tx pq index, with the PQ TX base already set (ready for context init) */
800 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
802 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
804 return *base_pq_idx + CM_TX_PQ_BASE;
807 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
809 u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
812 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
814 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
817 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
819 u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
822 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
824 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
827 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
829 u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
832 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
834 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
837 /* Functions for creating specific types of pqs */
838 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
840 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
842 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
845 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
846 ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
849 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
851 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
853 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
856 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
857 ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
860 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
862 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
864 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
867 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
868 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
871 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
873 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
875 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
878 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
879 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
882 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
884 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
887 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
890 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
891 for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
892 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
895 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
897 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
898 u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
900 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
903 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
905 qm_info->num_vf_pqs = num_vfs;
906 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
907 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
911 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
913 u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
914 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
916 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
919 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
920 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
921 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
925 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
927 /* rate limited pqs, must come first (FW assumption) */
928 ecore_init_qm_rl_pqs(p_hwfn);
930 /* pqs for multi cos */
931 ecore_init_qm_mcos_pqs(p_hwfn);
933 /* pure loopback pq */
934 ecore_init_qm_lb_pq(p_hwfn);
936 /* out of order pq */
937 ecore_init_qm_ooo_pq(p_hwfn);
940 ecore_init_qm_pure_ack_pq(p_hwfn);
942 /* pq for offloaded protocol */
943 ecore_init_qm_offload_pq(p_hwfn);
945 /* done sharing vports */
946 ecore_init_qm_advance_vport(p_hwfn);
949 ecore_init_qm_vf_pqs(p_hwfn);
952 /* compare values of getters against resources amounts */
953 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
955 if (ecore_init_qm_get_num_vports(p_hwfn) >
956 RESC_NUM(p_hwfn, ECORE_VPORT)) {
957 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
961 if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
962 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
966 return ECORE_SUCCESS;
970 * Function for verbose printing of the qm initialization results
972 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
974 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
975 struct init_qm_vport_params *vport;
976 struct init_qm_port_params *port;
977 struct init_qm_pq_params *pq;
980 /* top level params */
981 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
982 "qm init top level params: start_pq %d, start_vport %d,"
983 " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
984 qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
985 qm_info->offload_pq, qm_info->pure_ack_pq);
986 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
987 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
988 " num_vports %d, max_phys_tcs_per_port %d\n",
989 qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
990 qm_info->num_vf_pqs, qm_info->num_vports,
991 qm_info->max_phys_tcs_per_port);
992 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
993 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
994 " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
995 qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
996 qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
997 qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
1000 for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
1001 port = &qm_info->qm_port_params[i];
1002 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1003 "port idx %d, active %d, active_phys_tcs %d,"
1004 " num_pbf_cmd_lines %d, num_btb_blocks %d,"
1006 i, port->active, port->active_phys_tcs,
1007 port->num_pbf_cmd_lines, port->num_btb_blocks,
1012 for (i = 0; i < qm_info->num_vports; i++) {
1013 vport = &qm_info->qm_vport_params[i];
1014 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1015 "vport idx %d, vport_rl %d, wfq %d,"
1016 " first_tx_pq_id [ ",
1017 qm_info->start_vport + i, vport->vport_rl,
1019 for (tc = 0; tc < NUM_OF_TCS; tc++)
1020 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
1021 vport->first_tx_pq_id[tc]);
1022 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
1026 for (i = 0; i < qm_info->num_pqs; i++) {
1027 pq = &qm_info->qm_pq_params[i];
1028 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1029 "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
1030 qm_info->start_pq + i, pq->port_id, pq->vport_id,
1031 pq->tc_id, pq->wrr_group, pq->rl_valid);
1035 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
1037 /* reset params required for init run */
1038 ecore_init_qm_reset_params(p_hwfn);
1040 /* init QM top level params */
1041 ecore_init_qm_params(p_hwfn);
1043 /* init QM port params */
1044 ecore_init_qm_port_params(p_hwfn);
1046 /* init QM vport params */
1047 ecore_init_qm_vport_params(p_hwfn);
1049 /* init QM physical queue params */
1050 ecore_init_qm_pq_params(p_hwfn);
1052 /* display all that init */
1053 ecore_dp_init_qm_params(p_hwfn);
1056 /* This function reconfigures the QM pf on the fly.
1057 * For this purpose we:
1058 * 1. reconfigure the QM database
1059 * 2. set new values to runtime array
1060 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
1061 * 4. activate init tool in QM_PF stage
1062 * 5. send an sdm_qm_cmd through rbc interface to release the QM
1064 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
1065 struct ecore_ptt *p_ptt)
1067 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1069 enum _ecore_status_t rc;
1071 /* initialize ecore's qm data structure */
1072 ecore_init_qm_info(p_hwfn);
1074 /* stop PF's qm queues */
1075 OSAL_SPIN_LOCK(&qm_lock);
1076 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
1077 qm_info->start_pq, qm_info->num_pqs);
1078 OSAL_SPIN_UNLOCK(&qm_lock);
1082 /* clear the QM_PF runtime phase leftovers from previous init */
1083 ecore_init_clear_rt_data(p_hwfn);
1085 /* prepare QM portion of runtime array */
1086 ecore_qm_init_pf(p_hwfn, p_ptt, false);
1088 /* activate init tool on runtime array */
1089 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
1090 p_hwfn->hw_info.hw_mode);
1091 if (rc != ECORE_SUCCESS)
1094 /* start PF's qm queues */
1095 OSAL_SPIN_LOCK(&qm_lock);
1096 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
1097 qm_info->start_pq, qm_info->num_pqs);
1098 OSAL_SPIN_UNLOCK(&qm_lock);
1102 return ECORE_SUCCESS;
1105 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
1107 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1108 enum _ecore_status_t rc;
1110 rc = ecore_init_qm_sanity(p_hwfn);
1111 if (rc != ECORE_SUCCESS)
1114 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1115 sizeof(struct init_qm_pq_params) *
1116 ecore_init_qm_get_num_pqs(p_hwfn));
1117 if (!qm_info->qm_pq_params)
1120 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1121 sizeof(struct init_qm_vport_params) *
1122 ecore_init_qm_get_num_vports(p_hwfn));
1123 if (!qm_info->qm_vport_params)
1126 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1127 sizeof(struct init_qm_port_params) *
1128 p_hwfn->p_dev->num_ports_in_engine);
1129 if (!qm_info->qm_port_params)
1132 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1133 sizeof(struct ecore_wfq_data) *
1134 ecore_init_qm_get_num_vports(p_hwfn));
1135 if (!qm_info->wfq_data)
1138 return ECORE_SUCCESS;
1141 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
1142 ecore_qm_info_free(p_hwfn);
1145 /******************** End QM initialization ***************/
1147 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
1149 enum _ecore_status_t rc = ECORE_SUCCESS;
1153 for_each_hwfn(p_dev, i) {
1154 rc = ecore_l2_alloc(&p_dev->hwfns[i]);
1155 if (rc != ECORE_SUCCESS)
1161 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1162 sizeof(*p_dev->fw_data));
1163 if (!p_dev->fw_data)
1166 for_each_hwfn(p_dev, i) {
1167 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1168 u32 n_eqes, num_cons;
1170 /* initialize the doorbell recovery mechanism */
1171 rc = ecore_db_recovery_setup(p_hwfn);
1175 /* First allocate the context manager structure */
1176 rc = ecore_cxt_mngr_alloc(p_hwfn);
1180 /* Set the HW cid/tid numbers (in the context manager)
1181 * Must be done prior to any further computations.
1183 rc = ecore_cxt_set_pf_params(p_hwfn);
1187 rc = ecore_alloc_qm_data(p_hwfn);
1192 ecore_init_qm_info(p_hwfn);
1194 /* Compute the ILT client partition */
1195 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
1199 /* CID map / ILT shadow table / T2
1200 * The talbes sizes are determined by the computations above
1202 rc = ecore_cxt_tables_alloc(p_hwfn);
1206 /* SPQ, must follow ILT because initializes SPQ context */
1207 rc = ecore_spq_alloc(p_hwfn);
1211 /* SP status block allocation */
1212 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
1215 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1219 rc = ecore_iov_alloc(p_hwfn);
1224 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
1225 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
1226 /* Calculate the EQ size
1227 * ---------------------
1228 * Each ICID may generate up to one event at a time i.e.
1229 * the event must be handled/cleared before a new one
1230 * can be generated. We calculate the sum of events per
1231 * protocol and create an EQ deep enough to handle the
1233 * - Core - according to SPQ.
1234 * - RoCE - per QP there are a couple of ICIDs, one
1235 * responder and one requester, each can
1236 * generate an EQE => n_eqes_qp = 2 * n_qp.
1237 * Each CQ can generate an EQE. There are 2 CQs
1238 * per QP => n_eqes_cq = 2 * n_qp.
1239 * Hence the RoCE total is 4 * n_qp or
1241 * - ENet - There can be up to two events per VF. One
1242 * for VF-PF channel and another for VF FLR
1243 * initial cleanup. The number of VFs is
1244 * bounded by MAX_NUM_VFS_BB, and is much
1245 * smaller than RoCE's so we avoid exact
1248 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
1250 ecore_cxt_get_proto_cid_count(
1256 num_cons = ecore_cxt_get_proto_cid_count(
1261 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1262 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
1264 ecore_cxt_get_proto_cid_count(p_hwfn,
1267 n_eqes += 2 * num_cons;
1270 if (n_eqes > 0xFFFF) {
1271 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
1272 "The maximum of a u16 chain is 0x%x\n",
1277 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
1281 rc = ecore_consq_alloc(p_hwfn);
1285 rc = ecore_l2_alloc(p_hwfn);
1286 if (rc != ECORE_SUCCESS)
1289 /* DMA info initialization */
1290 rc = ecore_dmae_info_alloc(p_hwfn);
1292 DP_NOTICE(p_hwfn, true,
1293 "Failed to allocate memory for dmae_info"
1298 /* DCBX initialization */
1299 rc = ecore_dcbx_info_alloc(p_hwfn);
1301 DP_NOTICE(p_hwfn, true,
1302 "Failed to allocate memory for dcbx structure\n");
1307 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1308 sizeof(*p_dev->reset_stats));
1309 if (!p_dev->reset_stats) {
1310 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
1314 return ECORE_SUCCESS;
1319 ecore_resc_free(p_dev);
1323 void ecore_resc_setup(struct ecore_dev *p_dev)
1328 for_each_hwfn(p_dev, i)
1329 ecore_l2_setup(&p_dev->hwfns[i]);
1333 for_each_hwfn(p_dev, i) {
1334 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1336 ecore_cxt_mngr_setup(p_hwfn);
1337 ecore_spq_setup(p_hwfn);
1338 ecore_eq_setup(p_hwfn);
1339 ecore_consq_setup(p_hwfn);
1341 /* Read shadow of current MFW mailbox */
1342 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1343 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1344 p_hwfn->mcp_info->mfw_mb_cur,
1345 p_hwfn->mcp_info->mfw_mb_length);
1347 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1349 ecore_l2_setup(p_hwfn);
1350 ecore_iov_setup(p_hwfn);
1354 #define FINAL_CLEANUP_POLL_CNT (100)
1355 #define FINAL_CLEANUP_POLL_TIME (10)
1356 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1357 struct ecore_ptt *p_ptt,
1360 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1361 enum _ecore_status_t rc = ECORE_TIMEOUT;
1364 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1365 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1366 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1367 return ECORE_SUCCESS;
1371 addr = GTT_BAR0_MAP_REG_USDM_RAM +
1372 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1377 command |= X_FINAL_CLEANUP_AGG_INT <<
1378 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1379 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1380 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1381 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1383 /* Make sure notification is not set before initiating final cleanup */
1385 if (REG_RD(p_hwfn, addr)) {
1386 DP_NOTICE(p_hwfn, false,
1387 "Unexpected; Found final cleanup notification");
1388 DP_NOTICE(p_hwfn, false,
1389 " before initiating final cleanup\n");
1390 REG_WR(p_hwfn, addr, 0);
1393 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1394 "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1397 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1399 /* Poll until completion */
1400 while (!REG_RD(p_hwfn, addr) && count--)
1401 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1403 if (REG_RD(p_hwfn, addr))
1406 DP_NOTICE(p_hwfn, true,
1407 "Failed to receive FW final cleanup notification\n");
1409 /* Cleanup afterwards */
1410 REG_WR(p_hwfn, addr, 0);
1415 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1419 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1420 hw_mode |= 1 << MODE_BB;
1421 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1422 hw_mode |= 1 << MODE_K2;
1424 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1425 p_hwfn->p_dev->type);
1429 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1430 switch (p_hwfn->p_dev->num_ports_in_engine) {
1432 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1435 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1438 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1441 DP_NOTICE(p_hwfn, true,
1442 "num_ports_in_engine = %d not supported\n",
1443 p_hwfn->p_dev->num_ports_in_engine);
1447 if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS,
1448 &p_hwfn->p_dev->mf_bits))
1449 hw_mode |= 1 << MODE_MF_SD;
1451 hw_mode |= 1 << MODE_MF_SI;
1454 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1455 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1456 hw_mode |= 1 << MODE_FPGA;
1458 if (p_hwfn->p_dev->b_is_emul_full)
1459 hw_mode |= 1 << MODE_EMUL_FULL;
1461 hw_mode |= 1 << MODE_EMUL_REDUCED;
1465 hw_mode |= 1 << MODE_ASIC;
1467 if (ECORE_IS_CMT(p_hwfn->p_dev))
1468 hw_mode |= 1 << MODE_100G;
1470 p_hwfn->hw_info.hw_mode = hw_mode;
1472 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1473 "Configuring function for hw_mode: 0x%08x\n",
1474 p_hwfn->hw_info.hw_mode);
1476 return ECORE_SUCCESS;
1480 /* MFW-replacement initializations for non-ASIC */
1481 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1482 struct ecore_ptt *p_ptt)
1484 struct ecore_dev *p_dev = p_hwfn->p_dev;
1488 if (CHIP_REV_IS_EMUL(p_dev)) {
1489 if (ECORE_IS_AH(p_dev))
1493 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1495 if (CHIP_REV_IS_EMUL(p_dev) &&
1496 (ECORE_IS_AH(p_dev)))
1497 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1500 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1501 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1502 if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1503 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1505 if (CHIP_REV_IS_EMUL(p_dev)) {
1506 if (ECORE_IS_AH(p_dev)) {
1507 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1508 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1509 (p_dev->num_ports_in_engine >> 1));
1511 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1512 p_dev->num_ports_in_engine == 4 ? 0 : 3);
1517 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1518 for (i = 0; i < 100; i++) {
1520 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1524 DP_NOTICE(p_hwfn, true,
1525 "RBC done failed to complete in PSWRQ2\n");
1527 return ECORE_SUCCESS;
1531 /* Init run time data for all PFs and their VFs on an engine.
1532 * TBD - for VFs - Once we have parent PF info for each VF in
1533 * shmem available as CAU requires knowledge of parent PF for each VF.
1535 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1537 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1540 for_each_hwfn(p_dev, i) {
1541 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1542 struct ecore_igu_info *p_igu_info;
1543 struct ecore_igu_block *p_block;
1544 struct cau_sb_entry sb_entry;
1546 p_igu_info = p_hwfn->hw_info.p_igu_info;
1549 igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1551 p_block = &p_igu_info->entry[igu_sb_id];
1553 if (!p_block->is_pf)
1556 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1557 p_block->function_id, 0, 0);
1558 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1564 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
1565 struct ecore_ptt *p_ptt)
1567 u32 val, wr_mbs, cache_line_size;
1569 val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1582 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1587 cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
1588 switch (cache_line_size) {
1603 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1607 if (wr_mbs < OSAL_CACHE_LINE_SIZE)
1609 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1610 OSAL_CACHE_LINE_SIZE, wr_mbs);
1612 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1614 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1615 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1619 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1620 struct ecore_ptt *p_ptt,
1623 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1624 struct ecore_dev *p_dev = p_hwfn->p_dev;
1625 u8 vf_id, max_num_vfs;
1628 enum _ecore_status_t rc = ECORE_SUCCESS;
1630 ecore_init_cau_rt_data(p_dev);
1632 /* Program GTT windows */
1633 ecore_gtt_init(p_hwfn, p_ptt);
1636 if (CHIP_REV_IS_EMUL(p_dev)) {
1637 rc = ecore_hw_init_chip(p_hwfn, p_ptt);
1638 if (rc != ECORE_SUCCESS)
1643 if (p_hwfn->mcp_info) {
1644 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1645 qm_info->pf_rl_en = 1;
1646 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1647 qm_info->pf_wfq_en = 1;
1650 ecore_qm_common_rt_init(p_hwfn,
1651 p_dev->num_ports_in_engine,
1652 qm_info->max_phys_tcs_per_port,
1653 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1654 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1655 qm_info->qm_port_params);
1657 ecore_cxt_hw_init_common(p_hwfn);
1659 ecore_init_cache_line_size(p_hwfn, p_ptt);
1661 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ECORE_PATH_ID(p_hwfn),
1663 if (rc != ECORE_SUCCESS)
1666 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1667 * need to decide with which value, maybe runtime
1669 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1670 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1672 if (ECORE_IS_BB(p_dev)) {
1673 /* Workaround clears ROCE search for all functions to prevent
1674 * involving non initialized function in processing ROCE packet.
1676 num_pfs = NUM_OF_ENG_PFS(p_dev);
1677 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1678 ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1679 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1680 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1682 /* pretend to original PF */
1683 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1686 /* Workaround for avoiding CCFC execution error when getting packets
1687 * with CRC errors, and allowing instead the invoking of the FW error
1689 * This is not done inside the init tool since it currently can't
1690 * perform a pretending to VFs.
1692 max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1693 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1694 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1695 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1696 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1697 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1698 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1699 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1701 /* pretend to original PF */
1702 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1708 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1709 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1711 #define PMEG_IF_BYTE_COUNT 8
1713 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1714 struct ecore_ptt *p_ptt,
1715 u32 addr, u64 data, u8 reg_type, u8 port)
1717 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1718 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1719 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1720 (8 << PMEG_IF_BYTE_COUNT),
1721 (reg_type << 25) | (addr << 8) | port,
1722 (u32)((data >> 32) & 0xffffffff),
1723 (u32)(data & 0xffffffff));
1725 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1726 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1727 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1728 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1729 (reg_type << 25) | (addr << 8) | port);
1730 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1731 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1732 (data >> 32) & 0xffffffff);
1735 #define XLPORT_MODE_REG (0x20a)
1736 #define XLPORT_MAC_CONTROL (0x210)
1737 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1738 #define XLPORT_ENABLE_REG (0x20b)
1740 #define XLMAC_CTRL (0x600)
1741 #define XLMAC_MODE (0x601)
1742 #define XLMAC_RX_MAX_SIZE (0x608)
1743 #define XLMAC_TX_CTRL (0x604)
1744 #define XLMAC_PAUSE_CTRL (0x60d)
1745 #define XLMAC_PFC_CTRL (0x60e)
1747 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1748 struct ecore_ptt *p_ptt)
1750 u8 loopback = 0, port = p_hwfn->port_id * 2;
1752 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1754 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1755 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1757 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1758 /* XLMAC: SOFT RESET */
1759 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1760 /* XLMAC: Port Speed >= 10Gbps */
1761 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1762 /* XLMAC: Max Size */
1763 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1764 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1765 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1767 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1768 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1769 0x30ffffc000ULL, 0, port);
1770 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1771 port); /* XLMAC: TX_EN, RX_EN */
1772 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1773 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1774 0x1003 | (loopback << 2), 0, port);
1775 /* Enabled Parallel PFC interface */
1776 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1778 /* XLPORT port enable */
1779 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1782 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1783 struct ecore_ptt *p_ptt)
1785 u8 port = p_hwfn->port_id;
1786 u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1788 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1790 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1791 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1793 CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1794 (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1796 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1797 1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1799 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1800 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1802 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1803 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1805 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1806 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1808 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1810 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1812 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1814 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1818 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1819 struct ecore_ptt *p_ptt)
1821 if (ECORE_IS_AH(p_hwfn->p_dev))
1822 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1824 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1827 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1828 struct ecore_ptt *p_ptt, u8 port)
1830 int port_offset = port ? 0x800 : 0;
1831 u32 xmac_rxctrl = 0;
1834 /* FIXME: move to common start */
1835 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1836 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
1838 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1839 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
1841 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1843 /* Set the number of ports on the Warp Core to 10G */
1844 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1846 /* Soft reset of XMAC */
1847 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1848 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1850 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1851 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1853 /* FIXME: move to common end */
1854 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1855 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1857 /* Set Max packet size: initialize XMAC block register for port 0 */
1858 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1860 /* CRC append for Tx packets: init XMAC block register for port 1 */
1861 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1863 /* Enable TX and RX: initialize XMAC block register for port 1 */
1864 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1865 XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1866 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1867 XMAC_REG_RX_CTRL_BB + port_offset);
1868 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1869 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1873 static enum _ecore_status_t
1874 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1875 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1877 u32 dpi_bit_shift, dpi_count, dpi_page_size;
1881 /* Calculate DPI size
1882 * ------------------
1883 * The PWM region contains Doorbell Pages. The first is reserverd for
1884 * the kernel for, e.g, L2. The others are free to be used by non-
1885 * trusted applications, typically from user space. Each page, called a
1886 * doorbell page is sectioned into windows that allow doorbells to be
1887 * issued in parallel by the kernel/application. The size of such a
1888 * window (a.k.a. WID) is 1kB.
1890 * 1kB WID x N WIDS = DPI page size
1891 * DPI page size x N DPIs = PWM region size
1893 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1894 * in order to ensure that two applications won't share the same page.
1895 * It also must contain at least one WID per CPU to allow parallelism.
1896 * It also must be a power of 2, since it is stored as a bit shift.
1898 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1899 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1900 * containing 4 WIDs.
1902 n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus);
1903 dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids);
1904 dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) &
1905 ~(OSAL_PAGE_SIZE - 1);
1906 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1907 dpi_count = pwm_region_size / dpi_page_size;
1909 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1910 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1913 p_hwfn->dpi_size = dpi_page_size;
1914 p_hwfn->dpi_count = dpi_count;
1916 /* Update registers */
1917 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1919 if (dpi_count < min_dpis)
1920 return ECORE_NORESOURCES;
1922 return ECORE_SUCCESS;
1925 enum ECORE_ROCE_EDPM_MODE {
1926 ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1927 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1928 ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1931 static enum _ecore_status_t
1932 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1933 struct ecore_ptt *p_ptt)
1935 u32 pwm_regsize, norm_regsize;
1936 u32 non_pwm_conn, min_addr_reg1;
1937 u32 db_bar_size, n_cpus;
1940 enum _ecore_status_t rc = ECORE_SUCCESS;
1943 db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1944 if (ECORE_IS_CMT(p_hwfn->p_dev))
1947 /* Calculate doorbell regions
1948 * -----------------------------------
1949 * The doorbell BAR is made of two regions. The first is called normal
1950 * region and the second is called PWM region. In the normal region
1951 * each ICID has its own set of addresses so that writing to that
1952 * specific address identifies the ICID. In the Process Window Mode
1953 * region the ICID is given in the data written to the doorbell. The
1954 * above per PF register denotes the offset in the doorbell BAR in which
1955 * the PWM region begins.
1956 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1957 * non-PWM connection. The calculation below computes the total non-PWM
1958 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1959 * in units of 4,096 bytes.
1961 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1962 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1964 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1965 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn,
1967 min_addr_reg1 = norm_regsize / 4096;
1968 pwm_regsize = db_bar_size - norm_regsize;
1970 /* Check that the normal and PWM sizes are valid */
1971 if (db_bar_size < norm_regsize) {
1972 DP_ERR(p_hwfn->p_dev,
1973 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1974 db_bar_size, norm_regsize);
1975 return ECORE_NORESOURCES;
1977 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1978 DP_ERR(p_hwfn->p_dev,
1979 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1980 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1982 return ECORE_NORESOURCES;
1985 /* Calculate number of DPIs */
1986 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1987 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1988 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1989 /* Either EDPM is mandatory, or we are attempting to allocate a
1992 n_cpus = OSAL_NUM_CPUS();
1993 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1996 cond = ((rc != ECORE_SUCCESS) &&
1997 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1998 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1999 if (cond || p_hwfn->dcbx_no_edpm) {
2000 /* Either EDPM is disabled from user configuration, or it is
2001 * disabled via DCBx, or it is not mandatory and we failed to
2002 * allocated a WID per CPU.
2005 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2007 /* If we entered this flow due to DCBX then the DPM register is
2008 * already configured.
2013 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
2014 norm_regsize, pwm_regsize);
2016 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
2017 p_hwfn->dpi_size, p_hwfn->dpi_count,
2018 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
2019 "disabled" : "enabled");
2021 /* Check return codes from above calls */
2022 if (rc != ECORE_SUCCESS) {
2024 "Failed to allocate enough DPIs\n");
2025 return ECORE_NORESOURCES;
2029 p_hwfn->dpi_start_offset = norm_regsize;
2031 /* Update registers */
2032 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2033 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
2034 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2035 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2037 return ECORE_SUCCESS;
2040 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
2041 struct ecore_ptt *p_ptt,
2044 u32 ppf_to_eng_sel[NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE];
2046 enum _ecore_status_t rc = ECORE_SUCCESS;
2049 /* In CMT for non-RoCE packets - use connection based classification */
2050 val = ECORE_IS_CMT(p_hwfn->p_dev) ? 0x8 : 0x0;
2051 for (i = 0; i < NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE; i++)
2052 ppf_to_eng_sel[i] = val;
2053 STORE_RT_REG_AGG(p_hwfn, NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET,
2056 /* In CMT the gate should be cleared by the 2nd hwfn */
2057 if (!ECORE_IS_CMT(p_hwfn->p_dev) || !IS_LEAD_HWFN(p_hwfn))
2058 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
2060 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
2062 if (rc != ECORE_SUCCESS)
2065 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2068 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2069 return ECORE_SUCCESS;
2071 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2072 if (ECORE_IS_AH(p_hwfn->p_dev))
2073 return ECORE_SUCCESS;
2074 else if (ECORE_IS_BB(p_hwfn->p_dev))
2075 ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
2076 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2077 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
2078 /* Activate OPTE in CMT */
2081 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
2083 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
2084 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
2085 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
2086 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
2087 ecore_wr(p_hwfn, p_ptt,
2088 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
2089 ecore_wr(p_hwfn, p_ptt,
2090 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
2091 ecore_wr(p_hwfn, p_ptt,
2092 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
2096 ecore_emul_link_init(p_hwfn, p_ptt);
2098 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
2105 static enum _ecore_status_t
2106 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
2107 struct ecore_ptt *p_ptt,
2108 struct ecore_tunnel_info *p_tunn,
2111 enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
2113 u8 rel_pf_id = p_hwfn->rel_pf_id;
2115 enum _ecore_status_t rc = ECORE_SUCCESS;
2119 if (p_hwfn->mcp_info) {
2120 struct ecore_mcp_function_info *p_info;
2122 p_info = &p_hwfn->mcp_info->func_info;
2123 if (p_info->bandwidth_min)
2124 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2126 /* Update rate limit once we'll actually have a link */
2127 p_hwfn->qm_info.pf_rl = 100000;
2129 ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
2131 ecore_int_igu_init_rt(p_hwfn);
2133 /* Set VLAN in NIG if needed */
2134 if (hw_mode & (1 << MODE_MF_SD)) {
2135 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2136 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2137 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2138 p_hwfn->hw_info.ovlan);
2140 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2141 "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
2142 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
2146 /* Enable classification by MAC if needed */
2147 if (hw_mode & (1 << MODE_MF_SI)) {
2148 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2149 "Configuring TAGMAC_CLS_TYPE\n");
2150 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
2154 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
2155 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2156 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
2157 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2158 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
2159 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2161 /* perform debug configuration when chip is out of reset */
2162 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
2164 /* Sanity check before the PF init sequence that uses DMAE */
2165 rc = ecore_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
2169 /* PF Init sequence */
2170 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2174 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2175 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2179 /* Pure runtime initializations - directly to the HW */
2180 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2182 /* PCI relaxed ordering causes a decrease in the performance on some
2183 * systems. Till a root cause is found, disable this attribute in the
2187 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
2189 * DP_NOTICE(p_hwfn, true,
2190 * "Failed to find the PCIe Cap\n");
2193 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
2194 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
2195 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
2198 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2202 /* enable interrupts */
2203 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
2204 if (rc != ECORE_SUCCESS)
2207 /* send function start command */
2208 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2209 allow_npar_tx_switch);
2211 DP_NOTICE(p_hwfn, true,
2212 "Function start ramrod failed\n");
2214 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2215 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2216 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2218 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
2219 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
2221 ecore_wr(p_hwfn, p_ptt,
2222 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2225 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2226 "PRS_REG_SEARCH registers after start PFn\n");
2227 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
2228 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2229 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
2230 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
2231 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2232 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
2233 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
2234 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2235 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
2236 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
2237 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2238 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
2239 prs_reg = ecore_rd(p_hwfn, p_ptt,
2240 PRS_REG_SEARCH_TCP_FIRST_FRAG);
2241 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2242 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
2244 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2245 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2246 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2252 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
2253 struct ecore_ptt *p_ptt,
2256 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2258 /* Configure the PF's internal FID_enable for master transactions */
2259 ecore_wr(p_hwfn, p_ptt,
2260 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2262 /* Wait until value is set - try for 1 second every 50us */
2263 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2264 val = ecore_rd(p_hwfn, p_ptt,
2265 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2272 if (val != set_val) {
2273 DP_NOTICE(p_hwfn, true,
2274 "PFID_ENABLE_MASTER wasn't changed after a second\n");
2275 return ECORE_UNKNOWN_ERROR;
2278 return ECORE_SUCCESS;
2281 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
2282 struct ecore_ptt *p_main_ptt)
2284 /* Read shadow of current MFW mailbox */
2285 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
2286 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
2287 p_hwfn->mcp_info->mfw_mb_cur,
2288 p_hwfn->mcp_info->mfw_mb_length);
2291 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
2292 struct ecore_ptt *p_ptt)
2294 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
2295 1 << p_hwfn->abs_pf_id);
2299 ecore_fill_load_req_params(struct ecore_load_req_params *p_load_req,
2300 struct ecore_drv_load_params *p_drv_load)
2302 /* Make sure that if ecore-client didn't provide inputs, all the
2303 * expected defaults are indeed zero.
2305 OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
2306 OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
2307 OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
2309 OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
2311 if (p_drv_load != OSAL_NULL) {
2312 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2313 ECORE_DRV_ROLE_KDUMP :
2315 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2316 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2317 p_load_req->override_force_load =
2318 p_drv_load->override_force_load;
2322 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
2323 struct ecore_hw_init_params *p_params)
2325 if (p_params->p_tunn) {
2326 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2327 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2330 p_hwfn->b_int_enabled = 1;
2332 return ECORE_SUCCESS;
2335 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
2336 struct ecore_hw_init_params *p_params)
2338 struct ecore_load_req_params load_req_params;
2339 u32 load_code, resp, param, drv_mb_param;
2340 bool b_default_mtu = true;
2341 struct ecore_hwfn *p_hwfn;
2342 enum _ecore_status_t rc = ECORE_SUCCESS;
2345 if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) {
2346 DP_NOTICE(p_dev, false,
2347 "MSI mode is not supported for CMT devices\n");
2352 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
2353 if (rc != ECORE_SUCCESS)
2357 for_each_hwfn(p_dev, i) {
2358 p_hwfn = &p_dev->hwfns[i];
2360 /* If management didn't provide a default, set one of our own */
2361 if (!p_hwfn->hw_info.mtu) {
2362 p_hwfn->hw_info.mtu = 1500;
2363 b_default_mtu = false;
2367 ecore_vf_start(p_hwfn, p_params);
2371 rc = ecore_calc_hw_mode(p_hwfn);
2372 if (rc != ECORE_SUCCESS)
2375 ecore_fill_load_req_params(&load_req_params,
2376 p_params->p_drv_load_params);
2377 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
2379 if (rc != ECORE_SUCCESS) {
2380 DP_NOTICE(p_hwfn, true,
2381 "Failed sending a LOAD_REQ command\n");
2385 load_code = load_req_params.load_code;
2386 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2387 "Load request was sent. Load code: 0x%x\n",
2390 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
2393 * When coming back from hiberbate state, the registers from
2394 * which shadow is read initially are not initialized. It turns
2395 * out that these registers get initialized during the call to
2396 * ecore_mcp_load_req request. So we need to reread them here
2397 * to get the proper shadow register value.
2398 * Note: This is a workaround for the missing MFW
2399 * initialization. It may be removed once the implementation
2402 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2404 /* Only relevant for recovery:
2405 * Clear the indication after the LOAD_REQ command is responded
2408 p_dev->recov_in_prog = false;
2410 p_hwfn->first_on_engine = (load_code ==
2411 FW_MSG_CODE_DRV_LOAD_ENGINE);
2413 if (!qm_lock_init) {
2414 OSAL_SPIN_LOCK_INIT(&qm_lock);
2415 qm_lock_init = true;
2418 /* Clean up chip from previous driver if such remains exist.
2419 * This is not needed when the PF is the first one on the
2420 * engine, since afterwards we are going to init the FW.
2422 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2423 rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2424 p_hwfn->rel_pf_id, false);
2425 if (rc != ECORE_SUCCESS) {
2426 ecore_hw_err_notify(p_hwfn,
2427 ECORE_HW_ERR_RAMROD_FAIL);
2432 /* Log and clean previous pglue_b errors if such exist */
2433 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
2434 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2436 /* Enable the PF's internal FID_enable in the PXP */
2437 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2439 if (rc != ECORE_SUCCESS)
2442 switch (load_code) {
2443 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2444 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2445 p_hwfn->hw_info.hw_mode);
2446 if (rc != ECORE_SUCCESS)
2449 case FW_MSG_CODE_DRV_LOAD_PORT:
2450 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2451 p_hwfn->hw_info.hw_mode);
2452 if (rc != ECORE_SUCCESS)
2455 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2456 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2458 p_hwfn->hw_info.hw_mode,
2459 p_params->b_hw_start,
2461 p_params->allow_npar_tx_switch);
2464 DP_NOTICE(p_hwfn, false,
2465 "Unexpected load code [0x%08x]", load_code);
2470 if (rc != ECORE_SUCCESS) {
2471 DP_NOTICE(p_hwfn, true,
2472 "init phase failed for loadcode 0x%x (rc %d)\n",
2477 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2478 if (rc != ECORE_SUCCESS)
2481 /* send DCBX attention request command */
2482 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2483 "sending phony dcbx set command to trigger DCBx attention handling\n");
2484 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2485 DRV_MSG_CODE_SET_DCBX,
2486 1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
2488 if (rc != ECORE_SUCCESS) {
2489 DP_NOTICE(p_hwfn, true,
2490 "Failed to send DCBX attention request\n");
2494 p_hwfn->hw_init_done = true;
2498 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2499 drv_mb_param = STORM_FW_VERSION;
2500 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2501 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2502 drv_mb_param, &resp, ¶m);
2503 if (rc != ECORE_SUCCESS)
2504 DP_INFO(p_hwfn, "Failed to update firmware version\n");
2507 rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2508 p_hwfn->hw_info.mtu);
2509 if (rc != ECORE_SUCCESS)
2510 DP_INFO(p_hwfn, "Failed to update default mtu\n");
2512 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2514 ECORE_OV_DRIVER_STATE_DISABLED);
2515 if (rc != ECORE_SUCCESS)
2516 DP_INFO(p_hwfn, "Failed to update driver state\n");
2522 /* The MFW load lock should be released regardless of success or failure
2523 * of initialization.
2524 * TODO: replace this with an attempt to send cancel_load.
2526 ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2530 #define ECORE_HW_STOP_RETRY_LIMIT (10)
2531 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2532 struct ecore_hwfn *p_hwfn,
2533 struct ecore_ptt *p_ptt)
2538 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2539 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2540 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2542 if ((!ecore_rd(p_hwfn, p_ptt,
2543 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2544 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2547 /* Dependent on number of connection/tasks, possibly
2548 * 1ms sleep is required between polls
2553 if (i < ECORE_HW_STOP_RETRY_LIMIT)
2556 DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2557 " [Connection %02x Tasks %02x]\n",
2558 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2559 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2562 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2566 for_each_hwfn(p_dev, j) {
2567 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2568 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2570 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2574 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
2575 struct ecore_ptt *p_ptt,
2576 u32 addr, u32 expected_val)
2578 u32 val = ecore_rd(p_hwfn, p_ptt, addr);
2580 if (val != expected_val) {
2581 DP_NOTICE(p_hwfn, true,
2582 "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
2583 addr, val, expected_val);
2584 return ECORE_UNKNOWN_ERROR;
2587 return ECORE_SUCCESS;
2590 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2592 struct ecore_hwfn *p_hwfn;
2593 struct ecore_ptt *p_ptt;
2594 enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
2597 for_each_hwfn(p_dev, j) {
2598 p_hwfn = &p_dev->hwfns[j];
2599 p_ptt = p_hwfn->p_main_ptt;
2601 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2604 ecore_vf_pf_int_cleanup(p_hwfn);
2605 rc = ecore_vf_pf_reset(p_hwfn);
2606 if (rc != ECORE_SUCCESS) {
2607 DP_NOTICE(p_hwfn, true,
2608 "ecore_vf_pf_reset failed. rc = %d.\n",
2610 rc2 = ECORE_UNKNOWN_ERROR;
2615 /* mark the hw as uninitialized... */
2616 p_hwfn->hw_init_done = false;
2618 /* Send unload command to MCP */
2619 if (!p_dev->recov_in_prog) {
2620 rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
2621 if (rc != ECORE_SUCCESS) {
2622 DP_NOTICE(p_hwfn, true,
2623 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2625 rc2 = ECORE_UNKNOWN_ERROR;
2629 OSAL_DPC_SYNC(p_hwfn);
2631 /* After this point no MFW attentions are expected, e.g. prevent
2632 * race between pf stop and dcbx pf update.
2635 rc = ecore_sp_pf_stop(p_hwfn);
2636 if (rc != ECORE_SUCCESS) {
2637 DP_NOTICE(p_hwfn, true,
2638 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2640 rc2 = ECORE_UNKNOWN_ERROR;
2643 /* perform debug action after PF stop was sent */
2644 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
2646 /* close NIG to BRB gate */
2647 ecore_wr(p_hwfn, p_ptt,
2648 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2651 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2652 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2653 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2654 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2655 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2657 /* @@@TBD - clean transmission queues (5.b) */
2658 /* @@@TBD - clean BTB (5.c) */
2660 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2662 /* @@@TBD - verify DMAE requests are done (8) */
2664 /* Disable Attention Generation */
2665 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2666 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2667 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2668 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2669 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
2670 if (rc != ECORE_SUCCESS) {
2671 DP_NOTICE(p_hwfn, true,
2672 "Failed to return IGU CAM to default\n");
2673 rc2 = ECORE_UNKNOWN_ERROR;
2676 /* Need to wait 1ms to guarantee SBs are cleared */
2679 if (!p_dev->recov_in_prog) {
2680 ecore_verify_reg_val(p_hwfn, p_ptt,
2681 QM_REG_USG_CNT_PF_TX, 0);
2682 ecore_verify_reg_val(p_hwfn, p_ptt,
2683 QM_REG_USG_CNT_PF_OTHER, 0);
2684 /* @@@TBD - assert on incorrect xCFC values (10.b) */
2687 /* Disable PF in HW blocks */
2688 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2689 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2691 if (!p_dev->recov_in_prog) {
2692 ecore_mcp_unload_done(p_hwfn, p_ptt);
2693 if (rc != ECORE_SUCCESS) {
2694 DP_NOTICE(p_hwfn, true,
2695 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2697 rc2 = ECORE_UNKNOWN_ERROR;
2702 if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
2703 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2704 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2706 /* Clear the PF's internal FID_enable in the PXP.
2707 * In CMT this should only be done for first hw-function, and
2708 * only after all transactions have stopped for all active
2711 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2713 if (rc != ECORE_SUCCESS) {
2714 DP_NOTICE(p_hwfn, true,
2715 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2717 rc2 = ECORE_UNKNOWN_ERROR;
2724 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2728 for_each_hwfn(p_dev, j) {
2729 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2730 struct ecore_ptt *p_ptt;
2733 ecore_vf_pf_int_cleanup(p_hwfn);
2736 p_ptt = ecore_ptt_acquire(p_hwfn);
2740 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2741 "Shutting down the fastpath\n");
2743 ecore_wr(p_hwfn, p_ptt,
2744 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2746 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2747 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2748 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2749 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2750 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2752 /* @@@TBD - clean transmission queues (5.b) */
2753 /* @@@TBD - clean BTB (5.c) */
2755 /* @@@TBD - verify DMAE requests are done (8) */
2757 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2758 /* Need to wait 1ms to guarantee SBs are cleared */
2760 ecore_ptt_release(p_hwfn, p_ptt);
2763 return ECORE_SUCCESS;
2766 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2768 struct ecore_ptt *p_ptt;
2770 if (IS_VF(p_hwfn->p_dev))
2771 return ECORE_SUCCESS;
2773 p_ptt = ecore_ptt_acquire(p_hwfn);
2777 /* If roce info is allocated it means roce is initialized and should
2778 * be enabled in searcher.
2780 if (p_hwfn->p_rdma_info) {
2781 if (p_hwfn->b_rdma_enabled_in_prs)
2782 ecore_wr(p_hwfn, p_ptt,
2783 p_hwfn->rdma_prs_search_reg, 0x1);
2784 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2787 /* Re-open incoming traffic */
2788 ecore_wr(p_hwfn, p_ptt,
2789 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2790 ecore_ptt_release(p_hwfn, p_ptt);
2792 return ECORE_SUCCESS;
2795 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2796 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2798 ecore_ptt_pool_free(p_hwfn);
2799 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2802 /* Setup bar access */
2803 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2805 /* clear indirect access */
2806 if (ECORE_IS_AH(p_hwfn->p_dev)) {
2807 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2808 PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2809 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2810 PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2811 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2812 PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2813 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2814 PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2816 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2817 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2818 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2819 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2820 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2821 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2822 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2823 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2826 /* Clean previous pglue_b errors if such exist */
2827 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2829 /* enable internal target-read */
2830 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2831 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2834 static void get_function_id(struct ecore_hwfn *p_hwfn)
2837 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2838 PXP_PF_ME_OPAQUE_ADDR);
2840 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2842 /* Bits 16-19 from the ME registers are the pf_num */
2843 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2844 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2845 PXP_CONCRETE_FID_PFID);
2846 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2847 PXP_CONCRETE_FID_PORT);
2849 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2850 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2851 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2854 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2856 u32 *feat_num = p_hwfn->hw_info.feat_num;
2857 struct ecore_sb_cnt_info sb_cnt;
2860 OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
2861 ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
2863 /* L2 Queues require each: 1 status block. 1 L2 queue */
2864 if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
2865 /* Start by allocating VF queues, then PF's */
2866 feat_num[ECORE_VF_L2_QUE] =
2868 RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
2870 feat_num[ECORE_PF_L2_QUE] =
2872 sb_cnt.cnt - non_l2_sbs,
2873 RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2874 FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
2877 if (ECORE_IS_FCOE_PERSONALITY(p_hwfn))
2878 feat_num[ECORE_FCOE_CQ] =
2879 OSAL_MIN_T(u32, sb_cnt.cnt, RESC_NUM(p_hwfn,
2882 if (ECORE_IS_ISCSI_PERSONALITY(p_hwfn))
2883 feat_num[ECORE_ISCSI_CQ] =
2884 OSAL_MIN_T(u32, sb_cnt.cnt, RESC_NUM(p_hwfn,
2887 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2888 "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2889 (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2890 (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2891 (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2892 (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2893 (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2897 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2900 case ECORE_L2_QUEUE:
2914 case ECORE_RDMA_CNQ_RAM:
2915 return "RDMA_CNQ_RAM";
2918 case ECORE_LL2_QUEUE:
2920 case ECORE_CMDQS_CQS:
2922 case ECORE_RDMA_STATS_QUEUE:
2923 return "RDMA_STATS_QUEUE";
2929 return "UNKNOWN_RESOURCE";
2933 static enum _ecore_status_t
2934 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2935 struct ecore_ptt *p_ptt,
2936 enum ecore_resources res_id,
2940 enum _ecore_status_t rc;
2942 rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2943 resc_max_val, p_mcp_resp);
2944 if (rc != ECORE_SUCCESS) {
2945 DP_NOTICE(p_hwfn, true,
2946 "MFW response failure for a max value setting of resource %d [%s]\n",
2947 res_id, ecore_hw_get_resc_name(res_id));
2951 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2953 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2954 res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
2956 return ECORE_SUCCESS;
2959 static enum _ecore_status_t
2960 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2961 struct ecore_ptt *p_ptt)
2963 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2964 u32 resc_max_val, mcp_resp;
2966 enum _ecore_status_t rc;
2968 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2971 case ECORE_LL2_QUEUE:
2972 case ECORE_RDMA_CNQ_RAM:
2973 case ECORE_RDMA_STATS_QUEUE:
2981 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2982 resc_max_val, &mcp_resp);
2983 if (rc != ECORE_SUCCESS)
2986 /* There's no point to continue to the next resource if the
2987 * command is not supported by the MFW.
2988 * We do continue if the command is supported but the resource
2989 * is unknown to the MFW. Such a resource will be later
2990 * configured with the default allocation values.
2992 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2993 return ECORE_NOTIMPL;
2996 return ECORE_SUCCESS;
3000 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
3001 enum ecore_resources res_id,
3002 u32 *p_resc_num, u32 *p_resc_start)
3004 u8 num_funcs = p_hwfn->num_funcs_on_engine;
3005 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3008 case ECORE_L2_QUEUE:
3009 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
3010 MAX_NUM_L2_QUEUES_BB) / num_funcs;
3013 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3014 MAX_NUM_VPORTS_BB) / num_funcs;
3017 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
3018 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
3021 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
3022 MAX_QM_TX_QUEUES_BB) / num_funcs;
3025 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
3029 /* Each VFC resource can accommodate both a MAC and a VLAN */
3030 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3033 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
3034 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
3036 case ECORE_LL2_QUEUE:
3037 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
3039 case ECORE_RDMA_CNQ_RAM:
3040 case ECORE_CMDQS_CQS:
3041 /* CNQ/CMDQS are the same resource */
3043 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
3045 case ECORE_RDMA_STATS_QUEUE:
3047 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3048 MAX_NUM_VPORTS_BB) / num_funcs;
3065 /* Since we want its value to reflect whether MFW supports
3066 * the new scheme, have a default of 0.
3071 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3075 return ECORE_SUCCESS;
3078 static enum _ecore_status_t
3079 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
3080 bool drv_resc_alloc)
3082 u32 dflt_resc_num = 0, dflt_resc_start = 0;
3083 u32 mcp_resp, *p_resc_num, *p_resc_start;
3084 enum _ecore_status_t rc;
3086 p_resc_num = &RESC_NUM(p_hwfn, res_id);
3087 p_resc_start = &RESC_START(p_hwfn, res_id);
3089 rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3091 if (rc != ECORE_SUCCESS) {
3093 "Failed to get default amount for resource %d [%s]\n",
3094 res_id, ecore_hw_get_resc_name(res_id));
3099 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3100 *p_resc_num = dflt_resc_num;
3101 *p_resc_start = dflt_resc_start;
3106 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3107 &mcp_resp, p_resc_num, p_resc_start);
3108 if (rc != ECORE_SUCCESS) {
3109 DP_NOTICE(p_hwfn, true,
3110 "MFW response failure for an allocation request for"
3111 " resource %d [%s]\n",
3112 res_id, ecore_hw_get_resc_name(res_id));
3116 /* Default driver values are applied in the following cases:
3117 * - The resource allocation MB command is not supported by the MFW
3118 * - There is an internal error in the MFW while processing the request
3119 * - The resource ID is unknown to the MFW
3121 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3123 "Failed to receive allocation info for resource %d [%s]."
3124 " mcp_resp = 0x%x. Applying default values"
3126 res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
3127 dflt_resc_num, dflt_resc_start);
3129 *p_resc_num = dflt_resc_num;
3130 *p_resc_start = dflt_resc_start;
3134 if ((*p_resc_num != dflt_resc_num ||
3135 *p_resc_start != dflt_resc_start) &&
3136 res_id != ECORE_SB) {
3138 "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
3139 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
3140 *p_resc_start, dflt_resc_num, dflt_resc_start,
3141 drv_resc_alloc ? " - Applying default values" : "");
3142 if (drv_resc_alloc) {
3143 *p_resc_num = dflt_resc_num;
3144 *p_resc_start = dflt_resc_start;
3148 return ECORE_SUCCESS;
3151 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
3152 bool drv_resc_alloc)
3154 enum _ecore_status_t rc;
3157 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3158 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
3159 if (rc != ECORE_SUCCESS)
3163 return ECORE_SUCCESS;
3166 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
3167 struct ecore_ptt *p_ptt,
3168 bool drv_resc_alloc)
3170 struct ecore_resc_unlock_params resc_unlock_params;
3171 struct ecore_resc_lock_params resc_lock_params;
3172 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3174 enum _ecore_status_t rc;
3176 u32 *resc_start = p_hwfn->hw_info.resc_start;
3177 u32 *resc_num = p_hwfn->hw_info.resc_num;
3178 /* For AH, an equal share of the ILT lines between the maximal number of
3179 * PFs is not enough for RoCE. This would be solved by the future
3180 * resource allocation scheme, but isn't currently present for
3181 * FPGA/emulation. For now we keep a number that is sufficient for RoCE
3182 * to work - the BB number of ILT lines divided by its max PFs number.
3184 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
3187 /* Setting the max values of the soft resources and the following
3188 * resources allocation queries should be atomic. Since several PFs can
3189 * run in parallel - a resource lock is needed.
3190 * If either the resource lock or resource set value commands are not
3191 * supported - skip the max values setting, release the lock if
3192 * needed, and proceed to the queries. Other failures, including a
3193 * failure to acquire the lock, will cause this function to fail.
3194 * Old drivers that don't acquire the lock can run in parallel, and
3195 * their allocation values won't be affected by the updated max values.
3197 ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3198 ECORE_RESC_LOCK_RESC_ALLOC, false);
3200 rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3201 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3203 } else if (rc == ECORE_NOTIMPL) {
3205 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3206 } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
3207 DP_NOTICE(p_hwfn, false,
3208 "Failed to acquire the resource lock for the resource allocation commands\n");
3210 goto unlock_and_exit;
3212 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
3213 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3214 DP_NOTICE(p_hwfn, false,
3215 "Failed to set the max values of the soft resources\n");
3216 goto unlock_and_exit;
3217 } else if (rc == ECORE_NOTIMPL) {
3219 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3220 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3221 &resc_unlock_params);
3222 if (rc != ECORE_SUCCESS)
3224 "Failed to release the resource lock for the resource allocation commands\n");
3228 rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
3229 if (rc != ECORE_SUCCESS)
3230 goto unlock_and_exit;
3232 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3233 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3234 &resc_unlock_params);
3235 if (rc != ECORE_SUCCESS)
3237 "Failed to release the resource lock for the resource allocation commands\n");
3241 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3242 /* Reduced build contains less PQs */
3243 if (!(p_hwfn->p_dev->b_is_emul_full)) {
3244 resc_num[ECORE_PQ] = 32;
3245 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
3246 p_hwfn->enabled_func_idx;
3249 /* For AH emulation, since we have a possible maximal number of
3250 * 16 enabled PFs, in case there are not enough ILT lines -
3251 * allocate only first PF as RoCE and have all the other ETH
3252 * only with less ILT lines.
3254 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
3255 resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
3256 resc_num[ECORE_ILT],
3257 roce_min_ilt_lines);
3260 /* Correct the common ILT calculation if PF0 has more */
3261 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
3262 p_hwfn->p_dev->b_is_emul_full &&
3263 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
3264 resc_start[ECORE_ILT] += roce_min_ilt_lines -
3265 resc_num[ECORE_ILT];
3268 /* Sanity for ILT */
3269 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3270 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3271 DP_NOTICE(p_hwfn, true,
3272 "Can't assign ILT pages [%08x,...,%08x]\n",
3273 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
3279 /* This will also learn the number of SBs from MFW */
3280 if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
3283 ecore_hw_set_feat(p_hwfn);
3285 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3286 "The numbers for each resource are:\n");
3287 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
3288 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
3289 ecore_hw_get_resc_name(res_id),
3290 RESC_NUM(p_hwfn, res_id),
3291 RESC_START(p_hwfn, res_id));
3293 return ECORE_SUCCESS;
3296 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3297 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3298 &resc_unlock_params);
3302 static enum _ecore_status_t
3303 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
3304 struct ecore_ptt *p_ptt,
3305 struct ecore_hw_prepare_params *p_params)
3307 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
3308 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
3309 struct ecore_mcp_link_capabilities *p_caps;
3310 struct ecore_mcp_link_params *link;
3311 enum _ecore_status_t rc;
3313 /* Read global nvm_cfg address */
3314 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
3316 /* Verify MCP has initialized it */
3317 if (!nvm_cfg_addr) {
3318 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
3319 if (p_params->b_relaxed_probe)
3320 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
3324 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
3326 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
3328 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3329 OFFSETOF(struct nvm_cfg1, glob) +
3330 OFFSETOF(struct nvm_cfg1_glob, core_cfg);
3332 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
3334 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
3335 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
3336 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
3337 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
3339 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
3340 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
3342 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
3343 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
3345 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
3346 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
3348 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
3349 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
3351 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
3352 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
3354 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
3355 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
3357 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
3358 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
3360 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
3361 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
3363 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
3364 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
3366 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3367 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
3370 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
3375 /* Read DCBX configuration */
3376 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3377 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3378 dcbx_mode = ecore_rd(p_hwfn, p_ptt,
3380 OFFSETOF(struct nvm_cfg1_port, generic_cont0));
3381 dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
3382 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
3383 switch (dcbx_mode) {
3384 case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
3385 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
3387 case NVM_CFG1_PORT_DCBX_MODE_CEE:
3388 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
3390 case NVM_CFG1_PORT_DCBX_MODE_IEEE:
3391 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
3394 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
3397 /* Read default link configuration */
3398 link = &p_hwfn->mcp_info->link_input;
3399 p_caps = &p_hwfn->mcp_info->link_capabilities;
3400 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3401 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3402 link_temp = ecore_rd(p_hwfn, p_ptt,
3404 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
3405 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
3406 link->speed.advertised_speeds = link_temp;
3407 p_caps->speed_capabilities = link->speed.advertised_speeds;
3409 link_temp = ecore_rd(p_hwfn, p_ptt,
3411 OFFSETOF(struct nvm_cfg1_port, link_settings));
3412 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
3413 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
3414 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
3415 link->speed.autoneg = true;
3417 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
3418 link->speed.forced_speed = 1000;
3420 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
3421 link->speed.forced_speed = 10000;
3423 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3424 link->speed.forced_speed = 25000;
3426 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3427 link->speed.forced_speed = 40000;
3429 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3430 link->speed.forced_speed = 50000;
3432 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3433 link->speed.forced_speed = 100000;
3436 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
3439 p_caps->default_speed = link->speed.forced_speed;
3440 p_caps->default_speed_autoneg = link->speed.autoneg;
3442 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3443 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3444 link->pause.autoneg = !!(link_temp &
3445 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3446 link->pause.forced_rx = !!(link_temp &
3447 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3448 link->pause.forced_tx = !!(link_temp &
3449 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3450 link->loopback_mode = 0;
3452 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
3453 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
3454 OFFSETOF(struct nvm_cfg1_port, ext_phy));
3455 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
3456 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
3457 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
3458 link->eee.enable = true;
3459 switch (link_temp) {
3460 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
3461 p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
3462 link->eee.enable = false;
3464 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
3465 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
3467 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
3468 p_caps->eee_lpi_timer =
3469 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
3471 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
3472 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
3476 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
3477 link->eee.tx_lpi_enable = link->eee.enable;
3478 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
3480 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
3483 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3484 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
3485 link->speed.forced_speed, link->speed.advertised_speeds,
3486 link->speed.autoneg, link->pause.autoneg,
3487 p_caps->default_eee, p_caps->eee_lpi_timer);
3489 /* Read Multi-function information from shmem */
3490 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3491 OFFSETOF(struct nvm_cfg1, glob) +
3492 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3494 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3496 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3497 NVM_CFG1_GLOB_MF_MODE_OFFSET;
3500 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3501 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS;
3503 case NVM_CFG1_GLOB_MF_MODE_UFP:
3504 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
3505 1 << ECORE_MF_UFP_SPECIFIC;
3508 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3509 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3510 1 << ECORE_MF_LLH_PROTO_CLSS |
3511 1 << ECORE_MF_LL2_NON_UNICAST |
3512 1 << ECORE_MF_INTER_PF_SWITCH |
3513 1 << ECORE_MF_DISABLE_ARFS;
3515 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3516 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3517 1 << ECORE_MF_LLH_PROTO_CLSS |
3518 1 << ECORE_MF_LL2_NON_UNICAST;
3519 if (ECORE_IS_BB(p_hwfn->p_dev))
3520 p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
3523 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
3524 p_hwfn->p_dev->mf_bits);
3526 if (ECORE_IS_CMT(p_hwfn->p_dev))
3527 p_hwfn->p_dev->mf_bits |= (1 << ECORE_MF_DISABLE_ARFS);
3529 /* It's funny since we have another switch, but it's easier
3530 * to throw this away in linux this way. Long term, it might be
3531 * better to have have getters for needed ECORE_MF_* fields,
3532 * convert client code and eliminate this.
3535 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3536 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3538 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3539 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3541 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3542 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3544 case NVM_CFG1_GLOB_MF_MODE_UFP:
3545 p_hwfn->p_dev->mf_mode = ECORE_MF_UFP;
3549 /* Read Multi-function information from shmem */
3550 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3551 OFFSETOF(struct nvm_cfg1, glob) +
3552 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3554 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3555 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3556 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3557 &p_hwfn->hw_info.device_capabilities);
3558 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3559 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3560 &p_hwfn->hw_info.device_capabilities);
3561 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3562 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3563 &p_hwfn->hw_info.device_capabilities);
3564 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3565 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3566 &p_hwfn->hw_info.device_capabilities);
3567 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3568 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3569 &p_hwfn->hw_info.device_capabilities);
3571 rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3572 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3574 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3580 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3581 struct ecore_ptt *p_ptt)
3583 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3584 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3585 struct ecore_dev *p_dev = p_hwfn->p_dev;
3587 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3589 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3590 * in the other bits are selected.
3591 * Bits 1-15 are for functions 1-15, respectively, and their value is
3592 * '0' only for enabled functions (function 0 always exists and
3594 * In case of CMT in BB, only the "even" functions are enabled, and thus
3595 * the number of functions for both hwfns is learnt from the same bits.
3597 if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3598 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3599 MISCS_REG_FUNCTION_HIDE_BB_K2);
3601 reg_function_hide = 0;
3604 if (reg_function_hide & 0x1) {
3605 if (ECORE_IS_BB(p_dev)) {
3606 if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) {
3618 /* Get the number of the enabled functions on the engine */
3619 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3626 /* Get the PF index within the enabled functions */
3627 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3628 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3636 p_hwfn->num_funcs_on_engine = num_funcs;
3637 p_hwfn->enabled_func_idx = enabled_func_idx;
3640 if (CHIP_REV_IS_FPGA(p_dev)) {
3641 DP_NOTICE(p_hwfn, false,
3642 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3643 p_hwfn->num_funcs_on_engine = 4;
3647 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3648 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3649 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3650 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3653 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3654 struct ecore_ptt *p_ptt)
3656 struct ecore_dev *p_dev = p_hwfn->p_dev;
3660 /* Read the port mode */
3661 if (CHIP_REV_IS_FPGA(p_dev))
3663 else if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_CMT(p_dev))
3664 /* In CMT on emulation, assume 1 port */
3668 port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3670 if (port_mode < 3) {
3671 p_dev->num_ports_in_engine = 1;
3672 } else if (port_mode <= 5) {
3673 p_dev->num_ports_in_engine = 2;
3675 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3676 p_dev->num_ports_in_engine);
3678 /* Default num_ports_in_engine to something */
3679 p_dev->num_ports_in_engine = 1;
3683 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3684 struct ecore_ptt *p_ptt)
3686 struct ecore_dev *p_dev = p_hwfn->p_dev;
3690 p_dev->num_ports_in_engine = 0;
3693 if (CHIP_REV_IS_EMUL(p_dev)) {
3694 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3695 switch ((port & 0xf000) >> 12) {
3697 p_dev->num_ports_in_engine = 1;
3700 p_dev->num_ports_in_engine = 2;
3703 p_dev->num_ports_in_engine = 4;
3706 DP_NOTICE(p_hwfn, false,
3707 "Unknown port mode in ECO_RESERVED %08x\n",
3712 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3713 port = ecore_rd(p_hwfn, p_ptt,
3714 CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3717 p_dev->num_ports_in_engine++;
3720 if (!p_dev->num_ports_in_engine) {
3721 DP_NOTICE(p_hwfn, true, "All NIG ports are inactive\n");
3723 /* Default num_ports_in_engine to something */
3724 p_dev->num_ports_in_engine = 1;
3728 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3729 struct ecore_ptt *p_ptt)
3731 struct ecore_dev *p_dev = p_hwfn->p_dev;
3733 /* Determine the number of ports per engine */
3734 if (ECORE_IS_BB(p_dev))
3735 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3737 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3739 /* Get the total number of ports of the device */
3740 if (ECORE_IS_CMT(p_dev)) {
3741 /* In CMT there is always only one port */
3742 p_dev->num_ports = 1;
3744 } else if (CHIP_REV_IS_EMUL(p_dev) || CHIP_REV_IS_TEDIBEAR(p_dev)) {
3745 p_dev->num_ports = p_dev->num_ports_in_engine *
3746 ecore_device_num_engines(p_dev);
3749 u32 addr, global_offsize, global_addr;
3751 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
3753 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
3754 global_addr = SECTION_ADDR(global_offsize, 0);
3755 addr = global_addr + OFFSETOF(struct public_global, max_ports);
3756 p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
3760 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
3761 struct ecore_ptt *p_ptt)
3763 struct ecore_mcp_link_capabilities *p_caps;
3766 p_caps = &p_hwfn->mcp_info->link_capabilities;
3767 if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
3770 p_caps->eee_speed_caps = 0;
3771 eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
3772 OFFSETOF(struct public_port, eee_status));
3773 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
3774 EEE_SUPPORTED_SPEED_OFFSET;
3775 if (eee_status & EEE_1G_SUPPORTED)
3776 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
3777 if (eee_status & EEE_10G_ADV)
3778 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
3781 static enum _ecore_status_t
3782 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3783 enum ecore_pci_personality personality,
3784 struct ecore_hw_prepare_params *p_params)
3786 bool drv_resc_alloc = p_params->drv_resc_alloc;
3787 enum _ecore_status_t rc;
3789 /* Since all information is common, only first hwfns should do this */
3790 if (IS_LEAD_HWFN(p_hwfn)) {
3791 rc = ecore_iov_hw_info(p_hwfn);
3792 if (rc != ECORE_SUCCESS) {
3793 if (p_params->b_relaxed_probe)
3794 p_params->p_relaxed_res =
3795 ECORE_HW_PREPARE_BAD_IOV;
3801 if (IS_LEAD_HWFN(p_hwfn))
3802 ecore_hw_info_port_num(p_hwfn, p_ptt);
3804 ecore_mcp_get_capabilities(p_hwfn, p_ptt);
3807 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3809 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3810 if (rc != ECORE_SUCCESS)
3816 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3817 if (rc != ECORE_SUCCESS) {
3818 if (p_params->b_relaxed_probe)
3819 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3825 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3827 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3828 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3831 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3833 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3834 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3838 if (ecore_mcp_is_init(p_hwfn)) {
3839 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3840 p_hwfn->hw_info.ovlan =
3841 p_hwfn->mcp_info->func_info.ovlan;
3843 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3845 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
3847 ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
3850 if (personality != ECORE_PCI_DEFAULT) {
3851 p_hwfn->hw_info.personality = personality;
3852 } else if (ecore_mcp_is_init(p_hwfn)) {
3853 enum ecore_pci_personality protocol;
3855 protocol = p_hwfn->mcp_info->func_info.protocol;
3856 p_hwfn->hw_info.personality = protocol;
3860 /* To overcome ILT lack for emulation, until at least until we'll have
3861 * a definite answer from system about it, allow only PF0 to be RoCE.
3863 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3864 if (!p_hwfn->rel_pf_id)
3865 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3867 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3871 /* although in BB some constellations may support more than 4 tcs,
3872 * that can result in performance penalty in some cases. 4
3873 * represents a good tradeoff between performance and flexibility.
3875 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3877 /* start out with a single active tc. This can be increased either
3878 * by dcbx negotiation or by upper layer driver
3880 p_hwfn->hw_info.num_active_tc = 1;
3882 ecore_get_num_funcs(p_hwfn, p_ptt);
3884 if (ecore_mcp_is_init(p_hwfn))
3885 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3887 /* In case of forcing the driver's default resource allocation, calling
3888 * ecore_hw_get_resc() should come after initializing the personality
3889 * and after getting the number of functions, since the calculation of
3890 * the resources/features depends on them.
3891 * This order is not harmful if not forcing.
3893 rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
3894 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3896 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3902 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
3903 struct ecore_ptt *p_ptt)
3905 struct ecore_dev *p_dev = p_hwfn->p_dev;
3909 /* Read Vendor Id / Device Id */
3910 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3912 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3915 /* Determine type */
3916 device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
3917 switch (device_id_mask) {
3918 case ECORE_DEV_ID_MASK_BB:
3919 p_dev->type = ECORE_DEV_TYPE_BB;
3921 case ECORE_DEV_ID_MASK_AH:
3922 p_dev->type = ECORE_DEV_TYPE_AH;
3925 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
3927 return ECORE_ABORTED;
3930 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
3931 p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM);
3932 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
3933 p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV);
3935 /* Learn number of HW-functions */
3936 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
3938 if (tmp & (1 << p_hwfn->rel_pf_id)) {
3939 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3940 p_dev->num_hwfns = 2;
3942 p_dev->num_hwfns = 1;
3946 if (CHIP_REV_IS_EMUL(p_dev)) {
3947 /* For some reason we have problems with this register
3948 * in B0 emulation; Simply assume no CMT
3950 DP_NOTICE(p_dev->hwfns, false,
3951 "device on emul - assume no CMT\n");
3952 p_dev->num_hwfns = 1;
3956 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG);
3957 p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID);
3958 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
3959 p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL);
3961 DP_INFO(p_dev->hwfns,
3962 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n",
3963 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3964 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3965 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3968 if (ECORE_IS_BB_A0(p_dev)) {
3969 DP_NOTICE(p_dev->hwfns, false,
3970 "The chip type/rev (BB A0) is not supported!\n");
3971 return ECORE_ABORTED;
3974 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3975 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3977 if (CHIP_REV_IS_EMUL(p_dev)) {
3978 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3979 if (tmp & (1 << 29)) {
3980 DP_NOTICE(p_hwfn, false,
3981 "Emulation: Running on a FULL build\n");
3982 p_dev->b_is_emul_full = true;
3984 DP_NOTICE(p_hwfn, false,
3985 "Emulation: Running on a REDUCED build\n");
3990 return ECORE_SUCCESS;
3993 #ifndef LINUX_REMOVE
3994 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
4001 for_each_hwfn(p_dev, j) {
4002 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
4004 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
4005 "Mark hw/fw uninitialized\n");
4007 p_hwfn->hw_init_done = false;
4009 ecore_ptt_invalidate(p_hwfn);
4014 static enum _ecore_status_t
4015 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
4016 void OSAL_IOMEM * p_regview,
4017 void OSAL_IOMEM * p_doorbells,
4018 struct ecore_hw_prepare_params *p_params)
4020 struct ecore_mdump_retain_data mdump_retain;
4021 struct ecore_dev *p_dev = p_hwfn->p_dev;
4022 struct ecore_mdump_info mdump_info;
4023 enum _ecore_status_t rc = ECORE_SUCCESS;
4025 /* Split PCI bars evenly between hwfns */
4026 p_hwfn->regview = p_regview;
4027 p_hwfn->doorbells = p_doorbells;
4030 return ecore_vf_hw_prepare(p_hwfn);
4032 /* Validate that chip access is feasible */
4033 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
4035 "Reading the ME register returns all Fs; Preventing further chip access\n");
4036 if (p_params->b_relaxed_probe)
4037 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
4041 get_function_id(p_hwfn);
4043 /* Allocate PTT pool */
4044 rc = ecore_ptt_pool_alloc(p_hwfn);
4046 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
4047 if (p_params->b_relaxed_probe)
4048 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4052 /* Allocate the main PTT */
4053 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4055 /* First hwfn learns basic information, e.g., number of hwfns */
4056 if (!p_hwfn->my_id) {
4057 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
4058 if (rc != ECORE_SUCCESS) {
4059 if (p_params->b_relaxed_probe)
4060 p_params->p_relaxed_res =
4061 ECORE_HW_PREPARE_FAILED_DEV;
4066 ecore_hw_hwfn_prepare(p_hwfn);
4068 /* Initialize MCP structure */
4069 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4071 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
4072 if (p_params->b_relaxed_probe)
4073 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4077 /* Read the device configuration information from the HW and SHMEM */
4078 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
4079 p_params->personality, p_params);
4081 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
4085 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
4086 * called, since among others it sets the ports number in an engine.
4088 if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
4089 !p_dev->recov_in_prog) {
4090 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4091 if (rc != ECORE_SUCCESS)
4092 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
4095 /* Check if mdump logs/data are present and update the epoch value */
4096 if (IS_LEAD_HWFN(p_hwfn)) {
4098 if (!CHIP_REV_IS_EMUL(p_dev)) {
4100 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
4102 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
4103 DP_NOTICE(p_hwfn, false,
4104 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
4106 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
4108 if (rc == ECORE_SUCCESS && mdump_retain.valid)
4109 DP_NOTICE(p_hwfn, false,
4110 "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
4111 mdump_retain.epoch, mdump_retain.pf,
4112 mdump_retain.status);
4114 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
4121 /* Allocate the init RT array and initialize the init-ops engine */
4122 rc = ecore_init_alloc(p_hwfn);
4124 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
4125 if (p_params->b_relaxed_probe)
4126 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4130 if (CHIP_REV_IS_FPGA(p_dev)) {
4131 DP_NOTICE(p_hwfn, false,
4132 "FPGA: workaround; Prevent DMAE parities\n");
4133 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
4136 DP_NOTICE(p_hwfn, false,
4137 "FPGA: workaround: Set VF bar0 size\n");
4138 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4139 PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
4145 if (IS_LEAD_HWFN(p_hwfn))
4146 ecore_iov_free_hw_info(p_dev);
4147 ecore_mcp_free(p_hwfn);
4149 ecore_hw_hwfn_free(p_hwfn);
4154 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
4155 struct ecore_hw_prepare_params *p_params)
4157 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4158 enum _ecore_status_t rc;
4160 p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
4161 p_dev->allow_mdump = p_params->allow_mdump;
4163 if (p_params->b_relaxed_probe)
4164 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
4166 /* Store the precompiled init data ptrs */
4168 ecore_init_iro_array(p_dev);
4170 /* Initialize the first hwfn - will learn number of hwfns */
4171 rc = ecore_hw_prepare_single(p_hwfn,
4173 p_dev->doorbells, p_params);
4174 if (rc != ECORE_SUCCESS)
4177 p_params->personality = p_hwfn->hw_info.personality;
4179 /* initilalize 2nd hwfn if necessary */
4180 if (ECORE_IS_CMT(p_dev)) {
4181 void OSAL_IOMEM *p_regview, *p_doorbell;
4182 u8 OSAL_IOMEM *addr;
4184 /* adjust bar offset for second engine */
4185 addr = (u8 OSAL_IOMEM *)p_dev->regview +
4186 ecore_hw_bar_size(p_hwfn,
4189 p_regview = (void OSAL_IOMEM *)addr;
4191 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
4192 ecore_hw_bar_size(p_hwfn,
4195 p_doorbell = (void OSAL_IOMEM *)addr;
4197 /* prepare second hw function */
4198 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
4199 p_doorbell, p_params);
4201 /* in case of error, need to free the previously
4202 * initiliazed hwfn 0.
4204 if (rc != ECORE_SUCCESS) {
4205 if (p_params->b_relaxed_probe)
4206 p_params->p_relaxed_res =
4207 ECORE_HW_PREPARE_FAILED_ENG2;
4210 ecore_init_free(p_hwfn);
4211 ecore_mcp_free(p_hwfn);
4212 ecore_hw_hwfn_free(p_hwfn);
4214 DP_NOTICE(p_dev, true,
4215 "What do we need to free when VF hwfn1 init fails\n");
4224 void ecore_hw_remove(struct ecore_dev *p_dev)
4226 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4230 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4231 ECORE_OV_DRIVER_STATE_NOT_LOADED);
4233 for_each_hwfn(p_dev, i) {
4234 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4237 ecore_vf_pf_release(p_hwfn);
4241 ecore_init_free(p_hwfn);
4242 ecore_hw_hwfn_free(p_hwfn);
4243 ecore_mcp_free(p_hwfn);
4245 #ifdef CONFIG_ECORE_LOCK_ALLOC
4246 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
4250 ecore_iov_free_hw_info(p_dev);
4253 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
4254 struct ecore_chain *p_chain)
4256 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
4257 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
4258 struct ecore_chain_next *p_next;
4264 size = p_chain->elem_size * p_chain->usable_per_page;
4266 for (i = 0; i < p_chain->page_cnt; i++) {
4270 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
4271 p_virt_next = p_next->next_virt;
4272 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
4274 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
4275 ECORE_CHAIN_PAGE_SIZE);
4277 p_virt = p_virt_next;
4278 p_phys = p_phys_next;
4282 static void ecore_chain_free_single(struct ecore_dev *p_dev,
4283 struct ecore_chain *p_chain)
4285 if (!p_chain->p_virt_addr)
4288 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
4289 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
4292 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
4293 struct ecore_chain *p_chain)
4295 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
4296 u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
4297 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
4299 if (!pp_virt_addr_tbl)
4305 for (i = 0; i < page_cnt; i++) {
4306 if (!pp_virt_addr_tbl[i])
4309 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
4310 *(dma_addr_t *)p_pbl_virt,
4311 ECORE_CHAIN_PAGE_SIZE);
4313 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4316 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4318 if (!p_chain->b_external_pbl)
4319 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
4320 p_chain->pbl_sp.p_phys_table, pbl_size);
4322 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
4325 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4327 switch (p_chain->mode) {
4328 case ECORE_CHAIN_MODE_NEXT_PTR:
4329 ecore_chain_free_next_ptr(p_dev, p_chain);
4331 case ECORE_CHAIN_MODE_SINGLE:
4332 ecore_chain_free_single(p_dev, p_chain);
4334 case ECORE_CHAIN_MODE_PBL:
4335 ecore_chain_free_pbl(p_dev, p_chain);
4340 static enum _ecore_status_t
4341 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
4342 enum ecore_chain_cnt_type cnt_type,
4343 osal_size_t elem_size, u32 page_cnt)
4345 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
4347 /* The actual chain size can be larger than the maximal possible value
4348 * after rounding up the requested elements number to pages, and after
4349 * taking into acount the unusuable elements (next-ptr elements).
4350 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
4351 * size/capacity fields are of a u32 type.
4353 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
4354 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
4355 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
4356 chain_size > ECORE_U32_MAX)) {
4357 DP_NOTICE(p_dev, true,
4358 "The actual chain size (0x%lx) is larger than the maximal possible value\n",
4359 (unsigned long)chain_size);
4363 return ECORE_SUCCESS;
4366 static enum _ecore_status_t
4367 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4369 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
4370 dma_addr_t p_phys = 0;
4373 for (i = 0; i < p_chain->page_cnt; i++) {
4374 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4375 ECORE_CHAIN_PAGE_SIZE);
4377 DP_NOTICE(p_dev, true,
4378 "Failed to allocate chain memory\n");
4383 ecore_chain_init_mem(p_chain, p_virt, p_phys);
4384 ecore_chain_reset(p_chain);
4386 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4390 p_virt_prev = p_virt;
4392 /* Last page's next element should point to the beginning of the
4395 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4396 p_chain->p_virt_addr,
4397 p_chain->p_phys_addr);
4399 return ECORE_SUCCESS;
4402 static enum _ecore_status_t
4403 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4405 dma_addr_t p_phys = 0;
4406 void *p_virt = OSAL_NULL;
4408 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
4410 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
4414 ecore_chain_init_mem(p_chain, p_virt, p_phys);
4415 ecore_chain_reset(p_chain);
4417 return ECORE_SUCCESS;
4420 static enum _ecore_status_t
4421 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
4422 struct ecore_chain *p_chain,
4423 struct ecore_chain_ext_pbl *ext_pbl)
4425 u32 page_cnt = p_chain->page_cnt, size, i;
4426 dma_addr_t p_phys = 0, p_pbl_phys = 0;
4427 void **pp_virt_addr_tbl = OSAL_NULL;
4428 u8 *p_pbl_virt = OSAL_NULL;
4429 void *p_virt = OSAL_NULL;
4431 size = page_cnt * sizeof(*pp_virt_addr_tbl);
4432 pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
4433 if (!pp_virt_addr_tbl) {
4434 DP_NOTICE(p_dev, true,
4435 "Failed to allocate memory for the chain virtual addresses table\n");
4439 /* The allocation of the PBL table is done with its full size, since it
4440 * is expected to be successive.
4441 * ecore_chain_init_pbl_mem() is called even in a case of an allocation
4442 * failure, since pp_virt_addr_tbl was previously allocated, and it
4443 * should be saved to allow its freeing during the error flow.
4445 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4447 if (ext_pbl == OSAL_NULL) {
4448 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
4450 p_pbl_virt = ext_pbl->p_pbl_virt;
4451 p_pbl_phys = ext_pbl->p_pbl_phys;
4452 p_chain->b_external_pbl = true;
4455 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
4458 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
4462 for (i = 0; i < page_cnt; i++) {
4463 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4464 ECORE_CHAIN_PAGE_SIZE);
4466 DP_NOTICE(p_dev, true,
4467 "Failed to allocate chain memory\n");
4472 ecore_chain_init_mem(p_chain, p_virt, p_phys);
4473 ecore_chain_reset(p_chain);
4476 /* Fill the PBL table with the physical address of the page */
4477 *(dma_addr_t *)p_pbl_virt = p_phys;
4478 /* Keep the virtual address of the page */
4479 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
4481 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4484 return ECORE_SUCCESS;
4487 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
4488 enum ecore_chain_use_mode intended_use,
4489 enum ecore_chain_mode mode,
4490 enum ecore_chain_cnt_type cnt_type,
4491 u32 num_elems, osal_size_t elem_size,
4492 struct ecore_chain *p_chain,
4493 struct ecore_chain_ext_pbl *ext_pbl)
4496 enum _ecore_status_t rc = ECORE_SUCCESS;
4498 if (mode == ECORE_CHAIN_MODE_SINGLE)
4501 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4503 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
4506 DP_NOTICE(p_dev, true,
4507 "Cannot allocate a chain with the given arguments:\n"
4508 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4509 intended_use, mode, cnt_type, num_elems, elem_size);
4513 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
4514 mode, cnt_type, p_dev->dp_ctx);
4517 case ECORE_CHAIN_MODE_NEXT_PTR:
4518 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
4520 case ECORE_CHAIN_MODE_SINGLE:
4521 rc = ecore_chain_alloc_single(p_dev, p_chain);
4523 case ECORE_CHAIN_MODE_PBL:
4524 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
4530 return ECORE_SUCCESS;
4533 ecore_chain_free(p_dev, p_chain);
4537 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
4538 u16 src_id, u16 *dst_id)
4540 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
4543 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
4544 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
4545 DP_NOTICE(p_hwfn, true,
4546 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4552 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
4554 return ECORE_SUCCESS;
4557 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
4558 u8 src_id, u8 *dst_id)
4560 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
4563 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
4564 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
4565 DP_NOTICE(p_hwfn, true,
4566 "vport id [%d] is not valid, available indices [%d - %d]\n",
4572 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
4574 return ECORE_SUCCESS;
4577 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
4578 u8 src_id, u8 *dst_id)
4580 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
4583 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
4584 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
4585 DP_NOTICE(p_hwfn, true,
4586 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4592 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
4594 return ECORE_SUCCESS;
4597 static enum _ecore_status_t
4598 ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4599 struct ecore_ptt *p_ptt, u32 high, u32 low,
4605 /* Find a free entry and utilize it */
4606 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4607 en = ecore_rd(p_hwfn, p_ptt,
4608 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4612 ecore_wr(p_hwfn, p_ptt,
4613 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4614 2 * i * sizeof(u32), low);
4615 ecore_wr(p_hwfn, p_ptt,
4616 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4617 (2 * i + 1) * sizeof(u32), high);
4618 ecore_wr(p_hwfn, p_ptt,
4619 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4620 i * sizeof(u32), 0);
4621 ecore_wr(p_hwfn, p_ptt,
4622 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4623 i * sizeof(u32), 0);
4624 ecore_wr(p_hwfn, p_ptt,
4625 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4626 i * sizeof(u32), 1);
4630 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4631 return ECORE_NORESOURCES;
4635 return ECORE_SUCCESS;
4638 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4639 struct ecore_ptt *p_ptt, u8 *p_filter)
4641 u32 high, low, entry_num;
4642 enum _ecore_status_t rc = ECORE_SUCCESS;
4644 if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4645 &p_hwfn->p_dev->mf_bits))
4646 return ECORE_SUCCESS;
4648 high = p_filter[1] | (p_filter[0] << 8);
4649 low = p_filter[5] | (p_filter[4] << 8) |
4650 (p_filter[3] << 16) | (p_filter[2] << 24);
4652 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4653 rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low,
4655 if (rc != ECORE_SUCCESS) {
4656 DP_NOTICE(p_hwfn, false,
4657 "Failed to find an empty LLH filter to utilize\n");
4661 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4662 "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n",
4663 p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4664 p_filter[4], p_filter[5], entry_num);
4669 static enum _ecore_status_t
4670 ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4671 struct ecore_ptt *p_ptt, u32 high, u32 low,
4676 /* Find the entry and clean it */
4677 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4678 if (ecore_rd(p_hwfn, p_ptt,
4679 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4680 2 * i * sizeof(u32)) != low)
4682 if (ecore_rd(p_hwfn, p_ptt,
4683 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4684 (2 * i + 1) * sizeof(u32)) != high)
4687 ecore_wr(p_hwfn, p_ptt,
4688 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4689 ecore_wr(p_hwfn, p_ptt,
4690 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4691 2 * i * sizeof(u32), 0);
4692 ecore_wr(p_hwfn, p_ptt,
4693 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4694 (2 * i + 1) * sizeof(u32), 0);
4698 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4703 return ECORE_SUCCESS;
4706 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4707 struct ecore_ptt *p_ptt, u8 *p_filter)
4709 u32 high, low, entry_num;
4710 enum _ecore_status_t rc = ECORE_SUCCESS;
4712 if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4713 &p_hwfn->p_dev->mf_bits))
4716 high = p_filter[1] | (p_filter[0] << 8);
4717 low = p_filter[5] | (p_filter[4] << 8) |
4718 (p_filter[3] << 16) | (p_filter[2] << 24);
4720 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4721 rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high,
4723 if (rc != ECORE_SUCCESS) {
4724 DP_NOTICE(p_hwfn, false,
4725 "Tried to remove a non-configured filter\n");
4730 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4731 "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n",
4732 p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4733 p_filter[4], p_filter[5], entry_num);
4736 static enum _ecore_status_t
4737 ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4738 struct ecore_ptt *p_ptt,
4739 enum ecore_llh_port_filter_type_t type,
4740 u32 high, u32 low, u32 *p_entry_num)
4745 /* Find a free entry and utilize it */
4746 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4747 en = ecore_rd(p_hwfn, p_ptt,
4748 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4752 ecore_wr(p_hwfn, p_ptt,
4753 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4754 2 * i * sizeof(u32), low);
4755 ecore_wr(p_hwfn, p_ptt,
4756 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4757 (2 * i + 1) * sizeof(u32), high);
4758 ecore_wr(p_hwfn, p_ptt,
4759 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4760 i * sizeof(u32), 1);
4761 ecore_wr(p_hwfn, p_ptt,
4762 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4763 i * sizeof(u32), 1 << type);
4764 ecore_wr(p_hwfn, p_ptt,
4765 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1);
4769 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4770 return ECORE_NORESOURCES;
4774 return ECORE_SUCCESS;
4777 enum _ecore_status_t
4778 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4779 struct ecore_ptt *p_ptt,
4780 u16 source_port_or_eth_type,
4782 enum ecore_llh_port_filter_type_t type)
4784 u32 high, low, entry_num;
4785 enum _ecore_status_t rc = ECORE_SUCCESS;
4787 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
4788 &p_hwfn->p_dev->mf_bits))
4795 case ECORE_LLH_FILTER_ETHERTYPE:
4796 high = source_port_or_eth_type;
4798 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4799 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4800 low = source_port_or_eth_type << 16;
4802 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4803 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4806 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4807 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4808 low = (source_port_or_eth_type << 16) | dest_port;
4811 DP_NOTICE(p_hwfn, true,
4812 "Non valid LLH protocol filter type %d\n", type);
4816 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4817 rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4818 high, low, &entry_num);
4819 if (rc != ECORE_SUCCESS) {
4820 DP_NOTICE(p_hwfn, false,
4821 "Failed to find an empty LLH filter to utilize\n");
4825 case ECORE_LLH_FILTER_ETHERTYPE:
4826 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4827 "ETH type %x is added at %d\n",
4828 source_port_or_eth_type, entry_num);
4830 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4831 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4832 "TCP src port %x is added at %d\n",
4833 source_port_or_eth_type, entry_num);
4835 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4836 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4837 "UDP src port %x is added at %d\n",
4838 source_port_or_eth_type, entry_num);
4840 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4841 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4842 "TCP dst port %x is added at %d\n", dest_port,
4845 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4846 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4847 "UDP dst port %x is added at %d\n", dest_port,
4850 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4851 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4852 "TCP src/dst ports %x/%x are added at %d\n",
4853 source_port_or_eth_type, dest_port, entry_num);
4855 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4856 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4857 "UDP src/dst ports %x/%x are added at %d\n",
4858 source_port_or_eth_type, dest_port, entry_num);
4865 static enum _ecore_status_t
4866 ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4867 struct ecore_ptt *p_ptt,
4868 enum ecore_llh_port_filter_type_t type,
4869 u32 high, u32 low, u32 *p_entry_num)
4873 /* Find the entry and clean it */
4874 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4875 if (!ecore_rd(p_hwfn, p_ptt,
4876 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4879 if (!ecore_rd(p_hwfn, p_ptt,
4880 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4883 if (!(ecore_rd(p_hwfn, p_ptt,
4884 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4885 i * sizeof(u32)) & (1 << type)))
4887 if (ecore_rd(p_hwfn, p_ptt,
4888 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4889 2 * i * sizeof(u32)) != low)
4891 if (ecore_rd(p_hwfn, p_ptt,
4892 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4893 (2 * i + 1) * sizeof(u32)) != high)
4896 ecore_wr(p_hwfn, p_ptt,
4897 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4898 ecore_wr(p_hwfn, p_ptt,
4899 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4900 i * sizeof(u32), 0);
4901 ecore_wr(p_hwfn, p_ptt,
4902 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4903 i * sizeof(u32), 0);
4904 ecore_wr(p_hwfn, p_ptt,
4905 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4906 2 * i * sizeof(u32), 0);
4907 ecore_wr(p_hwfn, p_ptt,
4908 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4909 (2 * i + 1) * sizeof(u32), 0);
4913 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4918 return ECORE_SUCCESS;
4922 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4923 struct ecore_ptt *p_ptt,
4924 u16 source_port_or_eth_type,
4926 enum ecore_llh_port_filter_type_t type)
4928 u32 high, low, entry_num;
4929 enum _ecore_status_t rc = ECORE_SUCCESS;
4931 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
4932 &p_hwfn->p_dev->mf_bits))
4939 case ECORE_LLH_FILTER_ETHERTYPE:
4940 high = source_port_or_eth_type;
4942 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4943 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4944 low = source_port_or_eth_type << 16;
4946 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4947 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4950 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4951 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4952 low = (source_port_or_eth_type << 16) | dest_port;
4955 DP_NOTICE(p_hwfn, true,
4956 "Non valid LLH protocol filter type %d\n", type);
4960 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4961 rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4964 if (rc != ECORE_SUCCESS) {
4965 DP_NOTICE(p_hwfn, false,
4966 "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n",
4967 type, source_port_or_eth_type, dest_port);
4971 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4972 "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n",
4973 type, source_port_or_eth_type, dest_port, entry_num);
4976 static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn,
4977 struct ecore_ptt *p_ptt)
4981 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4984 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4985 ecore_wr(p_hwfn, p_ptt,
4986 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4987 i * sizeof(u32), 0);
4988 ecore_wr(p_hwfn, p_ptt,
4989 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4990 2 * i * sizeof(u32), 0);
4991 ecore_wr(p_hwfn, p_ptt,
4992 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4993 (2 * i + 1) * sizeof(u32), 0);
4997 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4998 struct ecore_ptt *p_ptt)
5000 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
5001 &p_hwfn->p_dev->mf_bits) &&
5002 !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
5003 &p_hwfn->p_dev->mf_bits))
5006 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5007 ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt);
5010 enum _ecore_status_t
5011 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
5012 struct ecore_ptt *p_ptt)
5014 if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
5015 ecore_wr(p_hwfn, p_ptt,
5016 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
5017 1 << p_hwfn->abs_pf_id / 2);
5018 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
5019 return ECORE_SUCCESS;
5022 DP_NOTICE(p_hwfn, false,
5023 "This function can't be set as default\n");
5027 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
5028 struct ecore_ptt *p_ptt,
5029 u32 hw_addr, void *p_eth_qzone,
5030 osal_size_t eth_qzone_size,
5033 struct coalescing_timeset *p_coal_timeset;
5035 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
5036 DP_NOTICE(p_hwfn, true,
5037 "Coalescing configuration not enabled\n");
5041 p_coal_timeset = p_eth_qzone;
5042 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
5043 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
5044 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
5045 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
5047 return ECORE_SUCCESS;
5050 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
5051 u16 rx_coal, u16 tx_coal,
5054 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
5055 enum _ecore_status_t rc = ECORE_SUCCESS;
5056 struct ecore_ptt *p_ptt;
5058 /* TODO - Configuring a single queue's coalescing but
5059 * claiming all queues are abiding same configuration
5060 * for PF and VF both.
5063 if (IS_VF(p_hwfn->p_dev))
5064 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
5067 p_ptt = ecore_ptt_acquire(p_hwfn);
5072 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
5075 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
5079 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
5082 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
5085 ecore_ptt_release(p_hwfn, p_ptt);
5090 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
5091 struct ecore_ptt *p_ptt,
5093 struct ecore_queue_cid *p_cid)
5095 struct ustorm_eth_queue_zone eth_qzone;
5096 u8 timeset, timer_res;
5098 enum _ecore_status_t rc;
5100 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5101 if (coalesce <= 0x7F) {
5103 } else if (coalesce <= 0xFF) {
5105 } else if (coalesce <= 0x1FF) {
5108 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5111 timeset = (u8)(coalesce >> timer_res);
5113 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5114 p_cid->sb_igu_id, false);
5115 if (rc != ECORE_SUCCESS)
5118 address = BAR0_MAP_REG_USDM_RAM +
5119 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5121 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
5122 sizeof(struct ustorm_eth_queue_zone), timeset);
5123 if (rc != ECORE_SUCCESS)
5130 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
5131 struct ecore_ptt *p_ptt,
5133 struct ecore_queue_cid *p_cid)
5135 struct xstorm_eth_queue_zone eth_qzone;
5136 u8 timeset, timer_res;
5138 enum _ecore_status_t rc;
5140 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5141 if (coalesce <= 0x7F) {
5143 } else if (coalesce <= 0xFF) {
5145 } else if (coalesce <= 0x1FF) {
5148 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5152 timeset = (u8)(coalesce >> timer_res);
5154 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5155 p_cid->sb_igu_id, true);
5156 if (rc != ECORE_SUCCESS)
5159 address = BAR0_MAP_REG_XSDM_RAM +
5160 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5162 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
5163 sizeof(struct xstorm_eth_queue_zone), timeset);
5168 /* Calculate final WFQ values for all vports and configure it.
5169 * After this configuration each vport must have
5170 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
5172 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5173 struct ecore_ptt *p_ptt,
5176 struct init_qm_vport_params *vport_params;
5179 vport_params = p_hwfn->qm_info.qm_vport_params;
5181 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5182 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5184 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
5186 ecore_init_vport_wfq(p_hwfn, p_ptt,
5187 vport_params[i].first_tx_pq_id,
5188 vport_params[i].vport_wfq);
5192 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn)
5196 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5197 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
5200 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5201 struct ecore_ptt *p_ptt)
5203 struct init_qm_vport_params *vport_params;
5206 vport_params = p_hwfn->qm_info.qm_vport_params;
5208 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5209 ecore_init_wfq_default_param(p_hwfn);
5210 ecore_init_vport_wfq(p_hwfn, p_ptt,
5211 vport_params[i].first_tx_pq_id,
5212 vport_params[i].vport_wfq);
5216 /* This function performs several validations for WFQ
5217 * configuration and required min rate for a given vport
5218 * 1. req_rate must be greater than one percent of min_pf_rate.
5219 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
5220 * rates to get less than one percent of min_pf_rate.
5221 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
5223 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
5224 u16 vport_id, u32 req_rate,
5227 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
5228 int non_requested_count = 0, req_count = 0, i, num_vports;
5230 num_vports = p_hwfn->qm_info.num_vports;
5232 /* Accounting for the vports which are configured for WFQ explicitly */
5234 for (i = 0; i < num_vports; i++) {
5237 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
5239 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5240 total_req_min_rate += tmp_speed;
5244 /* Include current vport data as well */
5246 total_req_min_rate += req_rate;
5247 non_requested_count = num_vports - req_count;
5249 /* validate possible error cases */
5250 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
5251 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5252 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5253 vport_id, req_rate, min_pf_rate);
5257 /* TBD - for number of vports greater than 100 */
5258 if (num_vports > ECORE_WFQ_UNIT) {
5259 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5260 "Number of vports is greater than %d\n",
5265 if (total_req_min_rate > min_pf_rate) {
5266 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5267 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5268 total_req_min_rate, min_pf_rate);
5272 /* Data left for non requested vports */
5273 total_left_rate = min_pf_rate - total_req_min_rate;
5274 left_rate_per_vp = total_left_rate / non_requested_count;
5276 /* validate if non requested get < 1% of min bw */
5277 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
5278 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5279 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5280 left_rate_per_vp, min_pf_rate);
5284 /* now req_rate for given vport passes all scenarios.
5285 * assign final wfq rates to all vports.
5287 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5288 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5290 for (i = 0; i < num_vports; i++) {
5291 if (p_hwfn->qm_info.wfq_data[i].configured)
5294 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5297 return ECORE_SUCCESS;
5300 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
5301 struct ecore_ptt *p_ptt,
5302 u16 vp_id, u32 rate)
5304 struct ecore_mcp_link_state *p_link;
5305 int rc = ECORE_SUCCESS;
5307 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
5309 if (!p_link->min_pf_rate) {
5310 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5311 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5315 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5317 if (rc == ECORE_SUCCESS)
5318 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5319 p_link->min_pf_rate);
5321 DP_NOTICE(p_hwfn, false,
5322 "Validation failed while configuring min rate\n");
5327 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
5328 struct ecore_ptt *p_ptt,
5331 bool use_wfq = false;
5332 int rc = ECORE_SUCCESS;
5335 /* Validate all pre configured vports for wfq */
5336 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5339 if (!p_hwfn->qm_info.wfq_data[i].configured)
5342 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5345 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5346 if (rc != ECORE_SUCCESS) {
5347 DP_NOTICE(p_hwfn, false,
5348 "WFQ validation failed while configuring min rate\n");
5353 if (rc == ECORE_SUCCESS && use_wfq)
5354 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5356 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5361 /* Main API for ecore clients to configure vport min rate.
5362 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5363 * rate - Speed in Mbps needs to be assigned to a given vport.
5365 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
5367 int i, rc = ECORE_INVAL;
5369 /* TBD - for multiple hardware functions - that is 100 gig */
5370 if (ECORE_IS_CMT(p_dev)) {
5371 DP_NOTICE(p_dev, false,
5372 "WFQ configuration is not supported for this device\n");
5376 for_each_hwfn(p_dev, i) {
5377 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5378 struct ecore_ptt *p_ptt;
5380 p_ptt = ecore_ptt_acquire(p_hwfn);
5382 return ECORE_TIMEOUT;
5384 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5386 if (rc != ECORE_SUCCESS) {
5387 ecore_ptt_release(p_hwfn, p_ptt);
5391 ecore_ptt_release(p_hwfn, p_ptt);
5397 /* API to configure WFQ from mcp link change */
5398 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
5399 struct ecore_ptt *p_ptt,
5404 /* TBD - for multiple hardware functions - that is 100 gig */
5405 if (ECORE_IS_CMT(p_dev)) {
5406 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
5407 "WFQ configuration is not supported for this device\n");
5411 for_each_hwfn(p_dev, i) {
5412 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5414 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5419 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
5420 struct ecore_ptt *p_ptt,
5421 struct ecore_mcp_link_state *p_link,
5424 int rc = ECORE_SUCCESS;
5426 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5428 if (!p_link->line_speed && (max_bw != 100))
5431 p_link->speed = (p_link->line_speed * max_bw) / 100;
5432 p_hwfn->qm_info.pf_rl = p_link->speed;
5434 /* Since the limiter also affects Tx-switched traffic, we don't want it
5435 * to limit such traffic in case there's no actual limit.
5436 * In that case, set limit to imaginary high boundary.
5439 p_hwfn->qm_info.pf_rl = 100000;
5441 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5442 p_hwfn->qm_info.pf_rl);
5444 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5445 "Configured MAX bandwidth to be %08x Mb/sec\n",
5451 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5452 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
5454 int i, rc = ECORE_INVAL;
5456 if (max_bw < 1 || max_bw > 100) {
5457 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
5461 for_each_hwfn(p_dev, i) {
5462 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5463 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5464 struct ecore_mcp_link_state *p_link;
5465 struct ecore_ptt *p_ptt;
5467 p_link = &p_lead->mcp_info->link_output;
5469 p_ptt = ecore_ptt_acquire(p_hwfn);
5471 return ECORE_TIMEOUT;
5473 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5476 ecore_ptt_release(p_hwfn, p_ptt);
5478 if (rc != ECORE_SUCCESS)
5485 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
5486 struct ecore_ptt *p_ptt,
5487 struct ecore_mcp_link_state *p_link,
5490 int rc = ECORE_SUCCESS;
5492 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5493 p_hwfn->qm_info.pf_wfq = min_bw;
5495 if (!p_link->line_speed)
5498 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5500 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5502 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5503 "Configured MIN bandwidth to be %d Mb/sec\n",
5504 p_link->min_pf_rate);
5509 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5510 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
5512 int i, rc = ECORE_INVAL;
5514 if (min_bw < 1 || min_bw > 100) {
5515 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
5519 for_each_hwfn(p_dev, i) {
5520 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5521 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5522 struct ecore_mcp_link_state *p_link;
5523 struct ecore_ptt *p_ptt;
5525 p_link = &p_lead->mcp_info->link_output;
5527 p_ptt = ecore_ptt_acquire(p_hwfn);
5529 return ECORE_TIMEOUT;
5531 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5533 if (rc != ECORE_SUCCESS) {
5534 ecore_ptt_release(p_hwfn, p_ptt);
5538 if (p_link->min_pf_rate) {
5539 u32 min_rate = p_link->min_pf_rate;
5541 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
5546 ecore_ptt_release(p_hwfn, p_ptt);
5552 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
5554 struct ecore_mcp_link_state *p_link;
5556 p_link = &p_hwfn->mcp_info->link_output;
5558 if (p_link->min_pf_rate)
5559 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5561 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
5562 sizeof(*p_hwfn->qm_info.wfq_data) *
5563 p_hwfn->qm_info.num_vports);
5566 int ecore_device_num_engines(struct ecore_dev *p_dev)
5568 return ECORE_IS_BB(p_dev) ? 2 : 1;
5571 int ecore_device_num_ports(struct ecore_dev *p_dev)
5573 return p_dev->num_ports;
5576 void ecore_set_fw_mac_addr(__le16 *fw_msb,
5581 ((u8 *)fw_msb)[0] = mac[1];
5582 ((u8 *)fw_msb)[1] = mac[0];
5583 ((u8 *)fw_mid)[0] = mac[3];
5584 ((u8 *)fw_mid)[1] = mac[2];
5585 ((u8 *)fw_lsb)[0] = mac[5];
5586 ((u8 *)fw_lsb)[1] = mac[4];