drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dev_api.h"
  32 #include "ecore_dcbx.h"
  33
  34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  35  * registers involved are not split and thus configuration is a race where
  36  * some of the PFs configuration might be lost.
  37  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  38  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  39  * there's more than a single compiled ecore component in system].
  40  */
  41 static osal_spinlock_t qm_lock;
  42 static bool qm_lock_init;
  43
  44 /* Configurable */
  45 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
  46                                          * load the driver. The number was
  47                                          * arbitrarily set.
  48                                          */
  49
  50 /* Derived */
  51 #define ECORE_MIN_PWM_REGION    ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
  52
  53 enum BAR_ID {
  54         BAR_ID_0,               /* used for GRC */
  55         BAR_ID_1                /* Used for doorbells */
  56 };
  57
  58 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
  59 {
  60         u32 bar_reg = (bar_id == BAR_ID_0 ?
  61                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  62         u32 val;
  63
  64         if (IS_VF(p_hwfn->p_dev)) {
  65                 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
  66                  * read from actual register, but we're currently not using
  67                  * it for actual doorbelling.
  68                  */
  69                 return 1 << 17;
  70         }
  71
  72         val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
  73         if (val)
  74                 return 1 << (val + 15);
  75
  76         /* The above registers were updated in the past only in CMT mode. Since
  77          * they were found to be useful MFW started updating them from 8.7.7.0.
  78          * In older MFW versions they are set to 0 which means disabled.
  79          */
  80         if (p_hwfn->p_dev->num_hwfns > 1) {
  81                 DP_NOTICE(p_hwfn, false,
  82                           "BAR size not configured. Assuming BAR size of 256kB"
  83                           " for GRC and 512kB for DB\n");
  84                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  85         } else {
  86                 DP_NOTICE(p_hwfn, false,
  87                           "BAR size not configured. Assuming BAR size of 512kB"
  88                           " for GRC and 512kB for DB\n");
  89                 val = 512 * 1024;
  90         }
  91
  92         return val;
  93 }
  94
  95 void ecore_init_dp(struct ecore_dev *p_dev,
  96                    u32 dp_module, u8 dp_level, void *dp_ctx)
  97 {
  98         u32 i;
  99
 100         p_dev->dp_level = dp_level;
 101         p_dev->dp_module = dp_module;
 102         p_dev->dp_ctx = dp_ctx;
 103         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 104                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 105
 106                 p_hwfn->dp_level = dp_level;
 107                 p_hwfn->dp_module = dp_module;
 108                 p_hwfn->dp_ctx = dp_ctx;
 109         }
 110 }
 111
 112 void ecore_init_struct(struct ecore_dev *p_dev)
 113 {
 114         u8 i;
 115
 116         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 117                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 118
 119                 p_hwfn->p_dev = p_dev;
 120                 p_hwfn->my_id = i;
 121                 p_hwfn->b_active = false;
 122
 123                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 124                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 125         }
 126
 127         /* hwfn 0 is always active */
 128         p_dev->hwfns[0].b_active = true;
 129
 130         /* set the default cache alignment to 128 (may be overridden later) */
 131         p_dev->cache_shift = 7;
 132 }
 133
 134 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 135 {
 136         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 137
 138         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 139         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 140         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 141         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 142 }
 143
 144 void ecore_resc_free(struct ecore_dev *p_dev)
 145 {
 146         int i;
 147
 148         if (IS_VF(p_dev))
 149                 return;
 150
 151         OSAL_FREE(p_dev, p_dev->fw_data);
 152
 153         OSAL_FREE(p_dev, p_dev->reset_stats);
 154
 155         for_each_hwfn(p_dev, i) {
 156                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 157
 158                 OSAL_FREE(p_dev, p_hwfn->p_tx_cids);
 159                 OSAL_FREE(p_dev, p_hwfn->p_rx_cids);
 160         }
 161
 162         for_each_hwfn(p_dev, i) {
 163                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 164
 165                 ecore_cxt_mngr_free(p_hwfn);
 166                 ecore_qm_info_free(p_hwfn);
 167                 ecore_spq_free(p_hwfn);
 168                 ecore_eq_free(p_hwfn, p_hwfn->p_eq);
 169                 ecore_consq_free(p_hwfn, p_hwfn->p_consq);
 170                 ecore_int_free(p_hwfn);
 171 #ifdef CONFIG_ECORE_LL2
 172                 ecore_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
 173 #endif
 174                 ecore_iov_free(p_hwfn);
 175                 ecore_dmae_info_free(p_hwfn);
 176                 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 177                 /* @@@TBD Flush work-queue ? */
 178         }
 179 }
 180
 181 static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn,
 182                                                bool b_sleepable)
 183 {
 184         u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue;
 185         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 186         struct init_qm_port_params *p_qm_port;
 187         bool init_rdma_offload_pq = false;
 188         bool init_pure_ack_pq = false;
 189         bool init_ooo_pq = false;
 190         u16 num_pqs, protocol_pqs;
 191         u16 num_pf_rls = 0;
 192         u16 num_vfs = 0;
 193         u32 pf_rl;
 194         u8 pf_wfq;
 195
 196         /* @TMP - saving the existing min/max bw config before resetting the
 197          * qm_info to restore them.
 198          */
 199         pf_rl = qm_info->pf_rl;
 200         pf_wfq = qm_info->pf_wfq;
 201
 202 #ifdef CONFIG_ECORE_SRIOV
 203         if (p_hwfn->p_dev->p_iov_info)
 204                 num_vfs = p_hwfn->p_dev->p_iov_info->total_vfs;
 205 #endif
 206         OSAL_MEM_ZERO(qm_info, sizeof(*qm_info));
 207
 208 #ifndef ASIC_ONLY
 209         /* @TMP - Don't allocate QM queues for VFs on emulation */
 210         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 211                 DP_NOTICE(p_hwfn, false,
 212                           "Emulation - skip configuring QM queues for VFs\n");
 213                 num_vfs = 0;
 214         }
 215 #endif
 216
 217         /* ethernet PFs require a pq per tc. Even if only a subset of the TCs
 218          * active, we want physical queues allocated for all of them, since we
 219          * don't have a good recycle flow. Non ethernet PFs require only a
 220          * single physical queue.
 221          */
 222         if (ECORE_IS_L2_PERSONALITY(p_hwfn))
 223                 protocol_pqs = p_hwfn->hw_info.num_hw_tc;
 224         else
 225                 protocol_pqs = 1;
 226
 227         num_pqs = protocol_pqs + num_vfs + 1;   /* The '1' is for pure-LB */
 228         num_vports = (u8)RESC_NUM(p_hwfn, ECORE_VPORT);
 229
 230         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
 231                 num_pqs++;      /* for RoCE queue */
 232                 init_rdma_offload_pq = true;
 233                 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn) {
 234                         /* Due to FW assumption that rl==vport, we limit the
 235                          * number of rate limiters by the minimum between its
 236                          * allocated number and the allocated number of vports.
 237                          * Another limitation is the number of supported qps
 238                          * with rate limiters in FW.
 239                          */
 240                         num_pf_rls =
 241                             (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 242                                              RESC_NUM(p_hwfn, ECORE_VPORT));
 243
 244                         /* we subtract num_vfs because each one requires a rate
 245                          * limiter, and one default rate limiter.
 246                          */
 247                         if (num_pf_rls < num_vfs + 1) {
 248                                 DP_ERR(p_hwfn, "No RL for DCQCN");
 249                                 DP_ERR(p_hwfn, "[num_pf_rls %d num_vfs %d]\n",
 250                                        num_pf_rls, num_vfs);
 251                                 return ECORE_INVAL;
 252                         }
 253                         num_pf_rls -= num_vfs + 1;
 254                 }
 255
 256                 num_pqs += num_pf_rls;
 257                 qm_info->num_pf_rls = (u8)num_pf_rls;
 258         }
 259
 260         if (ECORE_IS_IWARP_PERSONALITY(p_hwfn)) {
 261                 num_pqs += 3;   /* for iwarp queue / pure-ack / ooo */
 262                 init_rdma_offload_pq = true;
 263                 init_pure_ack_pq = true;
 264                 init_ooo_pq = true;
 265         }
 266
 267         if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 268                 num_pqs += 2;   /* for iSCSI pure-ACK / OOO queue */
 269                 init_pure_ack_pq = true;
 270                 init_ooo_pq = true;
 271         }
 272
 273         /* Sanity checking that setup requires legal number of resources */
 274         if (num_pqs > RESC_NUM(p_hwfn, ECORE_PQ)) {
 275                 DP_ERR(p_hwfn,
 276                        "Need too many Physical queues - 0x%04x avail %04x",
 277                        num_pqs, RESC_NUM(p_hwfn, ECORE_PQ));
 278                 return ECORE_INVAL;
 279         }
 280
 281         /* PQs will be arranged as follows: First per-TC PQ, then pure-LB queue,
 282          * then special queues (iSCSI pure-ACK / RoCE), then per-VF PQ.
 283          */
 284         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev,
 285                                             b_sleepable ? GFP_KERNEL :
 286                                             GFP_ATOMIC,
 287                                             sizeof(struct init_qm_pq_params) *
 288                                             num_pqs);
 289         if (!qm_info->qm_pq_params)
 290                 goto alloc_err;
 291
 292         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev,
 293                                                b_sleepable ? GFP_KERNEL :
 294                                                GFP_ATOMIC,
 295                                                sizeof(struct
 296                                                       init_qm_vport_params) *
 297                                                num_vports);
 298         if (!qm_info->qm_vport_params)
 299                 goto alloc_err;
 300
 301         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev,
 302                                               b_sleepable ? GFP_KERNEL :
 303                                               GFP_ATOMIC,
 304                                               sizeof(struct init_qm_port_params)
 305                                               * MAX_NUM_PORTS);
 306         if (!qm_info->qm_port_params)
 307                 goto alloc_err;
 308
 309         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev,
 310                                         b_sleepable ? GFP_KERNEL :
 311                                         GFP_ATOMIC,
 312                                         sizeof(struct ecore_wfq_data) *
 313                                         num_vports);
 314
 315         if (!qm_info->wfq_data)
 316                 goto alloc_err;
 317
 318         vport_id = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 319
 320         /* First init rate limited queues ( Due to RoCE assumption of
 321          * qpid=rlid )
 322          */
 323         for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
 324                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
 325                 qm_info->qm_pq_params[curr_queue].tc_id =
 326                     p_hwfn->hw_info.offload_tc;
 327                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 328                 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
 329         };
 330
 331         /* Protocol PQs */
 332         for (i = 0; i < protocol_pqs; i++) {
 333                 struct init_qm_pq_params *params =
 334                     &qm_info->qm_pq_params[curr_queue++];
 335
 336                 if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
 337                         params->vport_id = vport_id;
 338                         params->tc_id = i;
 339                         /* Note: this assumes that if we had a configuration
 340                          * with N tcs and subsequently another configuration
 341                          * With Fewer TCs, the in flight traffic (in QM queues,
 342                          * in FW, from driver to FW) will still trickle out and
 343                          * not get "stuck" in the QM. This is determined by the
 344                          * NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ. Unused TCs are
 345                          * supposed to be cleared in this map, allowing traffic
 346                          * to flush out. If this is not the case, we would need
 347                          * to set the TC of unused queues to 0, and reconfigure
 348                          * QM every time num of TCs changes. Unused queues in
 349                          * this context would mean those intended for TCs where
 350                          * tc_id > hw_info.num_active_tcs.
 351                          */
 352                         params->wrr_group = 1;  /* @@@TBD ECORE_WRR_MEDIUM */
 353                 } else {
 354                         params->vport_id = vport_id;
 355                         params->tc_id = p_hwfn->hw_info.offload_tc;
 356                         params->wrr_group = 1;  /* @@@TBD ECORE_WRR_MEDIUM */
 357                 }
 358         }
 359
 360         /* Then init pure-LB PQ */
 361         qm_info->pure_lb_pq = curr_queue;
 362         qm_info->qm_pq_params[curr_queue].vport_id =
 363             (u8)RESC_START(p_hwfn, ECORE_VPORT);
 364         qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
 365         qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 366         curr_queue++;
 367
 368         qm_info->offload_pq = 0;        /* Already initialized for iSCSI/FCoE */
 369         if (init_rdma_offload_pq) {
 370                 qm_info->offload_pq = curr_queue;
 371                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 372                 qm_info->qm_pq_params[curr_queue].tc_id =
 373                     p_hwfn->hw_info.offload_tc;
 374                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 375                 curr_queue++;
 376         }
 377
 378         if (init_pure_ack_pq) {
 379                 qm_info->pure_ack_pq = curr_queue;
 380                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 381                 qm_info->qm_pq_params[curr_queue].tc_id =
 382                     p_hwfn->hw_info.offload_tc;
 383                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 384                 curr_queue++;
 385         }
 386
 387         if (init_ooo_pq) {
 388                 qm_info->ooo_pq = curr_queue;
 389                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 390                 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
 391                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 392                 curr_queue++;
 393         }
 394
 395         /* Then init per-VF PQs */
 396         vf_offset = curr_queue;
 397         for (i = 0; i < num_vfs; i++) {
 398                 /* First vport is used by the PF */
 399                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
 400                 /* @@@TBD VF Multi-cos */
 401                 qm_info->qm_pq_params[curr_queue].tc_id = 0;
 402                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 403                 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
 404                 curr_queue++;
 405         };
 406
 407         qm_info->vf_queues_offset = vf_offset;
 408         qm_info->num_pqs = num_pqs;
 409         qm_info->num_vports = num_vports;
 410
 411         /* Initialize qm port parameters */
 412         num_ports = p_hwfn->p_dev->num_ports_in_engines;
 413         for (i = 0; i < num_ports; i++) {
 414                 p_qm_port = &qm_info->qm_port_params[i];
 415                 p_qm_port->active = 1;
 416                 /* @@@TMP - was NUM_OF_PHYS_TCS; Changed until dcbx will
 417                  * be in place
 418                  */
 419                 if (num_ports == 4)
 420                         p_qm_port->active_phys_tcs = 0xf;
 421                 else
 422                         p_qm_port->active_phys_tcs = 0x9f;
 423                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 424                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 425         }
 426
 427         if (ECORE_IS_AH(p_hwfn->p_dev) && (num_ports == 4))
 428                 qm_info->max_phys_tcs_per_port = NUM_PHYS_TCS_4PORT_K2;
 429         else
 430                 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
 431
 432         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 433
 434         qm_info->num_vf_pqs = num_vfs;
 435         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 436
 437         for (i = 0; i < qm_info->num_vports; i++)
 438                 qm_info->qm_vport_params[i].vport_wfq = 1;
 439
 440         qm_info->vport_rl_en = 1;
 441         qm_info->vport_wfq_en = 1;
 442         qm_info->pf_rl = pf_rl;
 443         qm_info->pf_wfq = pf_wfq;
 444
 445         return ECORE_SUCCESS;
 446
 447  alloc_err:
 448         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
 449         ecore_qm_info_free(p_hwfn);
 450         return ECORE_NOMEM;
 451 }
 452
 453 /* This function reconfigures the QM pf on the fly.
 454  * For this purpose we:
 455  * 1. reconfigure the QM database
 456  * 2. set new values to runtime arrat
 457  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 458  * 4. activate init tool in QM_PF stage
 459  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 460  */
 461 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
 462                                      struct ecore_ptt *p_ptt)
 463 {
 464         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 465         bool b_rc;
 466         enum _ecore_status_t rc;
 467
 468         /* qm_info is allocated in ecore_init_qm_info() which is already called
 469          * from ecore_resc_alloc() or previous call of ecore_qm_reconf().
 470          * The allocated size may change each init, so we free it before next
 471          * allocation.
 472          */
 473         ecore_qm_info_free(p_hwfn);
 474
 475         /* initialize ecore's qm data structure */
 476         rc = ecore_init_qm_info(p_hwfn, false);
 477         if (rc != ECORE_SUCCESS)
 478                 return rc;
 479
 480         /* stop PF's qm queues */
 481         OSAL_SPIN_LOCK(&qm_lock);
 482         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 483                                       qm_info->start_pq, qm_info->num_pqs);
 484         OSAL_SPIN_UNLOCK(&qm_lock);
 485         if (!b_rc)
 486                 return ECORE_INVAL;
 487
 488         /* clear the QM_PF runtime phase leftovers from previous init */
 489         ecore_init_clear_rt_data(p_hwfn);
 490
 491         /* prepare QM portion of runtime array */
 492         ecore_qm_init_pf(p_hwfn);
 493
 494         /* activate init tool on runtime array */
 495         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 496                             p_hwfn->hw_info.hw_mode);
 497         if (rc != ECORE_SUCCESS)
 498                 return rc;
 499
 500         /* start PF's qm queues */
 501         OSAL_SPIN_LOCK(&qm_lock);
 502         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 503                                       qm_info->start_pq, qm_info->num_pqs);
 504         OSAL_SPIN_UNLOCK(&qm_lock);
 505         if (!b_rc)
 506                 return ECORE_INVAL;
 507
 508         return ECORE_SUCCESS;
 509 }
 510
 511 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
 512 {
 513         struct ecore_consq *p_consq;
 514         struct ecore_eq *p_eq;
 515 #ifdef  CONFIG_ECORE_LL2
 516         struct ecore_ll2_info *p_ll2_info;
 517 #endif
 518         enum _ecore_status_t rc = ECORE_SUCCESS;
 519         int i;
 520
 521         if (IS_VF(p_dev))
 522                 return rc;
 523
 524         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 525                                      sizeof(*p_dev->fw_data));
 526         if (!p_dev->fw_data)
 527                 return ECORE_NOMEM;
 528
 529         /* Allocate Memory for the Queue->CID mapping */
 530         for_each_hwfn(p_dev, i) {
 531                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 532                 u32 num_tx_conns = RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 533                 int tx_size, rx_size;
 534
 535                 /* @@@TMP - resc management, change to actual required size */
 536                 if (p_hwfn->pf_params.eth_pf_params.num_cons > num_tx_conns)
 537                         num_tx_conns = p_hwfn->pf_params.eth_pf_params.num_cons;
 538                 tx_size = sizeof(struct ecore_hw_cid_data) * num_tx_conns;
 539                 rx_size = sizeof(struct ecore_hw_cid_data) *
 540                     RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 541
 542                 p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 543                                                 tx_size);
 544                 if (!p_hwfn->p_tx_cids) {
 545                         DP_NOTICE(p_hwfn, true,
 546                                   "Failed to allocate memory for Tx Cids\n");
 547                         goto alloc_no_mem;
 548                 }
 549
 550                 p_hwfn->p_rx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 551                                                 rx_size);
 552                 if (!p_hwfn->p_rx_cids) {
 553                         DP_NOTICE(p_hwfn, true,
 554                                   "Failed to allocate memory for Rx Cids\n");
 555                         goto alloc_no_mem;
 556                 }
 557         }
 558
 559         for_each_hwfn(p_dev, i) {
 560                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 561                 u32 n_eqes, num_cons;
 562
 563                 /* First allocate the context manager structure */
 564                 rc = ecore_cxt_mngr_alloc(p_hwfn);
 565                 if (rc)
 566                         goto alloc_err;
 567
 568                 /* Set the HW cid/tid numbers (in the contest manager)
 569                  * Must be done prior to any further computations.
 570                  */
 571                 rc = ecore_cxt_set_pf_params(p_hwfn);
 572                 if (rc)
 573                         goto alloc_err;
 574
 575                 /* Prepare and process QM requirements */
 576                 rc = ecore_init_qm_info(p_hwfn, true);
 577                 if (rc)
 578                         goto alloc_err;
 579
 580                 /* Compute the ILT client partition */
 581                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
 582                 if (rc)
 583                         goto alloc_err;
 584
 585                 /* CID map / ILT shadow table / T2
 586                  * The talbes sizes are determined by the computations above
 587                  */
 588                 rc = ecore_cxt_tables_alloc(p_hwfn);
 589                 if (rc)
 590                         goto alloc_err;
 591
 592                 /* SPQ, must follow ILT because initializes SPQ context */
 593                 rc = ecore_spq_alloc(p_hwfn);
 594                 if (rc)
 595                         goto alloc_err;
 596
 597                 /* SP status block allocation */
 598                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
 599                                                            RESERVED_PTT_DPC);
 600
 601                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 602                 if (rc)
 603                         goto alloc_err;
 604
 605                 rc = ecore_iov_alloc(p_hwfn);
 606                 if (rc)
 607                         goto alloc_err;
 608
 609                 /* EQ */
 610                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
 611                 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
 612                         /* Calculate the EQ size
 613                          * ---------------------
 614                          * Each ICID may generate up to one event at a time i.e.
 615                          * the event must be handled/cleared before a new one
 616                          * can be generated. We calculate the sum of events per
 617                          * protocol and create an EQ deep enough to handle the
 618                          * worst case:
 619                          * - Core - according to SPQ.
 620                          * - RoCE - per QP there are a couple of ICIDs, one
 621                          *          responder and one requester, each can
 622                          *          generate an EQE => n_eqes_qp = 2 * n_qp.
 623                          *          Each CQ can generate an EQE. There are 2 CQs
 624                          *          per QP => n_eqes_cq = 2 * n_qp.
 625                          *          Hence the RoCE total is 4 * n_qp or
 626                          *          2 * num_cons.
 627                          * - ENet - There can be up to two events per VF. One
 628                          *          for VF-PF channel and another for VF FLR
 629                          *          initial cleanup. The number of VFs is
 630                          *          bounded by MAX_NUM_VFS_BB, and is much
 631                          *          smaller than RoCE's so we avoid exact
 632                          *          calculation.
 633                          */
 634                         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
 635                                 num_cons =
 636                                     ecore_cxt_get_proto_cid_count(
 637                                                 p_hwfn,
 638                                                 PROTOCOLID_ROCE,
 639                                                 OSAL_NULL);
 640                                 num_cons *= 2;
 641                         } else {
 642                                 num_cons = ecore_cxt_get_proto_cid_count(
 643                                                 p_hwfn,
 644                                                 PROTOCOLID_IWARP,
 645                                                 OSAL_NULL);
 646                         }
 647                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 648                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 649                         num_cons =
 650                             ecore_cxt_get_proto_cid_count(p_hwfn,
 651                                                           PROTOCOLID_ISCSI,
 652                                                           OSAL_NULL);
 653                         n_eqes += 2 * num_cons;
 654                 }
 655
 656                 if (n_eqes > 0xFFFF) {
 657                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
 658                                        "The maximum of a u16 chain is 0x%x\n",
 659                                n_eqes, 0xFFFF);
 660                         goto alloc_no_mem;
 661                 }
 662
 663                 p_eq = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
 664                 if (!p_eq)
 665                         goto alloc_no_mem;
 666                 p_hwfn->p_eq = p_eq;
 667
 668                 p_consq = ecore_consq_alloc(p_hwfn);
 669                 if (!p_consq)
 670                         goto alloc_no_mem;
 671                 p_hwfn->p_consq = p_consq;
 672
 673 #ifdef CONFIG_ECORE_LL2
 674                 if (p_hwfn->using_ll2) {
 675                         p_ll2_info = ecore_ll2_alloc(p_hwfn);
 676                         if (!p_ll2_info)
 677                                 goto alloc_no_mem;
 678                         p_hwfn->p_ll2_info = p_ll2_info;
 679                 }
 680 #endif
 681
 682                 /* DMA info initialization */
 683                 rc = ecore_dmae_info_alloc(p_hwfn);
 684                 if (rc) {
 685                         DP_NOTICE(p_hwfn, true,
 686                                   "Failed to allocate memory for dmae_info structure\n");
 687                         goto alloc_err;
 688                 }
 689
 690                 /* DCBX initialization */
 691                 rc = ecore_dcbx_info_alloc(p_hwfn);
 692                 if (rc) {
 693                         DP_NOTICE(p_hwfn, true,
 694                                   "Failed to allocate memory for dcbx structure\n");
 695                         goto alloc_err;
 696                 }
 697         }
 698
 699         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 700                                          sizeof(*p_dev->reset_stats));
 701         if (!p_dev->reset_stats) {
 702                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
 703                 goto alloc_no_mem;
 704         }
 705
 706         return ECORE_SUCCESS;
 707
 708  alloc_no_mem:
 709         rc = ECORE_NOMEM;
 710  alloc_err:
 711         ecore_resc_free(p_dev);
 712         return rc;
 713 }
 714
 715 void ecore_resc_setup(struct ecore_dev *p_dev)
 716 {
 717         int i;
 718
 719         if (IS_VF(p_dev))
 720                 return;
 721
 722         for_each_hwfn(p_dev, i) {
 723                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 724
 725                 ecore_cxt_mngr_setup(p_hwfn);
 726                 ecore_spq_setup(p_hwfn);
 727                 ecore_eq_setup(p_hwfn, p_hwfn->p_eq);
 728                 ecore_consq_setup(p_hwfn, p_hwfn->p_consq);
 729
 730                 /* Read shadow of current MFW mailbox */
 731                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
 732                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
 733                             p_hwfn->mcp_info->mfw_mb_cur,
 734                             p_hwfn->mcp_info->mfw_mb_length);
 735
 736                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
 737
 738                 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
 739 #ifdef CONFIG_ECORE_LL2
 740                 if (p_hwfn->using_ll2)
 741                         ecore_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
 742 #endif
 743         }
 744 }
 745
 746 #define FINAL_CLEANUP_POLL_CNT  (100)
 747 #define FINAL_CLEANUP_POLL_TIME (10)
 748 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
 749                                          struct ecore_ptt *p_ptt,
 750                                          u16 id, bool is_vf)
 751 {
 752         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
 753         enum _ecore_status_t rc = ECORE_TIMEOUT;
 754
 755 #ifndef ASIC_ONLY
 756         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
 757             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 758                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
 759                 return ECORE_SUCCESS;
 760         }
 761 #endif
 762
 763         addr = GTT_BAR0_MAP_REG_USDM_RAM +
 764             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
 765
 766         if (is_vf)
 767                 id += 0x10;
 768
 769         command |= X_FINAL_CLEANUP_AGG_INT <<
 770             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
 771         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
 772         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
 773         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
 774
 775 /* Make sure notification is not set before initiating final cleanup */
 776
 777         if (REG_RD(p_hwfn, addr)) {
 778                 DP_NOTICE(p_hwfn, false,
 779                           "Unexpected; Found final cleanup notification");
 780                 DP_NOTICE(p_hwfn, false,
 781                           " before initiating final cleanup\n");
 782                 REG_WR(p_hwfn, addr, 0);
 783         }
 784
 785         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
 786                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
 787                    id, command);
 788
 789         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
 790
 791         /* Poll until completion */
 792         while (!REG_RD(p_hwfn, addr) && count--)
 793                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
 794
 795         if (REG_RD(p_hwfn, addr))
 796                 rc = ECORE_SUCCESS;
 797         else
 798                 DP_NOTICE(p_hwfn, true,
 799                           "Failed to receive FW final cleanup notification\n");
 800
 801         /* Cleanup afterwards */
 802         REG_WR(p_hwfn, addr, 0);
 803
 804         return rc;
 805 }
 806
 807 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
 808 {
 809         int hw_mode = 0;
 810
 811         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
 812                 hw_mode |= 1 << MODE_BB;
 813         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
 814                 hw_mode |= 1 << MODE_K2;
 815         } else {
 816                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
 817                           p_hwfn->p_dev->type);
 818                 return ECORE_INVAL;
 819         }
 820
 821         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
 822         switch (p_hwfn->p_dev->num_ports_in_engines) {
 823         case 1:
 824                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
 825                 break;
 826         case 2:
 827                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
 828                 break;
 829         case 4:
 830                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
 831                 break;
 832         default:
 833                 DP_NOTICE(p_hwfn, true,
 834                           "num_ports_in_engine = %d not supported\n",
 835                           p_hwfn->p_dev->num_ports_in_engines);
 836                 return ECORE_INVAL;
 837         }
 838
 839         switch (p_hwfn->p_dev->mf_mode) {
 840         case ECORE_MF_DEFAULT:
 841         case ECORE_MF_NPAR:
 842                 hw_mode |= 1 << MODE_MF_SI;
 843                 break;
 844         case ECORE_MF_OVLAN:
 845                 hw_mode |= 1 << MODE_MF_SD;
 846                 break;
 847         default:
 848                 DP_NOTICE(p_hwfn, true,
 849                           "Unsupported MF mode, init as DEFAULT\n");
 850                 hw_mode |= 1 << MODE_MF_SI;
 851         }
 852
 853 #ifndef ASIC_ONLY
 854         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 855                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
 856                         hw_mode |= 1 << MODE_FPGA;
 857                 } else {
 858                         if (p_hwfn->p_dev->b_is_emul_full)
 859                                 hw_mode |= 1 << MODE_EMUL_FULL;
 860                         else
 861                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
 862                 }
 863         } else
 864 #endif
 865                 hw_mode |= 1 << MODE_ASIC;
 866
 867         if (p_hwfn->p_dev->num_hwfns > 1)
 868                 hw_mode |= 1 << MODE_100G;
 869
 870         p_hwfn->hw_info.hw_mode = hw_mode;
 871
 872         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
 873                    "Configuring function for hw_mode: 0x%08x\n",
 874                    p_hwfn->hw_info.hw_mode);
 875
 876         return ECORE_SUCCESS;
 877 }
 878
 879 #ifndef ASIC_ONLY
 880 /* MFW-replacement initializations for non-ASIC */
 881 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
 882                                                struct ecore_ptt *p_ptt)
 883 {
 884         struct ecore_dev *p_dev = p_hwfn->p_dev;
 885         u32 pl_hv = 1;
 886         int i;
 887
 888         if (CHIP_REV_IS_EMUL(p_dev)) {
 889                 if (ECORE_IS_AH(p_dev))
 890                         pl_hv |= 0x600;
 891         }
 892
 893         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
 894
 895         if (CHIP_REV_IS_EMUL(p_dev) &&
 896             (ECORE_IS_AH(p_dev)))
 897                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
 898                          0x3ffffff);
 899
 900         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
 901         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
 902         if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
 903                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
 904
 905         if (CHIP_REV_IS_EMUL(p_dev)) {
 906                 if (ECORE_IS_AH(p_dev)) {
 907                         /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
 908                         ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
 909                                  (p_dev->num_ports_in_engines >> 1));
 910
 911                         ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
 912                                  p_dev->num_ports_in_engines == 4 ? 0 : 3);
 913                 }
 914         }
 915
 916         /* Poll on RBC */
 917         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
 918         for (i = 0; i < 100; i++) {
 919                 OSAL_UDELAY(50);
 920                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
 921                         break;
 922         }
 923         if (i == 100)
 924                 DP_NOTICE(p_hwfn, true,
 925                           "RBC done failed to complete in PSWRQ2\n");
 926
 927         return ECORE_SUCCESS;
 928 }
 929 #endif
 930
 931 /* Init run time data for all PFs and their VFs on an engine.
 932  * TBD - for VFs - Once we have parent PF info for each VF in
 933  * shmem available as CAU requires knowledge of parent PF for each VF.
 934  */
 935 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
 936 {
 937         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
 938         int i, sb_id;
 939
 940         for_each_hwfn(p_dev, i) {
 941                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 942                 struct ecore_igu_info *p_igu_info;
 943                 struct ecore_igu_block *p_block;
 944                 struct cau_sb_entry sb_entry;
 945
 946                 p_igu_info = p_hwfn->hw_info.p_igu_info;
 947
 948                 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
 949                      sb_id++) {
 950                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
 951
 952                         if (!p_block->is_pf)
 953                                 continue;
 954
 955                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
 956                                                 p_block->function_id, 0, 0);
 957                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
 958                 }
 959         }
 960 }
 961
 962 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
 963                                                  struct ecore_ptt *p_ptt,
 964                                                  int hw_mode)
 965 {
 966         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 967         struct ecore_dev *p_dev = p_hwfn->p_dev;
 968         u8 vf_id, max_num_vfs;
 969         u16 num_pfs, pf_id;
 970         u32 concrete_fid;
 971         enum _ecore_status_t rc = ECORE_SUCCESS;
 972
 973         ecore_init_cau_rt_data(p_dev);
 974
 975         /* Program GTT windows */
 976         ecore_gtt_init(p_hwfn);
 977
 978 #ifndef ASIC_ONLY
 979         if (CHIP_REV_IS_EMUL(p_dev)) {
 980                 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
 981                 if (rc != ECORE_SUCCESS)
 982                         return rc;
 983         }
 984 #endif
 985
 986         if (p_hwfn->mcp_info) {
 987                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
 988                         qm_info->pf_rl_en = 1;
 989                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
 990                         qm_info->pf_wfq_en = 1;
 991         }
 992
 993         ecore_qm_common_rt_init(p_hwfn,
 994                                 p_dev->num_ports_in_engines,
 995                                 qm_info->max_phys_tcs_per_port,
 996                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
 997                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
 998                                 qm_info->qm_port_params);
 999
1000         ecore_cxt_hw_init_common(p_hwfn);
1001
1002         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1003         if (rc != ECORE_SUCCESS)
1004                 return rc;
1005
1006         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1007          * need to decide with which value, maybe runtime
1008          */
1009         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1010         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1011
1012         if (ECORE_IS_BB(p_dev)) {
1013                 /* Workaround clears ROCE search for all functions to prevent
1014                  * involving non initialized function in processing ROCE packet.
1015                  */
1016                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1017                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1018                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1019                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1020                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1021                 }
1022                 /* pretend to original PF */
1023                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1024         }
1025
1026         /* Workaround for avoiding CCFC execution error when getting packets
1027          * with CRC errors, and allowing instead the invoking of the FW error
1028          * handler.
1029          * This is not done inside the init tool since it currently can't
1030          * perform a pretending to VFs.
1031          */
1032         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1033         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1034                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1035                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1036                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1037                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1038                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1039                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1040         }
1041         /* pretend to original PF */
1042         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1043
1044         return rc;
1045 }
1046
1047 #ifndef ASIC_ONLY
1048 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1049 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1050
1051 #define PMEG_IF_BYTE_COUNT      8
1052
1053 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1054                              struct ecore_ptt *p_ptt,
1055                              u32 addr, u64 data, u8 reg_type, u8 port)
1056 {
1057         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1058                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1059                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1060                    (8 << PMEG_IF_BYTE_COUNT),
1061                    (reg_type << 25) | (addr << 8) | port,
1062                    (u32)((data >> 32) & 0xffffffff),
1063                    (u32)(data & 0xffffffff));
1064
1065         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1066                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1067                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1068         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1069                  (reg_type << 25) | (addr << 8) | port);
1070         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1071         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1072                  (data >> 32) & 0xffffffff);
1073 }
1074
1075 #define XLPORT_MODE_REG (0x20a)
1076 #define XLPORT_MAC_CONTROL (0x210)
1077 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1078 #define XLPORT_ENABLE_REG (0x20b)
1079
1080 #define XLMAC_CTRL (0x600)
1081 #define XLMAC_MODE (0x601)
1082 #define XLMAC_RX_MAX_SIZE (0x608)
1083 #define XLMAC_TX_CTRL (0x604)
1084 #define XLMAC_PAUSE_CTRL (0x60d)
1085 #define XLMAC_PFC_CTRL (0x60e)
1086
1087 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1088                                     struct ecore_ptt *p_ptt)
1089 {
1090         u8 loopback = 0, port = p_hwfn->port_id * 2;
1091
1092         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1093
1094         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1095         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1096                          port);
1097         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1098         /* XLMAC: SOFT RESET */
1099         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1100         /* XLMAC: Port Speed >= 10Gbps */
1101         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1102         /* XLMAC: Max Size */
1103         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1104         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1105                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1106                          0, port);
1107         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1108         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1109                          0x30ffffc000ULL, 0, port);
1110         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1111                          port); /* XLMAC: TX_EN, RX_EN */
1112         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1113         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1114                          0x1003 | (loopback << 2), 0, port);
1115         /* Enabled Parallel PFC interface */
1116         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1117
1118         /* XLPORT port enable */
1119         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1120 }
1121
1122 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1123                                        struct ecore_ptt *p_ptt)
1124 {
1125         u8 port = p_hwfn->port_id;
1126         u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1127
1128         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1129
1130         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1131                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1132                  (port <<
1133                   CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1134                  (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1135
1136         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1137                  1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1138
1139         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1140                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1141
1142         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1143                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1144
1145         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1146                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1147
1148         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1149                  (0xA <<
1150                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1151                  (8 <<
1152                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1153
1154         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1155                  0xa853);
1156 }
1157
1158 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1159                                  struct ecore_ptt *p_ptt)
1160 {
1161         if (ECORE_IS_AH(p_hwfn->p_dev))
1162                 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1163         else /* BB */
1164                 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1165 }
1166
1167 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1168                                struct ecore_ptt *p_ptt,  u8 port)
1169 {
1170         int port_offset = port ? 0x800 : 0;
1171         u32 xmac_rxctrl = 0;
1172
1173         /* Reset of XMAC */
1174         /* FIXME: move to common start */
1175         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1176                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1177         OSAL_MSLEEP(1);
1178         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1179                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1180
1181         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1182
1183         /* Set the number of ports on the Warp Core to 10G */
1184         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1185
1186         /* Soft reset of XMAC */
1187         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1188                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1189         OSAL_MSLEEP(1);
1190         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1191                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1192
1193         /* FIXME: move to common end */
1194         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1195                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1196
1197         /* Set Max packet size: initialize XMAC block register for port 0 */
1198         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1199
1200         /* CRC append for Tx packets: init XMAC block register for port 1 */
1201         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1202
1203         /* Enable TX and RX: initialize XMAC block register for port 1 */
1204         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1205                  XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1206         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1207                                XMAC_REG_RX_CTRL_BB + port_offset);
1208         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1209         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1210 }
1211 #endif
1212
1213 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1214                                                struct ecore_ptt *p_ptt,
1215                                                int hw_mode)
1216 {
1217         enum _ecore_status_t rc = ECORE_SUCCESS;
1218
1219         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1220                             hw_mode);
1221         if (rc != ECORE_SUCCESS)
1222                 return rc;
1223 #ifndef ASIC_ONLY
1224         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1225                 return ECORE_SUCCESS;
1226
1227         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1228                 if (ECORE_IS_AH(p_hwfn->p_dev))
1229                         return ECORE_SUCCESS;
1230                 else if (ECORE_IS_BB(p_hwfn->p_dev))
1231                         ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
1232         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1233                 if (p_hwfn->p_dev->num_hwfns > 1) {
1234                         /* Activate OPTE in CMT */
1235                         u32 val;
1236
1237                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1238                         val |= 0x10;
1239                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1240                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1241                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1242                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1243                         ecore_wr(p_hwfn, p_ptt,
1244                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1245                         ecore_wr(p_hwfn, p_ptt,
1246                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1247                         ecore_wr(p_hwfn, p_ptt,
1248                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1249                                  0x55555555);
1250                 }
1251
1252                 ecore_emul_link_init(p_hwfn, p_ptt);
1253         } else {
1254                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1255         }
1256 #endif
1257
1258         return rc;
1259 }
1260
1261 static enum _ecore_status_t
1262 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1263                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1264 {
1265         u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1266         u32 dpi_bit_shift, dpi_count;
1267         u32 min_dpis;
1268
1269         /* Calculate DPI size
1270          * ------------------
1271          * The PWM region contains Doorbell Pages. The first is reserverd for
1272          * the kernel for, e.g, L2. The others are free to be used by non-
1273          * trusted applications, typically from user space. Each page, called a
1274          * doorbell page is sectioned into windows that allow doorbells to be
1275          * issued in parallel by the kernel/application. The size of such a
1276          * window (a.k.a. WID) is 1kB.
1277          * Summary:
1278          *    1kB WID x N WIDS = DPI page size
1279          *    DPI page size x N DPIs = PWM region size
1280          * Notes:
1281          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1282          * in order to ensure that two applications won't share the same page.
1283          * It also must contain at least one WID per CPU to allow parallelism.
1284          * It also must be a power of 2, since it is stored as a bit shift.
1285          *
1286          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1287          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1288          * containing 4 WIDs.
1289          */
1290         dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1291         dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1292         dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1293         dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1294         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1295
1296         dpi_count = pwm_region_size / dpi_page_size;
1297
1298         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1299         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1300
1301         /* Update hwfn */
1302         p_hwfn->dpi_size = dpi_page_size;
1303         p_hwfn->dpi_count = dpi_count;
1304
1305         /* Update registers */
1306         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1307
1308         if (dpi_count < min_dpis)
1309                 return ECORE_NORESOURCES;
1310
1311         return ECORE_SUCCESS;
1312 }
1313
1314 enum ECORE_ROCE_EDPM_MODE {
1315         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1316         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1317         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1318 };
1319
1320 static enum _ecore_status_t
1321 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1322                               struct ecore_ptt *p_ptt)
1323 {
1324         u32 pwm_regsize, norm_regsize;
1325         u32 non_pwm_conn, min_addr_reg1;
1326         u32 db_bar_size, n_cpus;
1327         u32 roce_edpm_mode;
1328         u32 pf_dems_shift;
1329         int rc = ECORE_SUCCESS;
1330         u8 cond;
1331
1332         db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1333         if (p_hwfn->p_dev->num_hwfns > 1)
1334                 db_bar_size /= 2;
1335
1336         /* Calculate doorbell regions
1337          * -----------------------------------
1338          * The doorbell BAR is made of two regions. The first is called normal
1339          * region and the second is called PWM region. In the normal region
1340          * each ICID has its own set of addresses so that writing to that
1341          * specific address identifies the ICID. In the Process Window Mode
1342          * region the ICID is given in the data written to the doorbell. The
1343          * above per PF register denotes the offset in the doorbell BAR in which
1344          * the PWM region begins.
1345          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1346          * non-PWM connection. The calculation below computes the total non-PWM
1347          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1348          * in units of 4,096 bytes.
1349          */
1350         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1351             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1352                                           OSAL_NULL) +
1353             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1354         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1355         min_addr_reg1 = norm_regsize / 4096;
1356         pwm_regsize = db_bar_size - norm_regsize;
1357
1358         /* Check that the normal and PWM sizes are valid */
1359         if (db_bar_size < norm_regsize) {
1360                 DP_ERR(p_hwfn->p_dev,
1361                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1362                        db_bar_size, norm_regsize);
1363                 return ECORE_NORESOURCES;
1364         }
1365         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1366                 DP_ERR(p_hwfn->p_dev,
1367                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1368                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1369                        norm_regsize);
1370                 return ECORE_NORESOURCES;
1371         }
1372
1373         /* Calculate number of DPIs */
1374         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1375         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1376             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1377                 /* Either EDPM is mandatory, or we are attempting to allocate a
1378                  * WID per CPU.
1379                  */
1380                 n_cpus = OSAL_NUM_ACTIVE_CPU();
1381                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1382         }
1383
1384         cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1385             (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1386         if (cond || p_hwfn->dcbx_no_edpm) {
1387                 /* Either EDPM is disabled from user configuration, or it is
1388                  * disabled via DCBx, or it is not mandatory and we failed to
1389                  * allocated a WID per CPU.
1390                  */
1391                 n_cpus = 1;
1392                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1393
1394                 /* If we entered this flow due to DCBX then the DPM register is
1395                  * already configured.
1396                  */
1397         }
1398
1399         DP_INFO(p_hwfn,
1400                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1401                 norm_regsize, pwm_regsize);
1402         DP_INFO(p_hwfn,
1403                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1404                 p_hwfn->dpi_size, p_hwfn->dpi_count,
1405                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1406                 "disabled" : "enabled");
1407
1408         /* Check return codes from above calls */
1409         if (rc) {
1410                 DP_ERR(p_hwfn,
1411                        "Failed to allocate enough DPIs\n");
1412                 return ECORE_NORESOURCES;
1413         }
1414
1415         /* Update hwfn */
1416         p_hwfn->dpi_start_offset = norm_regsize;
1417
1418         /* Update registers */
1419         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1420         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1421         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1422         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1423
1424         return ECORE_SUCCESS;
1425 }
1426
1427 static enum _ecore_status_t
1428 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1429                  struct ecore_ptt *p_ptt,
1430                  struct ecore_tunn_start_params *p_tunn,
1431                  int hw_mode,
1432                  bool b_hw_start,
1433                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1434 {
1435         u8 rel_pf_id = p_hwfn->rel_pf_id;
1436         u32 prs_reg;
1437         enum _ecore_status_t rc = ECORE_SUCCESS;
1438         u16 ctrl;
1439         int pos;
1440
1441         if (p_hwfn->mcp_info) {
1442                 struct ecore_mcp_function_info *p_info;
1443
1444                 p_info = &p_hwfn->mcp_info->func_info;
1445                 if (p_info->bandwidth_min)
1446                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1447
1448                 /* Update rate limit once we'll actually have a link */
1449                 p_hwfn->qm_info.pf_rl = 100000;
1450         }
1451         ecore_cxt_hw_init_pf(p_hwfn);
1452
1453         ecore_int_igu_init_rt(p_hwfn);
1454
1455         /* Set VLAN in NIG if needed */
1456         if (hw_mode & (1 << MODE_MF_SD)) {
1457                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1458                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1459                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1460                              p_hwfn->hw_info.ovlan);
1461         }
1462
1463         /* Enable classification by MAC if needed */
1464         if (hw_mode & (1 << MODE_MF_SI)) {
1465                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1466                            "Configuring TAGMAC_CLS_TYPE\n");
1467                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1468                              1);
1469         }
1470
1471         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
1472         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1473                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1474         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1475                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1476         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1477
1478         /* perform debug configuration when chip is out of reset */
1479         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1480
1481         /* Cleanup chip from previous driver if such remains exist */
1482         rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1483         if (rc != ECORE_SUCCESS) {
1484                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1485                 return rc;
1486         }
1487
1488         /* PF Init sequence */
1489         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1490         if (rc)
1491                 return rc;
1492
1493         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1494         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1495         if (rc)
1496                 return rc;
1497
1498         /* Pure runtime initializations - directly to the HW  */
1499         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1500
1501         /* PCI relaxed ordering causes a decrease in the performance on some
1502          * systems. Till a root cause is found, disable this attribute in the
1503          * PCI config space.
1504          */
1505         /* Not in use @DPDK
1506         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1507         * if (!pos) {
1508         *       DP_NOTICE(p_hwfn, true,
1509         *                 "Failed to find the PCIe Cap\n");
1510         *       return ECORE_IO;
1511         * }
1512         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1513         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1514         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1515         */
1516
1517         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1518         if (rc)
1519                 return rc;
1520         if (b_hw_start) {
1521                 /* enable interrupts */
1522                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1523                 if (rc != ECORE_SUCCESS)
1524                         return rc;
1525
1526                 /* send function start command */
1527                 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1528                                        allow_npar_tx_switch);
1529                 if (rc) {
1530                         DP_NOTICE(p_hwfn, true,
1531                                   "Function start ramrod failed\n");
1532                 } else {
1533                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1534                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1535                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1536
1537                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1538                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1539                                          (1 << 2));
1540                                 ecore_wr(p_hwfn, p_ptt,
1541                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1542                                     0x100);
1543                         }
1544                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1545                                    "PRS_REG_SEARCH registers after start PFn\n");
1546                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1547                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1548                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1549                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1550                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1551                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1552                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1553                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1554                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1555                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1556                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1557                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1558                         prs_reg = ecore_rd(p_hwfn, p_ptt,
1559                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
1560                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1561                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1562                                    prs_reg);
1563                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1564                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1565                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1566                 }
1567         }
1568         return rc;
1569 }
1570
1571 static enum _ecore_status_t
1572 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1573                       struct ecore_ptt *p_ptt, u8 enable)
1574 {
1575         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1576
1577         /* Change PF in PXP */
1578         ecore_wr(p_hwfn, p_ptt,
1579                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1580
1581         /* wait until value is set - try for 1 second every 50us */
1582         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1583                 val = ecore_rd(p_hwfn, p_ptt,
1584                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1585                 if (val == set_val)
1586                         break;
1587
1588                 OSAL_UDELAY(50);
1589         }
1590
1591         if (val != set_val) {
1592                 DP_NOTICE(p_hwfn, true,
1593                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1594                 return ECORE_UNKNOWN_ERROR;
1595         }
1596
1597         return ECORE_SUCCESS;
1598 }
1599
1600 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1601                                   struct ecore_ptt *p_main_ptt)
1602 {
1603         /* Read shadow of current MFW mailbox */
1604         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1605         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1606                     p_hwfn->mcp_info->mfw_mb_cur,
1607                     p_hwfn->mcp_info->mfw_mb_length);
1608 }
1609
1610 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1611                                    struct ecore_hw_init_params *p_params)
1612 {
1613         enum _ecore_status_t rc = ECORE_SUCCESS, mfw_rc;
1614         u32 load_code, param, drv_mb_param;
1615         bool b_default_mtu = true;
1616         struct ecore_hwfn *p_hwfn;
1617         int i;
1618
1619         if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
1620             (p_dev->num_hwfns > 1)) {
1621                 DP_NOTICE(p_dev, false,
1622                           "MSI mode is not supported for CMT devices\n");
1623                 return ECORE_INVAL;
1624         }
1625
1626         if (IS_PF(p_dev)) {
1627                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1628                 if (rc != ECORE_SUCCESS)
1629                         return rc;
1630         }
1631
1632         for_each_hwfn(p_dev, i) {
1633                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1634
1635                 /* If management didn't provide a default, set one of our own */
1636                 if (!p_hwfn->hw_info.mtu) {
1637                         p_hwfn->hw_info.mtu = 1500;
1638                         b_default_mtu = false;
1639                 }
1640
1641                 if (IS_VF(p_dev)) {
1642                         p_hwfn->b_int_enabled = 1;
1643                         continue;
1644                 }
1645
1646                 /* Enable DMAE in PXP */
1647                 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1648                 if (rc != ECORE_SUCCESS)
1649                         return rc;
1650
1651                 rc = ecore_calc_hw_mode(p_hwfn);
1652                 if (rc != ECORE_SUCCESS)
1653                         return rc;
1654
1655                 /* @@@TBD need to add here:
1656                  * Check for fan failure
1657                  * Prev_unload
1658                  */
1659                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1660                 if (rc) {
1661                         DP_NOTICE(p_hwfn, true,
1662                                   "Failed sending LOAD_REQ command\n");
1663                         return rc;
1664                 }
1665
1666                 /* CQ75580:
1667                  * When coming back from hiberbate state, the registers from
1668                  * which shadow is read initially are not initialized. It turns
1669                  * out that these registers get initialized during the call to
1670                  * ecore_mcp_load_req request. So we need to reread them here
1671                  * to get the proper shadow register value.
1672                  * Note: This is a workaround for the missing MFW
1673                  * initialization. It may be removed once the implementation
1674                  * is done.
1675                  */
1676                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1677
1678                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1679                            "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1680                            rc, load_code);
1681
1682                 /* Only relevant for recovery:
1683                  * Clear the indication after the LOAD_REQ command is responded
1684                  * by the MFW.
1685                  */
1686                 p_dev->recov_in_prog = false;
1687
1688                 p_hwfn->first_on_engine = (load_code ==
1689                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1690
1691                 if (!qm_lock_init) {
1692                         OSAL_SPIN_LOCK_INIT(&qm_lock);
1693                         qm_lock_init = true;
1694                 }
1695
1696                 switch (load_code) {
1697                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1698                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1699                                                   p_hwfn->hw_info.hw_mode);
1700                         if (rc)
1701                                 break;
1702                         /* Fall into */
1703                 case FW_MSG_CODE_DRV_LOAD_PORT:
1704                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1705                                                 p_hwfn->hw_info.hw_mode);
1706                         if (rc)
1707                                 break;
1708                         /* Fall into */
1709                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1710                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1711                                               p_params->p_tunn,
1712                                               p_hwfn->hw_info.hw_mode,
1713                                               p_params->b_hw_start,
1714                                               p_params->int_mode,
1715                                               p_params->allow_npar_tx_switch);
1716                         break;
1717                 default:
1718                         rc = ECORE_NOTIMPL;
1719                         break;
1720                 }
1721
1722                 if (rc != ECORE_SUCCESS)
1723                         DP_NOTICE(p_hwfn, true,
1724                                   "init phase failed for loadcode 0x%x (rc %d)\n",
1725                                   load_code, rc);
1726
1727                 /* ACK mfw regardless of success or failure of initialization */
1728                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1729                                        DRV_MSG_CODE_LOAD_DONE,
1730                                        0, &load_code, &param);
1731                 if (rc != ECORE_SUCCESS)
1732                         return rc;
1733                 if (mfw_rc != ECORE_SUCCESS) {
1734                         DP_NOTICE(p_hwfn, true,
1735                                   "Failed sending LOAD_DONE command\n");
1736                         return mfw_rc;
1737                 }
1738
1739                 /* send DCBX attention request command */
1740                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1741                            "sending phony dcbx set command to trigger DCBx attention handling\n");
1742                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1743                                        DRV_MSG_CODE_SET_DCBX,
1744                                        1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1745                                        &load_code, &param);
1746                 if (mfw_rc != ECORE_SUCCESS) {
1747                         DP_NOTICE(p_hwfn, true,
1748                                   "Failed to send DCBX attention request\n");
1749                         return mfw_rc;
1750                 }
1751
1752                 p_hwfn->hw_init_done = true;
1753         }
1754
1755         if (IS_PF(p_dev)) {
1756                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
1757                 drv_mb_param = (FW_MAJOR_VERSION << 24) |
1758                                (FW_MINOR_VERSION << 16) |
1759                                (FW_REVISION_VERSION << 8) |
1760                                (FW_ENGINEERING_VERSION);
1761                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1762                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1763                                    drv_mb_param, &load_code, &param);
1764                 if (rc != ECORE_SUCCESS)
1765                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
1766
1767                 if (!b_default_mtu)
1768                         rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
1769                                                       p_hwfn->hw_info.mtu);
1770                 if (rc != ECORE_SUCCESS)
1771                         DP_INFO(p_hwfn, "Failed to update default mtu\n");
1772
1773                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
1774                                                       p_hwfn->p_main_ptt,
1775                                                 ECORE_OV_DRIVER_STATE_DISABLED);
1776                 if (rc != ECORE_SUCCESS)
1777                         DP_INFO(p_hwfn, "Failed to update driver state\n");
1778         }
1779
1780         return rc;
1781 }
1782
1783 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
1784 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
1785                                  struct ecore_hwfn *p_hwfn,
1786                                  struct ecore_ptt *p_ptt)
1787 {
1788         int i;
1789
1790         /* close timers */
1791         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1792         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1793         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
1794                                                                         i++) {
1795                 if ((!ecore_rd(p_hwfn, p_ptt,
1796                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1797                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1798                         break;
1799
1800                 /* Dependent on number of connection/tasks, possibly
1801                  * 1ms sleep is required between polls
1802                  */
1803                 OSAL_MSLEEP(1);
1804         }
1805
1806         if (i < ECORE_HW_STOP_RETRY_LIMIT)
1807                 return;
1808
1809         DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
1810                   " [Connection %02x Tasks %02x]\n",
1811                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1812                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1813 }
1814
1815 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
1816 {
1817         int j;
1818
1819         for_each_hwfn(p_dev, j) {
1820                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1821                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1822
1823                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1824         }
1825 }
1826
1827 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
1828 {
1829         enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
1830         int j;
1831
1832         for_each_hwfn(p_dev, j) {
1833                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1834                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1835
1836                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
1837
1838                 if (IS_VF(p_dev)) {
1839                         ecore_vf_pf_int_cleanup(p_hwfn);
1840                         continue;
1841                 }
1842
1843                 /* mark the hw as uninitialized... */
1844                 p_hwfn->hw_init_done = false;
1845
1846                 rc = ecore_sp_pf_stop(p_hwfn);
1847                 if (rc)
1848                         DP_NOTICE(p_hwfn, true,
1849                                   "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
1850
1851                 /* perform debug action after PF stop was sent */
1852                 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
1853
1854                 /* close NIG to BRB gate */
1855                 ecore_wr(p_hwfn, p_ptt,
1856                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1857
1858                 /* close parser */
1859                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1860                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1861                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1862                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1863                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1864
1865                 /* @@@TBD - clean transmission queues (5.b) */
1866                 /* @@@TBD - clean BTB (5.c) */
1867
1868                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1869
1870                 /* @@@TBD - verify DMAE requests are done (8) */
1871
1872                 /* Disable Attention Generation */
1873                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1874                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1875                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1876                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1877                 /* Need to wait 1ms to guarantee SBs are cleared */
1878                 OSAL_MSLEEP(1);
1879         }
1880
1881         if (IS_PF(p_dev)) {
1882                 /* Disable DMAE in PXP - in CMT, this should only be done for
1883                  * first hw-function, and only after all transactions have
1884                  * stopped for all active hw-functions.
1885                  */
1886                 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
1887                                              p_dev->hwfns[0].p_main_ptt, false);
1888                 if (t_rc != ECORE_SUCCESS)
1889                         rc = t_rc;
1890         }
1891
1892         return rc;
1893 }
1894
1895 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
1896 {
1897         int j;
1898
1899         for_each_hwfn(p_dev, j) {
1900                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1901                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1902
1903                 if (IS_VF(p_dev)) {
1904                         ecore_vf_pf_int_cleanup(p_hwfn);
1905                         continue;
1906                 }
1907
1908                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1909                            "Shutting down the fastpath\n");
1910
1911                 ecore_wr(p_hwfn, p_ptt,
1912                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1913
1914                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1915                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1916                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1917                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1918                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1919
1920                 /* @@@TBD - clean transmission queues (5.b) */
1921                 /* @@@TBD - clean BTB (5.c) */
1922
1923                 /* @@@TBD - verify DMAE requests are done (8) */
1924
1925                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1926                 /* Need to wait 1ms to guarantee SBs are cleared */
1927                 OSAL_MSLEEP(1);
1928         }
1929 }
1930
1931 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
1932 {
1933         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1934
1935         if (IS_VF(p_hwfn->p_dev))
1936                 return;
1937
1938         /* If roce info is allocated it means roce is initialized and should
1939          * be enabled in searcher.
1940          */
1941         if (p_hwfn->p_rdma_info) {
1942                 if (p_hwfn->b_rdma_enabled_in_prs)
1943                         ecore_wr(p_hwfn, p_ptt,
1944                                  p_hwfn->rdma_prs_search_reg, 0x1);
1945                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
1946         }
1947
1948         /* Re-open incoming traffic */
1949         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1950                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1951 }
1952
1953 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
1954                                              struct ecore_ptt *p_ptt, u32 reg,
1955                                              bool expected)
1956 {
1957         u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
1958
1959         if (assert_val != expected) {
1960                 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
1961                           reg, expected);
1962                 return ECORE_UNKNOWN_ERROR;
1963         }
1964
1965         return 0;
1966 }
1967
1968 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
1969 {
1970         enum _ecore_status_t rc = ECORE_SUCCESS;
1971         u32 unload_resp, unload_param;
1972         int i;
1973
1974         for_each_hwfn(p_dev, i) {
1975                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1976
1977                 if (IS_VF(p_dev)) {
1978                         rc = ecore_vf_pf_reset(p_hwfn);
1979                         if (rc)
1980                                 return rc;
1981                         continue;
1982                 }
1983
1984                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
1985
1986                 /* Check for incorrect states */
1987                 if (!p_dev->recov_in_prog) {
1988                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1989                                          QM_REG_USG_CNT_PF_TX, 0);
1990                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1991                                          QM_REG_USG_CNT_PF_OTHER, 0);
1992                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
1993                 }
1994
1995                 /* Disable PF in HW blocks */
1996                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1997                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1998
1999                 if (p_dev->recov_in_prog) {
2000                         DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2001                                    "Recovery is in progress -> skip sending unload_req/done\n");
2002                         break;
2003                 }
2004
2005                 /* Send unload command to MCP */
2006                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2007                                    DRV_MSG_CODE_UNLOAD_REQ,
2008                                    DRV_MB_PARAM_UNLOAD_WOL_MCP,
2009                                    &unload_resp, &unload_param);
2010                 if (rc != ECORE_SUCCESS) {
2011                         DP_NOTICE(p_hwfn, true,
2012                                   "ecore_hw_reset: UNLOAD_REQ failed\n");
2013                         /* @@TBD - what to do? for now, assume ENG. */
2014                         unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
2015                 }
2016
2017                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2018                                    DRV_MSG_CODE_UNLOAD_DONE,
2019                                    0, &unload_resp, &unload_param);
2020                 if (rc != ECORE_SUCCESS) {
2021                         DP_NOTICE(p_hwfn,
2022                                   true, "ecore_hw_reset: UNLOAD_DONE failed\n");
2023                         /* @@@TBD - Should it really ASSERT here ? */
2024                         return rc;
2025                 }
2026         }
2027
2028         return rc;
2029 }
2030
2031 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2032 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2033 {
2034         ecore_ptt_pool_free(p_hwfn);
2035         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2036 }
2037
2038 /* Setup bar access */
2039 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2040 {
2041         /* clear indirect access */
2042         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2043                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2044                          PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2045                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2046                          PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2047                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2048                          PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2049                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2050                          PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2051         } else {
2052                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2053                          PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2054                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2055                          PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2056                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2057                          PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2058                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2059                          PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2060         }
2061
2062         /* Clean Previous errors if such exist */
2063         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2064                  PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2065
2066         /* enable internal target-read */
2067         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2068                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2069 }
2070
2071 static void get_function_id(struct ecore_hwfn *p_hwfn)
2072 {
2073         /* ME Register */
2074         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2075                                                   PXP_PF_ME_OPAQUE_ADDR);
2076
2077         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2078
2079         /* Bits 16-19 from the ME registers are the pf_num */
2080         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2081         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2082                                       PXP_CONCRETE_FID_PFID);
2083         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2084                                     PXP_CONCRETE_FID_PORT);
2085
2086         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2087                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2088                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2089 }
2090
2091 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2092 {
2093         u32 *feat_num = p_hwfn->hw_info.feat_num;
2094         struct ecore_sb_cnt_info sb_cnt_info;
2095         int num_features = 1;
2096
2097         /* L2 Queues require each: 1 status block. 1 L2 queue */
2098         feat_num[ECORE_PF_L2_QUE] =
2099             OSAL_MIN_T(u32,
2100                        RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2101                        RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2102
2103         OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2104         ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2105         feat_num[ECORE_VF_L2_QUE] =
2106                 OSAL_MIN_T(u32,
2107                            RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2108                            FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2109                            sb_cnt_info.sb_iov_cnt);
2110
2111         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2112                    "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d num_features=%d\n",
2113                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2114                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2115                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2116                    RESC_NUM(p_hwfn, ECORE_SB),
2117                    num_features);
2118 }
2119
2120 static enum resource_id_enum
2121 ecore_hw_get_mfw_res_id(enum ecore_resources res_id)
2122 {
2123         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2124
2125         switch (res_id) {
2126         case ECORE_SB:
2127                 mfw_res_id = RESOURCE_NUM_SB_E;
2128                 break;
2129         case ECORE_L2_QUEUE:
2130                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2131                 break;
2132         case ECORE_VPORT:
2133                 mfw_res_id = RESOURCE_NUM_VPORT_E;
2134                 break;
2135         case ECORE_RSS_ENG:
2136                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2137                 break;
2138         case ECORE_PQ:
2139                 mfw_res_id = RESOURCE_NUM_PQ_E;
2140                 break;
2141         case ECORE_RL:
2142                 mfw_res_id = RESOURCE_NUM_RL_E;
2143                 break;
2144         case ECORE_MAC:
2145         case ECORE_VLAN:
2146                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2147                 mfw_res_id = RESOURCE_VFC_FILTER_E;
2148                 break;
2149         case ECORE_ILT:
2150                 mfw_res_id = RESOURCE_ILT_E;
2151                 break;
2152         case ECORE_LL2_QUEUE:
2153                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2154                 break;
2155         case ECORE_RDMA_CNQ_RAM:
2156         case ECORE_CMDQS_CQS:
2157                 /* CNQ/CMDQS are the same resource */
2158                 mfw_res_id = RESOURCE_CQS_E;
2159                 break;
2160         case ECORE_RDMA_STATS_QUEUE:
2161                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2162                 break;
2163         default:
2164                 break;
2165         }
2166
2167         return mfw_res_id;
2168 }
2169
2170 static u32 ecore_hw_get_dflt_resc_num(struct ecore_hwfn *p_hwfn,
2171                                       enum ecore_resources res_id)
2172 {
2173         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2174         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2175         struct ecore_sb_cnt_info sb_cnt_info;
2176         u32 dflt_resc_num = 0;
2177
2178         switch (res_id) {
2179         case ECORE_SB:
2180                 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2181                 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2182                 dflt_resc_num = sb_cnt_info.sb_cnt;
2183                 break;
2184         case ECORE_L2_QUEUE:
2185                 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2186                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
2187                 break;
2188         case ECORE_VPORT:
2189                 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2190                                  MAX_NUM_VPORTS_BB) / num_funcs;
2191                 break;
2192         case ECORE_RSS_ENG:
2193                 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2194                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2195                 break;
2196         case ECORE_PQ:
2197                 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2198                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
2199                 break;
2200         case ECORE_RL:
2201                 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2202                 break;
2203         case ECORE_MAC:
2204         case ECORE_VLAN:
2205                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2206                 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2207                 break;
2208         case ECORE_ILT:
2209                 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2210                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2211                 break;
2212         case ECORE_LL2_QUEUE:
2213                 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2214                 break;
2215         case ECORE_RDMA_CNQ_RAM:
2216         case ECORE_CMDQS_CQS:
2217                 /* CNQ/CMDQS are the same resource */
2218                 /* @DPDK */
2219                 dflt_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2220                 break;
2221         case ECORE_RDMA_STATS_QUEUE:
2222                 /* @DPDK */
2223                 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2224                                  MAX_NUM_VPORTS_BB) / num_funcs;
2225                 break;
2226         default:
2227                 break;
2228         }
2229
2230         return dflt_resc_num;
2231 }
2232
2233 static const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2234 {
2235         switch (res_id) {
2236         case ECORE_SB:
2237                 return "SB";
2238         case ECORE_L2_QUEUE:
2239                 return "L2_QUEUE";
2240         case ECORE_VPORT:
2241                 return "VPORT";
2242         case ECORE_RSS_ENG:
2243                 return "RSS_ENG";
2244         case ECORE_PQ:
2245                 return "PQ";
2246         case ECORE_RL:
2247                 return "RL";
2248         case ECORE_MAC:
2249                 return "MAC";
2250         case ECORE_VLAN:
2251                 return "VLAN";
2252         case ECORE_RDMA_CNQ_RAM:
2253                 return "RDMA_CNQ_RAM";
2254         case ECORE_ILT:
2255                 return "ILT";
2256         case ECORE_LL2_QUEUE:
2257                 return "LL2_QUEUE";
2258         case ECORE_CMDQS_CQS:
2259                 return "CMDQS_CQS";
2260         case ECORE_RDMA_STATS_QUEUE:
2261                 return "RDMA_STATS_QUEUE";
2262         default:
2263                 return "UNKNOWN_RESOURCE";
2264         }
2265 }
2266
2267 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2268                                                    enum ecore_resources res_id,
2269                                                    bool drv_resc_alloc)
2270 {
2271         u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
2272         u32 *p_resc_num, *p_resc_start;
2273         struct resource_info resc_info;
2274         enum _ecore_status_t rc;
2275
2276         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2277         p_resc_start = &RESC_START(p_hwfn, res_id);
2278
2279         dflt_resc_num = ecore_hw_get_dflt_resc_num(p_hwfn, res_id);
2280         if (!dflt_resc_num) {
2281                 DP_ERR(p_hwfn,
2282                        "Failed to get default amount for resource %d [%s]\n",
2283                         res_id, ecore_hw_get_resc_name(res_id));
2284                 return ECORE_INVAL;
2285         }
2286         dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
2287
2288 #ifndef ASIC_ONLY
2289         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2290                 *p_resc_num = dflt_resc_num;
2291                 *p_resc_start = dflt_resc_start;
2292                 goto out;
2293         }
2294 #endif
2295
2296         OSAL_MEM_ZERO(&resc_info, sizeof(resc_info));
2297         resc_info.res_id = ecore_hw_get_mfw_res_id(res_id);
2298         if (resc_info.res_id == RESOURCE_NUM_INVALID) {
2299                 DP_ERR(p_hwfn,
2300                        "Failed to match resource %d with MFW resources\n",
2301                        res_id);
2302                 return ECORE_INVAL;
2303         }
2304
2305         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
2306                                      &mcp_resp, &mcp_param);
2307         if (rc != ECORE_SUCCESS) {
2308                 DP_NOTICE(p_hwfn, true,
2309                           "MFW response failure for an allocation request for"
2310                           " resource %d [%s]\n",
2311                           res_id, ecore_hw_get_resc_name(res_id));
2312                 return rc;
2313         }
2314
2315         /* Default driver values are applied in the following cases:
2316          * - The resource allocation MB command is not supported by the MFW
2317          * - There is an internal error in the MFW while processing the request
2318          * - The resource ID is unknown to the MFW
2319          */
2320         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
2321             mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
2322                 /* @DPDK */
2323                 DP_INFO(p_hwfn,
2324                         "Resource %d [%s]: No allocation info was received"
2325                         " [mcp_resp 0x%x]. Applying default values"
2326                         " [num %d, start %d].\n",
2327                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2328                         dflt_resc_num, dflt_resc_start);
2329
2330                 *p_resc_num = dflt_resc_num;
2331                 *p_resc_start = dflt_resc_start;
2332                 goto out;
2333         }
2334
2335         /* TBD - remove this when revising the handling of the SB resource */
2336         if (res_id == ECORE_SB) {
2337                 /* Excluding the slowpath SB */
2338                 resc_info.size -= 1;
2339                 resc_info.offset -= p_hwfn->enabled_func_idx;
2340         }
2341
2342         *p_resc_num = resc_info.size;
2343         *p_resc_start = resc_info.offset;
2344
2345         if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2346                 DP_INFO(p_hwfn,
2347                         "Resource %d [%s]: MFW allocation [num %d, start %d] differs from default values [num %d, start %d]%s\n",
2348                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2349                         *p_resc_start, dflt_resc_num, dflt_resc_start,
2350                         drv_resc_alloc ? " - Applying default values" : "");
2351                 if (drv_resc_alloc) {
2352                         *p_resc_num = dflt_resc_num;
2353                         *p_resc_start = dflt_resc_start;
2354                 }
2355         }
2356  out:
2357         return ECORE_SUCCESS;
2358 }
2359
2360 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2361                                               bool drv_resc_alloc)
2362 {
2363         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2364         enum _ecore_status_t rc;
2365         u8 res_id;
2366 #ifndef ASIC_ONLY
2367         u32 *resc_start = p_hwfn->hw_info.resc_start;
2368         u32 *resc_num = p_hwfn->hw_info.resc_num;
2369         /* For AH, an equal share of the ILT lines between the maximal number of
2370          * PFs is not enough for RoCE. This would be solved by the future
2371          * resource allocation scheme, but isn't currently present for
2372          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2373          * to work - the BB number of ILT lines divided by its max PFs number.
2374          */
2375         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2376 #endif
2377
2378         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2379                 rc = ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2380                 if (rc != ECORE_SUCCESS)
2381                         return rc;
2382         }
2383
2384 #ifndef ASIC_ONLY
2385         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2386                 /* Reduced build contains less PQs */
2387                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2388                         resc_num[ECORE_PQ] = 32;
2389                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2390                             p_hwfn->enabled_func_idx;
2391                 }
2392
2393                 /* For AH emulation, since we have a possible maximal number of
2394                  * 16 enabled PFs, in case there are not enough ILT lines -
2395                  * allocate only first PF as RoCE and have all the other ETH
2396                  * only with less ILT lines.
2397                  */
2398                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2399                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2400                                                          resc_num[ECORE_ILT],
2401                                                          roce_min_ilt_lines);
2402         }
2403
2404         /* Correct the common ILT calculation if PF0 has more */
2405         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2406             p_hwfn->p_dev->b_is_emul_full &&
2407             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2408                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2409                     resc_num[ECORE_ILT];
2410 #endif
2411
2412         /* Sanity for ILT */
2413         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2414             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2415                 DP_NOTICE(p_hwfn, true,
2416                           "Can't assign ILT pages [%08x,...,%08x]\n",
2417                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2418                                                                   ECORE_ILT) -
2419                           1);
2420                 return ECORE_INVAL;
2421         }
2422
2423         ecore_hw_set_feat(p_hwfn);
2424
2425         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2426                    "The numbers for each resource are:\n");
2427         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2428                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2429                            ecore_hw_get_resc_name(res_id),
2430                            RESC_NUM(p_hwfn, res_id),
2431                            RESC_START(p_hwfn, res_id));
2432
2433         return ECORE_SUCCESS;
2434 }
2435
2436 static enum _ecore_status_t
2437 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2438                       struct ecore_ptt *p_ptt,
2439                       struct ecore_hw_prepare_params *p_params)
2440 {
2441         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
2442         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2443         struct ecore_mcp_link_params *link;
2444         enum _ecore_status_t rc;
2445
2446         /* Read global nvm_cfg address */
2447         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2448
2449         /* Verify MCP has initialized it */
2450         if (!nvm_cfg_addr) {
2451                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2452                 if (p_params->b_relaxed_probe)
2453                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
2454                 return ECORE_INVAL;
2455         }
2456
2457 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2458
2459         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2460
2461         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2462             OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2463                                                        core_cfg);
2464
2465         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2466
2467         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2468                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2469         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2470                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2471                 break;
2472         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2473                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2474                 break;
2475         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2476                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2477                 break;
2478         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2479                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2480                 break;
2481         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2482                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2483                 break;
2484         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2485                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2486                 break;
2487         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2488                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2489                 break;
2490         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2491                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2492                 break;
2493         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2494                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
2495                 break;
2496         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2497                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2498                 break;
2499         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2500                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2501                 break;
2502         default:
2503                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2504                           core_cfg);
2505                 break;
2506         }
2507
2508         /* Read DCBX configuration */
2509         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2510                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2511         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
2512                              port_cfg_addr +
2513                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
2514         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
2515                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
2516         switch (dcbx_mode) {
2517         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
2518                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
2519                 break;
2520         case NVM_CFG1_PORT_DCBX_MODE_CEE:
2521                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
2522                 break;
2523         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
2524                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
2525                 break;
2526         default:
2527                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
2528         }
2529
2530         /* Read default link configuration */
2531         link = &p_hwfn->mcp_info->link_input;
2532         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2533             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2534         link_temp = ecore_rd(p_hwfn, p_ptt,
2535                              port_cfg_addr +
2536                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2537         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2538         link->speed.advertised_speeds = link_temp;
2539
2540         link_temp = link->speed.advertised_speeds;
2541         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2542
2543         link_temp = ecore_rd(p_hwfn, p_ptt,
2544                              port_cfg_addr +
2545                              OFFSETOF(struct nvm_cfg1_port, link_settings));
2546         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2547                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2548         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2549                 link->speed.autoneg = true;
2550                 break;
2551         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2552                 link->speed.forced_speed = 1000;
2553                 break;
2554         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2555                 link->speed.forced_speed = 10000;
2556                 break;
2557         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2558                 link->speed.forced_speed = 25000;
2559                 break;
2560         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2561                 link->speed.forced_speed = 40000;
2562                 break;
2563         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2564                 link->speed.forced_speed = 50000;
2565                 break;
2566         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2567                 link->speed.forced_speed = 100000;
2568                 break;
2569         default:
2570                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
2571         }
2572
2573         p_hwfn->mcp_info->link_capabilities.default_speed =
2574             link->speed.forced_speed;
2575         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2576             link->speed.autoneg;
2577
2578         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2579         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2580         link->pause.autoneg = !!(link_temp &
2581                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2582         link->pause.forced_rx = !!(link_temp &
2583                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2584         link->pause.forced_tx = !!(link_temp &
2585                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2586         link->loopback_mode = 0;
2587
2588         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2589                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2590                    link->speed.forced_speed, link->speed.advertised_speeds,
2591                    link->speed.autoneg, link->pause.autoneg);
2592
2593         /* Read Multi-function information from shmem */
2594         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2595             OFFSETOF(struct nvm_cfg1, glob) +
2596             OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
2597
2598         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
2599
2600         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2601             NVM_CFG1_GLOB_MF_MODE_OFFSET;
2602
2603         switch (mf_mode) {
2604         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2605                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
2606                 break;
2607         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2608                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
2609                 break;
2610         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2611                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
2612                 break;
2613         }
2614         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2615                 p_hwfn->p_dev->mf_mode);
2616
2617         /* Read Multi-function information from shmem */
2618         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2619             OFFSETOF(struct nvm_cfg1, glob) +
2620             OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
2621
2622         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
2623         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2624                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
2625                              &p_hwfn->hw_info.device_capabilities);
2626         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2627                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
2628                              &p_hwfn->hw_info.device_capabilities);
2629         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2630                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
2631                              &p_hwfn->hw_info.device_capabilities);
2632         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2633                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
2634                              &p_hwfn->hw_info.device_capabilities);
2635         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
2636                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
2637                              &p_hwfn->hw_info.device_capabilities);
2638
2639         rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2640         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
2641                 rc = ECORE_SUCCESS;
2642                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
2643         }
2644
2645         return rc;
2646 }
2647
2648 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
2649                                 struct ecore_ptt *p_ptt)
2650 {
2651         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2652         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2653         struct ecore_dev *p_dev = p_hwfn->p_dev;
2654
2655         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2656
2657         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2658          * in the other bits are selected.
2659          * Bits 1-15 are for functions 1-15, respectively, and their value is
2660          * '0' only for enabled functions (function 0 always exists and
2661          * enabled).
2662          * In case of CMT in BB, only the "even" functions are enabled, and thus
2663          * the number of functions for both hwfns is learnt from the same bits.
2664          */
2665         if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
2666                 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
2667                                              MISCS_REG_FUNCTION_HIDE_BB_K2);
2668         } else { /* E5 */
2669                 reg_function_hide = 0;
2670         }
2671
2672         if (reg_function_hide & 0x1) {
2673                 if (ECORE_IS_BB(p_dev)) {
2674                         if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
2675                                 num_funcs = 0;
2676                                 eng_mask = 0xaaaa;
2677                         } else {
2678                                 num_funcs = 1;
2679                                 eng_mask = 0x5554;
2680                         }
2681                 } else {
2682                         num_funcs = 1;
2683                         eng_mask = 0xfffe;
2684                 }
2685
2686                 /* Get the number of the enabled functions on the engine */
2687                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2688                 while (tmp) {
2689                         if (tmp & 0x1)
2690                                 num_funcs++;
2691                         tmp >>= 0x1;
2692                 }
2693
2694                 /* Get the PF index within the enabled functions */
2695                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2696                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2697                 while (tmp) {
2698                         if (tmp & 0x1)
2699                                 enabled_func_idx--;
2700                         tmp >>= 0x1;
2701                 }
2702         }
2703
2704         p_hwfn->num_funcs_on_engine = num_funcs;
2705         p_hwfn->enabled_func_idx = enabled_func_idx;
2706
2707 #ifndef ASIC_ONLY
2708         if (CHIP_REV_IS_FPGA(p_dev)) {
2709                 DP_NOTICE(p_hwfn, false,
2710                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
2711                 p_hwfn->num_funcs_on_engine = 4;
2712         }
2713 #endif
2714
2715         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2716                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2717                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
2718                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2719 }
2720
2721 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
2722                                       struct ecore_ptt *p_ptt)
2723 {
2724         u32 port_mode;
2725
2726 #ifndef ASIC_ONLY
2727         /* Read the port mode */
2728         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
2729                 port_mode = 4;
2730         else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
2731                  (p_hwfn->p_dev->num_hwfns > 1))
2732                 /* In CMT on emulation, assume 1 port */
2733                 port_mode = 1;
2734         else
2735 #endif
2736         port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
2737
2738         if (port_mode < 3) {
2739                 p_hwfn->p_dev->num_ports_in_engines = 1;
2740         } else if (port_mode <= 5) {
2741                 p_hwfn->p_dev->num_ports_in_engines = 2;
2742         } else {
2743                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
2744                           p_hwfn->p_dev->num_ports_in_engines);
2745
2746                 /* Default num_ports_in_engines to something */
2747                 p_hwfn->p_dev->num_ports_in_engines = 1;
2748         }
2749 }
2750
2751 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
2752                                          struct ecore_ptt *p_ptt)
2753 {
2754         u32 port;
2755         int i;
2756
2757         p_hwfn->p_dev->num_ports_in_engines = 0;
2758
2759 #ifndef ASIC_ONLY
2760         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2761                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
2762                 switch ((port & 0xf000) >> 12) {
2763                 case 1:
2764                         p_hwfn->p_dev->num_ports_in_engines = 1;
2765                         break;
2766                 case 3:
2767                         p_hwfn->p_dev->num_ports_in_engines = 2;
2768                         break;
2769                 case 0xf:
2770                         p_hwfn->p_dev->num_ports_in_engines = 4;
2771                         break;
2772                 default:
2773                         DP_NOTICE(p_hwfn, false,
2774                                   "Unknown port mode in ECO_RESERVED %08x\n",
2775                                   port);
2776                 }
2777         } else
2778 #endif
2779                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2780                         port = ecore_rd(p_hwfn, p_ptt,
2781                                         CNIG_REG_NIG_PORT0_CONF_K2_E5 +
2782                                         (i * 4));
2783                         if (port & 1)
2784                                 p_hwfn->p_dev->num_ports_in_engines++;
2785                 }
2786 }
2787
2788 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
2789                                    struct ecore_ptt *p_ptt)
2790 {
2791         if (ECORE_IS_BB(p_hwfn->p_dev))
2792                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
2793         else
2794                 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
2795 }
2796
2797 static enum _ecore_status_t
2798 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2799                   enum ecore_pci_personality personality,
2800                   struct ecore_hw_prepare_params *p_params)
2801 {
2802         bool drv_resc_alloc = p_params->drv_resc_alloc;
2803         enum _ecore_status_t rc;
2804
2805         /* Since all information is common, only first hwfns should do this */
2806         if (IS_LEAD_HWFN(p_hwfn)) {
2807                 rc = ecore_iov_hw_info(p_hwfn);
2808                 if (rc != ECORE_SUCCESS) {
2809                         if (p_params->b_relaxed_probe)
2810                                 p_params->p_relaxed_res =
2811                                                 ECORE_HW_PREPARE_BAD_IOV;
2812                         else
2813                                 return rc;
2814                 }
2815         }
2816
2817         /* TODO In get_hw_info, amoungst others:
2818          * Get MCP FW revision and determine according to it the supported
2819          * featrues (e.g. DCB)
2820          * Get boot mode
2821          * ecore_get_pcie_width_speed, WOL capability.
2822          * Number of global CQ-s (for storage
2823          */
2824         ecore_hw_info_port_num(p_hwfn, p_ptt);
2825
2826 #ifndef ASIC_ONLY
2827         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
2828 #endif
2829         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
2830         if (rc != ECORE_SUCCESS)
2831                 return rc;
2832 #ifndef ASIC_ONLY
2833         }
2834 #endif
2835
2836         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
2837         if (rc != ECORE_SUCCESS) {
2838                 if (p_params->b_relaxed_probe)
2839                         p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
2840                 else
2841                         return rc;
2842         }
2843
2844 #ifndef ASIC_ONLY
2845         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
2846 #endif
2847                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
2848                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
2849 #ifndef ASIC_ONLY
2850         } else {
2851                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
2852
2853                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
2854                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
2855         }
2856 #endif
2857
2858         if (ecore_mcp_is_init(p_hwfn)) {
2859                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
2860                         p_hwfn->hw_info.ovlan =
2861                             p_hwfn->mcp_info->func_info.ovlan;
2862
2863                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
2864         }
2865
2866         if (personality != ECORE_PCI_DEFAULT) {
2867                 p_hwfn->hw_info.personality = personality;
2868         } else if (ecore_mcp_is_init(p_hwfn)) {
2869                 enum ecore_pci_personality protocol;
2870
2871                 protocol = p_hwfn->mcp_info->func_info.protocol;
2872                 p_hwfn->hw_info.personality = protocol;
2873         }
2874
2875 #ifndef ASIC_ONLY
2876         /* To overcome ILT lack for emulation, until at least until we'll have
2877          * a definite answer from system about it, allow only PF0 to be RoCE.
2878          */
2879         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
2880                 if (!p_hwfn->rel_pf_id)
2881                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
2882                 else
2883                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
2884         }
2885 #endif
2886
2887         /* although in BB some constellations may support more than 4 tcs,
2888          * that can result in performance penalty in some cases. 4
2889          * represents a good tradeoff between performance and flexibility.
2890          */
2891         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2892
2893         /* start out with a single active tc. This can be increased either
2894          * by dcbx negotiation or by upper layer driver
2895          */
2896         p_hwfn->hw_info.num_active_tc = 1;
2897
2898         ecore_get_num_funcs(p_hwfn, p_ptt);
2899
2900         if (ecore_mcp_is_init(p_hwfn))
2901                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
2902
2903         /* In case of forcing the driver's default resource allocation, calling
2904          * ecore_hw_get_resc() should come after initializing the personality
2905          * and after getting the number of functions, since the calculation of
2906          * the resources/features depends on them.
2907          * This order is not harmful if not forcing.
2908          */
2909         rc = ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
2910         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
2911                 rc = ECORE_SUCCESS;
2912                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
2913         }
2914
2915         return rc;
2916 }
2917
2918 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
2919 {
2920         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2921         u32 tmp;
2922
2923         /* Read Vendor Id / Device Id */
2924         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
2925                                   &p_dev->vendor_id);
2926         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
2927                                   &p_dev->device_id);
2928
2929         /* Determine type */
2930         if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
2931                 p_dev->type = ECORE_DEV_TYPE_AH;
2932         else
2933                 p_dev->type = ECORE_DEV_TYPE_BB;
2934
2935         p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2936                                          MISCS_REG_CHIP_NUM);
2937         p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2938                                          MISCS_REG_CHIP_REV);
2939
2940         MASK_FIELD(CHIP_REV, p_dev->chip_rev);
2941
2942         /* Learn number of HW-functions */
2943         tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2944                        MISCS_REG_CMT_ENABLED_FOR_PAIR);
2945
2946         if (tmp & (1 << p_hwfn->rel_pf_id)) {
2947                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
2948                 p_dev->num_hwfns = 2;
2949         } else {
2950                 p_dev->num_hwfns = 1;
2951         }
2952
2953 #ifndef ASIC_ONLY
2954         if (CHIP_REV_IS_EMUL(p_dev)) {
2955                 /* For some reason we have problems with this register
2956                  * in B0 emulation; Simply assume no CMT
2957                  */
2958                 DP_NOTICE(p_dev->hwfns, false,
2959                           "device on emul - assume no CMT\n");
2960                 p_dev->num_hwfns = 1;
2961         }
2962 #endif
2963
2964         p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2965                                        MISCS_REG_CHIP_TEST_REG) >> 4;
2966         MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
2967         p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2968                                            MISCS_REG_CHIP_METAL);
2969         MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
2970         DP_INFO(p_dev->hwfns,
2971                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2972                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
2973                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
2974                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
2975                 p_dev->chip_metal);
2976
2977         if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
2978                 DP_NOTICE(p_dev->hwfns, false,
2979                           "The chip type/rev (BB A0) is not supported!\n");
2980                 return ECORE_ABORTED;
2981         }
2982 #ifndef ASIC_ONLY
2983         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
2984                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2985                          MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
2986
2987         if (CHIP_REV_IS_EMUL(p_dev)) {
2988                 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2989                                MISCS_REG_ECO_RESERVED);
2990                 if (tmp & (1 << 29)) {
2991                         DP_NOTICE(p_hwfn, false,
2992                                   "Emulation: Running on a FULL build\n");
2993                         p_dev->b_is_emul_full = true;
2994                 } else {
2995                         DP_NOTICE(p_hwfn, false,
2996                                   "Emulation: Running on a REDUCED build\n");
2997                 }
2998         }
2999 #endif
3000
3001         return ECORE_SUCCESS;
3002 }
3003
3004 #ifndef LINUX_REMOVE
3005 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3006 {
3007         int j;
3008
3009         if (IS_VF(p_dev))
3010                 return;
3011
3012         for_each_hwfn(p_dev, j) {
3013                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3014
3015                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
3016                            "Mark hw/fw uninitialized\n");
3017
3018                 p_hwfn->hw_init_done = false;
3019                 p_hwfn->first_on_engine = false;
3020
3021                 ecore_ptt_invalidate(p_hwfn);
3022         }
3023 }
3024 #endif
3025
3026 static enum _ecore_status_t
3027 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
3028                         void OSAL_IOMEM * p_regview,
3029                         void OSAL_IOMEM * p_doorbells,
3030                         struct ecore_hw_prepare_params *p_params)
3031 {
3032         struct ecore_dev *p_dev = p_hwfn->p_dev;
3033         struct ecore_mdump_info mdump_info;
3034         enum _ecore_status_t rc = ECORE_SUCCESS;
3035
3036         /* Split PCI bars evenly between hwfns */
3037         p_hwfn->regview = p_regview;
3038         p_hwfn->doorbells = p_doorbells;
3039
3040         if (IS_VF(p_dev))
3041                 return ecore_vf_hw_prepare(p_hwfn);
3042
3043         /* Validate that chip access is feasible */
3044         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3045                 DP_ERR(p_hwfn,
3046                        "Reading the ME register returns all Fs; Preventing further chip access\n");
3047                 if (p_params->b_relaxed_probe)
3048                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
3049                 return ECORE_INVAL;
3050         }
3051
3052         get_function_id(p_hwfn);
3053
3054         /* Allocate PTT pool */
3055         rc = ecore_ptt_pool_alloc(p_hwfn);
3056         if (rc) {
3057                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
3058                 if (p_params->b_relaxed_probe)
3059                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3060                 goto err0;
3061         }
3062
3063         /* Allocate the main PTT */
3064         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3065
3066         /* First hwfn learns basic information, e.g., number of hwfns */
3067         if (!p_hwfn->my_id) {
3068                 rc = ecore_get_dev_info(p_dev);
3069                 if (rc != ECORE_SUCCESS) {
3070                         if (p_params->b_relaxed_probe)
3071                                 p_params->p_relaxed_res =
3072                                         ECORE_HW_PREPARE_FAILED_DEV;
3073                         goto err1;
3074                 }
3075         }
3076
3077         ecore_hw_hwfn_prepare(p_hwfn);
3078
3079         /* Initialize MCP structure */
3080         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3081         if (rc) {
3082                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3083                 if (p_params->b_relaxed_probe)
3084                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3085                 goto err1;
3086         }
3087
3088         /* Read the device configuration information from the HW and SHMEM */
3089         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3090                                p_params->personality, p_params);
3091         if (rc) {
3092                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3093                 goto err2;
3094         }
3095
3096         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3097          * called, since among others it sets the ports number in an engine.
3098          */
3099         if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3100             !p_dev->recov_in_prog) {
3101                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3102                 if (rc != ECORE_SUCCESS)
3103                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3104         }
3105
3106         /* Check if mdump logs are present and update the epoch value */
3107         if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) {
3108                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3109                                               &mdump_info);
3110                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) {
3111                         DP_NOTICE(p_hwfn, false,
3112                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3113                 }
3114
3115                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3116                                            p_params->epoch);
3117         }
3118
3119         /* Allocate the init RT array and initialize the init-ops engine */
3120         rc = ecore_init_alloc(p_hwfn);
3121         if (rc) {
3122                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3123                 if (p_params->b_relaxed_probe)
3124                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3125                 goto err2;
3126         }
3127 #ifndef ASIC_ONLY
3128         if (CHIP_REV_IS_FPGA(p_dev)) {
3129                 DP_NOTICE(p_hwfn, false,
3130                           "FPGA: workaround; Prevent DMAE parities\n");
3131                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
3132                          7);
3133
3134                 DP_NOTICE(p_hwfn, false,
3135                           "FPGA: workaround: Set VF bar0 size\n");
3136                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3137                          PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
3138         }
3139 #endif
3140
3141         return rc;
3142  err2:
3143         if (IS_LEAD_HWFN(p_hwfn))
3144                 ecore_iov_free_hw_info(p_dev);
3145         ecore_mcp_free(p_hwfn);
3146  err1:
3147         ecore_hw_hwfn_free(p_hwfn);
3148  err0:
3149         return rc;
3150 }
3151
3152 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3153                                       struct ecore_hw_prepare_params *p_params)
3154 {
3155         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3156         enum _ecore_status_t rc;
3157
3158         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3159
3160         if (p_params->b_relaxed_probe)
3161                 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
3162
3163         /* Store the precompiled init data ptrs */
3164         if (IS_PF(p_dev))
3165                 ecore_init_iro_array(p_dev);
3166
3167         /* Initialize the first hwfn - will learn number of hwfns */
3168         rc = ecore_hw_prepare_single(p_hwfn,
3169                                      p_dev->regview,
3170                                      p_dev->doorbells, p_params);
3171         if (rc != ECORE_SUCCESS)
3172                 return rc;
3173
3174         p_params->personality = p_hwfn->hw_info.personality;
3175
3176         /* initilalize 2nd hwfn if necessary */
3177         if (p_dev->num_hwfns > 1) {
3178                 void OSAL_IOMEM *p_regview, *p_doorbell;
3179                 u8 OSAL_IOMEM *addr;
3180
3181                 /* adjust bar offset for second engine */
3182                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3183                     ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3184                 p_regview = (void OSAL_IOMEM *)addr;
3185
3186                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3187                     ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3188                 p_doorbell = (void OSAL_IOMEM *)addr;
3189
3190                 /* prepare second hw function */
3191                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3192                                              p_doorbell, p_params);
3193
3194                 /* in case of error, need to free the previously
3195                  * initiliazed hwfn 0.
3196                  */
3197                 if (rc != ECORE_SUCCESS) {
3198                         if (p_params->b_relaxed_probe)
3199                                 p_params->p_relaxed_res =
3200                                                 ECORE_HW_PREPARE_FAILED_ENG2;
3201
3202                         if (IS_PF(p_dev)) {
3203                                 ecore_init_free(p_hwfn);
3204                                 ecore_mcp_free(p_hwfn);
3205                                 ecore_hw_hwfn_free(p_hwfn);
3206                         } else {
3207                                 DP_NOTICE(p_dev, true,
3208                                           "What do we need to free when VF hwfn1 init fails\n");
3209                         }
3210                         return rc;
3211                 }
3212         }
3213
3214         return rc;
3215 }
3216
3217 void ecore_hw_remove(struct ecore_dev *p_dev)
3218 {
3219         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3220         int i;
3221
3222         if (IS_PF(p_dev))
3223                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3224                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
3225
3226         for_each_hwfn(p_dev, i) {
3227                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3228
3229                 if (IS_VF(p_dev)) {
3230                         ecore_vf_pf_release(p_hwfn);
3231                         continue;
3232                 }
3233
3234                 ecore_init_free(p_hwfn);
3235                 ecore_hw_hwfn_free(p_hwfn);
3236                 ecore_mcp_free(p_hwfn);
3237
3238                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3239         }
3240
3241         ecore_iov_free_hw_info(p_dev);
3242 }
3243
3244 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3245                                       struct ecore_chain *p_chain)
3246 {
3247         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3248         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3249         struct ecore_chain_next *p_next;
3250         u32 size, i;
3251
3252         if (!p_virt)
3253                 return;
3254
3255         size = p_chain->elem_size * p_chain->usable_per_page;
3256
3257         for (i = 0; i < p_chain->page_cnt; i++) {
3258                 if (!p_virt)
3259                         break;
3260
3261                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3262                 p_virt_next = p_next->next_virt;
3263                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3264
3265                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3266                                        ECORE_CHAIN_PAGE_SIZE);
3267
3268                 p_virt = p_virt_next;
3269                 p_phys = p_phys_next;
3270         }
3271 }
3272
3273 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3274                                     struct ecore_chain *p_chain)
3275 {
3276         if (!p_chain->p_virt_addr)
3277                 return;
3278
3279         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3280                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3281 }
3282
3283 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3284                                  struct ecore_chain *p_chain)
3285 {
3286         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3287         u8 *p_pbl_virt = (u8 *)p_chain->pbl.p_virt_table;
3288         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3289
3290         if (!pp_virt_addr_tbl)
3291                 return;
3292
3293         if (!p_chain->pbl.p_virt_table)
3294                 goto out;
3295
3296         for (i = 0; i < page_cnt; i++) {
3297                 if (!pp_virt_addr_tbl[i])
3298                         break;
3299
3300                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3301                                        *(dma_addr_t *)p_pbl_virt,
3302                                        ECORE_CHAIN_PAGE_SIZE);
3303
3304                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3305         }
3306
3307         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3308
3309         if (!p_chain->pbl.external)
3310                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table,
3311                                        p_chain->pbl.p_phys_table, pbl_size);
3312  out:
3313         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3314 }
3315
3316 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3317 {
3318         switch (p_chain->mode) {
3319         case ECORE_CHAIN_MODE_NEXT_PTR:
3320                 ecore_chain_free_next_ptr(p_dev, p_chain);
3321                 break;
3322         case ECORE_CHAIN_MODE_SINGLE:
3323                 ecore_chain_free_single(p_dev, p_chain);
3324                 break;
3325         case ECORE_CHAIN_MODE_PBL:
3326                 ecore_chain_free_pbl(p_dev, p_chain);
3327                 break;
3328         }
3329 }
3330
3331 static enum _ecore_status_t
3332 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3333                                enum ecore_chain_cnt_type cnt_type,
3334                                osal_size_t elem_size, u32 page_cnt)
3335 {
3336         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3337
3338         /* The actual chain size can be larger than the maximal possible value
3339          * after rounding up the requested elements number to pages, and after
3340          * taking into acount the unusuable elements (next-ptr elements).
3341          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3342          * size/capacity fields are of a u32 type.
3343          */
3344         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3345              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3346             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3347              chain_size > ECORE_U32_MAX)) {
3348                 DP_NOTICE(p_dev, true,
3349                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3350                           (unsigned long)chain_size);
3351                 return ECORE_INVAL;
3352         }
3353
3354         return ECORE_SUCCESS;
3355 }
3356
3357 static enum _ecore_status_t
3358 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3359 {
3360         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3361         dma_addr_t p_phys = 0;
3362         u32 i;
3363
3364         for (i = 0; i < p_chain->page_cnt; i++) {
3365                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3366                                                  ECORE_CHAIN_PAGE_SIZE);
3367                 if (!p_virt) {
3368                         DP_NOTICE(p_dev, true,
3369                                   "Failed to allocate chain memory\n");
3370                         return ECORE_NOMEM;
3371                 }
3372
3373                 if (i == 0) {
3374                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3375                         ecore_chain_reset(p_chain);
3376                 } else {
3377                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3378                                                        p_virt, p_phys);
3379                 }
3380
3381                 p_virt_prev = p_virt;
3382         }
3383         /* Last page's next element should point to the beginning of the
3384          * chain.
3385          */
3386         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3387                                        p_chain->p_virt_addr,
3388                                        p_chain->p_phys_addr);
3389
3390         return ECORE_SUCCESS;
3391 }
3392
3393 static enum _ecore_status_t
3394 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3395 {
3396         dma_addr_t p_phys = 0;
3397         void *p_virt = OSAL_NULL;
3398
3399         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3400         if (!p_virt) {
3401                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3402                 return ECORE_NOMEM;
3403         }
3404
3405         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3406         ecore_chain_reset(p_chain);
3407
3408         return ECORE_SUCCESS;
3409 }
3410
3411 static enum _ecore_status_t
3412 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3413                       struct ecore_chain *p_chain,
3414                       struct ecore_chain_ext_pbl *ext_pbl)
3415 {
3416         void *p_virt = OSAL_NULL;
3417         u8 *p_pbl_virt = OSAL_NULL;
3418         void **pp_virt_addr_tbl = OSAL_NULL;
3419         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3420         u32 page_cnt = p_chain->page_cnt, size, i;
3421
3422         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3423         pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
3424         if (!pp_virt_addr_tbl) {
3425                 DP_NOTICE(p_dev, true,
3426                           "Failed to allocate memory for the chain virtual addresses table\n");
3427                 return ECORE_NOMEM;
3428         }
3429         OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
3430
3431         /* The allocation of the PBL table is done with its full size, since it
3432          * is expected to be successive.
3433          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3434          * failure, since pp_virt_addr_tbl was previously allocated, and it
3435          * should be saved to allow its freeing during the error flow.
3436          */
3437         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3438
3439         if (ext_pbl == OSAL_NULL) {
3440                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3441         } else {
3442                 p_pbl_virt = ext_pbl->p_pbl_virt;
3443                 p_pbl_phys = ext_pbl->p_pbl_phys;
3444                 p_chain->pbl.external = true;
3445         }
3446
3447         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3448                                  pp_virt_addr_tbl);
3449         if (!p_pbl_virt) {
3450                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3451                 return ECORE_NOMEM;
3452         }
3453
3454         for (i = 0; i < page_cnt; i++) {
3455                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3456                                                  ECORE_CHAIN_PAGE_SIZE);
3457                 if (!p_virt) {
3458                         DP_NOTICE(p_dev, true,
3459                                   "Failed to allocate chain memory\n");
3460                         return ECORE_NOMEM;
3461                 }
3462
3463                 if (i == 0) {
3464                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3465                         ecore_chain_reset(p_chain);
3466                 }
3467
3468                 /* Fill the PBL table with the physical address of the page */
3469                 *(dma_addr_t *)p_pbl_virt = p_phys;
3470                 /* Keep the virtual address of the page */
3471                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3472
3473                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3474         }
3475
3476         return ECORE_SUCCESS;
3477 }
3478
3479 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3480                                        enum ecore_chain_use_mode intended_use,
3481                                        enum ecore_chain_mode mode,
3482                                        enum ecore_chain_cnt_type cnt_type,
3483                                        u32 num_elems, osal_size_t elem_size,
3484                                        struct ecore_chain *p_chain,
3485                                        struct ecore_chain_ext_pbl *ext_pbl)
3486 {
3487         u32 page_cnt;
3488         enum _ecore_status_t rc = ECORE_SUCCESS;
3489
3490         if (mode == ECORE_CHAIN_MODE_SINGLE)
3491                 page_cnt = 1;
3492         else
3493                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3494
3495         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3496                                             page_cnt);
3497         if (rc) {
3498                 DP_NOTICE(p_dev, true,
3499                           "Cannot allocate a chain with the given arguments:\n"
3500                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3501                           intended_use, mode, cnt_type, num_elems, elem_size);
3502                 return rc;
3503         }
3504
3505         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3506                                 mode, cnt_type, p_dev->dp_ctx);
3507
3508         switch (mode) {
3509         case ECORE_CHAIN_MODE_NEXT_PTR:
3510                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3511                 break;
3512         case ECORE_CHAIN_MODE_SINGLE:
3513                 rc = ecore_chain_alloc_single(p_dev, p_chain);
3514                 break;
3515         case ECORE_CHAIN_MODE_PBL:
3516                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
3517                 break;
3518         }
3519         if (rc)
3520                 goto nomem;
3521
3522         return ECORE_SUCCESS;
3523
3524  nomem:
3525         ecore_chain_free(p_dev, p_chain);
3526         return rc;
3527 }
3528
3529 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3530                                        u16 src_id, u16 *dst_id)
3531 {
3532         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3533                 u16 min, max;
3534
3535                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3536                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3537                 DP_NOTICE(p_hwfn, true,
3538                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3539                           src_id, min, max);
3540
3541                 return ECORE_INVAL;
3542         }
3543
3544         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3545
3546         return ECORE_SUCCESS;
3547 }
3548
3549 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3550                                     u8 src_id, u8 *dst_id)
3551 {
3552         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3553                 u8 min, max;
3554
3555                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3556                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3557                 DP_NOTICE(p_hwfn, true,
3558                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3559                           src_id, min, max);
3560
3561                 return ECORE_INVAL;
3562         }
3563
3564         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3565
3566         return ECORE_SUCCESS;
3567 }
3568
3569 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
3570                                       u8 src_id, u8 *dst_id)
3571 {
3572         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
3573                 u8 min, max;
3574
3575                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
3576                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
3577                 DP_NOTICE(p_hwfn, true,
3578                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3579                           src_id, min, max);
3580
3581                 return ECORE_INVAL;
3582         }
3583
3584         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
3585
3586         return ECORE_SUCCESS;
3587 }
3588
3589 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
3590                                               struct ecore_ptt *p_ptt,
3591                                               u8 *p_filter)
3592 {
3593         u32 high, low, en;
3594         int i;
3595
3596         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3597                 return ECORE_SUCCESS;
3598
3599         high = p_filter[1] | (p_filter[0] << 8);
3600         low = p_filter[5] | (p_filter[4] << 8) |
3601             (p_filter[3] << 16) | (p_filter[2] << 24);
3602
3603         /* Find a free entry and utilize it */
3604         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3605                 en = ecore_rd(p_hwfn, p_ptt,
3606                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3607                 if (en)
3608                         continue;
3609                 ecore_wr(p_hwfn, p_ptt,
3610                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3611                          2 * i * sizeof(u32), low);
3612                 ecore_wr(p_hwfn, p_ptt,
3613                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3614                          (2 * i + 1) * sizeof(u32), high);
3615                 ecore_wr(p_hwfn, p_ptt,
3616                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3617                 ecore_wr(p_hwfn, p_ptt,
3618                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3619                          i * sizeof(u32), 0);
3620                 ecore_wr(p_hwfn, p_ptt,
3621                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3622                 break;
3623         }
3624         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3625                 DP_NOTICE(p_hwfn, false,
3626                           "Failed to find an empty LLH filter to utilize\n");
3627                 return ECORE_INVAL;
3628         }
3629
3630         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3631                    "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
3632                    p_filter[0], p_filter[1], p_filter[2],
3633                    p_filter[3], p_filter[4], p_filter[5], i);
3634
3635         return ECORE_SUCCESS;
3636 }
3637
3638 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
3639                                  struct ecore_ptt *p_ptt, u8 *p_filter)
3640 {
3641         u32 high, low;
3642         int i;
3643
3644         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3645                 return;
3646
3647         high = p_filter[1] | (p_filter[0] << 8);
3648         low = p_filter[5] | (p_filter[4] << 8) |
3649             (p_filter[3] << 16) | (p_filter[2] << 24);
3650
3651         /* Find the entry and clean it */
3652         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3653                 if (ecore_rd(p_hwfn, p_ptt,
3654                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3655                              2 * i * sizeof(u32)) != low)
3656                         continue;
3657                 if (ecore_rd(p_hwfn, p_ptt,
3658                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3659                              (2 * i + 1) * sizeof(u32)) != high)
3660                         continue;
3661
3662                 ecore_wr(p_hwfn, p_ptt,
3663                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3664                 ecore_wr(p_hwfn, p_ptt,
3665                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3666                          2 * i * sizeof(u32), 0);
3667                 ecore_wr(p_hwfn, p_ptt,
3668                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3669                          (2 * i + 1) * sizeof(u32), 0);
3670                 break;
3671         }
3672         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3673                 DP_NOTICE(p_hwfn, false,
3674                           "Tried to remove a non-configured filter\n");
3675 }
3676
3677 enum _ecore_status_t
3678 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
3679                               struct ecore_ptt *p_ptt,
3680                               u16 source_port_or_eth_type,
3681                               u16 dest_port,
3682                               enum ecore_llh_port_filter_type_t type)
3683 {
3684         u32 high, low, en;
3685         int i;
3686
3687         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3688                 return ECORE_SUCCESS;
3689
3690         high = 0;
3691         low = 0;
3692         switch (type) {
3693         case ECORE_LLH_FILTER_ETHERTYPE:
3694                 high = source_port_or_eth_type;
3695                 break;
3696         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3697         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3698                 low = source_port_or_eth_type << 16;
3699                 break;
3700         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3701         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3702                 low = dest_port;
3703                 break;
3704         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3705         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3706                 low = (source_port_or_eth_type << 16) | dest_port;
3707                 break;
3708         default:
3709                 DP_NOTICE(p_hwfn, true,
3710                           "Non valid LLH protocol filter type %d\n", type);
3711                 return ECORE_INVAL;
3712         }
3713         /* Find a free entry and utilize it */
3714         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3715                 en = ecore_rd(p_hwfn, p_ptt,
3716                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3717                 if (en)
3718                         continue;
3719                 ecore_wr(p_hwfn, p_ptt,
3720                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3721                          2 * i * sizeof(u32), low);
3722                 ecore_wr(p_hwfn, p_ptt,
3723                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3724                          (2 * i + 1) * sizeof(u32), high);
3725                 ecore_wr(p_hwfn, p_ptt,
3726                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3727                 ecore_wr(p_hwfn, p_ptt,
3728                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3729                          i * sizeof(u32), 1 << type);
3730                 ecore_wr(p_hwfn, p_ptt,
3731                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3732                 break;
3733         }
3734         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3735                 DP_NOTICE(p_hwfn, false,
3736                           "Failed to find an empty LLH filter to utilize\n");
3737                 return ECORE_NORESOURCES;
3738         }
3739         switch (type) {
3740         case ECORE_LLH_FILTER_ETHERTYPE:
3741                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3742                            "ETH type %x is added at %d\n",
3743                            source_port_or_eth_type, i);
3744                 break;
3745         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3746                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3747                            "TCP src port %x is added at %d\n",
3748                            source_port_or_eth_type, i);
3749                 break;
3750         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3751                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3752                            "UDP src port %x is added at %d\n",
3753                            source_port_or_eth_type, i);
3754                 break;
3755         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3756                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3757                            "TCP dst port %x is added at %d\n", dest_port, i);
3758                 break;
3759         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3760                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3761                            "UDP dst port %x is added at %d\n", dest_port, i);
3762                 break;
3763         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3764                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3765                            "TCP src/dst ports %x/%x are added at %d\n",
3766                            source_port_or_eth_type, dest_port, i);
3767                 break;
3768         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3769                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3770                            "UDP src/dst ports %x/%x are added at %d\n",
3771                            source_port_or_eth_type, dest_port, i);
3772                 break;
3773         }
3774         return ECORE_SUCCESS;
3775 }
3776
3777 void
3778 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
3779                                  struct ecore_ptt *p_ptt,
3780                                  u16 source_port_or_eth_type,
3781                                  u16 dest_port,
3782                                  enum ecore_llh_port_filter_type_t type)
3783 {
3784         u32 high, low;
3785         int i;
3786
3787         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3788                 return;
3789
3790         high = 0;
3791         low = 0;
3792         switch (type) {
3793         case ECORE_LLH_FILTER_ETHERTYPE:
3794                 high = source_port_or_eth_type;
3795                 break;
3796         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3797         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3798                 low = source_port_or_eth_type << 16;
3799                 break;
3800         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3801         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3802                 low = dest_port;
3803                 break;
3804         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3805         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3806                 low = (source_port_or_eth_type << 16) | dest_port;
3807                 break;
3808         default:
3809                 DP_NOTICE(p_hwfn, true,
3810                           "Non valid LLH protocol filter type %d\n", type);
3811                 return;
3812         }
3813
3814         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3815                 if (!ecore_rd(p_hwfn, p_ptt,
3816                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3817                         continue;
3818                 if (!ecore_rd(p_hwfn, p_ptt,
3819                               NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3820                         continue;
3821                 if (!(ecore_rd(p_hwfn, p_ptt,
3822                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3823                                i * sizeof(u32)) & (1 << type)))
3824                         continue;
3825                 if (ecore_rd(p_hwfn, p_ptt,
3826                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3827                              2 * i * sizeof(u32)) != low)
3828                         continue;
3829                 if (ecore_rd(p_hwfn, p_ptt,
3830                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3831                              (2 * i + 1) * sizeof(u32)) != high)
3832                         continue;
3833
3834                 ecore_wr(p_hwfn, p_ptt,
3835                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3836                 ecore_wr(p_hwfn, p_ptt,
3837                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3838                 ecore_wr(p_hwfn, p_ptt,
3839                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3840                          i * sizeof(u32), 0);
3841                 ecore_wr(p_hwfn, p_ptt,
3842                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3843                          2 * i * sizeof(u32), 0);
3844                 ecore_wr(p_hwfn, p_ptt,
3845                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3846                          (2 * i + 1) * sizeof(u32), 0);
3847                 break;
3848         }
3849
3850         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3851                 DP_NOTICE(p_hwfn, false,
3852                           "Tried to remove a non-configured filter\n");
3853 }
3854
3855 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
3856                                  struct ecore_ptt *p_ptt)
3857 {
3858         int i;
3859
3860         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3861                 return;
3862
3863         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3864                 ecore_wr(p_hwfn, p_ptt,
3865                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3866                 ecore_wr(p_hwfn, p_ptt,
3867                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3868                          2 * i * sizeof(u32), 0);
3869                 ecore_wr(p_hwfn, p_ptt,
3870                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3871                          (2 * i + 1) * sizeof(u32), 0);
3872         }
3873 }
3874
3875 enum _ecore_status_t
3876 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
3877                                   struct ecore_ptt *p_ptt)
3878 {
3879         if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
3880                 ecore_wr(p_hwfn, p_ptt,
3881                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
3882                          1 << p_hwfn->abs_pf_id / 2);
3883                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
3884                 return ECORE_SUCCESS;
3885         }
3886
3887         DP_NOTICE(p_hwfn, false,
3888                   "This function can't be set as default\n");
3889         return ECORE_INVAL;
3890 }
3891
3892 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
3893                                                struct ecore_ptt *p_ptt,
3894                                                u32 hw_addr, void *p_eth_qzone,
3895                                                osal_size_t eth_qzone_size,
3896                                                u8 timeset)
3897 {
3898         struct coalescing_timeset *p_coal_timeset;
3899
3900         if (IS_VF(p_hwfn->p_dev)) {
3901                 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n");
3902                 return ECORE_INVAL;
3903         }
3904
3905         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
3906                 DP_NOTICE(p_hwfn, true,
3907                           "Coalescing configuration not enabled\n");
3908                 return ECORE_INVAL;
3909         }
3910
3911         p_coal_timeset = p_eth_qzone;
3912         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
3913         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3914         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3915         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3916
3917         return ECORE_SUCCESS;
3918 }
3919
3920 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
3921                                             struct ecore_ptt *p_ptt,
3922                                             u16 coalesce, u16 qid, u16 sb_id)
3923 {
3924         struct ustorm_eth_queue_zone eth_qzone;
3925         u8 timeset, timer_res;
3926         u16 fw_qid = 0;
3927         u32 address;
3928         enum _ecore_status_t rc;
3929
3930         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3931         if (coalesce <= 0x7F) {
3932                 timer_res = 0;
3933         } else if (coalesce <= 0xFF) {
3934                 timer_res = 1;
3935         } else if (coalesce <= 0x1FF) {
3936                 timer_res = 2;
3937         } else {
3938                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3939                 return ECORE_INVAL;
3940         }
3941         timeset = (u8)(coalesce >> timer_res);
3942
3943         rc = ecore_fw_l2_queue(p_hwfn, qid, &fw_qid);
3944         if (rc != ECORE_SUCCESS)
3945                 return rc;
3946
3947         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
3948         if (rc != ECORE_SUCCESS)
3949                 goto out;
3950
3951         address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3952
3953         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3954                                 sizeof(struct ustorm_eth_queue_zone), timeset);
3955         if (rc != ECORE_SUCCESS)
3956                 goto out;
3957
3958         p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
3959  out:
3960         return rc;
3961 }
3962
3963 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
3964                                             struct ecore_ptt *p_ptt,
3965                                             u16 coalesce, u16 qid, u16 sb_id)
3966 {
3967         struct xstorm_eth_queue_zone eth_qzone;
3968         u8 timeset, timer_res;
3969         u16 fw_qid = 0;
3970         u32 address;
3971         enum _ecore_status_t rc;
3972
3973         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3974         if (coalesce <= 0x7F) {
3975                 timer_res = 0;
3976         } else if (coalesce <= 0xFF) {
3977                 timer_res = 1;
3978         } else if (coalesce <= 0x1FF) {
3979                 timer_res = 2;
3980         } else {
3981                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3982                 return ECORE_INVAL;
3983         }
3984
3985         timeset = (u8)(coalesce >> timer_res);
3986
3987         rc = ecore_fw_l2_queue(p_hwfn, qid, &fw_qid);
3988         if (rc != ECORE_SUCCESS)
3989                 return rc;
3990
3991         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
3992         if (rc != ECORE_SUCCESS)
3993                 goto out;
3994
3995         address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3996
3997         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3998                                 sizeof(struct xstorm_eth_queue_zone), timeset);
3999         if (rc != ECORE_SUCCESS)
4000                 goto out;
4001
4002         p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
4003  out:
4004         return rc;
4005 }
4006
4007 /* Calculate final WFQ values for all vports and configure it.
4008  * After this configuration each vport must have
4009  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
4010  */
4011 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4012                                                struct ecore_ptt *p_ptt,
4013                                                u32 min_pf_rate)
4014 {
4015         struct init_qm_vport_params *vport_params;
4016         int i;
4017
4018         vport_params = p_hwfn->qm_info.qm_vport_params;
4019
4020         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4021                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4022
4023                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
4024                     min_pf_rate;
4025                 ecore_init_vport_wfq(p_hwfn, p_ptt,
4026                                      vport_params[i].first_tx_pq_id,
4027                                      vport_params[i].vport_wfq);
4028         }
4029 }
4030
4031 static void
4032 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
4033 {
4034         int i;
4035
4036         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4037                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4038 }
4039
4040 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4041                                              struct ecore_ptt *p_ptt,
4042                                              u32 min_pf_rate)
4043 {
4044         struct init_qm_vport_params *vport_params;
4045         int i;
4046
4047         vport_params = p_hwfn->qm_info.qm_vport_params;
4048
4049         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4050                 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
4051                 ecore_init_vport_wfq(p_hwfn, p_ptt,
4052                                      vport_params[i].first_tx_pq_id,
4053                                      vport_params[i].vport_wfq);
4054         }
4055 }
4056
4057 /* This function performs several validations for WFQ
4058  * configuration and required min rate for a given vport
4059  * 1. req_rate must be greater than one percent of min_pf_rate.
4060  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4061  *    rates to get less than one percent of min_pf_rate.
4062  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4063  */
4064 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
4065                                                  u16 vport_id, u32 req_rate,
4066                                                  u32 min_pf_rate)
4067 {
4068         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4069         int non_requested_count = 0, req_count = 0, i, num_vports;
4070
4071         num_vports = p_hwfn->qm_info.num_vports;
4072
4073 /* Accounting for the vports which are configured for WFQ explicitly */
4074
4075         for (i = 0; i < num_vports; i++) {
4076                 u32 tmp_speed;
4077
4078                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
4079                         req_count++;
4080                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4081                         total_req_min_rate += tmp_speed;
4082                 }
4083         }
4084
4085         /* Include current vport data as well */
4086         req_count++;
4087         total_req_min_rate += req_rate;
4088         non_requested_count = num_vports - req_count;
4089
4090         /* validate possible error cases */
4091         if (req_rate > min_pf_rate) {
4092                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4093                            "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4094                            vport_id, req_rate, min_pf_rate);
4095                 return ECORE_INVAL;
4096         }
4097
4098         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
4099                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4100                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4101                            vport_id, req_rate, min_pf_rate);
4102                 return ECORE_INVAL;
4103         }
4104
4105         /* TBD - for number of vports greater than 100 */
4106         if (num_vports > ECORE_WFQ_UNIT) {
4107                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4108                            "Number of vports is greater than %d\n",
4109                            ECORE_WFQ_UNIT);
4110                 return ECORE_INVAL;
4111         }
4112
4113         if (total_req_min_rate > min_pf_rate) {
4114                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4115                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4116                            total_req_min_rate, min_pf_rate);
4117                 return ECORE_INVAL;
4118         }
4119
4120         /* Data left for non requested vports */
4121         total_left_rate = min_pf_rate - total_req_min_rate;
4122         left_rate_per_vp = total_left_rate / non_requested_count;
4123
4124         /* validate if non requested get < 1% of min bw */
4125         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4126                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4127                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4128                            left_rate_per_vp, min_pf_rate);
4129                 return ECORE_INVAL;
4130         }
4131
4132         /* now req_rate for given vport passes all scenarios.
4133          * assign final wfq rates to all vports.
4134          */
4135         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4136         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4137
4138         for (i = 0; i < num_vports; i++) {
4139                 if (p_hwfn->qm_info.wfq_data[i].configured)
4140                         continue;
4141
4142                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4143         }
4144
4145         return ECORE_SUCCESS;
4146 }
4147
4148 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4149                                        struct ecore_ptt *p_ptt,
4150                                        u16 vp_id, u32 rate)
4151 {
4152         struct ecore_mcp_link_state *p_link;
4153         int rc = ECORE_SUCCESS;
4154
4155         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4156
4157         if (!p_link->min_pf_rate) {
4158                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4159                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4160                 return rc;
4161         }
4162
4163         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4164
4165         if (rc == ECORE_SUCCESS)
4166                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4167                                                    p_link->min_pf_rate);
4168         else
4169                 DP_NOTICE(p_hwfn, false,
4170                           "Validation failed while configuring min rate\n");
4171
4172         return rc;
4173 }
4174
4175 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4176                                                    struct ecore_ptt *p_ptt,
4177                                                    u32 min_pf_rate)
4178 {
4179         bool use_wfq = false;
4180         int rc = ECORE_SUCCESS;
4181         u16 i;
4182
4183         /* Validate all pre configured vports for wfq */
4184         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4185                 u32 rate;
4186
4187                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4188                         continue;
4189
4190                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4191                 use_wfq = true;
4192
4193                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4194                 if (rc != ECORE_SUCCESS) {
4195                         DP_NOTICE(p_hwfn, false,
4196                                   "WFQ validation failed while configuring min rate\n");
4197                         break;
4198                 }
4199         }
4200
4201         if (rc == ECORE_SUCCESS && use_wfq)
4202                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4203         else
4204                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4205
4206         return rc;
4207 }
4208
4209 /* Main API for ecore clients to configure vport min rate.
4210  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4211  * rate - Speed in Mbps needs to be assigned to a given vport.
4212  */
4213 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4214 {
4215         int i, rc = ECORE_INVAL;
4216
4217         /* TBD - for multiple hardware functions - that is 100 gig */
4218         if (p_dev->num_hwfns > 1) {
4219                 DP_NOTICE(p_dev, false,
4220                           "WFQ configuration is not supported for this device\n");
4221                 return rc;
4222         }
4223
4224         for_each_hwfn(p_dev, i) {
4225                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4226                 struct ecore_ptt *p_ptt;
4227
4228                 p_ptt = ecore_ptt_acquire(p_hwfn);
4229                 if (!p_ptt)
4230                         return ECORE_TIMEOUT;
4231
4232                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4233
4234                 if (rc != ECORE_SUCCESS) {
4235                         ecore_ptt_release(p_hwfn, p_ptt);
4236                         return rc;
4237                 }
4238
4239                 ecore_ptt_release(p_hwfn, p_ptt);
4240         }
4241
4242         return rc;
4243 }
4244
4245 /* API to configure WFQ from mcp link change */
4246 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4247                                            u32 min_pf_rate)
4248 {
4249         int i;
4250
4251         /* TBD - for multiple hardware functions - that is 100 gig */
4252         if (p_dev->num_hwfns > 1) {
4253                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4254                            "WFQ configuration is not supported for this device\n");
4255                 return;
4256         }
4257
4258         for_each_hwfn(p_dev, i) {
4259                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4260
4261                 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4262                                                         p_hwfn->p_dpc_ptt,
4263                                                         min_pf_rate);
4264         }
4265 }
4266
4267 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4268                                        struct ecore_ptt *p_ptt,
4269                                        struct ecore_mcp_link_state *p_link,
4270                                        u8 max_bw)
4271 {
4272         int rc = ECORE_SUCCESS;
4273
4274         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4275
4276         if (!p_link->line_speed && (max_bw != 100))
4277                 return rc;
4278
4279         p_link->speed = (p_link->line_speed * max_bw) / 100;
4280         p_hwfn->qm_info.pf_rl = p_link->speed;
4281
4282         /* Since the limiter also affects Tx-switched traffic, we don't want it
4283          * to limit such traffic in case there's no actual limit.
4284          * In that case, set limit to imaginary high boundary.
4285          */
4286         if (max_bw == 100)
4287                 p_hwfn->qm_info.pf_rl = 100000;
4288
4289         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4290                               p_hwfn->qm_info.pf_rl);
4291
4292         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4293                    "Configured MAX bandwidth to be %08x Mb/sec\n",
4294                    p_link->speed);
4295
4296         return rc;
4297 }
4298
4299 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4300 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4301 {
4302         int i, rc = ECORE_INVAL;
4303
4304         if (max_bw < 1 || max_bw > 100) {
4305                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4306                 return rc;
4307         }
4308
4309         for_each_hwfn(p_dev, i) {
4310                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4311                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4312                 struct ecore_mcp_link_state *p_link;
4313                 struct ecore_ptt *p_ptt;
4314
4315                 p_link = &p_lead->mcp_info->link_output;
4316
4317                 p_ptt = ecore_ptt_acquire(p_hwfn);
4318                 if (!p_ptt)
4319                         return ECORE_TIMEOUT;
4320
4321                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4322                                                         p_link, max_bw);
4323
4324                 ecore_ptt_release(p_hwfn, p_ptt);
4325
4326                 if (rc != ECORE_SUCCESS)
4327                         break;
4328         }
4329
4330         return rc;
4331 }
4332
4333 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4334                                        struct ecore_ptt *p_ptt,
4335                                        struct ecore_mcp_link_state *p_link,
4336                                        u8 min_bw)
4337 {
4338         int rc = ECORE_SUCCESS;
4339
4340         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4341         p_hwfn->qm_info.pf_wfq = min_bw;
4342
4343         if (!p_link->line_speed)
4344                 return rc;
4345
4346         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4347
4348         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4349
4350         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4351                    "Configured MIN bandwidth to be %d Mb/sec\n",
4352                    p_link->min_pf_rate);
4353
4354         return rc;
4355 }
4356
4357 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4358 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4359 {
4360         int i, rc = ECORE_INVAL;
4361
4362         if (min_bw < 1 || min_bw > 100) {
4363                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4364                 return rc;
4365         }
4366
4367         for_each_hwfn(p_dev, i) {
4368                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4369                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4370                 struct ecore_mcp_link_state *p_link;
4371                 struct ecore_ptt *p_ptt;
4372
4373                 p_link = &p_lead->mcp_info->link_output;
4374
4375                 p_ptt = ecore_ptt_acquire(p_hwfn);
4376                 if (!p_ptt)
4377                         return ECORE_TIMEOUT;
4378
4379                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4380                                                         p_link, min_bw);
4381                 if (rc != ECORE_SUCCESS) {
4382                         ecore_ptt_release(p_hwfn, p_ptt);
4383                         return rc;
4384                 }
4385
4386                 if (p_link->min_pf_rate) {
4387                         u32 min_rate = p_link->min_pf_rate;
4388
4389                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4390                                                                      p_ptt,
4391                                                                      min_rate);
4392                 }
4393
4394                 ecore_ptt_release(p_hwfn, p_ptt);
4395         }
4396
4397         return rc;
4398 }
4399
4400 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4401 {
4402         struct ecore_mcp_link_state *p_link;
4403
4404         p_link = &p_hwfn->mcp_info->link_output;
4405
4406         if (p_link->min_pf_rate)
4407                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4408                                                  p_link->min_pf_rate);
4409
4410         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4411                     sizeof(*p_hwfn->qm_info.wfq_data) *
4412                     p_hwfn->qm_info.num_vports);
4413 }
4414
4415 int ecore_device_num_engines(struct ecore_dev *p_dev)
4416 {
4417         return ECORE_IS_BB(p_dev) ? 2 : 1;
4418 }
4419
4420 int ecore_device_num_ports(struct ecore_dev *p_dev)
4421 {
4422         /* in CMT always only one port */
4423         if (p_dev->num_hwfns > 1)
4424                 return 1;
4425
4426         return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
4427 }
4428
4429 void ecore_set_fw_mac_addr(__le16 *fw_msb,
4430                           __le16 *fw_mid,
4431                           __le16 *fw_lsb,
4432                           u8 *mac)
4433 {
4434         ((u8 *)fw_msb)[0] = mac[1];
4435         ((u8 *)fw_msb)[1] = mac[0];
4436         ((u8 *)fw_mid)[0] = mac[3];
4437         ((u8 *)fw_mid)[1] = mac[2];
4438         ((u8 *)fw_lsb)[0] = mac[5];
4439         ((u8 *)fw_lsb)[1] = mac[4];
4440 }