2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_gtt_reg_addr.h"
13 #include "ecore_chain.h"
14 #include "ecore_status.h"
16 #include "ecore_rt_defs.h"
17 #include "ecore_init_ops.h"
18 #include "ecore_int.h"
19 #include "ecore_cxt.h"
20 #include "ecore_spq.h"
21 #include "ecore_init_fw_funcs.h"
22 #include "ecore_sp_commands.h"
23 #include "ecore_dev_api.h"
24 #include "ecore_sriov.h"
26 #include "ecore_mcp.h"
27 #include "ecore_hw_defs.h"
28 #include "mcp_public.h"
29 #include "ecore_iro.h"
31 #include "ecore_dev_api.h"
32 #include "ecore_dcbx.h"
34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
35 * registers involved are not split and thus configuration is a race where
36 * some of the PFs configuration might be lost.
37 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
38 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
39 * there's more than a single compiled ecore component in system].
41 static osal_spinlock_t qm_lock;
42 static bool qm_lock_init;
45 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to
46 * load the driver. The number was
51 #define ECORE_MIN_PWM_REGION ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
54 BAR_ID_0, /* used for GRC */
55 BAR_ID_1 /* Used for doorbells */
58 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
60 u32 bar_reg = (bar_id == BAR_ID_0 ?
61 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
64 if (IS_VF(p_hwfn->p_dev)) {
65 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
66 * read from actual register, but we're currently not using
67 * it for actual doorbelling.
72 val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
74 /* The above registers were updated in the past only in CMT mode. Since
75 * they were found to be useful MFW started updating them from 8.7.7.0.
76 * In older MFW versions they are set to 0 which means disabled.
79 if (p_hwfn->p_dev->num_hwfns > 1) {
80 DP_NOTICE(p_hwfn, false,
81 "BAR size not configured. Assuming BAR size");
82 DP_NOTICE(p_hwfn, false,
83 "of 256kB for GRC and 512kB for DB\n");
84 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
86 DP_NOTICE(p_hwfn, false,
87 "BAR size not configured. Assuming BAR size");
88 DP_NOTICE(p_hwfn, false,
89 "of 512kB for GRC and 512kB for DB\n");
94 return 1 << (val + 15);
97 void ecore_init_dp(struct ecore_dev *p_dev,
98 u32 dp_module, u8 dp_level, void *dp_ctx)
102 p_dev->dp_level = dp_level;
103 p_dev->dp_module = dp_module;
104 p_dev->dp_ctx = dp_ctx;
105 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
106 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
108 p_hwfn->dp_level = dp_level;
109 p_hwfn->dp_module = dp_module;
110 p_hwfn->dp_ctx = dp_ctx;
114 void ecore_init_struct(struct ecore_dev *p_dev)
118 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
119 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
121 p_hwfn->p_dev = p_dev;
123 p_hwfn->b_active = false;
125 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
126 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
129 /* hwfn 0 is always active */
130 p_dev->hwfns[0].b_active = true;
132 /* set the default cache alignment to 128 (may be overridden later) */
133 p_dev->cache_shift = 7;
136 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
138 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
140 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
141 qm_info->qm_pq_params = OSAL_NULL;
142 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
143 qm_info->qm_vport_params = OSAL_NULL;
144 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
145 qm_info->qm_port_params = OSAL_NULL;
146 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
147 qm_info->wfq_data = OSAL_NULL;
150 void ecore_resc_free(struct ecore_dev *p_dev)
157 OSAL_FREE(p_dev, p_dev->fw_data);
158 p_dev->fw_data = OSAL_NULL;
160 OSAL_FREE(p_dev, p_dev->reset_stats);
162 for_each_hwfn(p_dev, i) {
163 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
165 OSAL_FREE(p_dev, p_hwfn->p_tx_cids);
166 p_hwfn->p_tx_cids = OSAL_NULL;
167 OSAL_FREE(p_dev, p_hwfn->p_rx_cids);
168 p_hwfn->p_rx_cids = OSAL_NULL;
171 for_each_hwfn(p_dev, i) {
172 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
174 ecore_cxt_mngr_free(p_hwfn);
175 ecore_qm_info_free(p_hwfn);
176 ecore_spq_free(p_hwfn);
177 ecore_eq_free(p_hwfn, p_hwfn->p_eq);
178 ecore_consq_free(p_hwfn, p_hwfn->p_consq);
179 ecore_int_free(p_hwfn);
180 #ifdef CONFIG_ECORE_LL2
181 ecore_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
183 ecore_iov_free(p_hwfn);
184 ecore_dmae_info_free(p_hwfn);
185 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
186 /* @@@TBD Flush work-queue ? */
190 static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn,
193 u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue;
194 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
195 struct init_qm_port_params *p_qm_port;
196 bool init_rdma_offload_pq = false;
197 bool init_pure_ack_pq = false;
198 bool init_ooo_pq = false;
199 u16 num_pqs, protocol_pqs;
205 /* @TMP - saving the existing min/max bw config before resetting the
206 * qm_info to restore them.
208 pf_rl = qm_info->pf_rl;
209 pf_wfq = qm_info->pf_wfq;
211 #ifdef CONFIG_ECORE_SRIOV
212 if (p_hwfn->p_dev->p_iov_info)
213 num_vfs = p_hwfn->p_dev->p_iov_info->total_vfs;
215 OSAL_MEM_ZERO(qm_info, sizeof(*qm_info));
218 /* @TMP - Don't allocate QM queues for VFs on emulation */
219 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
220 DP_NOTICE(p_hwfn, false,
221 "Emulation - skip configuring QM queues for VFs\n");
226 /* ethernet PFs require a pq per tc. Even if only a subset of the TCs
227 * active, we want physical queues allocated for all of them, since we
228 * don't have a good recycle flow. Non ethernet PFs require only a
229 * single physical queue.
231 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE ||
232 p_hwfn->hw_info.personality == ECORE_PCI_IWARP ||
233 p_hwfn->hw_info.personality == ECORE_PCI_ETH)
234 protocol_pqs = p_hwfn->hw_info.num_hw_tc;
238 num_pqs = protocol_pqs + num_vfs + 1; /* The '1' is for pure-LB */
239 num_vports = (u8)RESC_NUM(p_hwfn, ECORE_VPORT);
241 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
242 num_pqs++; /* for RoCE queue */
243 init_rdma_offload_pq = true;
244 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn) {
245 /* Due to FW assumption that rl==vport, we limit the
246 * number of rate limiters by the minimum between its
247 * allocated number and the allocated number of vports.
248 * Another limitation is the number of supported qps
249 * with rate limiters in FW.
252 (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
253 RESC_NUM(p_hwfn, ECORE_VPORT));
255 /* we subtract num_vfs because each one requires a rate
256 * limiter, and one default rate limiter.
258 if (num_pf_rls < num_vfs + 1) {
259 DP_ERR(p_hwfn, "No RL for DCQCN");
260 DP_ERR(p_hwfn, "[num_pf_rls %d num_vfs %d]\n",
261 num_pf_rls, num_vfs);
264 num_pf_rls -= num_vfs + 1;
267 num_pqs += num_pf_rls;
268 qm_info->num_pf_rls = (u8)num_pf_rls;
271 if (p_hwfn->hw_info.personality == ECORE_PCI_IWARP) {
272 num_pqs += 3; /* for iwarp queue / pure-ack / ooo */
273 init_rdma_offload_pq = true;
274 init_pure_ack_pq = true;
278 if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
279 num_pqs += 2; /* for iSCSI pure-ACK / OOO queue */
280 init_pure_ack_pq = true;
284 /* Sanity checking that setup requires legal number of resources */
285 if (num_pqs > RESC_NUM(p_hwfn, ECORE_PQ)) {
287 "Need too many Physical queues - 0x%04x avail %04x",
288 num_pqs, RESC_NUM(p_hwfn, ECORE_PQ));
292 /* PQs will be arranged as follows: First per-TC PQ, then pure-LB queue,
293 * then special queues (iSCSI pure-ACK / RoCE), then per-VF PQ.
295 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev,
296 b_sleepable ? GFP_KERNEL :
298 sizeof(struct init_qm_pq_params) *
300 if (!qm_info->qm_pq_params)
303 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev,
304 b_sleepable ? GFP_KERNEL :
307 init_qm_vport_params) *
309 if (!qm_info->qm_vport_params)
312 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev,
313 b_sleepable ? GFP_KERNEL :
315 sizeof(struct init_qm_port_params)
317 if (!qm_info->qm_port_params)
320 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev,
321 b_sleepable ? GFP_KERNEL :
323 sizeof(struct ecore_wfq_data) *
326 if (!qm_info->wfq_data)
329 vport_id = (u8)RESC_START(p_hwfn, ECORE_VPORT);
331 /* First init rate limited queues ( Due to RoCE assumption of
334 for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
335 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
336 qm_info->qm_pq_params[curr_queue].tc_id =
337 p_hwfn->hw_info.offload_tc;
338 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
339 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
343 for (i = 0; i < protocol_pqs; i++) {
344 struct init_qm_pq_params *params =
345 &qm_info->qm_pq_params[curr_queue++];
347 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE ||
348 p_hwfn->hw_info.personality == ECORE_PCI_IWARP ||
349 p_hwfn->hw_info.personality == ECORE_PCI_ETH) {
350 params->vport_id = vport_id;
352 /* Note: this assumes that if we had a configuration
353 * with N tcs and subsequently another configuration
354 * With Fewer TCs, the in flight traffic (in QM queues,
355 * in FW, from driver to FW) will still trickle out and
356 * not get "stuck" in the QM. This is determined by the
357 * NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ. Unused TCs are
358 * supposed to be cleared in this map, allowing traffic
359 * to flush out. If this is not the case, we would need
360 * to set the TC of unused queues to 0, and reconfigure
361 * QM every time num of TCs changes. Unused queues in
362 * this context would mean those intended for TCs where
363 * tc_id > hw_info.num_active_tcs.
365 params->wrr_group = 1; /* @@@TBD ECORE_WRR_MEDIUM */
367 params->vport_id = vport_id;
368 params->tc_id = p_hwfn->hw_info.offload_tc;
369 params->wrr_group = 1; /* @@@TBD ECORE_WRR_MEDIUM */
373 /* Then init pure-LB PQ */
374 qm_info->pure_lb_pq = curr_queue;
375 qm_info->qm_pq_params[curr_queue].vport_id =
376 (u8)RESC_START(p_hwfn, ECORE_VPORT);
377 qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
378 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
381 qm_info->offload_pq = 0; /* Already initialized for iSCSI/FCoE */
382 if (init_rdma_offload_pq) {
383 qm_info->offload_pq = curr_queue;
384 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
385 qm_info->qm_pq_params[curr_queue].tc_id =
386 p_hwfn->hw_info.offload_tc;
387 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
391 if (init_pure_ack_pq) {
392 qm_info->pure_ack_pq = curr_queue;
393 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
394 qm_info->qm_pq_params[curr_queue].tc_id =
395 p_hwfn->hw_info.offload_tc;
396 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
401 qm_info->ooo_pq = curr_queue;
402 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
403 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
404 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
408 /* Then init per-VF PQs */
409 vf_offset = curr_queue;
410 for (i = 0; i < num_vfs; i++) {
411 /* First vport is used by the PF */
412 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
413 /* @@@TBD VF Multi-cos */
414 qm_info->qm_pq_params[curr_queue].tc_id = 0;
415 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
416 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
420 qm_info->vf_queues_offset = vf_offset;
421 qm_info->num_pqs = num_pqs;
422 qm_info->num_vports = num_vports;
424 /* Initialize qm port parameters */
425 num_ports = p_hwfn->p_dev->num_ports_in_engines;
426 for (i = 0; i < num_ports; i++) {
427 p_qm_port = &qm_info->qm_port_params[i];
428 p_qm_port->active = 1;
429 /* @@@TMP - was NUM_OF_PHYS_TCS; Changed until dcbx will
433 p_qm_port->active_phys_tcs = 0xf;
435 p_qm_port->active_phys_tcs = 0x9f;
436 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
437 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
440 if (ECORE_IS_AH(p_hwfn->p_dev) && (num_ports == 4))
441 qm_info->max_phys_tcs_per_port = NUM_PHYS_TCS_4PORT_K2;
443 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
445 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
447 qm_info->num_vf_pqs = num_vfs;
448 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
450 for (i = 0; i < qm_info->num_vports; i++)
451 qm_info->qm_vport_params[i].vport_wfq = 1;
453 qm_info->vport_rl_en = 1;
454 qm_info->vport_wfq_en = 1;
455 qm_info->pf_rl = pf_rl;
456 qm_info->pf_wfq = pf_wfq;
458 return ECORE_SUCCESS;
461 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
462 ecore_qm_info_free(p_hwfn);
466 /* This function reconfigures the QM pf on the fly.
467 * For this purpose we:
468 * 1. reconfigure the QM database
469 * 2. set new values to runtime arrat
470 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
471 * 4. activate init tool in QM_PF stage
472 * 5. send an sdm_qm_cmd through rbc interface to release the QM
474 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
475 struct ecore_ptt *p_ptt)
477 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
479 enum _ecore_status_t rc;
481 /* qm_info is allocated in ecore_init_qm_info() which is already called
482 * from ecore_resc_alloc() or previous call of ecore_qm_reconf().
483 * The allocated size may change each init, so we free it before next
486 ecore_qm_info_free(p_hwfn);
488 /* initialize ecore's qm data structure */
489 rc = ecore_init_qm_info(p_hwfn, false);
490 if (rc != ECORE_SUCCESS)
493 /* stop PF's qm queues */
494 OSAL_SPIN_LOCK(&qm_lock);
495 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
496 qm_info->start_pq, qm_info->num_pqs);
497 OSAL_SPIN_UNLOCK(&qm_lock);
501 /* clear the QM_PF runtime phase leftovers from previous init */
502 ecore_init_clear_rt_data(p_hwfn);
504 /* prepare QM portion of runtime array */
505 ecore_qm_init_pf(p_hwfn);
507 /* activate init tool on runtime array */
508 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
509 p_hwfn->hw_info.hw_mode);
510 if (rc != ECORE_SUCCESS)
513 /* start PF's qm queues */
514 OSAL_SPIN_LOCK(&qm_lock);
515 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
516 qm_info->start_pq, qm_info->num_pqs);
517 OSAL_SPIN_UNLOCK(&qm_lock);
521 return ECORE_SUCCESS;
524 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
526 struct ecore_consq *p_consq;
527 struct ecore_eq *p_eq;
528 #ifdef CONFIG_ECORE_LL2
529 struct ecore_ll2_info *p_ll2_info;
531 enum _ecore_status_t rc = ECORE_SUCCESS;
537 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
538 sizeof(*p_dev->fw_data));
542 /* Allocate Memory for the Queue->CID mapping */
543 for_each_hwfn(p_dev, i) {
544 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
545 u32 num_tx_conns = RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
546 int tx_size, rx_size;
548 /* @@@TMP - resc management, change to actual required size */
549 if (p_hwfn->pf_params.eth_pf_params.num_cons > num_tx_conns)
550 num_tx_conns = p_hwfn->pf_params.eth_pf_params.num_cons;
551 tx_size = sizeof(struct ecore_hw_cid_data) * num_tx_conns;
552 rx_size = sizeof(struct ecore_hw_cid_data) *
553 RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
555 p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
557 if (!p_hwfn->p_tx_cids) {
558 DP_NOTICE(p_hwfn, true,
559 "Failed to allocate memory for Tx Cids\n");
563 p_hwfn->p_rx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
565 if (!p_hwfn->p_rx_cids) {
566 DP_NOTICE(p_hwfn, true,
567 "Failed to allocate memory for Rx Cids\n");
572 for_each_hwfn(p_dev, i) {
573 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
574 u32 n_eqes, num_cons;
576 /* First allocate the context manager structure */
577 rc = ecore_cxt_mngr_alloc(p_hwfn);
581 /* Set the HW cid/tid numbers (in the contest manager)
582 * Must be done prior to any further computations.
584 rc = ecore_cxt_set_pf_params(p_hwfn);
588 /* Prepare and process QM requirements */
589 rc = ecore_init_qm_info(p_hwfn, true);
593 /* Compute the ILT client partition */
594 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
598 /* CID map / ILT shadow table / T2
599 * The talbes sizes are determined by the computations above
601 rc = ecore_cxt_tables_alloc(p_hwfn);
605 /* SPQ, must follow ILT because initializes SPQ context */
606 rc = ecore_spq_alloc(p_hwfn);
610 /* SP status block allocation */
611 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
614 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
618 rc = ecore_iov_alloc(p_hwfn);
623 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
624 if ((p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) ||
625 (p_hwfn->hw_info.personality == ECORE_PCI_IWARP)) {
626 /* Calculate the EQ size
627 * ---------------------
628 * Each ICID may generate up to one event at a time i.e.
629 * the event must be handled/cleared before a new one
630 * can be generated. We calculate the sum of events per
631 * protocol and create an EQ deep enough to handle the
633 * - Core - according to SPQ.
634 * - RoCE - per QP there are a couple of ICIDs, one
635 * responder and one requester, each can
636 * generate an EQE => n_eqes_qp = 2 * n_qp.
637 * Each CQ can generate an EQE. There are 2 CQs
638 * per QP => n_eqes_cq = 2 * n_qp.
639 * Hence the RoCE total is 4 * n_qp or
641 * - ENet - There can be up to two events per VF. One
642 * for VF-PF channel and another for VF FLR
643 * initial cleanup. The number of VFs is
644 * bounded by MAX_NUM_VFS_BB, and is much
645 * smaller than RoCE's so we avoid exact
648 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
650 ecore_cxt_get_proto_cid_count(
656 num_cons = ecore_cxt_get_proto_cid_count(
661 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
662 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
664 ecore_cxt_get_proto_cid_count(p_hwfn,
665 PROTOCOLID_ISCSI, 0);
666 n_eqes += 2 * num_cons;
669 if (n_eqes > 0xFFFF) {
670 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
671 "The maximum of a u16 chain is 0x%x\n",
677 p_eq = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
682 p_consq = ecore_consq_alloc(p_hwfn);
685 p_hwfn->p_consq = p_consq;
687 #ifdef CONFIG_ECORE_LL2
688 if (p_hwfn->using_ll2) {
689 p_ll2_info = ecore_ll2_alloc(p_hwfn);
692 p_hwfn->p_ll2_info = p_ll2_info;
696 /* DMA info initialization */
697 rc = ecore_dmae_info_alloc(p_hwfn);
699 DP_NOTICE(p_hwfn, true,
700 "Failed to allocate memory for dmae_info structure\n");
704 /* DCBX initialization */
705 rc = ecore_dcbx_info_alloc(p_hwfn);
707 DP_NOTICE(p_hwfn, true,
708 "Failed to allocate memory for dcbx structure\n");
713 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
714 sizeof(*p_dev->reset_stats));
715 if (!p_dev->reset_stats) {
716 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
720 return ECORE_SUCCESS;
725 ecore_resc_free(p_dev);
729 void ecore_resc_setup(struct ecore_dev *p_dev)
736 for_each_hwfn(p_dev, i) {
737 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
739 ecore_cxt_mngr_setup(p_hwfn);
740 ecore_spq_setup(p_hwfn);
741 ecore_eq_setup(p_hwfn, p_hwfn->p_eq);
742 ecore_consq_setup(p_hwfn, p_hwfn->p_consq);
744 /* Read shadow of current MFW mailbox */
745 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
746 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
747 p_hwfn->mcp_info->mfw_mb_cur,
748 p_hwfn->mcp_info->mfw_mb_length);
750 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
752 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
753 #ifdef CONFIG_ECORE_LL2
754 if (p_hwfn->using_ll2)
755 ecore_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
760 #define FINAL_CLEANUP_POLL_CNT (100)
761 #define FINAL_CLEANUP_POLL_TIME (10)
762 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
763 struct ecore_ptt *p_ptt,
766 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
767 enum _ecore_status_t rc = ECORE_TIMEOUT;
770 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
771 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
772 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
773 return ECORE_SUCCESS;
777 addr = GTT_BAR0_MAP_REG_USDM_RAM +
778 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
783 command |= X_FINAL_CLEANUP_AGG_INT <<
784 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
785 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
786 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
787 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
789 /* Make sure notification is not set before initiating final cleanup */
791 if (REG_RD(p_hwfn, addr)) {
792 DP_NOTICE(p_hwfn, false,
793 "Unexpected; Found final cleanup notification");
794 DP_NOTICE(p_hwfn, false,
795 " before initiating final cleanup\n");
796 REG_WR(p_hwfn, addr, 0);
799 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
800 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
801 id, OSAL_CPU_TO_LE32(command));
803 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN,
804 OSAL_CPU_TO_LE32(command));
806 /* Poll until completion */
807 while (!REG_RD(p_hwfn, addr) && count--)
808 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
810 if (REG_RD(p_hwfn, addr))
813 DP_NOTICE(p_hwfn, true,
814 "Failed to receive FW final cleanup notification\n");
816 /* Cleanup afterwards */
817 REG_WR(p_hwfn, addr, 0);
822 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
826 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
827 hw_mode |= 1 << MODE_BB_B0;
828 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
829 hw_mode |= 1 << MODE_K2;
831 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
832 p_hwfn->p_dev->type);
836 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
837 switch (p_hwfn->p_dev->num_ports_in_engines) {
839 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
842 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
845 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
848 DP_NOTICE(p_hwfn, true,
849 "num_ports_in_engine = %d not supported\n",
850 p_hwfn->p_dev->num_ports_in_engines);
854 switch (p_hwfn->p_dev->mf_mode) {
855 case ECORE_MF_DEFAULT:
857 hw_mode |= 1 << MODE_MF_SI;
860 hw_mode |= 1 << MODE_MF_SD;
863 DP_NOTICE(p_hwfn, true,
864 "Unsupported MF mode, init as DEFAULT\n");
865 hw_mode |= 1 << MODE_MF_SI;
869 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
870 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
871 hw_mode |= 1 << MODE_FPGA;
873 if (p_hwfn->p_dev->b_is_emul_full)
874 hw_mode |= 1 << MODE_EMUL_FULL;
876 hw_mode |= 1 << MODE_EMUL_REDUCED;
880 hw_mode |= 1 << MODE_ASIC;
882 if (p_hwfn->p_dev->num_hwfns > 1)
883 hw_mode |= 1 << MODE_100G;
885 p_hwfn->hw_info.hw_mode = hw_mode;
887 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
888 "Configuring function for hw_mode: 0x%08x\n",
889 p_hwfn->hw_info.hw_mode);
891 return ECORE_SUCCESS;
895 /* MFW-replacement initializations for non-ASIC */
896 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
897 struct ecore_ptt *p_ptt)
902 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
905 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
907 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
908 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2, 0x3ffffff);
910 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
911 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
912 if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))
913 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0, 4);
915 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
916 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
917 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
918 (p_hwfn->p_dev->num_ports_in_engines >> 1));
920 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
921 p_hwfn->p_dev->num_ports_in_engines == 4 ? 0 : 3);
925 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
926 for (i = 0; i < 100; i++) {
928 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
932 DP_NOTICE(p_hwfn, true,
933 "RBC done failed to complete in PSWRQ2\n");
935 return ECORE_SUCCESS;
939 /* Init run time data for all PFs and their VFs on an engine.
940 * TBD - for VFs - Once we have parent PF info for each VF in
941 * shmem available as CAU requires knowledge of parent PF for each VF.
943 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
945 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
948 for_each_hwfn(p_dev, i) {
949 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
950 struct ecore_igu_info *p_igu_info;
951 struct ecore_igu_block *p_block;
952 struct cau_sb_entry sb_entry;
954 p_igu_info = p_hwfn->hw_info.p_igu_info;
956 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
958 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
963 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
964 p_block->function_id, 0, 0);
965 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
970 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
971 struct ecore_ptt *p_ptt,
974 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
975 struct ecore_dev *p_dev = p_hwfn->p_dev;
976 u8 vf_id, max_num_vfs;
979 enum _ecore_status_t rc = ECORE_SUCCESS;
981 ecore_init_cau_rt_data(p_dev);
983 /* Program GTT windows */
984 ecore_gtt_init(p_hwfn);
987 if (CHIP_REV_IS_EMUL(p_dev)) {
988 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
989 if (rc != ECORE_SUCCESS)
994 if (p_hwfn->mcp_info) {
995 if (p_hwfn->mcp_info->func_info.bandwidth_max)
996 qm_info->pf_rl_en = 1;
997 if (p_hwfn->mcp_info->func_info.bandwidth_min)
998 qm_info->pf_wfq_en = 1;
1001 ecore_qm_common_rt_init(p_hwfn,
1002 p_dev->num_ports_in_engines,
1003 qm_info->max_phys_tcs_per_port,
1004 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1005 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1006 qm_info->qm_port_params);
1008 ecore_cxt_hw_init_common(p_hwfn);
1010 /* Close gate from NIG to BRB/Storm; By default they are open, but
1011 * we close them to prevent NIG from passing data to reset blocks.
1012 * Should have been done in the ENGINE phase, but init-tool lacks
1013 * proper port-pretend capabilities.
1015 ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1016 ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1017 ecore_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
1018 ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1019 ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1020 ecore_port_unpretend(p_hwfn, p_ptt);
1022 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1023 if (rc != ECORE_SUCCESS)
1026 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1027 * need to decide with which value, maybe runtime
1029 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1030 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1032 if (ECORE_IS_BB(p_dev)) {
1033 /* Workaround clears ROCE search for all functions to prevent
1034 * involving non initialized function in processing ROCE packet.
1036 num_pfs = NUM_OF_ENG_PFS(p_dev);
1037 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1038 ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1039 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1040 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1042 /* pretend to original PF */
1043 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1046 /* Workaround for avoiding CCFC execution error when getting packets
1047 * with CRC errors, and allowing instead the invoking of the FW error
1049 * This is not done inside the init tool since it currently can't
1050 * perform a pretending to VFs.
1052 max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1053 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1054 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1055 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1056 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1057 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1058 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1059 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1061 /* pretend to original PF */
1062 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1068 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1069 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1071 #define PMEG_IF_BYTE_COUNT 8
1073 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1074 struct ecore_ptt *p_ptt,
1075 u32 addr, u64 data, u8 reg_type, u8 port)
1077 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1078 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1079 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) |
1080 (8 << PMEG_IF_BYTE_COUNT),
1081 (reg_type << 25) | (addr << 8) | port,
1082 (u32)((data >> 32) & 0xffffffff),
1083 (u32)(data & 0xffffffff));
1085 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0,
1086 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) &
1087 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1088 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB_B0,
1089 (reg_type << 25) | (addr << 8) | port);
1090 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
1092 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
1093 (data >> 32) & 0xffffffff);
1096 #define XLPORT_MODE_REG (0x20a)
1097 #define XLPORT_MAC_CONTROL (0x210)
1098 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1099 #define XLPORT_ENABLE_REG (0x20b)
1101 #define XLMAC_CTRL (0x600)
1102 #define XLMAC_MODE (0x601)
1103 #define XLMAC_RX_MAX_SIZE (0x608)
1104 #define XLMAC_TX_CTRL (0x604)
1105 #define XLMAC_PAUSE_CTRL (0x60d)
1106 #define XLMAC_PFC_CTRL (0x60e)
1108 static void ecore_emul_link_init_ah(struct ecore_hwfn *p_hwfn,
1109 struct ecore_ptt *p_ptt)
1111 u8 port = p_hwfn->port_id;
1112 u32 mac_base = NWM_REG_MAC0 + (port << 2) * NWM_REG_MAC0_SIZE;
1114 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2 + (port << 2),
1115 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_SHIFT) |
1116 (port << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_SHIFT)
1117 | (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_SHIFT));
1119 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE,
1120 1 << ETH_MAC_REG_XIF_MODE_XGMII_SHIFT);
1122 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH,
1123 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_SHIFT);
1125 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH,
1126 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_SHIFT);
1128 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS,
1129 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_SHIFT);
1131 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS,
1132 (0xA << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_SHIFT) |
1133 (8 << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_SHIFT));
1135 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG, 0xa853);
1138 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1139 struct ecore_ptt *p_ptt)
1141 u8 loopback = 0, port = p_hwfn->port_id * 2;
1143 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1145 if (ECORE_IS_AH(p_hwfn->p_dev)) {
1146 ecore_emul_link_init_ah(p_hwfn, p_ptt);
1150 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1151 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1153 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1154 /* XLMAC: SOFT RESET */
1155 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1156 /* XLMAC: Port Speed >= 10Gbps */
1157 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1158 /* XLMAC: Max Size */
1159 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1160 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1161 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1163 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1164 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1165 0x30ffffc000ULL, 0, port);
1166 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1167 port); /* XLMAC: TX_EN, RX_EN */
1168 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1169 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1170 0x1003 | (loopback << 2), 0, port);
1171 /* Enabled Parallel PFC interface */
1172 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1174 /* XLPORT port enable */
1175 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1178 static void ecore_link_init(struct ecore_hwfn *p_hwfn,
1179 struct ecore_ptt *p_ptt, u8 port)
1181 int port_offset = port ? 0x800 : 0;
1182 u32 xmac_rxctrl = 0;
1185 /* FIXME: move to common start */
1186 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1187 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
1189 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1190 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
1192 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1194 /* Set the number of ports on the Warp Core to 10G */
1195 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1197 /* Soft reset of XMAC */
1198 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1199 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1201 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1202 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1204 /* FIXME: move to common end */
1205 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1206 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE + port_offset, 0x20);
1208 /* Set Max packet size: initialize XMAC block register for port 0 */
1209 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE + port_offset, 0x2710);
1211 /* CRC append for Tx packets: init XMAC block register for port 1 */
1212 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO + port_offset, 0xC800);
1214 /* Enable TX and RX: initialize XMAC block register for port 1 */
1215 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL + port_offset,
1216 XMAC_REG_CTRL_TX_EN | XMAC_REG_CTRL_RX_EN);
1217 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset);
1218 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE;
1219 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset, xmac_rxctrl);
1223 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1224 struct ecore_ptt *p_ptt,
1227 enum _ecore_status_t rc = ECORE_SUCCESS;
1229 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1231 if (rc != ECORE_SUCCESS)
1234 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1235 return ECORE_SUCCESS;
1237 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1238 if (ECORE_IS_AH(p_hwfn->p_dev))
1239 return ECORE_SUCCESS;
1240 ecore_link_init(p_hwfn, p_ptt, p_hwfn->port_id);
1241 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1242 if (p_hwfn->p_dev->num_hwfns > 1) {
1243 /* Activate OPTE in CMT */
1246 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1248 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1249 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1250 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1251 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1252 ecore_wr(p_hwfn, p_ptt,
1253 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1254 ecore_wr(p_hwfn, p_ptt,
1255 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1256 ecore_wr(p_hwfn, p_ptt,
1257 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1261 ecore_emul_link_init(p_hwfn, p_ptt);
1263 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1270 static enum _ecore_status_t
1271 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1272 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1274 u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1275 u32 dpi_bit_shift, dpi_count;
1278 /* Calculate DPI size
1279 * ------------------
1280 * The PWM region contains Doorbell Pages. The first is reserverd for
1281 * the kernel for, e.g, L2. The others are free to be used by non-
1282 * trusted applications, typically from user space. Each page, called a
1283 * doorbell page is sectioned into windows that allow doorbells to be
1284 * issued in parallel by the kernel/application. The size of such a
1285 * window (a.k.a. WID) is 1kB.
1287 * 1kB WID x N WIDS = DPI page size
1288 * DPI page size x N DPIs = PWM region size
1290 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1291 * in order to ensure that two applications won't share the same page.
1292 * It also must contain at least one WID per CPU to allow parallelism.
1293 * It also must be a power of 2, since it is stored as a bit shift.
1295 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1296 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1297 * containing 4 WIDs.
1299 dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1300 dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1301 dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1302 dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1303 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1305 dpi_count = pwm_region_size / dpi_page_size;
1307 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1308 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1311 p_hwfn->dpi_size = dpi_page_size;
1312 p_hwfn->dpi_count = dpi_count;
1314 /* Update registers */
1315 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1317 if (dpi_count < min_dpis)
1318 return ECORE_NORESOURCES;
1320 return ECORE_SUCCESS;
1323 enum ECORE_ROCE_EDPM_MODE {
1324 ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1325 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1326 ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1329 static enum _ecore_status_t
1330 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1331 struct ecore_ptt *p_ptt)
1333 u32 pwm_regsize, norm_regsize;
1334 u32 non_pwm_conn, min_addr_reg1;
1335 u32 db_bar_size, n_cpus;
1338 int rc = ECORE_SUCCESS;
1341 db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1342 if (p_hwfn->p_dev->num_hwfns > 1)
1345 /* Calculate doorbell regions
1346 * -----------------------------------
1347 * The doorbell BAR is made of two regions. The first is called normal
1348 * region and the second is called PWM region. In the normal region
1349 * each ICID has its own set of addresses so that writing to that
1350 * specific address identifies the ICID. In the Process Window Mode
1351 * region the ICID is given in the data written to the doorbell. The
1352 * above per PF register denotes the offset in the doorbell BAR in which
1353 * the PWM region begins.
1354 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1355 * non-PWM connection. The calculation below computes the total non-PWM
1356 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1357 * in units of 4,096 bytes.
1359 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1360 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1362 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1363 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1364 min_addr_reg1 = norm_regsize / 4096;
1365 pwm_regsize = db_bar_size - norm_regsize;
1367 /* Check that the normal and PWM sizes are valid */
1368 if (db_bar_size < norm_regsize) {
1369 DP_ERR(p_hwfn->p_dev,
1370 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1371 db_bar_size, norm_regsize);
1372 return ECORE_NORESOURCES;
1374 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1375 DP_ERR(p_hwfn->p_dev,
1376 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1377 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1379 return ECORE_NORESOURCES;
1382 /* Calculate number of DPIs */
1383 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1384 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1385 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1386 /* Either EDPM is mandatory, or we are attempting to allocate a
1389 n_cpus = OSAL_NUM_ACTIVE_CPU();
1390 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1393 cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1394 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1395 if (cond || p_hwfn->dcbx_no_edpm) {
1396 /* Either EDPM is disabled from user configuration, or it is
1397 * disabled via DCBx, or it is not mandatory and we failed to
1398 * allocated a WID per CPU.
1401 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1403 /* If we entered this flow due to DCBX then the DPM register is
1404 * already configured.
1409 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1410 norm_regsize, pwm_regsize);
1412 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1413 p_hwfn->dpi_size, p_hwfn->dpi_count,
1414 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1415 "disabled" : "enabled");
1417 /* Check return codes from above calls */
1420 "Failed to allocate enough DPIs\n");
1421 return ECORE_NORESOURCES;
1425 p_hwfn->dpi_start_offset = norm_regsize;
1427 /* Update registers */
1428 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1429 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1430 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1431 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1433 return ECORE_SUCCESS;
1436 static enum _ecore_status_t
1437 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1438 struct ecore_ptt *p_ptt,
1439 struct ecore_tunn_start_params *p_tunn,
1442 enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1444 u8 rel_pf_id = p_hwfn->rel_pf_id;
1446 enum _ecore_status_t rc = ECORE_SUCCESS;
1450 if (p_hwfn->mcp_info) {
1451 struct ecore_mcp_function_info *p_info;
1453 p_info = &p_hwfn->mcp_info->func_info;
1454 if (p_info->bandwidth_min)
1455 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1457 /* Update rate limit once we'll actually have a link */
1458 p_hwfn->qm_info.pf_rl = 100000;
1460 ecore_cxt_hw_init_pf(p_hwfn);
1462 ecore_int_igu_init_rt(p_hwfn);
1464 /* Set VLAN in NIG if needed */
1465 if (hw_mode & (1 << MODE_MF_SD)) {
1466 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1467 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1468 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1469 p_hwfn->hw_info.ovlan);
1472 /* Enable classification by MAC if needed */
1473 if (hw_mode & (1 << MODE_MF_SI)) {
1474 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1475 "Configuring TAGMAC_CLS_TYPE\n");
1476 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1480 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
1481 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1482 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1483 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1484 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1485 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1487 /* perform debug configuration when chip is out of reset */
1488 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1490 /* Cleanup chip from previous driver if such remains exist */
1491 rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1492 if (rc != ECORE_SUCCESS) {
1493 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1497 /* PF Init sequence */
1498 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1502 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1503 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1507 /* Pure runtime initializations - directly to the HW */
1508 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1510 /* PCI relaxed ordering causes a decrease in the performance on some
1511 * systems. Till a root cause is found, disable this attribute in the
1515 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1517 * DP_NOTICE(p_hwfn, true,
1518 * "Failed to find the PCIe Cap\n");
1521 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1522 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1523 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1526 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1530 /* enable interrupts */
1531 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1532 if (rc != ECORE_SUCCESS)
1535 /* send function start command */
1536 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1537 allow_npar_tx_switch);
1539 DP_NOTICE(p_hwfn, true,
1540 "Function start ramrod failed\n");
1542 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1543 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1544 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1546 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1547 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1549 ecore_wr(p_hwfn, p_ptt,
1550 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1553 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1554 "PRS_REG_SEARCH registers after start PFn\n");
1555 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1556 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1557 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1558 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1559 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1560 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1561 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1562 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1563 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1564 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1565 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1566 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1567 prs_reg = ecore_rd(p_hwfn, p_ptt,
1568 PRS_REG_SEARCH_TCP_FIRST_FRAG);
1569 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1570 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1572 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1573 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1574 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1580 static enum _ecore_status_t
1581 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1582 struct ecore_ptt *p_ptt, u8 enable)
1584 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1586 /* Change PF in PXP */
1587 ecore_wr(p_hwfn, p_ptt,
1588 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1590 /* wait until value is set - try for 1 second every 50us */
1591 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1592 val = ecore_rd(p_hwfn, p_ptt,
1593 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1600 if (val != set_val) {
1601 DP_NOTICE(p_hwfn, true,
1602 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1603 return ECORE_UNKNOWN_ERROR;
1606 return ECORE_SUCCESS;
1609 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1610 struct ecore_ptt *p_main_ptt)
1612 /* Read shadow of current MFW mailbox */
1613 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1614 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1615 p_hwfn->mcp_info->mfw_mb_cur,
1616 p_hwfn->mcp_info->mfw_mb_length);
1619 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1620 struct ecore_hw_init_params *p_params)
1622 enum _ecore_status_t rc, mfw_rc;
1623 u32 load_code, param;
1626 if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
1627 (p_dev->num_hwfns > 1)) {
1628 DP_NOTICE(p_dev, false,
1629 "MSI mode is not supported for CMT devices\n");
1634 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1635 if (rc != ECORE_SUCCESS)
1639 for_each_hwfn(p_dev, i) {
1640 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1643 p_hwfn->b_int_enabled = 1;
1647 /* Enable DMAE in PXP */
1648 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1649 if (rc != ECORE_SUCCESS)
1652 rc = ecore_calc_hw_mode(p_hwfn);
1653 if (rc != ECORE_SUCCESS)
1656 /* @@@TBD need to add here:
1657 * Check for fan failure
1660 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1662 DP_NOTICE(p_hwfn, true,
1663 "Failed sending LOAD_REQ command\n");
1668 * When coming back from hiberbate state, the registers from
1669 * which shadow is read initially are not initialized. It turns
1670 * out that these registers get initialized during the call to
1671 * ecore_mcp_load_req request. So we need to reread them here
1672 * to get the proper shadow register value.
1673 * Note: This is a workaround for the missinginig MFW
1674 * initialization. It may be removed once the implementation
1677 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1679 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1680 "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1683 /* Only relevant for recovery:
1684 * Clear the indication after the LOAD_REQ command is responded
1687 p_dev->recov_in_prog = false;
1689 p_hwfn->first_on_engine = (load_code ==
1690 FW_MSG_CODE_DRV_LOAD_ENGINE);
1692 if (!qm_lock_init) {
1693 OSAL_SPIN_LOCK_INIT(&qm_lock);
1694 qm_lock_init = true;
1697 switch (load_code) {
1698 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1699 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1700 p_hwfn->hw_info.hw_mode);
1704 case FW_MSG_CODE_DRV_LOAD_PORT:
1705 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1706 p_hwfn->hw_info.hw_mode);
1710 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1711 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1713 p_hwfn->hw_info.hw_mode,
1714 p_params->b_hw_start,
1716 p_params->allow_npar_tx_switch);
1723 if (rc != ECORE_SUCCESS)
1724 DP_NOTICE(p_hwfn, true,
1725 "init phase failed for loadcode 0x%x (rc %d)\n",
1728 /* ACK mfw regardless of success or failure of initialization */
1729 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1730 DRV_MSG_CODE_LOAD_DONE,
1731 0, &load_code, ¶m);
1732 if (rc != ECORE_SUCCESS)
1734 if (mfw_rc != ECORE_SUCCESS) {
1735 DP_NOTICE(p_hwfn, true,
1736 "Failed sending LOAD_DONE command\n");
1740 /* send DCBX attention request command */
1741 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1742 "sending phony dcbx set command to trigger DCBx attention handling\n");
1743 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1744 DRV_MSG_CODE_SET_DCBX,
1745 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1746 &load_code, ¶m);
1747 if (mfw_rc != ECORE_SUCCESS) {
1748 DP_NOTICE(p_hwfn, true,
1749 "Failed to send DCBX attention request\n");
1753 p_hwfn->hw_init_done = true;
1756 return ECORE_SUCCESS;
1759 #define ECORE_HW_STOP_RETRY_LIMIT (10)
1760 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
1761 struct ecore_hwfn *p_hwfn,
1762 struct ecore_ptt *p_ptt)
1767 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1768 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1769 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
1771 if ((!ecore_rd(p_hwfn, p_ptt,
1772 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1773 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1776 /* Dependent on number of connection/tasks, possibly
1777 * 1ms sleep is required between polls
1782 if (i < ECORE_HW_STOP_RETRY_LIMIT)
1785 DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
1786 " [Connection %02x Tasks %02x]\n",
1787 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1788 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1791 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
1795 for_each_hwfn(p_dev, j) {
1796 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1797 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1799 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1803 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
1805 enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
1808 for_each_hwfn(p_dev, j) {
1809 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1810 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1812 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
1815 ecore_vf_pf_int_cleanup(p_hwfn);
1819 /* mark the hw as uninitialized... */
1820 p_hwfn->hw_init_done = false;
1822 rc = ecore_sp_pf_stop(p_hwfn);
1824 DP_NOTICE(p_hwfn, true,
1825 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
1827 /* perform debug action after PF stop was sent */
1828 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
1830 /* close NIG to BRB gate */
1831 ecore_wr(p_hwfn, p_ptt,
1832 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1835 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1836 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1837 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1838 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1839 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1841 /* @@@TBD - clean transmission queues (5.b) */
1842 /* @@@TBD - clean BTB (5.c) */
1844 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1846 /* @@@TBD - verify DMAE requests are done (8) */
1848 /* Disable Attention Generation */
1849 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1850 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1851 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1852 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1853 /* Need to wait 1ms to guarantee SBs are cleared */
1858 /* Disable DMAE in PXP - in CMT, this should only be done for
1859 * first hw-function, and only after all transactions have
1860 * stopped for all active hw-functions.
1862 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
1863 p_dev->hwfns[0].p_main_ptt, false);
1864 if (t_rc != ECORE_SUCCESS)
1871 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
1875 for_each_hwfn(p_dev, j) {
1876 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1877 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1880 ecore_vf_pf_int_cleanup(p_hwfn);
1884 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1885 "Shutting down the fastpath\n");
1887 ecore_wr(p_hwfn, p_ptt,
1888 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1890 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1891 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1892 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1893 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1894 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1896 /* @@@TBD - clean transmission queues (5.b) */
1897 /* @@@TBD - clean BTB (5.c) */
1899 /* @@@TBD - verify DMAE requests are done (8) */
1901 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1902 /* Need to wait 1ms to guarantee SBs are cleared */
1907 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
1909 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1911 if (IS_VF(p_hwfn->p_dev))
1914 /* If roce info is allocated it means roce is initialized and should
1915 * be enabled in searcher.
1917 if (p_hwfn->p_rdma_info) {
1918 if (p_hwfn->b_rdma_enabled_in_prs)
1919 ecore_wr(p_hwfn, p_ptt,
1920 p_hwfn->rdma_prs_search_reg, 0x1);
1921 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
1924 /* Re-open incoming traffic */
1925 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1926 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1929 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
1930 struct ecore_ptt *p_ptt, u32 reg,
1933 u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
1935 if (assert_val != expected) {
1936 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
1938 return ECORE_UNKNOWN_ERROR;
1944 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
1946 enum _ecore_status_t rc = ECORE_SUCCESS;
1947 u32 unload_resp, unload_param;
1950 for_each_hwfn(p_dev, i) {
1951 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1954 rc = ecore_vf_pf_reset(p_hwfn);
1960 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
1962 /* Check for incorrect states */
1963 if (!p_dev->recov_in_prog) {
1964 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1965 QM_REG_USG_CNT_PF_TX, 0);
1966 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1967 QM_REG_USG_CNT_PF_OTHER, 0);
1968 /* @@@TBD - assert on incorrect xCFC values (10.b) */
1971 /* Disable PF in HW blocks */
1972 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1973 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1975 if (p_dev->recov_in_prog) {
1976 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1977 "Recovery is in progress -> skip sending unload_req/done\n");
1981 /* Send unload command to MCP */
1982 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1983 DRV_MSG_CODE_UNLOAD_REQ,
1984 DRV_MB_PARAM_UNLOAD_WOL_MCP,
1985 &unload_resp, &unload_param);
1986 if (rc != ECORE_SUCCESS) {
1987 DP_NOTICE(p_hwfn, true,
1988 "ecore_hw_reset: UNLOAD_REQ failed\n");
1989 /* @@TBD - what to do? for now, assume ENG. */
1990 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
1993 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1994 DRV_MSG_CODE_UNLOAD_DONE,
1995 0, &unload_resp, &unload_param);
1996 if (rc != ECORE_SUCCESS) {
1998 true, "ecore_hw_reset: UNLOAD_DONE failed\n");
1999 /* @@@TBD - Should it really ASSERT here ? */
2007 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2008 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2010 ecore_ptt_pool_free(p_hwfn);
2011 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2014 /* Setup bar access */
2015 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2017 /* clear indirect access */
2018 if (ECORE_IS_AH(p_hwfn->p_dev)) {
2019 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2020 PGLUE_B_REG_PGL_ADDR_E8_F0, 0);
2021 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2022 PGLUE_B_REG_PGL_ADDR_EC_F0, 0);
2023 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2024 PGLUE_B_REG_PGL_ADDR_F0_F0, 0);
2025 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2026 PGLUE_B_REG_PGL_ADDR_F4_F0, 0);
2028 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2029 PGLUE_B_REG_PGL_ADDR_88_F0, 0);
2030 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2031 PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
2032 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2033 PGLUE_B_REG_PGL_ADDR_90_F0, 0);
2034 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2035 PGLUE_B_REG_PGL_ADDR_94_F0, 0);
2038 /* Clean Previous errors if such exist */
2039 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2040 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2042 /* enable internal target-read */
2043 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2044 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2047 static void get_function_id(struct ecore_hwfn *p_hwfn)
2050 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2051 PXP_PF_ME_OPAQUE_ADDR);
2053 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2055 /* Bits 16-19 from the ME registers are the pf_num */
2056 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2057 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2058 PXP_CONCRETE_FID_PFID);
2059 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2060 PXP_CONCRETE_FID_PORT);
2062 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2063 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2064 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2067 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2069 u32 *feat_num = p_hwfn->hw_info.feat_num;
2070 int num_features = 1;
2072 /* L2 Queues require each: 1 status block. 1 L2 queue */
2073 feat_num[ECORE_PF_L2_QUE] =
2075 RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2076 RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2078 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2079 "#PF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d num_features=%d\n",
2080 feat_num[ECORE_PF_L2_QUE],
2081 feat_num[ECORE_RDMA_CNQ],
2082 RESC_NUM(p_hwfn, ECORE_SB), num_features);
2085 static enum resource_id_enum
2086 ecore_hw_get_mfw_res_id(enum ecore_resources res_id)
2088 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2092 mfw_res_id = RESOURCE_NUM_SB_E;
2094 case ECORE_L2_QUEUE:
2095 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2098 mfw_res_id = RESOURCE_NUM_VPORT_E;
2101 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2104 mfw_res_id = RESOURCE_NUM_PQ_E;
2107 mfw_res_id = RESOURCE_NUM_RL_E;
2111 /* Each VFC resource can accommodate both a MAC and a VLAN */
2112 mfw_res_id = RESOURCE_VFC_FILTER_E;
2115 mfw_res_id = RESOURCE_ILT_E;
2117 case ECORE_LL2_QUEUE:
2118 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2120 case ECORE_RDMA_CNQ_RAM:
2121 case ECORE_CMDQS_CQS:
2122 /* CNQ/CMDQS are the same resource */
2123 mfw_res_id = RESOURCE_CQS_E;
2125 case ECORE_RDMA_STATS_QUEUE:
2126 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2135 static u32 ecore_hw_get_dflt_resc_num(struct ecore_hwfn *p_hwfn,
2136 enum ecore_resources res_id)
2138 u8 num_funcs = p_hwfn->num_funcs_on_engine;
2139 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2140 struct ecore_sb_cnt_info sb_cnt_info;
2141 u32 dflt_resc_num = 0;
2145 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2146 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2147 dflt_resc_num = sb_cnt_info.sb_cnt;
2149 case ECORE_L2_QUEUE:
2150 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2151 MAX_NUM_L2_QUEUES_BB) / num_funcs;
2154 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2155 MAX_NUM_VPORTS_BB) / num_funcs;
2158 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2159 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2162 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2163 MAX_QM_TX_QUEUES_BB) / num_funcs;
2166 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2170 /* Each VFC resource can accommodate both a MAC and a VLAN */
2171 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2174 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2175 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2177 case ECORE_LL2_QUEUE:
2178 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2180 case ECORE_RDMA_CNQ_RAM:
2181 case ECORE_CMDQS_CQS:
2182 /* CNQ/CMDQS are the same resource */
2184 dflt_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2186 case ECORE_RDMA_STATS_QUEUE:
2188 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2189 MAX_NUM_VPORTS_BB) / num_funcs;
2195 return dflt_resc_num;
2198 static const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2203 case ECORE_L2_QUEUE:
2217 case ECORE_RDMA_CNQ_RAM:
2218 return "RDMA_CNQ_RAM";
2221 case ECORE_LL2_QUEUE:
2223 case ECORE_CMDQS_CQS:
2225 case ECORE_RDMA_STATS_QUEUE:
2226 return "RDMA_STATS_QUEUE";
2228 return "UNKNOWN_RESOURCE";
2232 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2233 enum ecore_resources res_id,
2234 bool drv_resc_alloc)
2236 u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
2237 u32 *p_resc_num, *p_resc_start;
2238 struct resource_info resc_info;
2239 enum _ecore_status_t rc;
2241 p_resc_num = &RESC_NUM(p_hwfn, res_id);
2242 p_resc_start = &RESC_START(p_hwfn, res_id);
2244 dflt_resc_num = ecore_hw_get_dflt_resc_num(p_hwfn, res_id);
2245 if (!dflt_resc_num) {
2247 "Failed to get default amount for resource %d [%s]\n",
2248 res_id, ecore_hw_get_resc_name(res_id));
2251 dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
2254 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2255 *p_resc_num = dflt_resc_num;
2256 *p_resc_start = dflt_resc_start;
2261 OSAL_MEM_ZERO(&resc_info, sizeof(resc_info));
2262 resc_info.res_id = ecore_hw_get_mfw_res_id(res_id);
2263 if (resc_info.res_id == RESOURCE_NUM_INVALID) {
2265 "Failed to match resource %d with MFW resources\n",
2270 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
2271 &mcp_resp, &mcp_param);
2272 if (rc != ECORE_SUCCESS) {
2273 DP_NOTICE(p_hwfn, true,
2274 "MFW response failure for an allocation request for"
2275 " resource %d [%s]\n",
2276 res_id, ecore_hw_get_resc_name(res_id));
2280 /* Default driver values are applied in the following cases:
2281 * - The resource allocation MB command is not supported by the MFW
2282 * - There is an internal error in the MFW while processing the request
2283 * - The resource ID is unknown to the MFW
2285 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
2286 mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
2289 "Resource %d [%s]: No allocation info was received"
2290 " [mcp_resp 0x%x]. Applying default values"
2291 " [num %d, start %d].\n",
2292 res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2293 dflt_resc_num, dflt_resc_start);
2295 *p_resc_num = dflt_resc_num;
2296 *p_resc_start = dflt_resc_start;
2300 /* TBD - remove this when revising the handling of the SB resource */
2301 if (res_id == ECORE_SB) {
2302 /* Excluding the slowpath SB */
2303 resc_info.size -= 1;
2304 resc_info.offset -= p_hwfn->enabled_func_idx;
2307 *p_resc_num = resc_info.size;
2308 *p_resc_start = resc_info.offset;
2310 if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2311 DP_NOTICE(p_hwfn, false,
2312 "Resource %d [%s]: MFW allocation [num %d, start %d]"
2313 " differs from default values [num %d, start %d]%s\n",
2314 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2315 *p_resc_start, dflt_resc_num, dflt_resc_start,
2316 drv_resc_alloc ? " - Applying default values" : "");
2317 if (drv_resc_alloc) {
2318 *p_resc_num = dflt_resc_num;
2319 *p_resc_start = dflt_resc_start;
2323 return ECORE_SUCCESS;
2326 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2327 bool drv_resc_alloc)
2329 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2330 enum _ecore_status_t rc;
2333 u32 *resc_start = p_hwfn->hw_info.resc_start;
2334 u32 *resc_num = p_hwfn->hw_info.resc_num;
2335 /* For AH, an equal share of the ILT lines between the maximal number of
2336 * PFs is not enough for RoCE. This would be solved by the future
2337 * resource allocation scheme, but isn't currently present for
2338 * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2339 * to work - the BB number of ILT lines divided by its max PFs number.
2341 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2344 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2346 * Force the driver's default resource allocation in case there
2347 * is a diff with the MFW allocation value.
2349 rc = ecore_hw_set_resc_info(p_hwfn, res_id,
2350 b_ah || drv_resc_alloc);
2351 if (rc != ECORE_SUCCESS)
2356 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2357 /* Reduced build contains less PQs */
2358 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2359 resc_num[ECORE_PQ] = 32;
2360 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2361 p_hwfn->enabled_func_idx;
2364 /* For AH emulation, since we have a possible maximal number of
2365 * 16 enabled PFs, in case there are not enough ILT lines -
2366 * allocate only first PF as RoCE and have all the other ETH
2367 * only with less ILT lines.
2369 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2370 resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2371 resc_num[ECORE_ILT],
2372 roce_min_ilt_lines);
2375 /* Correct the common ILT calculation if PF0 has more */
2376 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2377 p_hwfn->p_dev->b_is_emul_full &&
2378 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2379 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2380 resc_num[ECORE_ILT];
2383 /* Sanity for ILT */
2384 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2385 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2386 DP_NOTICE(p_hwfn, true,
2387 "Can't assign ILT pages [%08x,...,%08x]\n",
2388 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2394 ecore_hw_set_feat(p_hwfn);
2396 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2397 "The numbers for each resource are:\n");
2398 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2399 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2400 ecore_hw_get_resc_name(res_id),
2401 RESC_NUM(p_hwfn, res_id),
2402 RESC_START(p_hwfn, res_id));
2404 return ECORE_SUCCESS;
2407 static enum _ecore_status_t ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2408 struct ecore_ptt *p_ptt)
2410 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
2411 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2412 struct ecore_mcp_link_params *link;
2414 /* Read global nvm_cfg address */
2415 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2417 /* Verify MCP has initialized it */
2418 if (!nvm_cfg_addr) {
2419 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2423 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
2425 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2427 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2428 OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2431 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2433 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2434 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2435 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2436 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2438 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2439 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2441 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2442 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2444 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2445 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2447 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2448 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2450 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2451 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2453 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2454 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2456 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2457 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2459 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2460 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
2462 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2463 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2465 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2466 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2469 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2474 /* Read default link configuration */
2475 link = &p_hwfn->mcp_info->link_input;
2476 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2477 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2478 link_temp = ecore_rd(p_hwfn, p_ptt,
2480 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2481 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2482 link->speed.advertised_speeds = link_temp;
2484 link_temp = link->speed.advertised_speeds;
2485 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2487 link_temp = ecore_rd(p_hwfn, p_ptt,
2489 OFFSETOF(struct nvm_cfg1_port, link_settings));
2490 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2491 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2492 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2493 link->speed.autoneg = true;
2495 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2496 link->speed.forced_speed = 1000;
2498 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2499 link->speed.forced_speed = 10000;
2501 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2502 link->speed.forced_speed = 25000;
2504 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2505 link->speed.forced_speed = 40000;
2507 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2508 link->speed.forced_speed = 50000;
2510 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2511 link->speed.forced_speed = 100000;
2514 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
2517 p_hwfn->mcp_info->link_capabilities.default_speed =
2518 link->speed.forced_speed;
2519 p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2520 link->speed.autoneg;
2522 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2523 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2524 link->pause.autoneg = !!(link_temp &
2525 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2526 link->pause.forced_rx = !!(link_temp &
2527 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2528 link->pause.forced_tx = !!(link_temp &
2529 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2530 link->loopback_mode = 0;
2532 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2533 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2534 link->speed.forced_speed, link->speed.advertised_speeds,
2535 link->speed.autoneg, link->pause.autoneg);
2537 /* Read Multi-function information from shmem */
2538 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2539 OFFSETOF(struct nvm_cfg1, glob) +
2540 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
2542 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
2544 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2545 NVM_CFG1_GLOB_MF_MODE_OFFSET;
2548 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2549 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
2551 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2552 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
2554 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2555 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
2558 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2559 p_hwfn->p_dev->mf_mode);
2561 /* Read Multi-function information from shmem */
2562 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2563 OFFSETOF(struct nvm_cfg1, glob) +
2564 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
2566 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
2567 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2568 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
2569 &p_hwfn->hw_info.device_capabilities);
2570 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2571 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
2572 &p_hwfn->hw_info.device_capabilities);
2573 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2574 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
2575 &p_hwfn->hw_info.device_capabilities);
2576 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2577 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
2578 &p_hwfn->hw_info.device_capabilities);
2579 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
2580 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
2581 &p_hwfn->hw_info.device_capabilities);
2583 return ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2586 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
2587 struct ecore_ptt *p_ptt)
2589 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2590 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2591 struct ecore_dev *p_dev = p_hwfn->p_dev;
2593 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2595 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2596 * in the other bits are selected.
2597 * Bits 1-15 are for functions 1-15, respectively, and their value is
2598 * '0' only for enabled functions (function 0 always exists and
2600 * In case of CMT in BB, only the "even" functions are enabled, and thus
2601 * the number of functions for both hwfns is learnt from the same bits.
2603 reg_function_hide = ecore_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2605 if (reg_function_hide & 0x1) {
2606 if (ECORE_IS_BB(p_dev)) {
2607 if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
2619 /* Get the number of the enabled functions on the engine */
2620 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2627 /* Get the PF index within the enabled functions */
2628 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2629 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2637 p_hwfn->num_funcs_on_engine = num_funcs;
2638 p_hwfn->enabled_func_idx = enabled_func_idx;
2641 if (CHIP_REV_IS_FPGA(p_dev)) {
2642 DP_NOTICE(p_hwfn, false,
2643 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
2644 p_hwfn->num_funcs_on_engine = 4;
2648 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2649 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2650 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
2651 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2654 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
2655 struct ecore_ptt *p_ptt)
2660 /* Read the port mode */
2661 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
2663 else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
2664 (p_hwfn->p_dev->num_hwfns > 1))
2665 /* In CMT on emulation, assume 1 port */
2669 port_mode = ecore_rd(p_hwfn, p_ptt,
2670 CNIG_REG_NW_PORT_MODE_BB_B0);
2672 if (port_mode < 3) {
2673 p_hwfn->p_dev->num_ports_in_engines = 1;
2674 } else if (port_mode <= 5) {
2675 p_hwfn->p_dev->num_ports_in_engines = 2;
2677 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
2678 p_hwfn->p_dev->num_ports_in_engines);
2680 /* Default num_ports_in_engines to something */
2681 p_hwfn->p_dev->num_ports_in_engines = 1;
2685 static void ecore_hw_info_port_num_ah(struct ecore_hwfn *p_hwfn,
2686 struct ecore_ptt *p_ptt)
2691 p_hwfn->p_dev->num_ports_in_engines = 0;
2694 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2695 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
2696 switch ((port & 0xf000) >> 12) {
2698 p_hwfn->p_dev->num_ports_in_engines = 1;
2701 p_hwfn->p_dev->num_ports_in_engines = 2;
2704 p_hwfn->p_dev->num_ports_in_engines = 4;
2707 DP_NOTICE(p_hwfn, false,
2708 "Unknown port mode in ECO_RESERVED %08x\n",
2713 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2714 port = ecore_rd(p_hwfn, p_ptt,
2715 CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2717 p_hwfn->p_dev->num_ports_in_engines++;
2721 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
2722 struct ecore_ptt *p_ptt)
2724 if (ECORE_IS_BB(p_hwfn->p_dev))
2725 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
2727 ecore_hw_info_port_num_ah(p_hwfn, p_ptt);
2730 static enum _ecore_status_t
2731 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2732 enum ecore_pci_personality personality, bool drv_resc_alloc)
2734 enum _ecore_status_t rc;
2736 /* Since all information is common, only first hwfns should do this */
2737 if (IS_LEAD_HWFN(p_hwfn)) {
2738 rc = ecore_iov_hw_info(p_hwfn);
2739 if (rc != ECORE_SUCCESS)
2743 /* TODO In get_hw_info, amoungst others:
2744 * Get MCP FW revision and determine according to it the supported
2745 * featrues (e.g. DCB)
2747 * ecore_get_pcie_width_speed, WOL capability.
2748 * Number of global CQ-s (for storage
2750 ecore_hw_info_port_num(p_hwfn, p_ptt);
2753 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
2755 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt);
2756 if (rc != ECORE_SUCCESS)
2762 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
2763 if (rc != ECORE_SUCCESS)
2767 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
2769 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
2770 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
2773 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
2775 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
2776 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
2780 if (ecore_mcp_is_init(p_hwfn)) {
2781 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
2782 p_hwfn->hw_info.ovlan =
2783 p_hwfn->mcp_info->func_info.ovlan;
2785 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
2788 if (personality != ECORE_PCI_DEFAULT)
2789 p_hwfn->hw_info.personality = personality;
2790 else if (ecore_mcp_is_init(p_hwfn))
2791 p_hwfn->hw_info.personality =
2792 p_hwfn->mcp_info->func_info.protocol;
2795 /* To overcome ILT lack for emulation, until at least until we'll have
2796 * a definite answer from system about it, allow only PF0 to be RoCE.
2798 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
2799 if (!p_hwfn->rel_pf_id)
2800 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
2802 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
2806 /* although in BB some constellations may support more than 4 tcs,
2807 * that can result in performance penalty in some cases. 4
2808 * represents a good tradeoff between performance and flexibility.
2810 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2812 /* start out with a single active tc. This can be increased either
2813 * by dcbx negotiation or by upper layer driver
2815 p_hwfn->hw_info.num_active_tc = 1;
2817 ecore_get_num_funcs(p_hwfn, p_ptt);
2819 /* In case of forcing the driver's default resource allocation, calling
2820 * ecore_hw_get_resc() should come after initializing the personality
2821 * and after getting the number of functions, since the calculation of
2822 * the resources/features depends on them.
2823 * This order is not harmful if not forcing.
2825 return ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
2828 #define ECORE_DEV_ID_MASK 0xff00
2829 #define ECORE_DEV_ID_MASK_BB 0x1600
2830 #define ECORE_DEV_ID_MASK_AH 0x8000
2832 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
2834 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2837 /* Read Vendor Id / Device Id */
2838 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
2840 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
2843 /* Determine type */
2844 if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
2845 p_dev->type = ECORE_DEV_TYPE_AH;
2847 p_dev->type = ECORE_DEV_TYPE_BB;
2849 p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2850 MISCS_REG_CHIP_NUM);
2851 p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2852 MISCS_REG_CHIP_REV);
2854 MASK_FIELD(CHIP_REV, p_dev->chip_rev);
2856 /* Learn number of HW-functions */
2857 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2858 MISCS_REG_CMT_ENABLED_FOR_PAIR);
2860 if (tmp & (1 << p_hwfn->rel_pf_id)) {
2861 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
2862 p_dev->num_hwfns = 2;
2864 p_dev->num_hwfns = 1;
2868 if (CHIP_REV_IS_EMUL(p_dev)) {
2869 /* For some reason we have problems with this register
2870 * in B0 emulation; Simply assume no CMT
2872 DP_NOTICE(p_dev->hwfns, false,
2873 "device on emul - assume no CMT\n");
2874 p_dev->num_hwfns = 1;
2878 p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2879 MISCS_REG_CHIP_TEST_REG) >> 4;
2880 MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
2881 p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2882 MISCS_REG_CHIP_METAL);
2883 MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
2884 DP_INFO(p_dev->hwfns,
2885 "Chip details - %s%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2886 ECORE_IS_BB(p_dev) ? "BB" : "AH",
2887 CHIP_REV_IS_A0(p_dev) ? 0 : 1,
2888 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
2891 if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
2892 DP_NOTICE(p_dev->hwfns, false,
2893 "The chip type/rev (BB A0) is not supported!\n");
2894 return ECORE_ABORTED;
2897 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
2898 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2899 MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
2901 if (CHIP_REV_IS_EMUL(p_dev)) {
2902 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2903 MISCS_REG_ECO_RESERVED);
2904 if (tmp & (1 << 29)) {
2905 DP_NOTICE(p_hwfn, false,
2906 "Emulation: Running on a FULL build\n");
2907 p_dev->b_is_emul_full = true;
2909 DP_NOTICE(p_hwfn, false,
2910 "Emulation: Running on a REDUCED build\n");
2915 return ECORE_SUCCESS;
2918 #ifndef LINUX_REMOVE
2919 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
2926 for_each_hwfn(p_dev, j) {
2927 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2929 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2930 "Mark hw/fw uninitialized\n");
2932 p_hwfn->hw_init_done = false;
2933 p_hwfn->first_on_engine = false;
2935 ecore_ptt_invalidate(p_hwfn);
2940 static enum _ecore_status_t
2941 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
2942 void OSAL_IOMEM * p_regview,
2943 void OSAL_IOMEM * p_doorbells,
2944 struct ecore_hw_prepare_params *p_params)
2946 struct ecore_dev *p_dev = p_hwfn->p_dev;
2947 struct ecore_mdump_info mdump_info;
2948 enum _ecore_status_t rc = ECORE_SUCCESS;
2950 /* Split PCI bars evenly between hwfns */
2951 p_hwfn->regview = p_regview;
2952 p_hwfn->doorbells = p_doorbells;
2955 return ecore_vf_hw_prepare(p_hwfn);
2957 /* Validate that chip access is feasible */
2958 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2960 "Reading the ME register returns all Fs; Preventing further chip access\n");
2964 get_function_id(p_hwfn);
2966 /* Allocate PTT pool */
2967 rc = ecore_ptt_pool_alloc(p_hwfn);
2969 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
2973 /* Allocate the main PTT */
2974 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2976 /* First hwfn learns basic information, e.g., number of hwfns */
2977 if (!p_hwfn->my_id) {
2978 rc = ecore_get_dev_info(p_dev);
2979 if (rc != ECORE_SUCCESS)
2983 ecore_hw_hwfn_prepare(p_hwfn);
2985 /* Initialize MCP structure */
2986 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2988 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
2992 /* Read the device configuration information from the HW and SHMEM */
2993 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
2994 p_params->personality, p_params->drv_resc_alloc);
2996 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3000 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3001 * called, since among others it sets the ports number in an engine.
3003 if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3004 !p_dev->recov_in_prog) {
3005 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3006 if (rc != ECORE_SUCCESS)
3007 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3010 /* Check if mdump logs are present and update the epoch value */
3011 if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) {
3012 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3014 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) {
3015 DP_NOTICE(p_hwfn, false,
3016 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3019 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3023 /* Allocate the init RT array and initialize the init-ops engine */
3024 rc = ecore_init_alloc(p_hwfn);
3026 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3030 if (CHIP_REV_IS_FPGA(p_dev)) {
3031 DP_NOTICE(p_hwfn, false,
3032 "FPGA: workaround; Prevent DMAE parities\n");
3033 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK, 7);
3035 DP_NOTICE(p_hwfn, false,
3036 "FPGA: workaround: Set VF bar0 size\n");
3037 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3038 PGLUE_B_REG_VF_BAR0_SIZE, 4);
3044 if (IS_LEAD_HWFN(p_hwfn))
3045 ecore_iov_free_hw_info(p_dev);
3046 ecore_mcp_free(p_hwfn);
3048 ecore_hw_hwfn_free(p_hwfn);
3053 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3054 struct ecore_hw_prepare_params *p_params)
3056 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3057 enum _ecore_status_t rc;
3059 p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3061 /* Store the precompiled init data ptrs */
3063 ecore_init_iro_array(p_dev);
3065 /* Initialize the first hwfn - will learn number of hwfns */
3066 rc = ecore_hw_prepare_single(p_hwfn,
3068 p_dev->doorbells, p_params);
3069 if (rc != ECORE_SUCCESS)
3072 p_params->personality = p_hwfn->hw_info.personality;
3074 /* initilalize 2nd hwfn if necessary */
3075 if (p_dev->num_hwfns > 1) {
3076 void OSAL_IOMEM *p_regview, *p_doorbell;
3077 u8 OSAL_IOMEM *addr;
3079 /* adjust bar offset for second engine */
3080 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3081 ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3082 p_regview = (void OSAL_IOMEM *)addr;
3084 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3085 ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3086 p_doorbell = (void OSAL_IOMEM *)addr;
3088 /* prepare second hw function */
3089 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3090 p_doorbell, p_params);
3092 /* in case of error, need to free the previously
3093 * initiliazed hwfn 0.
3095 if (rc != ECORE_SUCCESS) {
3097 ecore_init_free(p_hwfn);
3098 ecore_mcp_free(p_hwfn);
3099 ecore_hw_hwfn_free(p_hwfn);
3101 DP_NOTICE(p_dev, true,
3102 "What do we need to free when VF hwfn1 init fails\n");
3111 void ecore_hw_remove(struct ecore_dev *p_dev)
3115 for_each_hwfn(p_dev, i) {
3116 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3119 ecore_vf_pf_release(p_hwfn);
3123 ecore_init_free(p_hwfn);
3124 ecore_hw_hwfn_free(p_hwfn);
3125 ecore_mcp_free(p_hwfn);
3127 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3130 ecore_iov_free_hw_info(p_dev);
3133 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3134 struct ecore_chain *p_chain)
3136 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3137 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3138 struct ecore_chain_next *p_next;
3144 size = p_chain->elem_size * p_chain->usable_per_page;
3146 for (i = 0; i < p_chain->page_cnt; i++) {
3150 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3151 p_virt_next = p_next->next_virt;
3152 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3154 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3155 ECORE_CHAIN_PAGE_SIZE);
3157 p_virt = p_virt_next;
3158 p_phys = p_phys_next;
3162 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3163 struct ecore_chain *p_chain)
3165 if (!p_chain->p_virt_addr)
3168 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3169 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3172 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3173 struct ecore_chain *p_chain)
3175 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3176 u8 *p_pbl_virt = (u8 *)p_chain->pbl.p_virt_table;
3177 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3179 if (!pp_virt_addr_tbl)
3182 if (!p_chain->pbl.p_virt_table)
3185 for (i = 0; i < page_cnt; i++) {
3186 if (!pp_virt_addr_tbl[i])
3189 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3190 *(dma_addr_t *)p_pbl_virt,
3191 ECORE_CHAIN_PAGE_SIZE);
3193 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3196 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3198 if (!p_chain->pbl.external)
3199 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table,
3200 p_chain->pbl.p_phys_table, pbl_size);
3202 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3205 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3207 switch (p_chain->mode) {
3208 case ECORE_CHAIN_MODE_NEXT_PTR:
3209 ecore_chain_free_next_ptr(p_dev, p_chain);
3211 case ECORE_CHAIN_MODE_SINGLE:
3212 ecore_chain_free_single(p_dev, p_chain);
3214 case ECORE_CHAIN_MODE_PBL:
3215 ecore_chain_free_pbl(p_dev, p_chain);
3220 static enum _ecore_status_t
3221 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3222 enum ecore_chain_cnt_type cnt_type,
3223 osal_size_t elem_size, u32 page_cnt)
3225 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3227 /* The actual chain size can be larger than the maximal possible value
3228 * after rounding up the requested elements number to pages, and after
3229 * taking into acount the unusuable elements (next-ptr elements).
3230 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3231 * size/capacity fields are of a u32 type.
3233 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3234 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3235 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3236 chain_size > ECORE_U32_MAX)) {
3237 DP_NOTICE(p_dev, true,
3238 "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3239 (unsigned long)chain_size);
3243 return ECORE_SUCCESS;
3246 static enum _ecore_status_t
3247 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3249 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3250 dma_addr_t p_phys = 0;
3253 for (i = 0; i < p_chain->page_cnt; i++) {
3254 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3255 ECORE_CHAIN_PAGE_SIZE);
3257 DP_NOTICE(p_dev, true,
3258 "Failed to allocate chain memory\n");
3263 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3264 ecore_chain_reset(p_chain);
3266 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3270 p_virt_prev = p_virt;
3272 /* Last page's next element should point to the beginning of the
3275 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3276 p_chain->p_virt_addr,
3277 p_chain->p_phys_addr);
3279 return ECORE_SUCCESS;
3282 static enum _ecore_status_t
3283 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3285 dma_addr_t p_phys = 0;
3286 void *p_virt = OSAL_NULL;
3288 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3290 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3294 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3295 ecore_chain_reset(p_chain);
3297 return ECORE_SUCCESS;
3300 static enum _ecore_status_t
3301 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3302 struct ecore_chain *p_chain,
3303 struct ecore_chain_ext_pbl *ext_pbl)
3305 void *p_virt = OSAL_NULL;
3306 u8 *p_pbl_virt = OSAL_NULL;
3307 void **pp_virt_addr_tbl = OSAL_NULL;
3308 dma_addr_t p_phys = 0, p_pbl_phys = 0;
3309 u32 page_cnt = p_chain->page_cnt, size, i;
3311 size = page_cnt * sizeof(*pp_virt_addr_tbl);
3312 pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
3313 if (!pp_virt_addr_tbl) {
3314 DP_NOTICE(p_dev, true,
3315 "Failed to allocate memory for the chain virtual addresses table\n");
3318 OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
3320 /* The allocation of the PBL table is done with its full size, since it
3321 * is expected to be successive.
3322 * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3323 * failure, since pp_virt_addr_tbl was previously allocated, and it
3324 * should be saved to allow its freeing during the error flow.
3326 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3328 if (ext_pbl == OSAL_NULL) {
3329 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3331 p_pbl_virt = ext_pbl->p_pbl_virt;
3332 p_pbl_phys = ext_pbl->p_pbl_phys;
3333 p_chain->pbl.external = true;
3336 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3339 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3343 for (i = 0; i < page_cnt; i++) {
3344 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3345 ECORE_CHAIN_PAGE_SIZE);
3347 DP_NOTICE(p_dev, true,
3348 "Failed to allocate chain memory\n");
3353 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3354 ecore_chain_reset(p_chain);
3357 /* Fill the PBL table with the physical address of the page */
3358 *(dma_addr_t *)p_pbl_virt = p_phys;
3359 /* Keep the virtual address of the page */
3360 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3362 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3365 return ECORE_SUCCESS;
3368 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3369 enum ecore_chain_use_mode intended_use,
3370 enum ecore_chain_mode mode,
3371 enum ecore_chain_cnt_type cnt_type,
3372 u32 num_elems, osal_size_t elem_size,
3373 struct ecore_chain *p_chain,
3374 struct ecore_chain_ext_pbl *ext_pbl)
3377 enum _ecore_status_t rc = ECORE_SUCCESS;
3379 if (mode == ECORE_CHAIN_MODE_SINGLE)
3382 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3384 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3387 DP_NOTICE(p_dev, true,
3388 "Cannot allocate a chain with the given arguments:\n"
3389 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3390 intended_use, mode, cnt_type, num_elems, elem_size);
3394 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3395 mode, cnt_type, p_dev->dp_ctx);
3398 case ECORE_CHAIN_MODE_NEXT_PTR:
3399 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3401 case ECORE_CHAIN_MODE_SINGLE:
3402 rc = ecore_chain_alloc_single(p_dev, p_chain);
3404 case ECORE_CHAIN_MODE_PBL:
3405 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
3411 return ECORE_SUCCESS;
3414 ecore_chain_free(p_dev, p_chain);
3418 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3419 u16 src_id, u16 *dst_id)
3421 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3424 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3425 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3426 DP_NOTICE(p_hwfn, true,
3427 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3433 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3435 return ECORE_SUCCESS;
3438 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3439 u8 src_id, u8 *dst_id)
3441 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3444 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3445 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3446 DP_NOTICE(p_hwfn, true,
3447 "vport id [%d] is not valid, available indices [%d - %d]\n",
3453 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3455 return ECORE_SUCCESS;
3458 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
3459 u8 src_id, u8 *dst_id)
3461 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
3464 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
3465 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
3466 DP_NOTICE(p_hwfn, true,
3467 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3473 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
3475 return ECORE_SUCCESS;
3478 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
3479 struct ecore_ptt *p_ptt,
3485 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3486 return ECORE_SUCCESS;
3488 high = p_filter[1] | (p_filter[0] << 8);
3489 low = p_filter[5] | (p_filter[4] << 8) |
3490 (p_filter[3] << 16) | (p_filter[2] << 24);
3492 /* Find a free entry and utilize it */
3493 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3494 en = ecore_rd(p_hwfn, p_ptt,
3495 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3498 ecore_wr(p_hwfn, p_ptt,
3499 NIG_REG_LLH_FUNC_FILTER_VALUE +
3500 2 * i * sizeof(u32), low);
3501 ecore_wr(p_hwfn, p_ptt,
3502 NIG_REG_LLH_FUNC_FILTER_VALUE +
3503 (2 * i + 1) * sizeof(u32), high);
3504 ecore_wr(p_hwfn, p_ptt,
3505 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3506 ecore_wr(p_hwfn, p_ptt,
3507 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3508 i * sizeof(u32), 0);
3509 ecore_wr(p_hwfn, p_ptt,
3510 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3513 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3514 DP_NOTICE(p_hwfn, false,
3515 "Failed to find an empty LLH filter to utilize\n");
3519 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3520 "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
3521 p_filter[0], p_filter[1], p_filter[2],
3522 p_filter[3], p_filter[4], p_filter[5], i);
3524 return ECORE_SUCCESS;
3527 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
3528 struct ecore_ptt *p_ptt, u8 *p_filter)
3533 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3536 high = p_filter[1] | (p_filter[0] << 8);
3537 low = p_filter[5] | (p_filter[4] << 8) |
3538 (p_filter[3] << 16) | (p_filter[2] << 24);
3540 /* Find the entry and clean it */
3541 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3542 if (ecore_rd(p_hwfn, p_ptt,
3543 NIG_REG_LLH_FUNC_FILTER_VALUE +
3544 2 * i * sizeof(u32)) != low)
3546 if (ecore_rd(p_hwfn, p_ptt,
3547 NIG_REG_LLH_FUNC_FILTER_VALUE +
3548 (2 * i + 1) * sizeof(u32)) != high)
3551 ecore_wr(p_hwfn, p_ptt,
3552 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3553 ecore_wr(p_hwfn, p_ptt,
3554 NIG_REG_LLH_FUNC_FILTER_VALUE +
3555 2 * i * sizeof(u32), 0);
3556 ecore_wr(p_hwfn, p_ptt,
3557 NIG_REG_LLH_FUNC_FILTER_VALUE +
3558 (2 * i + 1) * sizeof(u32), 0);
3561 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3562 DP_NOTICE(p_hwfn, false,
3563 "Tried to remove a non-configured filter\n");
3566 enum _ecore_status_t
3567 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
3568 struct ecore_ptt *p_ptt,
3569 u16 source_port_or_eth_type,
3571 enum ecore_llh_port_filter_type_t type)
3576 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3577 return ECORE_SUCCESS;
3582 case ECORE_LLH_FILTER_ETHERTYPE:
3583 high = source_port_or_eth_type;
3585 case ECORE_LLH_FILTER_TCP_SRC_PORT:
3586 case ECORE_LLH_FILTER_UDP_SRC_PORT:
3587 low = source_port_or_eth_type << 16;
3589 case ECORE_LLH_FILTER_TCP_DEST_PORT:
3590 case ECORE_LLH_FILTER_UDP_DEST_PORT:
3593 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3594 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3595 low = (source_port_or_eth_type << 16) | dest_port;
3598 DP_NOTICE(p_hwfn, true,
3599 "Non valid LLH protocol filter type %d\n", type);
3602 /* Find a free entry and utilize it */
3603 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3604 en = ecore_rd(p_hwfn, p_ptt,
3605 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3608 ecore_wr(p_hwfn, p_ptt,
3609 NIG_REG_LLH_FUNC_FILTER_VALUE +
3610 2 * i * sizeof(u32), low);
3611 ecore_wr(p_hwfn, p_ptt,
3612 NIG_REG_LLH_FUNC_FILTER_VALUE +
3613 (2 * i + 1) * sizeof(u32), high);
3614 ecore_wr(p_hwfn, p_ptt,
3615 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3616 ecore_wr(p_hwfn, p_ptt,
3617 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3618 i * sizeof(u32), 1 << type);
3619 ecore_wr(p_hwfn, p_ptt,
3620 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3623 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3624 DP_NOTICE(p_hwfn, false,
3625 "Failed to find an empty LLH filter to utilize\n");
3626 return ECORE_NORESOURCES;
3629 case ECORE_LLH_FILTER_ETHERTYPE:
3630 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3631 "ETH type %x is added at %d\n",
3632 source_port_or_eth_type, i);
3634 case ECORE_LLH_FILTER_TCP_SRC_PORT:
3635 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3636 "TCP src port %x is added at %d\n",
3637 source_port_or_eth_type, i);
3639 case ECORE_LLH_FILTER_UDP_SRC_PORT:
3640 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3641 "UDP src port %x is added at %d\n",
3642 source_port_or_eth_type, i);
3644 case ECORE_LLH_FILTER_TCP_DEST_PORT:
3645 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3646 "TCP dst port %x is added at %d\n", dest_port, i);
3648 case ECORE_LLH_FILTER_UDP_DEST_PORT:
3649 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3650 "UDP dst port %x is added at %d\n", dest_port, i);
3652 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3653 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3654 "TCP src/dst ports %x/%x are added at %d\n",
3655 source_port_or_eth_type, dest_port, i);
3657 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3658 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3659 "UDP src/dst ports %x/%x are added at %d\n",
3660 source_port_or_eth_type, dest_port, i);
3663 return ECORE_SUCCESS;
3667 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
3668 struct ecore_ptt *p_ptt,
3669 u16 source_port_or_eth_type,
3671 enum ecore_llh_port_filter_type_t type)
3676 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3682 case ECORE_LLH_FILTER_ETHERTYPE:
3683 high = source_port_or_eth_type;
3685 case ECORE_LLH_FILTER_TCP_SRC_PORT:
3686 case ECORE_LLH_FILTER_UDP_SRC_PORT:
3687 low = source_port_or_eth_type << 16;
3689 case ECORE_LLH_FILTER_TCP_DEST_PORT:
3690 case ECORE_LLH_FILTER_UDP_DEST_PORT:
3693 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3694 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3695 low = (source_port_or_eth_type << 16) | dest_port;
3698 DP_NOTICE(p_hwfn, true,
3699 "Non valid LLH protocol filter type %d\n", type);
3703 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3704 if (!ecore_rd(p_hwfn, p_ptt,
3705 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3707 if (!ecore_rd(p_hwfn, p_ptt,
3708 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3710 if (!(ecore_rd(p_hwfn, p_ptt,
3711 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3712 i * sizeof(u32)) & (1 << type)))
3714 if (ecore_rd(p_hwfn, p_ptt,
3715 NIG_REG_LLH_FUNC_FILTER_VALUE +
3716 2 * i * sizeof(u32)) != low)
3718 if (ecore_rd(p_hwfn, p_ptt,
3719 NIG_REG_LLH_FUNC_FILTER_VALUE +
3720 (2 * i + 1) * sizeof(u32)) != high)
3723 ecore_wr(p_hwfn, p_ptt,
3724 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3725 ecore_wr(p_hwfn, p_ptt,
3726 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3727 ecore_wr(p_hwfn, p_ptt,
3728 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3729 i * sizeof(u32), 0);
3730 ecore_wr(p_hwfn, p_ptt,
3731 NIG_REG_LLH_FUNC_FILTER_VALUE +
3732 2 * i * sizeof(u32), 0);
3733 ecore_wr(p_hwfn, p_ptt,
3734 NIG_REG_LLH_FUNC_FILTER_VALUE +
3735 (2 * i + 1) * sizeof(u32), 0);
3739 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3740 DP_NOTICE(p_hwfn, false,
3741 "Tried to remove a non-configured filter\n");
3744 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
3745 struct ecore_ptt *p_ptt)
3749 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3752 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3753 ecore_wr(p_hwfn, p_ptt,
3754 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3755 ecore_wr(p_hwfn, p_ptt,
3756 NIG_REG_LLH_FUNC_FILTER_VALUE +
3757 2 * i * sizeof(u32), 0);
3758 ecore_wr(p_hwfn, p_ptt,
3759 NIG_REG_LLH_FUNC_FILTER_VALUE +
3760 (2 * i + 1) * sizeof(u32), 0);
3764 enum _ecore_status_t
3765 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
3766 struct ecore_ptt *p_ptt)
3768 if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
3769 ecore_wr(p_hwfn, p_ptt,
3770 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
3771 1 << p_hwfn->abs_pf_id / 2);
3772 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
3773 return ECORE_SUCCESS;
3776 DP_NOTICE(p_hwfn, false,
3777 "This function can't be set as default\n");
3781 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
3782 struct ecore_ptt *p_ptt,
3783 u32 hw_addr, void *p_eth_qzone,
3784 osal_size_t eth_qzone_size,
3787 struct coalescing_timeset *p_coal_timeset;
3789 if (IS_VF(p_hwfn->p_dev)) {
3790 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n");
3794 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
3795 DP_NOTICE(p_hwfn, true,
3796 "Coalescing configuration not enabled\n");
3800 p_coal_timeset = p_eth_qzone;
3801 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
3802 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3803 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3804 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3806 return ECORE_SUCCESS;
3809 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
3810 struct ecore_ptt *p_ptt,
3811 u16 coalesce, u8 qid, u16 sb_id)
3813 struct ustorm_eth_queue_zone eth_qzone;
3814 u8 timeset, timer_res;
3817 enum _ecore_status_t rc;
3819 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3820 if (coalesce <= 0x7F) {
3822 } else if (coalesce <= 0xFF) {
3824 } else if (coalesce <= 0x1FF) {
3827 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3830 timeset = (u8)(coalesce >> timer_res);
3832 rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3833 if (rc != ECORE_SUCCESS)
3836 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
3837 if (rc != ECORE_SUCCESS)
3840 address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3842 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
3843 sizeof(struct ustorm_eth_queue_zone), timeset);
3844 if (rc != ECORE_SUCCESS)
3847 p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
3852 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
3853 struct ecore_ptt *p_ptt,
3854 u16 coalesce, u8 qid, u16 sb_id)
3856 struct xstorm_eth_queue_zone eth_qzone;
3857 u8 timeset, timer_res;
3860 enum _ecore_status_t rc;
3862 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3863 if (coalesce <= 0x7F) {
3865 } else if (coalesce <= 0xFF) {
3867 } else if (coalesce <= 0x1FF) {
3870 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3874 timeset = (u8)(coalesce >> timer_res);
3876 rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3877 if (rc != ECORE_SUCCESS)
3880 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
3881 if (rc != ECORE_SUCCESS)
3884 address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3886 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
3887 sizeof(struct xstorm_eth_queue_zone), timeset);
3888 if (rc != ECORE_SUCCESS)
3891 p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
3896 /* Calculate final WFQ values for all vports and configure it.
3897 * After this configuration each vport must have
3898 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
3900 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3901 struct ecore_ptt *p_ptt,
3904 struct init_qm_vport_params *vport_params;
3907 vport_params = p_hwfn->qm_info.qm_vport_params;
3909 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3910 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3912 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
3914 ecore_init_vport_wfq(p_hwfn, p_ptt,
3915 vport_params[i].first_tx_pq_id,
3916 vport_params[i].vport_wfq);
3921 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
3925 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3926 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3929 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3930 struct ecore_ptt *p_ptt,
3933 struct init_qm_vport_params *vport_params;
3936 vport_params = p_hwfn->qm_info.qm_vport_params;
3938 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3939 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
3940 ecore_init_vport_wfq(p_hwfn, p_ptt,
3941 vport_params[i].first_tx_pq_id,
3942 vport_params[i].vport_wfq);
3946 /* This function performs several validations for WFQ
3947 * configuration and required min rate for a given vport
3948 * 1. req_rate must be greater than one percent of min_pf_rate.
3949 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
3950 * rates to get less than one percent of min_pf_rate.
3951 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
3953 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
3954 u16 vport_id, u32 req_rate,
3957 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3958 int non_requested_count = 0, req_count = 0, i, num_vports;
3960 num_vports = p_hwfn->qm_info.num_vports;
3962 /* Accounting for the vports which are configured for WFQ explicitly */
3964 for (i = 0; i < num_vports; i++) {
3967 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
3969 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3970 total_req_min_rate += tmp_speed;
3974 /* Include current vport data as well */
3976 total_req_min_rate += req_rate;
3977 non_requested_count = num_vports - req_count;
3979 /* validate possible error cases */
3980 if (req_rate > min_pf_rate) {
3981 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3982 "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
3983 vport_id, req_rate, min_pf_rate);
3987 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
3988 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3989 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3990 vport_id, req_rate, min_pf_rate);
3994 /* TBD - for number of vports greater than 100 */
3995 if (num_vports > ECORE_WFQ_UNIT) {
3996 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3997 "Number of vports is greater than %d\n",
4002 if (total_req_min_rate > min_pf_rate) {
4003 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4004 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4005 total_req_min_rate, min_pf_rate);
4009 /* Data left for non requested vports */
4010 total_left_rate = min_pf_rate - total_req_min_rate;
4011 left_rate_per_vp = total_left_rate / non_requested_count;
4013 /* validate if non requested get < 1% of min bw */
4014 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4015 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4016 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4017 left_rate_per_vp, min_pf_rate);
4021 /* now req_rate for given vport passes all scenarios.
4022 * assign final wfq rates to all vports.
4024 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4025 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4027 for (i = 0; i < num_vports; i++) {
4028 if (p_hwfn->qm_info.wfq_data[i].configured)
4031 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4034 return ECORE_SUCCESS;
4037 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4038 struct ecore_ptt *p_ptt,
4039 u16 vp_id, u32 rate)
4041 struct ecore_mcp_link_state *p_link;
4042 int rc = ECORE_SUCCESS;
4044 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4046 if (!p_link->min_pf_rate) {
4047 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4048 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4052 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4054 if (rc == ECORE_SUCCESS)
4055 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4056 p_link->min_pf_rate);
4058 DP_NOTICE(p_hwfn, false,
4059 "Validation failed while configuring min rate\n");
4064 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4065 struct ecore_ptt *p_ptt,
4068 bool use_wfq = false;
4069 int rc = ECORE_SUCCESS;
4072 /* Validate all pre configured vports for wfq */
4073 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4076 if (!p_hwfn->qm_info.wfq_data[i].configured)
4079 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4082 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4083 if (rc != ECORE_SUCCESS) {
4084 DP_NOTICE(p_hwfn, false,
4085 "WFQ validation failed while configuring min rate\n");
4090 if (rc == ECORE_SUCCESS && use_wfq)
4091 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4093 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4098 /* Main API for ecore clients to configure vport min rate.
4099 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4100 * rate - Speed in Mbps needs to be assigned to a given vport.
4102 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4104 int i, rc = ECORE_INVAL;
4106 /* TBD - for multiple hardware functions - that is 100 gig */
4107 if (p_dev->num_hwfns > 1) {
4108 DP_NOTICE(p_dev, false,
4109 "WFQ configuration is not supported for this device\n");
4113 for_each_hwfn(p_dev, i) {
4114 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4115 struct ecore_ptt *p_ptt;
4117 p_ptt = ecore_ptt_acquire(p_hwfn);
4119 return ECORE_TIMEOUT;
4121 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4123 if (rc != ECORE_SUCCESS) {
4124 ecore_ptt_release(p_hwfn, p_ptt);
4128 ecore_ptt_release(p_hwfn, p_ptt);
4134 /* API to configure WFQ from mcp link change */
4135 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4140 /* TBD - for multiple hardware functions - that is 100 gig */
4141 if (p_dev->num_hwfns > 1) {
4142 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4143 "WFQ configuration is not supported for this device\n");
4147 for_each_hwfn(p_dev, i) {
4148 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4150 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4156 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4157 struct ecore_ptt *p_ptt,
4158 struct ecore_mcp_link_state *p_link,
4161 int rc = ECORE_SUCCESS;
4163 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4165 if (!p_link->line_speed && (max_bw != 100))
4168 p_link->speed = (p_link->line_speed * max_bw) / 100;
4169 p_hwfn->qm_info.pf_rl = p_link->speed;
4171 /* Since the limiter also affects Tx-switched traffic, we don't want it
4172 * to limit such traffic in case there's no actual limit.
4173 * In that case, set limit to imaginary high boundary.
4176 p_hwfn->qm_info.pf_rl = 100000;
4178 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4179 p_hwfn->qm_info.pf_rl);
4181 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4182 "Configured MAX bandwidth to be %08x Mb/sec\n",
4188 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4189 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4191 int i, rc = ECORE_INVAL;
4193 if (max_bw < 1 || max_bw > 100) {
4194 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4198 for_each_hwfn(p_dev, i) {
4199 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4200 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4201 struct ecore_mcp_link_state *p_link;
4202 struct ecore_ptt *p_ptt;
4204 p_link = &p_lead->mcp_info->link_output;
4206 p_ptt = ecore_ptt_acquire(p_hwfn);
4208 return ECORE_TIMEOUT;
4210 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4213 ecore_ptt_release(p_hwfn, p_ptt);
4215 if (rc != ECORE_SUCCESS)
4222 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4223 struct ecore_ptt *p_ptt,
4224 struct ecore_mcp_link_state *p_link,
4227 int rc = ECORE_SUCCESS;
4229 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4230 p_hwfn->qm_info.pf_wfq = min_bw;
4232 if (!p_link->line_speed)
4235 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4237 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4239 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4240 "Configured MIN bandwidth to be %d Mb/sec\n",
4241 p_link->min_pf_rate);
4246 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4247 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4249 int i, rc = ECORE_INVAL;
4251 if (min_bw < 1 || min_bw > 100) {
4252 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4256 for_each_hwfn(p_dev, i) {
4257 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4258 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4259 struct ecore_mcp_link_state *p_link;
4260 struct ecore_ptt *p_ptt;
4262 p_link = &p_lead->mcp_info->link_output;
4264 p_ptt = ecore_ptt_acquire(p_hwfn);
4266 return ECORE_TIMEOUT;
4268 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4270 if (rc != ECORE_SUCCESS) {
4271 ecore_ptt_release(p_hwfn, p_ptt);
4275 if (p_link->min_pf_rate) {
4276 u32 min_rate = p_link->min_pf_rate;
4278 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4283 ecore_ptt_release(p_hwfn, p_ptt);
4289 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4291 struct ecore_mcp_link_state *p_link;
4293 p_link = &p_hwfn->mcp_info->link_output;
4295 if (p_link->min_pf_rate)
4296 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4297 p_link->min_pf_rate);
4299 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4300 sizeof(*p_hwfn->qm_info.wfq_data) *
4301 p_hwfn->qm_info.num_vports);
4304 int ecore_device_num_engines(struct ecore_dev *p_dev)
4306 return ECORE_IS_BB(p_dev) ? 2 : 1;
4309 int ecore_device_num_ports(struct ecore_dev *p_dev)
4311 /* in CMT always only one port */
4312 if (p_dev->num_hwfns > 1)
4315 return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
4318 void ecore_set_fw_mac_addr(__le16 *fw_msb,
4323 ((u8 *)fw_msb)[0] = mac[1];
4324 ((u8 *)fw_msb)[1] = mac[0];
4325 ((u8 *)fw_mid)[0] = mac[3];
4326 ((u8 *)fw_mid)[1] = mac[2];
4327 ((u8 *)fw_lsb)[0] = mac[5];
4328 ((u8 *)fw_lsb)[1] = mac[4];