drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dev_api.h"
  32 #include "ecore_dcbx.h"
  33 #include "ecore_l2.h"
  34
  35 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  36  * registers involved are not split and thus configuration is a race where
  37  * some of the PFs configuration might be lost.
  38  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  39  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  40  * there's more than a single compiled ecore component in system].
  41  */
  42 static osal_spinlock_t qm_lock;
  43 static bool qm_lock_init;
  44
  45 /* Configurable */
  46 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
  47                                          * load the driver. The number was
  48                                          * arbitrarily set.
  49                                          */
  50
  51 /* Derived */
  52 #define ECORE_MIN_PWM_REGION    ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
  53
  54 enum BAR_ID {
  55         BAR_ID_0,               /* used for GRC */
  56         BAR_ID_1                /* Used for doorbells */
  57 };
  58
  59 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
  60                              struct ecore_ptt *p_ptt,
  61                              enum BAR_ID bar_id)
  62 {
  63         u32 bar_reg = (bar_id == BAR_ID_0 ?
  64                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  65         u32 val;
  66
  67         if (IS_VF(p_hwfn->p_dev)) {
  68                 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
  69                  * read from actual register, but we're currently not using
  70                  * it for actual doorbelling.
  71                  */
  72                 return 1 << 17;
  73         }
  74
  75         val = ecore_rd(p_hwfn, p_ptt, bar_reg);
  76         if (val)
  77                 return 1 << (val + 15);
  78
  79         /* The above registers were updated in the past only in CMT mode. Since
  80          * they were found to be useful MFW started updating them from 8.7.7.0.
  81          * In older MFW versions they are set to 0 which means disabled.
  82          */
  83         if (p_hwfn->p_dev->num_hwfns > 1) {
  84                 DP_INFO(p_hwfn,
  85                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
  86                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  87         } else {
  88                 DP_INFO(p_hwfn,
  89                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
  90                 val = 512 * 1024;
  91         }
  92
  93         return val;
  94 }
  95
  96 void ecore_init_dp(struct ecore_dev *p_dev,
  97                    u32 dp_module, u8 dp_level, void *dp_ctx)
  98 {
  99         u32 i;
 100
 101         p_dev->dp_level = dp_level;
 102         p_dev->dp_module = dp_module;
 103         p_dev->dp_ctx = dp_ctx;
 104         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 105                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 106
 107                 p_hwfn->dp_level = dp_level;
 108                 p_hwfn->dp_module = dp_module;
 109                 p_hwfn->dp_ctx = dp_ctx;
 110         }
 111 }
 112
 113 void ecore_init_struct(struct ecore_dev *p_dev)
 114 {
 115         u8 i;
 116
 117         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 118                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 119
 120                 p_hwfn->p_dev = p_dev;
 121                 p_hwfn->my_id = i;
 122                 p_hwfn->b_active = false;
 123
 124 #ifdef CONFIG_ECORE_LOCK_ALLOC
 125                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 126 #endif
 127                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 128         }
 129
 130         /* hwfn 0 is always active */
 131         p_dev->hwfns[0].b_active = true;
 132
 133         /* set the default cache alignment to 128 (may be overridden later) */
 134         p_dev->cache_shift = 7;
 135 }
 136
 137 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 138 {
 139         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 140
 141         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 142         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 143         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 144         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 145 }
 146
 147 void ecore_resc_free(struct ecore_dev *p_dev)
 148 {
 149         int i;
 150
 151         if (IS_VF(p_dev)) {
 152                 for_each_hwfn(p_dev, i)
 153                         ecore_l2_free(&p_dev->hwfns[i]);
 154                 return;
 155         }
 156
 157         OSAL_FREE(p_dev, p_dev->fw_data);
 158
 159         OSAL_FREE(p_dev, p_dev->reset_stats);
 160
 161         for_each_hwfn(p_dev, i) {
 162                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 163
 164                 ecore_cxt_mngr_free(p_hwfn);
 165                 ecore_qm_info_free(p_hwfn);
 166                 ecore_spq_free(p_hwfn);
 167                 ecore_eq_free(p_hwfn);
 168                 ecore_consq_free(p_hwfn);
 169                 ecore_int_free(p_hwfn);
 170                 ecore_iov_free(p_hwfn);
 171                 ecore_l2_free(p_hwfn);
 172                 ecore_dmae_info_free(p_hwfn);
 173                 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 174                 /* @@@TBD Flush work-queue ? */
 175         }
 176 }
 177
 178 /******************** QM initialization *******************/
 179
 180 /* bitmaps for indicating active traffic classes.
 181  * Special case for Arrowhead 4 port
 182  */
 183 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
 184 #define ACTIVE_TCS_BMAP 0x9f
 185 /* 0..3 actually used, OOO and high priority stuff all use 3 */
 186 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 187
 188 /* determines the physical queue flags for a given PF. */
 189 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
 190 {
 191         u32 flags;
 192
 193         /* common flags */
 194         flags = PQ_FLAGS_LB;
 195
 196         /* feature flags */
 197         if (IS_ECORE_SRIOV(p_hwfn->p_dev))
 198                 flags |= PQ_FLAGS_VFS;
 199
 200         /* protocol flags */
 201         switch (p_hwfn->hw_info.personality) {
 202         case ECORE_PCI_ETH:
 203                 flags |= PQ_FLAGS_MCOS;
 204                 break;
 205         case ECORE_PCI_FCOE:
 206                 flags |= PQ_FLAGS_OFLD;
 207                 break;
 208         case ECORE_PCI_ISCSI:
 209                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 210                 break;
 211         case ECORE_PCI_ETH_ROCE:
 212                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
 213                 break;
 214         case ECORE_PCI_ETH_IWARP:
 215                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 216                          PQ_FLAGS_OFLD;
 217                 break;
 218         default:
 219                 DP_ERR(p_hwfn, "unknown personality %d\n",
 220                        p_hwfn->hw_info.personality);
 221                 return 0;
 222         }
 223         return flags;
 224 }
 225
 226 /* Getters for resource amounts necessary for qm initialization */
 227 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
 228 {
 229         return p_hwfn->hw_info.num_hw_tc;
 230 }
 231
 232 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
 233 {
 234         return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
 235                         p_hwfn->p_dev->p_iov_info->total_vfs : 0;
 236 }
 237
 238 #define NUM_DEFAULT_RLS 1
 239
 240 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
 241 {
 242         u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 243
 244         /* @DPDK */
 245         /* num RLs can't exceed resource amount of rls or vports or the
 246          * dcqcn qps
 247          */
 248         num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 249                                      (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
 250
 251         /* make sure after we reserve the default and VF rls we'll have
 252          * something left
 253          */
 254         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
 255                 DP_NOTICE(p_hwfn, false,
 256                           "no rate limiters left for PF rate limiting"
 257                           " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
 258                 return 0;
 259         }
 260
 261         /* subtract rls necessary for VFs and one default one for the PF */
 262         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 263
 264         return num_pf_rls;
 265 }
 266
 267 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
 268 {
 269         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 270
 271         /* all pqs share the same vport (hence the 1 below), except for vfs
 272          * and pf_rl pqs
 273          */
 274         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 275                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 276                (!!(PQ_FLAGS_VFS & pq_flags)) *
 277                 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
 278 }
 279
 280 /* calc amount of PQs according to the requested flags */
 281 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
 282 {
 283         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 284
 285         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 286                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 287                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 288                 ecore_init_qm_get_num_tcs(p_hwfn) +
 289                (!!(PQ_FLAGS_LB & pq_flags)) +
 290                (!!(PQ_FLAGS_OOO & pq_flags)) +
 291                (!!(PQ_FLAGS_ACK & pq_flags)) +
 292                (!!(PQ_FLAGS_OFLD & pq_flags)) +
 293                (!!(PQ_FLAGS_VFS & pq_flags)) *
 294                 ecore_init_qm_get_num_vfs(p_hwfn);
 295 }
 296
 297 /* initialize the top level QM params */
 298 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
 299 {
 300         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 301         bool four_port;
 302
 303         /* pq and vport bases for this PF */
 304         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 305         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 306
 307         /* rate limiting and weighted fair queueing are always enabled */
 308         qm_info->vport_rl_en = 1;
 309         qm_info->vport_wfq_en = 1;
 310
 311         /* TC config is different for AH 4 port */
 312         four_port = p_hwfn->p_dev->num_ports_in_engines == MAX_NUM_PORTS_K2;
 313
 314         /* in AH 4 port we have fewer TCs per port */
 315         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 316                                                      NUM_OF_PHYS_TCS;
 317
 318         /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
 319          * 4 otherwise
 320          */
 321         if (!qm_info->ooo_tc)
 322                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 323                                               DCBX_TCP_OOO_TC;
 324 }
 325
 326 /* initialize qm vport params */
 327 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
 328 {
 329         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 330         u8 i;
 331
 332         /* all vports participate in weighted fair queueing */
 333         for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
 334                 qm_info->qm_vport_params[i].vport_wfq = 1;
 335 }
 336
 337 /* initialize qm port params */
 338 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
 339 {
 340         /* Initialize qm port parameters */
 341         u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engines;
 342
 343         /* indicate how ooo and high pri traffic is dealt with */
 344         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 345                 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
 346
 347         for (i = 0; i < num_ports; i++) {
 348                 struct init_qm_port_params *p_qm_port =
 349                         &p_hwfn->qm_info.qm_port_params[i];
 350
 351                 p_qm_port->active = 1;
 352                 p_qm_port->active_phys_tcs = active_phys_tcs;
 353                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 354                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 355         }
 356 }
 357
 358 /* Reset the params which must be reset for qm init. QM init may be called as
 359  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 360  * params may be affected by the init but would simply recalculate to the same
 361  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 362  * affected as these amounts stay the same.
 363  */
 364 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
 365 {
 366         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 367
 368         qm_info->num_pqs = 0;
 369         qm_info->num_vports = 0;
 370         qm_info->num_pf_rls = 0;
 371         qm_info->num_vf_pqs = 0;
 372         qm_info->first_vf_pq = 0;
 373         qm_info->first_mcos_pq = 0;
 374         qm_info->first_rl_pq = 0;
 375 }
 376
 377 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
 378 {
 379         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 380
 381         qm_info->num_vports++;
 382
 383         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 384                 DP_ERR(p_hwfn,
 385                        "vport overflow! qm_info->num_vports %d,"
 386                        " qm_init_get_num_vports() %d\n",
 387                        qm_info->num_vports,
 388                        ecore_init_qm_get_num_vports(p_hwfn));
 389 }
 390
 391 /* initialize a single pq and manage qm_info resources accounting.
 392  * The pq_init_flags param determines whether the PQ is rate limited
 393  * (for VF or PF)
 394  * and whether a new vport is allocated to the pq or not (i.e. vport will be
 395  * shared)
 396  */
 397
 398 /* flags for pq init */
 399 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 400 #define PQ_INIT_PF_RL           (1 << 1)
 401 #define PQ_INIT_VF_RL           (1 << 2)
 402
 403 /* defines for pq init */
 404 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 405 #define PQ_INIT_DEFAULT_TC              0
 406 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 407
 408 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
 409                              struct ecore_qm_info *qm_info,
 410                              u8 tc, u32 pq_init_flags)
 411 {
 412         u16 pq_idx = qm_info->num_pqs, max_pq =
 413                                         ecore_init_qm_get_num_pqs(p_hwfn);
 414
 415         if (pq_idx > max_pq)
 416                 DP_ERR(p_hwfn,
 417                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 418
 419         /* init pq params */
 420         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 421                                                  qm_info->num_vports;
 422         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 423         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 424         qm_info->qm_pq_params[pq_idx].rl_valid =
 425                 (pq_init_flags & PQ_INIT_PF_RL ||
 426                  pq_init_flags & PQ_INIT_VF_RL);
 427
 428         /* qm params accounting */
 429         qm_info->num_pqs++;
 430         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 431                 qm_info->num_vports++;
 432
 433         if (pq_init_flags & PQ_INIT_PF_RL)
 434                 qm_info->num_pf_rls++;
 435
 436         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 437                 DP_ERR(p_hwfn,
 438                        "vport overflow! qm_info->num_vports %d,"
 439                        " qm_init_get_num_vports() %d\n",
 440                        qm_info->num_vports,
 441                        ecore_init_qm_get_num_vports(p_hwfn));
 442
 443         if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
 444                 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
 445                        " qm_init_get_num_pf_rls() %d\n",
 446                        qm_info->num_pf_rls,
 447                        ecore_init_qm_get_num_pf_rls(p_hwfn));
 448 }
 449
 450 /* get pq index according to PQ_FLAGS */
 451 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
 452                                              u32 pq_flags)
 453 {
 454         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 455
 456         /* Can't have multiple flags set here */
 457         if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
 458                                 sizeof(pq_flags)) > 1)
 459                 goto err;
 460
 461         switch (pq_flags) {
 462         case PQ_FLAGS_RLS:
 463                 return &qm_info->first_rl_pq;
 464         case PQ_FLAGS_MCOS:
 465                 return &qm_info->first_mcos_pq;
 466         case PQ_FLAGS_LB:
 467                 return &qm_info->pure_lb_pq;
 468         case PQ_FLAGS_OOO:
 469                 return &qm_info->ooo_pq;
 470         case PQ_FLAGS_ACK:
 471                 return &qm_info->pure_ack_pq;
 472         case PQ_FLAGS_OFLD:
 473                 return &qm_info->offload_pq;
 474         case PQ_FLAGS_VFS:
 475                 return &qm_info->first_vf_pq;
 476         default:
 477                 goto err;
 478         }
 479
 480 err:
 481         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 482         return OSAL_NULL;
 483 }
 484
 485 /* save pq index in qm info */
 486 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
 487                                   u32 pq_flags, u16 pq_val)
 488 {
 489         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 490
 491         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 492 }
 493
 494 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 495 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
 496 {
 497         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 498
 499         return *base_pq_idx + CM_TX_PQ_BASE;
 500 }
 501
 502 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
 503 {
 504         u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
 505
 506         if (tc > max_tc)
 507                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 508
 509         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 510 }
 511
 512 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
 513 {
 514         u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
 515
 516         if (vf > max_vf)
 517                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 518
 519         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 520 }
 521
 522 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
 523 {
 524         u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
 525
 526         if (rl > max_rl)
 527                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 528
 529         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 530 }
 531
 532 /* Functions for creating specific types of pqs */
 533 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
 534 {
 535         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 536
 537         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 538                 return;
 539
 540         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 541         ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 542 }
 543
 544 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
 545 {
 546         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 547
 548         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 549                 return;
 550
 551         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 552         ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 553 }
 554
 555 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
 556 {
 557         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 558
 559         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 560                 return;
 561
 562         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 563         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 564 }
 565
 566 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
 567 {
 568         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 569
 570         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 571                 return;
 572
 573         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 574         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 575 }
 576
 577 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
 578 {
 579         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 580         u8 tc_idx;
 581
 582         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 583                 return;
 584
 585         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 586         for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 587                 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 588 }
 589
 590 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
 591 {
 592         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 593         u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 594
 595         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 596                 return;
 597
 598         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 599
 600         qm_info->num_vf_pqs = num_vfs;
 601         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 602                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
 603                                  PQ_INIT_VF_RL);
 604 }
 605
 606 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
 607 {
 608         u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
 609         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 610
 611         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 612                 return;
 613
 614         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 615         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 616                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
 617                                  PQ_INIT_PF_RL);
 618 }
 619
 620 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
 621 {
 622         /* rate limited pqs, must come first (FW assumption) */
 623         ecore_init_qm_rl_pqs(p_hwfn);
 624
 625         /* pqs for multi cos */
 626         ecore_init_qm_mcos_pqs(p_hwfn);
 627
 628         /* pure loopback pq */
 629         ecore_init_qm_lb_pq(p_hwfn);
 630
 631         /* out of order pq */
 632         ecore_init_qm_ooo_pq(p_hwfn);
 633
 634         /* pure ack pq */
 635         ecore_init_qm_pure_ack_pq(p_hwfn);
 636
 637         /* pq for offloaded protocol */
 638         ecore_init_qm_offload_pq(p_hwfn);
 639
 640         /* done sharing vports */
 641         ecore_init_qm_advance_vport(p_hwfn);
 642
 643         /* pqs for vfs */
 644         ecore_init_qm_vf_pqs(p_hwfn);
 645 }
 646
 647 /* compare values of getters against resources amounts */
 648 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
 649 {
 650         if (ecore_init_qm_get_num_vports(p_hwfn) >
 651             RESC_NUM(p_hwfn, ECORE_VPORT)) {
 652                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 653                 return ECORE_INVAL;
 654         }
 655
 656         if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
 657                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 658                 return ECORE_INVAL;
 659         }
 660
 661         return ECORE_SUCCESS;
 662 }
 663
 664 /*
 665  * Function for verbose printing of the qm initialization results
 666  */
 667 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
 668 {
 669         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 670         struct init_qm_vport_params *vport;
 671         struct init_qm_port_params *port;
 672         struct init_qm_pq_params *pq;
 673         int i, tc;
 674
 675         /* top level params */
 676         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 677                    "qm init top level params: start_pq %d, start_vport %d,"
 678                    " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 679                    qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
 680                    qm_info->offload_pq, qm_info->pure_ack_pq);
 681         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 682                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
 683                    " num_vports %d, max_phys_tcs_per_port %d\n",
 684                    qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
 685                    qm_info->num_vf_pqs, qm_info->num_vports,
 686                    qm_info->max_phys_tcs_per_port);
 687         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 688                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
 689                    " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
 690                    qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
 691                    qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
 692                    qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
 693
 694         /* port table */
 695         for (i = 0; i < p_hwfn->p_dev->num_ports_in_engines; i++) {
 696                 port = &qm_info->qm_port_params[i];
 697                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 698                            "port idx %d, active %d, active_phys_tcs %d,"
 699                            " num_pbf_cmd_lines %d, num_btb_blocks %d,"
 700                            " reserved %d\n",
 701                            i, port->active, port->active_phys_tcs,
 702                            port->num_pbf_cmd_lines, port->num_btb_blocks,
 703                            port->reserved);
 704         }
 705
 706         /* vport table */
 707         for (i = 0; i < qm_info->num_vports; i++) {
 708                 vport = &qm_info->qm_vport_params[i];
 709                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 710                            "vport idx %d, vport_rl %d, wfq %d,"
 711                            " first_tx_pq_id [ ",
 712                            qm_info->start_vport + i, vport->vport_rl,
 713                            vport->vport_wfq);
 714                 for (tc = 0; tc < NUM_OF_TCS; tc++)
 715                         DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
 716                                    vport->first_tx_pq_id[tc]);
 717                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
 718         }
 719
 720         /* pq table */
 721         for (i = 0; i < qm_info->num_pqs; i++) {
 722                 pq = &qm_info->qm_pq_params[i];
 723                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 724                            "pq idx %d, vport_id %d, tc %d, wrr_grp %d,"
 725                            " rl_valid %d\n",
 726                            qm_info->start_pq + i, pq->vport_id, pq->tc_id,
 727                            pq->wrr_group, pq->rl_valid);
 728         }
 729 }
 730
 731 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
 732 {
 733         /* reset params required for init run */
 734         ecore_init_qm_reset_params(p_hwfn);
 735
 736         /* init QM top level params */
 737         ecore_init_qm_params(p_hwfn);
 738
 739         /* init QM port params */
 740         ecore_init_qm_port_params(p_hwfn);
 741
 742         /* init QM vport params */
 743         ecore_init_qm_vport_params(p_hwfn);
 744
 745         /* init QM physical queue params */
 746         ecore_init_qm_pq_params(p_hwfn);
 747
 748         /* display all that init */
 749         ecore_dp_init_qm_params(p_hwfn);
 750 }
 751
 752 /* This function reconfigures the QM pf on the fly.
 753  * For this purpose we:
 754  * 1. reconfigure the QM database
 755  * 2. set new values to runtime array
 756  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 757  * 4. activate init tool in QM_PF stage
 758  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 759  */
 760 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
 761                                      struct ecore_ptt *p_ptt)
 762 {
 763         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 764         bool b_rc;
 765         enum _ecore_status_t rc;
 766
 767         /* initialize ecore's qm data structure */
 768         ecore_init_qm_info(p_hwfn);
 769
 770         /* stop PF's qm queues */
 771         OSAL_SPIN_LOCK(&qm_lock);
 772         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 773                                       qm_info->start_pq, qm_info->num_pqs);
 774         OSAL_SPIN_UNLOCK(&qm_lock);
 775         if (!b_rc)
 776                 return ECORE_INVAL;
 777
 778         /* clear the QM_PF runtime phase leftovers from previous init */
 779         ecore_init_clear_rt_data(p_hwfn);
 780
 781         /* prepare QM portion of runtime array */
 782         ecore_qm_init_pf(p_hwfn, p_ptt);
 783
 784         /* activate init tool on runtime array */
 785         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 786                             p_hwfn->hw_info.hw_mode);
 787         if (rc != ECORE_SUCCESS)
 788                 return rc;
 789
 790         /* start PF's qm queues */
 791         OSAL_SPIN_LOCK(&qm_lock);
 792         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 793                                       qm_info->start_pq, qm_info->num_pqs);
 794         OSAL_SPIN_UNLOCK(&qm_lock);
 795         if (!b_rc)
 796                 return ECORE_INVAL;
 797
 798         return ECORE_SUCCESS;
 799 }
 800
 801 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
 802 {
 803         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 804         enum _ecore_status_t rc;
 805
 806         rc = ecore_init_qm_sanity(p_hwfn);
 807         if (rc != ECORE_SUCCESS)
 808                 goto alloc_err;
 809
 810         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 811                                             sizeof(struct init_qm_pq_params) *
 812                                             ecore_init_qm_get_num_pqs(p_hwfn));
 813         if (!qm_info->qm_pq_params)
 814                 goto alloc_err;
 815
 816         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 817                                        sizeof(struct init_qm_vport_params) *
 818                                        ecore_init_qm_get_num_vports(p_hwfn));
 819         if (!qm_info->qm_vport_params)
 820                 goto alloc_err;
 821
 822         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 823                                       sizeof(struct init_qm_port_params) *
 824                                       p_hwfn->p_dev->num_ports_in_engines);
 825         if (!qm_info->qm_port_params)
 826                 goto alloc_err;
 827
 828         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 829                                         sizeof(struct ecore_wfq_data) *
 830                                         ecore_init_qm_get_num_vports(p_hwfn));
 831         if (!qm_info->wfq_data)
 832                 goto alloc_err;
 833
 834         return ECORE_SUCCESS;
 835
 836 alloc_err:
 837         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
 838         ecore_qm_info_free(p_hwfn);
 839         return ECORE_NOMEM;
 840 }
 841 /******************** End QM initialization ***************/
 842
 843 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
 844 {
 845         enum _ecore_status_t rc = ECORE_SUCCESS;
 846         int i;
 847
 848         if (IS_VF(p_dev)) {
 849                 for_each_hwfn(p_dev, i) {
 850                         rc = ecore_l2_alloc(&p_dev->hwfns[i]);
 851                         if (rc != ECORE_SUCCESS)
 852                                 return rc;
 853                 }
 854                 return rc;
 855         }
 856
 857         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 858                                      sizeof(*p_dev->fw_data));
 859         if (!p_dev->fw_data)
 860                 return ECORE_NOMEM;
 861
 862         for_each_hwfn(p_dev, i) {
 863                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 864                 u32 n_eqes, num_cons;
 865
 866                 /* First allocate the context manager structure */
 867                 rc = ecore_cxt_mngr_alloc(p_hwfn);
 868                 if (rc)
 869                         goto alloc_err;
 870
 871                 /* Set the HW cid/tid numbers (in the contest manager)
 872                  * Must be done prior to any further computations.
 873                  */
 874                 rc = ecore_cxt_set_pf_params(p_hwfn);
 875                 if (rc)
 876                         goto alloc_err;
 877
 878                 rc = ecore_alloc_qm_data(p_hwfn);
 879                 if (rc)
 880                         goto alloc_err;
 881
 882                 /* init qm info */
 883                 ecore_init_qm_info(p_hwfn);
 884
 885                 /* Compute the ILT client partition */
 886                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
 887                 if (rc)
 888                         goto alloc_err;
 889
 890                 /* CID map / ILT shadow table / T2
 891                  * The talbes sizes are determined by the computations above
 892                  */
 893                 rc = ecore_cxt_tables_alloc(p_hwfn);
 894                 if (rc)
 895                         goto alloc_err;
 896
 897                 /* SPQ, must follow ILT because initializes SPQ context */
 898                 rc = ecore_spq_alloc(p_hwfn);
 899                 if (rc)
 900                         goto alloc_err;
 901
 902                 /* SP status block allocation */
 903                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
 904                                                            RESERVED_PTT_DPC);
 905
 906                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 907                 if (rc)
 908                         goto alloc_err;
 909
 910                 rc = ecore_iov_alloc(p_hwfn);
 911                 if (rc)
 912                         goto alloc_err;
 913
 914                 /* EQ */
 915                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
 916                 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
 917                         /* Calculate the EQ size
 918                          * ---------------------
 919                          * Each ICID may generate up to one event at a time i.e.
 920                          * the event must be handled/cleared before a new one
 921                          * can be generated. We calculate the sum of events per
 922                          * protocol and create an EQ deep enough to handle the
 923                          * worst case:
 924                          * - Core - according to SPQ.
 925                          * - RoCE - per QP there are a couple of ICIDs, one
 926                          *        responder and one requester, each can
 927                          *        generate an EQE => n_eqes_qp = 2 * n_qp.
 928                          *        Each CQ can generate an EQE. There are 2 CQs
 929                          *        per QP => n_eqes_cq = 2 * n_qp.
 930                          *        Hence the RoCE total is 4 * n_qp or
 931                          *        2 * num_cons.
 932                          * - ENet - There can be up to two events per VF. One
 933                          *        for VF-PF channel and another for VF FLR
 934                          *        initial cleanup. The number of VFs is
 935                          *        bounded by MAX_NUM_VFS_BB, and is much
 936                          *        smaller than RoCE's so we avoid exact
 937                          *        calculation.
 938                          */
 939                         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
 940                                 num_cons =
 941                                     ecore_cxt_get_proto_cid_count(
 942                                                 p_hwfn,
 943                                                 PROTOCOLID_ROCE,
 944                                                 OSAL_NULL);
 945                                 num_cons *= 2;
 946                         } else {
 947                                 num_cons = ecore_cxt_get_proto_cid_count(
 948                                                 p_hwfn,
 949                                                 PROTOCOLID_IWARP,
 950                                                 OSAL_NULL);
 951                         }
 952                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 953                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 954                         num_cons =
 955                             ecore_cxt_get_proto_cid_count(p_hwfn,
 956                                                           PROTOCOLID_ISCSI,
 957                                                           OSAL_NULL);
 958                         n_eqes += 2 * num_cons;
 959                 }
 960
 961                 if (n_eqes > 0xFFFF) {
 962                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
 963                                        "The maximum of a u16 chain is 0x%x\n",
 964                                n_eqes, 0xFFFF);
 965                         goto alloc_no_mem;
 966                 }
 967
 968                 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
 969                 if (rc)
 970                         goto alloc_err;
 971
 972                 rc = ecore_consq_alloc(p_hwfn);
 973                 if (rc)
 974                         goto alloc_err;
 975
 976                 rc = ecore_l2_alloc(p_hwfn);
 977                 if (rc != ECORE_SUCCESS)
 978                         goto alloc_err;
 979
 980                 /* DMA info initialization */
 981                 rc = ecore_dmae_info_alloc(p_hwfn);
 982                 if (rc) {
 983                         DP_NOTICE(p_hwfn, true,
 984                                   "Failed to allocate memory for dmae_info"
 985                                   " structure\n");
 986                         goto alloc_err;
 987                 }
 988
 989                 /* DCBX initialization */
 990                 rc = ecore_dcbx_info_alloc(p_hwfn);
 991                 if (rc) {
 992                         DP_NOTICE(p_hwfn, true,
 993                                   "Failed to allocate memory for dcbx structure\n");
 994                         goto alloc_err;
 995                 }
 996         }
 997
 998         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 999                                          sizeof(*p_dev->reset_stats));
1000         if (!p_dev->reset_stats) {
1001                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
1002                 goto alloc_no_mem;
1003         }
1004
1005         return ECORE_SUCCESS;
1006
1007 alloc_no_mem:
1008         rc = ECORE_NOMEM;
1009 alloc_err:
1010         ecore_resc_free(p_dev);
1011         return rc;
1012 }
1013
1014 void ecore_resc_setup(struct ecore_dev *p_dev)
1015 {
1016         int i;
1017
1018         if (IS_VF(p_dev)) {
1019                 for_each_hwfn(p_dev, i)
1020                         ecore_l2_setup(&p_dev->hwfns[i]);
1021                 return;
1022         }
1023
1024         for_each_hwfn(p_dev, i) {
1025                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1026
1027                 ecore_cxt_mngr_setup(p_hwfn);
1028                 ecore_spq_setup(p_hwfn);
1029                 ecore_eq_setup(p_hwfn);
1030                 ecore_consq_setup(p_hwfn);
1031
1032                 /* Read shadow of current MFW mailbox */
1033                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1034                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1035                             p_hwfn->mcp_info->mfw_mb_cur,
1036                             p_hwfn->mcp_info->mfw_mb_length);
1037
1038                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1039
1040                 ecore_l2_setup(p_hwfn);
1041                 ecore_iov_setup(p_hwfn);
1042         }
1043 }
1044
1045 #define FINAL_CLEANUP_POLL_CNT  (100)
1046 #define FINAL_CLEANUP_POLL_TIME (10)
1047 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1048                                          struct ecore_ptt *p_ptt,
1049                                          u16 id, bool is_vf)
1050 {
1051         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1052         enum _ecore_status_t rc = ECORE_TIMEOUT;
1053
1054 #ifndef ASIC_ONLY
1055         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1056             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1057                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1058                 return ECORE_SUCCESS;
1059         }
1060 #endif
1061
1062         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1063             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1064
1065         if (is_vf)
1066                 id += 0x10;
1067
1068         command |= X_FINAL_CLEANUP_AGG_INT <<
1069             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1070         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1071         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1072         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1073
1074 /* Make sure notification is not set before initiating final cleanup */
1075
1076         if (REG_RD(p_hwfn, addr)) {
1077                 DP_NOTICE(p_hwfn, false,
1078                           "Unexpected; Found final cleanup notification");
1079                 DP_NOTICE(p_hwfn, false,
1080                           " before initiating final cleanup\n");
1081                 REG_WR(p_hwfn, addr, 0);
1082         }
1083
1084         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1085                    "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1086                    id, command);
1087
1088         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1089
1090         /* Poll until completion */
1091         while (!REG_RD(p_hwfn, addr) && count--)
1092                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1093
1094         if (REG_RD(p_hwfn, addr))
1095                 rc = ECORE_SUCCESS;
1096         else
1097                 DP_NOTICE(p_hwfn, true,
1098                           "Failed to receive FW final cleanup notification\n");
1099
1100         /* Cleanup afterwards */
1101         REG_WR(p_hwfn, addr, 0);
1102
1103         return rc;
1104 }
1105
1106 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1107 {
1108         int hw_mode = 0;
1109
1110         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1111                 hw_mode |= 1 << MODE_BB;
1112         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1113                 hw_mode |= 1 << MODE_K2;
1114         } else {
1115                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1116                           p_hwfn->p_dev->type);
1117                 return ECORE_INVAL;
1118         }
1119
1120         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1121         switch (p_hwfn->p_dev->num_ports_in_engines) {
1122         case 1:
1123                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1124                 break;
1125         case 2:
1126                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1127                 break;
1128         case 4:
1129                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1130                 break;
1131         default:
1132                 DP_NOTICE(p_hwfn, true,
1133                           "num_ports_in_engine = %d not supported\n",
1134                           p_hwfn->p_dev->num_ports_in_engines);
1135                 return ECORE_INVAL;
1136         }
1137
1138         switch (p_hwfn->p_dev->mf_mode) {
1139         case ECORE_MF_DEFAULT:
1140         case ECORE_MF_NPAR:
1141                 hw_mode |= 1 << MODE_MF_SI;
1142                 break;
1143         case ECORE_MF_OVLAN:
1144                 hw_mode |= 1 << MODE_MF_SD;
1145                 break;
1146         default:
1147                 DP_NOTICE(p_hwfn, true,
1148                           "Unsupported MF mode, init as DEFAULT\n");
1149                 hw_mode |= 1 << MODE_MF_SI;
1150         }
1151
1152 #ifndef ASIC_ONLY
1153         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1154                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1155                         hw_mode |= 1 << MODE_FPGA;
1156                 } else {
1157                         if (p_hwfn->p_dev->b_is_emul_full)
1158                                 hw_mode |= 1 << MODE_EMUL_FULL;
1159                         else
1160                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
1161                 }
1162         } else
1163 #endif
1164                 hw_mode |= 1 << MODE_ASIC;
1165
1166         if (p_hwfn->p_dev->num_hwfns > 1)
1167                 hw_mode |= 1 << MODE_100G;
1168
1169         p_hwfn->hw_info.hw_mode = hw_mode;
1170
1171         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1172                    "Configuring function for hw_mode: 0x%08x\n",
1173                    p_hwfn->hw_info.hw_mode);
1174
1175         return ECORE_SUCCESS;
1176 }
1177
1178 #ifndef ASIC_ONLY
1179 /* MFW-replacement initializations for non-ASIC */
1180 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1181                                                struct ecore_ptt *p_ptt)
1182 {
1183         struct ecore_dev *p_dev = p_hwfn->p_dev;
1184         u32 pl_hv = 1;
1185         int i;
1186
1187         if (CHIP_REV_IS_EMUL(p_dev)) {
1188                 if (ECORE_IS_AH(p_dev))
1189                         pl_hv |= 0x600;
1190         }
1191
1192         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1193
1194         if (CHIP_REV_IS_EMUL(p_dev) &&
1195             (ECORE_IS_AH(p_dev)))
1196                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1197                          0x3ffffff);
1198
1199         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1200         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1201         if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1202                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1203
1204         if (CHIP_REV_IS_EMUL(p_dev)) {
1205                 if (ECORE_IS_AH(p_dev)) {
1206                         /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1207                         ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1208                                  (p_dev->num_ports_in_engines >> 1));
1209
1210                         ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1211                                  p_dev->num_ports_in_engines == 4 ? 0 : 3);
1212                 }
1213         }
1214
1215         /* Poll on RBC */
1216         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1217         for (i = 0; i < 100; i++) {
1218                 OSAL_UDELAY(50);
1219                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1220                         break;
1221         }
1222         if (i == 100)
1223                 DP_NOTICE(p_hwfn, true,
1224                           "RBC done failed to complete in PSWRQ2\n");
1225
1226         return ECORE_SUCCESS;
1227 }
1228 #endif
1229
1230 /* Init run time data for all PFs and their VFs on an engine.
1231  * TBD - for VFs - Once we have parent PF info for each VF in
1232  * shmem available as CAU requires knowledge of parent PF for each VF.
1233  */
1234 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1235 {
1236         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1237         int i, igu_sb_id;
1238
1239         for_each_hwfn(p_dev, i) {
1240                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1241                 struct ecore_igu_info *p_igu_info;
1242                 struct ecore_igu_block *p_block;
1243                 struct cau_sb_entry sb_entry;
1244
1245                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1246
1247                 for (igu_sb_id = 0;
1248                      igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1249                      igu_sb_id++) {
1250                         p_block = &p_igu_info->entry[igu_sb_id];
1251
1252                         if (!p_block->is_pf)
1253                                 continue;
1254
1255                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1256                                                 p_block->function_id, 0, 0);
1257                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1258                                          sb_entry);
1259                 }
1260         }
1261 }
1262
1263 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
1264                                        struct ecore_ptt *p_ptt)
1265 {
1266         u32 val, wr_mbs, cache_line_size;
1267
1268         val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1269         switch (val) {
1270         case 0:
1271                 wr_mbs = 128;
1272                 break;
1273         case 1:
1274                 wr_mbs = 256;
1275                 break;
1276         case 2:
1277                 wr_mbs = 512;
1278                 break;
1279         default:
1280                 DP_INFO(p_hwfn,
1281                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1282                         val);
1283                 return;
1284         }
1285
1286         cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
1287         switch (cache_line_size) {
1288         case 32:
1289                 val = 0;
1290                 break;
1291         case 64:
1292                 val = 1;
1293                 break;
1294         case 128:
1295                 val = 2;
1296                 break;
1297         case 256:
1298                 val = 3;
1299                 break;
1300         default:
1301                 DP_INFO(p_hwfn,
1302                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1303                         cache_line_size);
1304         }
1305
1306         if (wr_mbs < OSAL_CACHE_LINE_SIZE)
1307                 DP_INFO(p_hwfn,
1308                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1309                         OSAL_CACHE_LINE_SIZE, wr_mbs);
1310
1311         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1312         if (val > 0) {
1313                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1314                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1315         }
1316 }
1317
1318 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1319                                                  struct ecore_ptt *p_ptt,
1320                                                  int hw_mode)
1321 {
1322         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1323         struct ecore_dev *p_dev = p_hwfn->p_dev;
1324         u8 vf_id, max_num_vfs;
1325         u16 num_pfs, pf_id;
1326         u32 concrete_fid;
1327         enum _ecore_status_t rc = ECORE_SUCCESS;
1328
1329         ecore_init_cau_rt_data(p_dev);
1330
1331         /* Program GTT windows */
1332         ecore_gtt_init(p_hwfn, p_ptt);
1333
1334 #ifndef ASIC_ONLY
1335         if (CHIP_REV_IS_EMUL(p_dev)) {
1336                 rc = ecore_hw_init_chip(p_hwfn, p_ptt);
1337                 if (rc != ECORE_SUCCESS)
1338                         return rc;
1339         }
1340 #endif
1341
1342         if (p_hwfn->mcp_info) {
1343                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1344                         qm_info->pf_rl_en = 1;
1345                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1346                         qm_info->pf_wfq_en = 1;
1347         }
1348
1349         ecore_qm_common_rt_init(p_hwfn,
1350                                 p_dev->num_ports_in_engines,
1351                                 qm_info->max_phys_tcs_per_port,
1352                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1353                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1354                                 qm_info->qm_port_params);
1355
1356         ecore_cxt_hw_init_common(p_hwfn);
1357
1358         ecore_init_cache_line_size(p_hwfn, p_ptt);
1359
1360         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1361         if (rc != ECORE_SUCCESS)
1362                 return rc;
1363
1364         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1365          * need to decide with which value, maybe runtime
1366          */
1367         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1368         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1369
1370         if (ECORE_IS_BB(p_dev)) {
1371                 /* Workaround clears ROCE search for all functions to prevent
1372                  * involving non initialized function in processing ROCE packet.
1373                  */
1374                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1375                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1376                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1377                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1378                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1379                 }
1380                 /* pretend to original PF */
1381                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1382         }
1383
1384         /* Workaround for avoiding CCFC execution error when getting packets
1385          * with CRC errors, and allowing instead the invoking of the FW error
1386          * handler.
1387          * This is not done inside the init tool since it currently can't
1388          * perform a pretending to VFs.
1389          */
1390         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1391         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1392                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1393                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1394                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1395                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1396                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1397                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1398         }
1399         /* pretend to original PF */
1400         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1401
1402         return rc;
1403 }
1404
1405 #ifndef ASIC_ONLY
1406 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1407 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1408
1409 #define PMEG_IF_BYTE_COUNT      8
1410
1411 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1412                              struct ecore_ptt *p_ptt,
1413                              u32 addr, u64 data, u8 reg_type, u8 port)
1414 {
1415         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1416                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1417                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1418                    (8 << PMEG_IF_BYTE_COUNT),
1419                    (reg_type << 25) | (addr << 8) | port,
1420                    (u32)((data >> 32) & 0xffffffff),
1421                    (u32)(data & 0xffffffff));
1422
1423         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1424                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1425                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1426         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1427                  (reg_type << 25) | (addr << 8) | port);
1428         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1429         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1430                  (data >> 32) & 0xffffffff);
1431 }
1432
1433 #define XLPORT_MODE_REG (0x20a)
1434 #define XLPORT_MAC_CONTROL (0x210)
1435 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1436 #define XLPORT_ENABLE_REG (0x20b)
1437
1438 #define XLMAC_CTRL (0x600)
1439 #define XLMAC_MODE (0x601)
1440 #define XLMAC_RX_MAX_SIZE (0x608)
1441 #define XLMAC_TX_CTRL (0x604)
1442 #define XLMAC_PAUSE_CTRL (0x60d)
1443 #define XLMAC_PFC_CTRL (0x60e)
1444
1445 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1446                                     struct ecore_ptt *p_ptt)
1447 {
1448         u8 loopback = 0, port = p_hwfn->port_id * 2;
1449
1450         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1451
1452         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1453         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1454                          port);
1455         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1456         /* XLMAC: SOFT RESET */
1457         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1458         /* XLMAC: Port Speed >= 10Gbps */
1459         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1460         /* XLMAC: Max Size */
1461         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1462         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1463                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1464                          0, port);
1465         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1466         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1467                          0x30ffffc000ULL, 0, port);
1468         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1469                          port); /* XLMAC: TX_EN, RX_EN */
1470         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1471         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1472                          0x1003 | (loopback << 2), 0, port);
1473         /* Enabled Parallel PFC interface */
1474         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1475
1476         /* XLPORT port enable */
1477         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1478 }
1479
1480 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1481                                        struct ecore_ptt *p_ptt)
1482 {
1483         u8 port = p_hwfn->port_id;
1484         u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1485
1486         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1487
1488         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1489                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1490                  (port <<
1491                   CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1492                  (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1493
1494         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1495                  1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1496
1497         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1498                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1499
1500         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1501                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1502
1503         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1504                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1505
1506         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1507                  (0xA <<
1508                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1509                  (8 <<
1510                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1511
1512         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1513                  0xa853);
1514 }
1515
1516 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1517                                  struct ecore_ptt *p_ptt)
1518 {
1519         if (ECORE_IS_AH(p_hwfn->p_dev))
1520                 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1521         else /* BB */
1522                 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1523 }
1524
1525 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1526                                struct ecore_ptt *p_ptt,  u8 port)
1527 {
1528         int port_offset = port ? 0x800 : 0;
1529         u32 xmac_rxctrl = 0;
1530
1531         /* Reset of XMAC */
1532         /* FIXME: move to common start */
1533         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1534                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1535         OSAL_MSLEEP(1);
1536         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1537                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1538
1539         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1540
1541         /* Set the number of ports on the Warp Core to 10G */
1542         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1543
1544         /* Soft reset of XMAC */
1545         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1546                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1547         OSAL_MSLEEP(1);
1548         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1549                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1550
1551         /* FIXME: move to common end */
1552         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1553                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1554
1555         /* Set Max packet size: initialize XMAC block register for port 0 */
1556         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1557
1558         /* CRC append for Tx packets: init XMAC block register for port 1 */
1559         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1560
1561         /* Enable TX and RX: initialize XMAC block register for port 1 */
1562         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1563                  XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1564         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1565                                XMAC_REG_RX_CTRL_BB + port_offset);
1566         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1567         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1568 }
1569 #endif
1570
1571 static enum _ecore_status_t
1572 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1573                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1574 {
1575         u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1576         u32 dpi_bit_shift, dpi_count;
1577         u32 min_dpis;
1578
1579         /* Calculate DPI size
1580          * ------------------
1581          * The PWM region contains Doorbell Pages. The first is reserverd for
1582          * the kernel for, e.g, L2. The others are free to be used by non-
1583          * trusted applications, typically from user space. Each page, called a
1584          * doorbell page is sectioned into windows that allow doorbells to be
1585          * issued in parallel by the kernel/application. The size of such a
1586          * window (a.k.a. WID) is 1kB.
1587          * Summary:
1588          *    1kB WID x N WIDS = DPI page size
1589          *    DPI page size x N DPIs = PWM region size
1590          * Notes:
1591          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1592          * in order to ensure that two applications won't share the same page.
1593          * It also must contain at least one WID per CPU to allow parallelism.
1594          * It also must be a power of 2, since it is stored as a bit shift.
1595          *
1596          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1597          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1598          * containing 4 WIDs.
1599          */
1600         dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1601         dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1602         dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1603         dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1604         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1605
1606         dpi_count = pwm_region_size / dpi_page_size;
1607
1608         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1609         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1610
1611         /* Update hwfn */
1612         p_hwfn->dpi_size = dpi_page_size;
1613         p_hwfn->dpi_count = dpi_count;
1614
1615         /* Update registers */
1616         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1617
1618         if (dpi_count < min_dpis)
1619                 return ECORE_NORESOURCES;
1620
1621         return ECORE_SUCCESS;
1622 }
1623
1624 enum ECORE_ROCE_EDPM_MODE {
1625         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1626         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1627         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1628 };
1629
1630 static enum _ecore_status_t
1631 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1632                               struct ecore_ptt *p_ptt)
1633 {
1634         u32 pwm_regsize, norm_regsize;
1635         u32 non_pwm_conn, min_addr_reg1;
1636         u32 db_bar_size, n_cpus;
1637         u32 roce_edpm_mode;
1638         u32 pf_dems_shift;
1639         enum _ecore_status_t rc = ECORE_SUCCESS;
1640         u8 cond;
1641
1642         db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1643         if (p_hwfn->p_dev->num_hwfns > 1)
1644                 db_bar_size /= 2;
1645
1646         /* Calculate doorbell regions
1647          * -----------------------------------
1648          * The doorbell BAR is made of two regions. The first is called normal
1649          * region and the second is called PWM region. In the normal region
1650          * each ICID has its own set of addresses so that writing to that
1651          * specific address identifies the ICID. In the Process Window Mode
1652          * region the ICID is given in the data written to the doorbell. The
1653          * above per PF register denotes the offset in the doorbell BAR in which
1654          * the PWM region begins.
1655          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1656          * non-PWM connection. The calculation below computes the total non-PWM
1657          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1658          * in units of 4,096 bytes.
1659          */
1660         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1661             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1662                                           OSAL_NULL) +
1663             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1664         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1665         min_addr_reg1 = norm_regsize / 4096;
1666         pwm_regsize = db_bar_size - norm_regsize;
1667
1668         /* Check that the normal and PWM sizes are valid */
1669         if (db_bar_size < norm_regsize) {
1670                 DP_ERR(p_hwfn->p_dev,
1671                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1672                        db_bar_size, norm_regsize);
1673                 return ECORE_NORESOURCES;
1674         }
1675         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1676                 DP_ERR(p_hwfn->p_dev,
1677                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1678                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1679                        norm_regsize);
1680                 return ECORE_NORESOURCES;
1681         }
1682
1683         /* Calculate number of DPIs */
1684         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1685         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1686             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1687                 /* Either EDPM is mandatory, or we are attempting to allocate a
1688                  * WID per CPU.
1689                  */
1690                 n_cpus = OSAL_NUM_ACTIVE_CPU();
1691                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1692         }
1693
1694         cond = ((rc != ECORE_SUCCESS) &&
1695                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1696                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1697         if (cond || p_hwfn->dcbx_no_edpm) {
1698                 /* Either EDPM is disabled from user configuration, or it is
1699                  * disabled via DCBx, or it is not mandatory and we failed to
1700                  * allocated a WID per CPU.
1701                  */
1702                 n_cpus = 1;
1703                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1704
1705                 /* If we entered this flow due to DCBX then the DPM register is
1706                  * already configured.
1707                  */
1708         }
1709
1710         DP_INFO(p_hwfn,
1711                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1712                 norm_regsize, pwm_regsize);
1713         DP_INFO(p_hwfn,
1714                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1715                 p_hwfn->dpi_size, p_hwfn->dpi_count,
1716                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1717                 "disabled" : "enabled");
1718
1719         /* Check return codes from above calls */
1720         if (rc != ECORE_SUCCESS) {
1721                 DP_ERR(p_hwfn,
1722                        "Failed to allocate enough DPIs\n");
1723                 return ECORE_NORESOURCES;
1724         }
1725
1726         /* Update hwfn */
1727         p_hwfn->dpi_start_offset = norm_regsize;
1728
1729         /* Update registers */
1730         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1731         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1732         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1733         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1734
1735         return ECORE_SUCCESS;
1736 }
1737
1738 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1739                                                struct ecore_ptt *p_ptt,
1740                                                int hw_mode)
1741 {
1742         enum _ecore_status_t rc = ECORE_SUCCESS;
1743
1744         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1745                             hw_mode);
1746         if (rc != ECORE_SUCCESS)
1747                 return rc;
1748
1749         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
1750
1751 #ifndef ASIC_ONLY
1752         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1753                 return ECORE_SUCCESS;
1754
1755         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1756                 if (ECORE_IS_AH(p_hwfn->p_dev))
1757                         return ECORE_SUCCESS;
1758                 else if (ECORE_IS_BB(p_hwfn->p_dev))
1759                         ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
1760         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1761                 if (p_hwfn->p_dev->num_hwfns > 1) {
1762                         /* Activate OPTE in CMT */
1763                         u32 val;
1764
1765                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1766                         val |= 0x10;
1767                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1768                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1769                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1770                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1771                         ecore_wr(p_hwfn, p_ptt,
1772                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1773                         ecore_wr(p_hwfn, p_ptt,
1774                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1775                         ecore_wr(p_hwfn, p_ptt,
1776                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1777                                  0x55555555);
1778                 }
1779
1780                 ecore_emul_link_init(p_hwfn, p_ptt);
1781         } else {
1782                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1783         }
1784 #endif
1785
1786         return rc;
1787 }
1788
1789 static enum _ecore_status_t
1790 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1791                  struct ecore_ptt *p_ptt,
1792                  struct ecore_tunnel_info *p_tunn,
1793                  int hw_mode,
1794                  bool b_hw_start,
1795                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1796 {
1797         u8 rel_pf_id = p_hwfn->rel_pf_id;
1798         u32 prs_reg;
1799         enum _ecore_status_t rc = ECORE_SUCCESS;
1800         u16 ctrl;
1801         int pos;
1802
1803         if (p_hwfn->mcp_info) {
1804                 struct ecore_mcp_function_info *p_info;
1805
1806                 p_info = &p_hwfn->mcp_info->func_info;
1807                 if (p_info->bandwidth_min)
1808                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1809
1810                 /* Update rate limit once we'll actually have a link */
1811                 p_hwfn->qm_info.pf_rl = 100000;
1812         }
1813         ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
1814
1815         ecore_int_igu_init_rt(p_hwfn);
1816
1817         /* Set VLAN in NIG if needed */
1818         if (hw_mode & (1 << MODE_MF_SD)) {
1819                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1820                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1821                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1822                              p_hwfn->hw_info.ovlan);
1823         }
1824
1825         /* Enable classification by MAC if needed */
1826         if (hw_mode & (1 << MODE_MF_SI)) {
1827                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1828                            "Configuring TAGMAC_CLS_TYPE\n");
1829                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1830                              1);
1831         }
1832
1833         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
1834         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1835                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1836         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1837                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1838         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1839
1840         /* perform debug configuration when chip is out of reset */
1841         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1842
1843         /* PF Init sequence */
1844         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1845         if (rc)
1846                 return rc;
1847
1848         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1849         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1850         if (rc)
1851                 return rc;
1852
1853         /* Pure runtime initializations - directly to the HW  */
1854         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1855
1856         /* PCI relaxed ordering causes a decrease in the performance on some
1857          * systems. Till a root cause is found, disable this attribute in the
1858          * PCI config space.
1859          */
1860         /* Not in use @DPDK
1861         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1862         * if (!pos) {
1863         *       DP_NOTICE(p_hwfn, true,
1864         *                 "Failed to find the PCIe Cap\n");
1865         *       return ECORE_IO;
1866         * }
1867         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1868         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1869         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1870         */
1871
1872         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1873         if (rc)
1874                 return rc;
1875         if (b_hw_start) {
1876                 /* enable interrupts */
1877                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1878                 if (rc != ECORE_SUCCESS)
1879                         return rc;
1880
1881                 /* send function start command */
1882                 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_tunn,
1883                                        p_hwfn->p_dev->mf_mode,
1884                                        allow_npar_tx_switch);
1885                 if (rc) {
1886                         DP_NOTICE(p_hwfn, true,
1887                                   "Function start ramrod failed\n");
1888                 } else {
1889                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1890                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1891                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1892
1893                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1894                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1895                                          (1 << 2));
1896                                 ecore_wr(p_hwfn, p_ptt,
1897                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1898                                     0x100);
1899                         }
1900                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1901                                    "PRS_REG_SEARCH registers after start PFn\n");
1902                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1903                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1904                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1905                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1906                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1907                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1908                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1909                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1910                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1911                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1912                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1913                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1914                         prs_reg = ecore_rd(p_hwfn, p_ptt,
1915                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
1916                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1917                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1918                                    prs_reg);
1919                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1920                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1921                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1922                 }
1923         }
1924         return rc;
1925 }
1926
1927 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
1928                                                   struct ecore_ptt *p_ptt,
1929                                                   bool b_enable)
1930 {
1931         u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
1932
1933         /* Configure the PF's internal FID_enable for master transactions */
1934         ecore_wr(p_hwfn, p_ptt,
1935                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1936
1937         /* Wait until value is set - try for 1 second every 50us */
1938         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1939                 val = ecore_rd(p_hwfn, p_ptt,
1940                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1941                 if (val == set_val)
1942                         break;
1943
1944                 OSAL_UDELAY(50);
1945         }
1946
1947         if (val != set_val) {
1948                 DP_NOTICE(p_hwfn, true,
1949                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1950                 return ECORE_UNKNOWN_ERROR;
1951         }
1952
1953         return ECORE_SUCCESS;
1954 }
1955
1956 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1957                                   struct ecore_ptt *p_main_ptt)
1958 {
1959         /* Read shadow of current MFW mailbox */
1960         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1961         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1962                     p_hwfn->mcp_info->mfw_mb_cur,
1963                     p_hwfn->mcp_info->mfw_mb_length);
1964 }
1965
1966 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
1967                                     struct ecore_hw_init_params *p_params)
1968 {
1969         if (p_params->p_tunn) {
1970                 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1971                 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1972         }
1973
1974         p_hwfn->b_int_enabled = 1;
1975
1976         return ECORE_SUCCESS;
1977 }
1978
1979 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
1980                                      struct ecore_ptt *p_ptt)
1981 {
1982         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
1983                  1 << p_hwfn->abs_pf_id);
1984 }
1985
1986 static void
1987 ecore_fill_load_req_params(struct ecore_load_req_params *p_load_req,
1988                            struct ecore_drv_load_params *p_drv_load)
1989 {
1990         /* Make sure that if ecore-client didn't provide inputs, all the
1991          * expected defaults are indeed zero.
1992          */
1993         OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
1994         OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
1995         OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
1996
1997         OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
1998
1999         if (p_drv_load != OSAL_NULL) {
2000                 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2001                                        ECORE_DRV_ROLE_KDUMP :
2002                                        ECORE_DRV_ROLE_OS;
2003                 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2004                 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2005                 p_load_req->override_force_load =
2006                         p_drv_load->override_force_load;
2007         }
2008 }
2009
2010 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
2011                                    struct ecore_hw_init_params *p_params)
2012 {
2013         struct ecore_load_req_params load_req_params;
2014         u32 load_code, resp, param, drv_mb_param;
2015         bool b_default_mtu = true;
2016         struct ecore_hwfn *p_hwfn;
2017         enum _ecore_status_t rc = ECORE_SUCCESS;
2018         int i;
2019
2020         if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
2021             (p_dev->num_hwfns > 1)) {
2022                 DP_NOTICE(p_dev, false,
2023                           "MSI mode is not supported for CMT devices\n");
2024                 return ECORE_INVAL;
2025         }
2026
2027         if (IS_PF(p_dev)) {
2028                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
2029                 if (rc != ECORE_SUCCESS)
2030                         return rc;
2031         }
2032
2033         for_each_hwfn(p_dev, i) {
2034                 p_hwfn = &p_dev->hwfns[i];
2035
2036                 /* If management didn't provide a default, set one of our own */
2037                 if (!p_hwfn->hw_info.mtu) {
2038                         p_hwfn->hw_info.mtu = 1500;
2039                         b_default_mtu = false;
2040                 }
2041
2042                 if (IS_VF(p_dev)) {
2043                         ecore_vf_start(p_hwfn, p_params);
2044                         continue;
2045                 }
2046
2047                 rc = ecore_calc_hw_mode(p_hwfn);
2048                 if (rc != ECORE_SUCCESS)
2049                         return rc;
2050
2051                 ecore_fill_load_req_params(&load_req_params,
2052                                            p_params->p_drv_load_params);
2053                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
2054                                         &load_req_params);
2055                 if (rc != ECORE_SUCCESS) {
2056                         DP_NOTICE(p_hwfn, true,
2057                                   "Failed sending a LOAD_REQ command\n");
2058                         return rc;
2059                 }
2060
2061                 load_code = load_req_params.load_code;
2062                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2063                            "Load request was sent. Load code: 0x%x\n",
2064                            load_code);
2065
2066                 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
2067
2068                 /* CQ75580:
2069                  * When coming back from hiberbate state, the registers from
2070                  * which shadow is read initially are not initialized. It turns
2071                  * out that these registers get initialized during the call to
2072                  * ecore_mcp_load_req request. So we need to reread them here
2073                  * to get the proper shadow register value.
2074                  * Note: This is a workaround for the missing MFW
2075                  * initialization. It may be removed once the implementation
2076                  * is done.
2077                  */
2078                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2079
2080                 /* Only relevant for recovery:
2081                  * Clear the indication after the LOAD_REQ command is responded
2082                  * by the MFW.
2083                  */
2084                 p_dev->recov_in_prog = false;
2085
2086                 p_hwfn->first_on_engine = (load_code ==
2087                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
2088
2089                 if (!qm_lock_init) {
2090                         OSAL_SPIN_LOCK_INIT(&qm_lock);
2091                         qm_lock_init = true;
2092                 }
2093
2094                 /* Clean up chip from previous driver if such remains exist.
2095                  * This is not needed when the PF is the first one on the
2096                  * engine, since afterwards we are going to init the FW.
2097                  */
2098                 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2099                         rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2100                                                  p_hwfn->rel_pf_id, false);
2101                         if (rc != ECORE_SUCCESS) {
2102                                 ecore_hw_err_notify(p_hwfn,
2103                                                     ECORE_HW_ERR_RAMROD_FAIL);
2104                                 goto load_err;
2105                         }
2106                 }
2107
2108                 /* Log and clean previous pglue_b errors if such exist */
2109                 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
2110                 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2111
2112                 /* Enable the PF's internal FID_enable in the PXP */
2113                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2114                                                   true);
2115                 if (rc != ECORE_SUCCESS)
2116                         goto load_err;
2117
2118                 switch (load_code) {
2119                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2120                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2121                                                   p_hwfn->hw_info.hw_mode);
2122                         if (rc != ECORE_SUCCESS)
2123                                 break;
2124                         /* Fall into */
2125                 case FW_MSG_CODE_DRV_LOAD_PORT:
2126                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2127                                                 p_hwfn->hw_info.hw_mode);
2128                         if (rc != ECORE_SUCCESS)
2129                                 break;
2130                         /* Fall into */
2131                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2132                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2133                                               p_params->p_tunn,
2134                                               p_hwfn->hw_info.hw_mode,
2135                                               p_params->b_hw_start,
2136                                               p_params->int_mode,
2137                                               p_params->allow_npar_tx_switch);
2138                         break;
2139                 default:
2140                         DP_NOTICE(p_hwfn, false,
2141                                   "Unexpected load code [0x%08x]", load_code);
2142                         rc = ECORE_NOTIMPL;
2143                         break;
2144                 }
2145
2146                 if (rc != ECORE_SUCCESS) {
2147                         DP_NOTICE(p_hwfn, true,
2148                                   "init phase failed for loadcode 0x%x (rc %d)\n",
2149                                   load_code, rc);
2150                         goto load_err;
2151                 }
2152
2153                 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2154                 if (rc != ECORE_SUCCESS)
2155                         return rc;
2156
2157                 /* send DCBX attention request command */
2158                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2159                            "sending phony dcbx set command to trigger DCBx attention handling\n");
2160                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2161                                    DRV_MSG_CODE_SET_DCBX,
2162                                    1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, &resp,
2163                                    &param);
2164                 if (rc != ECORE_SUCCESS) {
2165                         DP_NOTICE(p_hwfn, true,
2166                                   "Failed to send DCBX attention request\n");
2167                         return rc;
2168                 }
2169
2170                 p_hwfn->hw_init_done = true;
2171         }
2172
2173         if (IS_PF(p_dev)) {
2174                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2175                 drv_mb_param = STORM_FW_VERSION;
2176                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2177                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2178                                    drv_mb_param, &resp, &param);
2179                 if (rc != ECORE_SUCCESS)
2180                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
2181
2182                 if (!b_default_mtu)
2183                         rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2184                                                       p_hwfn->hw_info.mtu);
2185                 if (rc != ECORE_SUCCESS)
2186                         DP_INFO(p_hwfn, "Failed to update default mtu\n");
2187
2188                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2189                                                       p_hwfn->p_main_ptt,
2190                                                 ECORE_OV_DRIVER_STATE_DISABLED);
2191                 if (rc != ECORE_SUCCESS)
2192                         DP_INFO(p_hwfn, "Failed to update driver state\n");
2193         }
2194
2195         return rc;
2196
2197 load_err:
2198         /* The MFW load lock should be released regardless of success or failure
2199          * of initialization.
2200          * TODO: replace this with an attempt to send cancel_load.
2201          */
2202         ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2203         return rc;
2204 }
2205
2206 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
2207 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2208                                  struct ecore_hwfn *p_hwfn,
2209                                  struct ecore_ptt *p_ptt)
2210 {
2211         int i;
2212
2213         /* close timers */
2214         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2215         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2216         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2217                                                                         i++) {
2218                 if ((!ecore_rd(p_hwfn, p_ptt,
2219                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2220                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2221                         break;
2222
2223                 /* Dependent on number of connection/tasks, possibly
2224                  * 1ms sleep is required between polls
2225                  */
2226                 OSAL_MSLEEP(1);
2227         }
2228
2229         if (i < ECORE_HW_STOP_RETRY_LIMIT)
2230                 return;
2231
2232         DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2233                   " [Connection %02x Tasks %02x]\n",
2234                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2235                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2236 }
2237
2238 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2239 {
2240         int j;
2241
2242         for_each_hwfn(p_dev, j) {
2243                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2244                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2245
2246                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2247         }
2248 }
2249
2250 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
2251                                                  struct ecore_ptt *p_ptt,
2252                                                  u32 addr, u32 expected_val)
2253 {
2254         u32 val = ecore_rd(p_hwfn, p_ptt, addr);
2255
2256         if (val != expected_val) {
2257                 DP_NOTICE(p_hwfn, true,
2258                           "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
2259                           addr, val, expected_val);
2260                 return ECORE_UNKNOWN_ERROR;
2261         }
2262
2263         return ECORE_SUCCESS;
2264 }
2265
2266 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2267 {
2268         struct ecore_hwfn *p_hwfn;
2269         struct ecore_ptt *p_ptt;
2270         enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
2271         int j;
2272
2273         for_each_hwfn(p_dev, j) {
2274                 p_hwfn = &p_dev->hwfns[j];
2275                 p_ptt = p_hwfn->p_main_ptt;
2276
2277                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2278
2279                 if (IS_VF(p_dev)) {
2280                         ecore_vf_pf_int_cleanup(p_hwfn);
2281                         rc = ecore_vf_pf_reset(p_hwfn);
2282                         if (rc != ECORE_SUCCESS) {
2283                                 DP_NOTICE(p_hwfn, true,
2284                                           "ecore_vf_pf_reset failed. rc = %d.\n",
2285                                           rc);
2286                                 rc2 = ECORE_UNKNOWN_ERROR;
2287                         }
2288                         continue;
2289                 }
2290
2291                 /* mark the hw as uninitialized... */
2292                 p_hwfn->hw_init_done = false;
2293
2294                 /* Send unload command to MCP */
2295                 if (!p_dev->recov_in_prog) {
2296                         rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
2297                         if (rc != ECORE_SUCCESS) {
2298                                 DP_NOTICE(p_hwfn, true,
2299                                           "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2300                                           rc);
2301                                 rc2 = ECORE_UNKNOWN_ERROR;
2302                         }
2303                 }
2304
2305                 OSAL_DPC_SYNC(p_hwfn);
2306
2307                 /* After this point no MFW attentions are expected, e.g. prevent
2308                  * race between pf stop and dcbx pf update.
2309                  */
2310
2311                 rc = ecore_sp_pf_stop(p_hwfn);
2312                 if (rc != ECORE_SUCCESS) {
2313                         DP_NOTICE(p_hwfn, true,
2314                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2315                                   rc);
2316                         rc2 = ECORE_UNKNOWN_ERROR;
2317                 }
2318
2319                 /* perform debug action after PF stop was sent */
2320                 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
2321
2322                 /* close NIG to BRB gate */
2323                 ecore_wr(p_hwfn, p_ptt,
2324                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2325
2326                 /* close parser */
2327                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2328                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2329                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2330                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2331                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2332
2333                 /* @@@TBD - clean transmission queues (5.b) */
2334                 /* @@@TBD - clean BTB (5.c) */
2335
2336                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2337
2338                 /* @@@TBD - verify DMAE requests are done (8) */
2339
2340                 /* Disable Attention Generation */
2341                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2342                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2343                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2344                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2345                 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
2346                 if (rc != ECORE_SUCCESS) {
2347                         DP_NOTICE(p_hwfn, true,
2348                                   "Failed to return IGU CAM to default\n");
2349                         rc2 = ECORE_UNKNOWN_ERROR;
2350                 }
2351
2352                 /* Need to wait 1ms to guarantee SBs are cleared */
2353                 OSAL_MSLEEP(1);
2354
2355                 if (!p_dev->recov_in_prog) {
2356                         ecore_verify_reg_val(p_hwfn, p_ptt,
2357                                              QM_REG_USG_CNT_PF_TX, 0);
2358                         ecore_verify_reg_val(p_hwfn, p_ptt,
2359                                              QM_REG_USG_CNT_PF_OTHER, 0);
2360                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
2361                 }
2362
2363                 /* Disable PF in HW blocks */
2364                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2365                 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2366
2367                 if (!p_dev->recov_in_prog) {
2368                         ecore_mcp_unload_done(p_hwfn, p_ptt);
2369                         if (rc != ECORE_SUCCESS) {
2370                                 DP_NOTICE(p_hwfn, true,
2371                                           "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2372                                           rc);
2373                                 rc2 = ECORE_UNKNOWN_ERROR;
2374                         }
2375                 }
2376         } /* hwfn loop */
2377
2378         if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
2379                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2380                 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2381
2382                  /* Clear the PF's internal FID_enable in the PXP.
2383                   * In CMT this should only be done for first hw-function, and
2384                   * only after all transactions have stopped for all active
2385                   * hw-functions.
2386                   */
2387                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2388                                                   false);
2389                 if (rc != ECORE_SUCCESS) {
2390                         DP_NOTICE(p_hwfn, true,
2391                                   "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2392                                   rc);
2393                         rc2 = ECORE_UNKNOWN_ERROR;
2394                 }
2395         }
2396
2397         return rc2;
2398 }
2399
2400 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2401 {
2402         int j;
2403
2404         for_each_hwfn(p_dev, j) {
2405                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2406                 struct ecore_ptt *p_ptt;
2407
2408                 if (IS_VF(p_dev)) {
2409                         ecore_vf_pf_int_cleanup(p_hwfn);
2410                         continue;
2411                 }
2412                 p_ptt = ecore_ptt_acquire(p_hwfn);
2413                 if (!p_ptt)
2414                         return ECORE_AGAIN;
2415
2416                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2417                            "Shutting down the fastpath\n");
2418
2419                 ecore_wr(p_hwfn, p_ptt,
2420                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2421
2422                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2423                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2424                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2425                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2426                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2427
2428                 /* @@@TBD - clean transmission queues (5.b) */
2429                 /* @@@TBD - clean BTB (5.c) */
2430
2431                 /* @@@TBD - verify DMAE requests are done (8) */
2432
2433                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2434                 /* Need to wait 1ms to guarantee SBs are cleared */
2435                 OSAL_MSLEEP(1);
2436                 ecore_ptt_release(p_hwfn, p_ptt);
2437         }
2438
2439         return ECORE_SUCCESS;
2440 }
2441
2442 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2443 {
2444         struct ecore_ptt *p_ptt;
2445
2446         if (IS_VF(p_hwfn->p_dev))
2447                 return ECORE_SUCCESS;
2448
2449         p_ptt = ecore_ptt_acquire(p_hwfn);
2450         if (!p_ptt)
2451                 return ECORE_AGAIN;
2452
2453         /* If roce info is allocated it means roce is initialized and should
2454          * be enabled in searcher.
2455          */
2456         if (p_hwfn->p_rdma_info) {
2457                 if (p_hwfn->b_rdma_enabled_in_prs)
2458                         ecore_wr(p_hwfn, p_ptt,
2459                                  p_hwfn->rdma_prs_search_reg, 0x1);
2460                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2461         }
2462
2463         /* Re-open incoming traffic */
2464         ecore_wr(p_hwfn, p_ptt,
2465                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2466         ecore_ptt_release(p_hwfn, p_ptt);
2467
2468         return ECORE_SUCCESS;
2469 }
2470
2471 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2472 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2473 {
2474         ecore_ptt_pool_free(p_hwfn);
2475         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2476 }
2477
2478 /* Setup bar access */
2479 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2480 {
2481         /* clear indirect access */
2482         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2483                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2484                          PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2485                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2486                          PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2487                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2488                          PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2489                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2490                          PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2491         } else {
2492                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2493                          PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2494                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2495                          PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2496                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2497                          PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2498                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2499                          PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2500         }
2501
2502         /* Clean previous pglue_b errors if such exist */
2503         ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2504
2505         /* enable internal target-read */
2506         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2507                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2508 }
2509
2510 static void get_function_id(struct ecore_hwfn *p_hwfn)
2511 {
2512         /* ME Register */
2513         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2514                                                   PXP_PF_ME_OPAQUE_ADDR);
2515
2516         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2517
2518         /* Bits 16-19 from the ME registers are the pf_num */
2519         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2520         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2521                                       PXP_CONCRETE_FID_PFID);
2522         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2523                                     PXP_CONCRETE_FID_PORT);
2524
2525         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2526                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2527                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2528 }
2529
2530 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2531 {
2532         u32 *feat_num = p_hwfn->hw_info.feat_num;
2533         struct ecore_sb_cnt_info sb_cnt;
2534         u32 non_l2_sbs = 0;
2535
2536         OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
2537         ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
2538
2539         /* L2 Queues require each: 1 status block. 1 L2 queue */
2540         if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
2541                 /* Start by allocating VF queues, then PF's */
2542                 feat_num[ECORE_VF_L2_QUE] =
2543                         OSAL_MIN_T(u32,
2544                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
2545                                    sb_cnt.iov_cnt);
2546                 feat_num[ECORE_PF_L2_QUE] =
2547                         OSAL_MIN_T(u32,
2548                                    sb_cnt.cnt - non_l2_sbs,
2549                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2550                                    FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
2551         }
2552
2553         feat_num[ECORE_FCOE_CQ] = OSAL_MIN_T(u32, sb_cnt.cnt,
2554                                              RESC_NUM(p_hwfn,
2555                                                       ECORE_CMDQS_CQS));
2556         feat_num[ECORE_ISCSI_CQ] = OSAL_MIN_T(u32, sb_cnt.cnt,
2557                                               RESC_NUM(p_hwfn,
2558                                                        ECORE_CMDQS_CQS));
2559
2560         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2561                    "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2562                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2563                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2564                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2565                    (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2566                    (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2567                    (int)sb_cnt.cnt);
2568 }
2569
2570 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2571 {
2572         switch (res_id) {
2573         case ECORE_L2_QUEUE:
2574                 return "L2_QUEUE";
2575         case ECORE_VPORT:
2576                 return "VPORT";
2577         case ECORE_RSS_ENG:
2578                 return "RSS_ENG";
2579         case ECORE_PQ:
2580                 return "PQ";
2581         case ECORE_RL:
2582                 return "RL";
2583         case ECORE_MAC:
2584                 return "MAC";
2585         case ECORE_VLAN:
2586                 return "VLAN";
2587         case ECORE_RDMA_CNQ_RAM:
2588                 return "RDMA_CNQ_RAM";
2589         case ECORE_ILT:
2590                 return "ILT";
2591         case ECORE_LL2_QUEUE:
2592                 return "LL2_QUEUE";
2593         case ECORE_CMDQS_CQS:
2594                 return "CMDQS_CQS";
2595         case ECORE_RDMA_STATS_QUEUE:
2596                 return "RDMA_STATS_QUEUE";
2597         case ECORE_BDQ:
2598                 return "BDQ";
2599         case ECORE_SB:
2600                 return "SB";
2601         default:
2602                 return "UNKNOWN_RESOURCE";
2603         }
2604 }
2605
2606 static enum _ecore_status_t
2607 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2608                               struct ecore_ptt *p_ptt,
2609                               enum ecore_resources res_id,
2610                               u32 resc_max_val,
2611                               u32 *p_mcp_resp)
2612 {
2613         enum _ecore_status_t rc;
2614
2615         rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2616                                         resc_max_val, p_mcp_resp);
2617         if (rc != ECORE_SUCCESS) {
2618                 DP_NOTICE(p_hwfn, true,
2619                           "MFW response failure for a max value setting of resource %d [%s]\n",
2620                           res_id, ecore_hw_get_resc_name(res_id));
2621                 return rc;
2622         }
2623
2624         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2625                 DP_INFO(p_hwfn,
2626                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2627                         res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
2628
2629         return ECORE_SUCCESS;
2630 }
2631
2632 static enum _ecore_status_t
2633 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2634                             struct ecore_ptt *p_ptt)
2635 {
2636         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2637         u32 resc_max_val, mcp_resp;
2638         u8 res_id;
2639         enum _ecore_status_t rc;
2640
2641         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2642                 /* @DPDK */
2643                 switch (res_id) {
2644                 case ECORE_LL2_QUEUE:
2645                 case ECORE_RDMA_CNQ_RAM:
2646                 case ECORE_RDMA_STATS_QUEUE:
2647                 case ECORE_BDQ:
2648                         resc_max_val = 0;
2649                         break;
2650                 default:
2651                         continue;
2652                 }
2653
2654                 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2655                                                    resc_max_val, &mcp_resp);
2656                 if (rc != ECORE_SUCCESS)
2657                         return rc;
2658
2659                 /* There's no point to continue to the next resource if the
2660                  * command is not supported by the MFW.
2661                  * We do continue if the command is supported but the resource
2662                  * is unknown to the MFW. Such a resource will be later
2663                  * configured with the default allocation values.
2664                  */
2665                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2666                         return ECORE_NOTIMPL;
2667         }
2668
2669         return ECORE_SUCCESS;
2670 }
2671
2672 static
2673 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
2674                                             enum ecore_resources res_id,
2675                                             u32 *p_resc_num, u32 *p_resc_start)
2676 {
2677         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2678         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2679
2680         switch (res_id) {
2681         case ECORE_L2_QUEUE:
2682                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2683                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
2684                 break;
2685         case ECORE_VPORT:
2686                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2687                                  MAX_NUM_VPORTS_BB) / num_funcs;
2688                 break;
2689         case ECORE_RSS_ENG:
2690                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2691                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2692                 break;
2693         case ECORE_PQ:
2694                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2695                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
2696                 break;
2697         case ECORE_RL:
2698                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2699                 break;
2700         case ECORE_MAC:
2701         case ECORE_VLAN:
2702                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2703                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2704                 break;
2705         case ECORE_ILT:
2706                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2707                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2708                 break;
2709         case ECORE_LL2_QUEUE:
2710                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2711                 break;
2712         case ECORE_RDMA_CNQ_RAM:
2713         case ECORE_CMDQS_CQS:
2714                 /* CNQ/CMDQS are the same resource */
2715                 /* @DPDK */
2716                 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2717                 break;
2718         case ECORE_RDMA_STATS_QUEUE:
2719                 /* @DPDK */
2720                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2721                                  MAX_NUM_VPORTS_BB) / num_funcs;
2722                 break;
2723         case ECORE_BDQ:
2724                 /* @DPDK */
2725                 *p_resc_num = 0;
2726                 break;
2727         default:
2728                 break;
2729         }
2730
2731
2732         switch (res_id) {
2733         case ECORE_BDQ:
2734                 if (!*p_resc_num)
2735                         *p_resc_start = 0;
2736                 break;
2737         case ECORE_SB:
2738                 /* Since we want its value to reflect whether MFW supports
2739                  * the new scheme, have a default of 0.
2740                  */
2741                 *p_resc_num = 0;
2742                 break;
2743         default:
2744                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2745                 break;
2746         }
2747
2748         return ECORE_SUCCESS;
2749 }
2750
2751 static enum _ecore_status_t
2752 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
2753                          bool drv_resc_alloc)
2754 {
2755         u32 dflt_resc_num = 0, dflt_resc_start = 0;
2756         u32 mcp_resp, *p_resc_num, *p_resc_start;
2757         enum _ecore_status_t rc;
2758
2759         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2760         p_resc_start = &RESC_START(p_hwfn, res_id);
2761
2762         rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2763                                     &dflt_resc_start);
2764         if (rc != ECORE_SUCCESS) {
2765                 DP_ERR(p_hwfn,
2766                        "Failed to get default amount for resource %d [%s]\n",
2767                         res_id, ecore_hw_get_resc_name(res_id));
2768                 return rc;
2769         }
2770
2771 #ifndef ASIC_ONLY
2772         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2773                 *p_resc_num = dflt_resc_num;
2774                 *p_resc_start = dflt_resc_start;
2775                 goto out;
2776         }
2777 #endif
2778
2779         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2780                                      &mcp_resp, p_resc_num, p_resc_start);
2781         if (rc != ECORE_SUCCESS) {
2782                 DP_NOTICE(p_hwfn, true,
2783                           "MFW response failure for an allocation request for"
2784                           " resource %d [%s]\n",
2785                           res_id, ecore_hw_get_resc_name(res_id));
2786                 return rc;
2787         }
2788
2789         /* Default driver values are applied in the following cases:
2790          * - The resource allocation MB command is not supported by the MFW
2791          * - There is an internal error in the MFW while processing the request
2792          * - The resource ID is unknown to the MFW
2793          */
2794         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2795                 DP_INFO(p_hwfn,
2796                         "Failed to receive allocation info for resource %d [%s]."
2797                         " mcp_resp = 0x%x. Applying default values"
2798                         " [%d,%d].\n",
2799                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2800                         dflt_resc_num, dflt_resc_start);
2801
2802                 *p_resc_num = dflt_resc_num;
2803                 *p_resc_start = dflt_resc_start;
2804                 goto out;
2805         }
2806
2807         if ((*p_resc_num != dflt_resc_num ||
2808              *p_resc_start != dflt_resc_start) &&
2809             res_id != ECORE_SB) {
2810                 DP_INFO(p_hwfn,
2811                         "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
2812                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2813                         *p_resc_start, dflt_resc_num, dflt_resc_start,
2814                         drv_resc_alloc ? " - Applying default values" : "");
2815                 if (drv_resc_alloc) {
2816                         *p_resc_num = dflt_resc_num;
2817                         *p_resc_start = dflt_resc_start;
2818                 }
2819         }
2820 out:
2821         return ECORE_SUCCESS;
2822 }
2823
2824 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2825                                                    bool drv_resc_alloc)
2826 {
2827         enum _ecore_status_t rc;
2828         u8 res_id;
2829
2830         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2831                 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2832                 if (rc != ECORE_SUCCESS)
2833                         return rc;
2834         }
2835
2836         return ECORE_SUCCESS;
2837 }
2838
2839 #define ECORE_RESC_ALLOC_LOCK_RETRY_CNT         10
2840 #define ECORE_RESC_ALLOC_LOCK_RETRY_INTVL_US    10000 /* 10 msec */
2841
2842 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2843                                               struct ecore_ptt *p_ptt,
2844                                               bool drv_resc_alloc)
2845 {
2846         struct ecore_resc_unlock_params resc_unlock_params;
2847         struct ecore_resc_lock_params resc_lock_params;
2848         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2849         u8 res_id;
2850         enum _ecore_status_t rc;
2851 #ifndef ASIC_ONLY
2852         u32 *resc_start = p_hwfn->hw_info.resc_start;
2853         u32 *resc_num = p_hwfn->hw_info.resc_num;
2854         /* For AH, an equal share of the ILT lines between the maximal number of
2855          * PFs is not enough for RoCE. This would be solved by the future
2856          * resource allocation scheme, but isn't currently present for
2857          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2858          * to work - the BB number of ILT lines divided by its max PFs number.
2859          */
2860         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2861 #endif
2862
2863         /* Setting the max values of the soft resources and the following
2864          * resources allocation queries should be atomic. Since several PFs can
2865          * run in parallel - a resource lock is needed.
2866          * If either the resource lock or resource set value commands are not
2867          * supported - skip the the max values setting, release the lock if
2868          * needed, and proceed to the queries. Other failures, including a
2869          * failure to acquire the lock, will cause this function to fail.
2870          * Old drivers that don't acquire the lock can run in parallel, and
2871          * their allocation values won't be affected by the updated max values.
2872          */
2873         OSAL_MEM_ZERO(&resc_lock_params, sizeof(resc_lock_params));
2874         resc_lock_params.resource = ECORE_RESC_LOCK_RESC_ALLOC;
2875         resc_lock_params.retry_num = ECORE_RESC_ALLOC_LOCK_RETRY_CNT;
2876         resc_lock_params.retry_interval = ECORE_RESC_ALLOC_LOCK_RETRY_INTVL_US;
2877         resc_lock_params.sleep_b4_retry = true;
2878         OSAL_MEM_ZERO(&resc_unlock_params, sizeof(resc_unlock_params));
2879         resc_unlock_params.resource = ECORE_RESC_LOCK_RESC_ALLOC;
2880
2881         rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
2882         if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
2883                 return rc;
2884         } else if (rc == ECORE_NOTIMPL) {
2885                 DP_INFO(p_hwfn,
2886                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2887         } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
2888                 DP_NOTICE(p_hwfn, false,
2889                           "Failed to acquire the resource lock for the resource allocation commands\n");
2890                 rc = ECORE_BUSY;
2891                 goto unlock_and_exit;
2892         } else {
2893                 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
2894                 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
2895                         DP_NOTICE(p_hwfn, false,
2896                                   "Failed to set the max values of the soft resources\n");
2897                         goto unlock_and_exit;
2898                 } else if (rc == ECORE_NOTIMPL) {
2899                         DP_INFO(p_hwfn,
2900                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2901                         rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
2902                                                    &resc_unlock_params);
2903                         if (rc != ECORE_SUCCESS)
2904                                 DP_INFO(p_hwfn,
2905                                         "Failed to release the resource lock for the resource allocation commands\n");
2906                 }
2907         }
2908
2909         rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
2910         if (rc != ECORE_SUCCESS)
2911                 goto unlock_and_exit;
2912
2913         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2914                 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
2915                                            &resc_unlock_params);
2916                 if (rc != ECORE_SUCCESS)
2917                         DP_INFO(p_hwfn,
2918                                 "Failed to release the resource lock for the resource allocation commands\n");
2919         }
2920
2921 #ifndef ASIC_ONLY
2922         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2923                 /* Reduced build contains less PQs */
2924                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2925                         resc_num[ECORE_PQ] = 32;
2926                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2927                             p_hwfn->enabled_func_idx;
2928                 }
2929
2930                 /* For AH emulation, since we have a possible maximal number of
2931                  * 16 enabled PFs, in case there are not enough ILT lines -
2932                  * allocate only first PF as RoCE and have all the other ETH
2933                  * only with less ILT lines.
2934                  */
2935                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2936                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2937                                                          resc_num[ECORE_ILT],
2938                                                          roce_min_ilt_lines);
2939         }
2940
2941         /* Correct the common ILT calculation if PF0 has more */
2942         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2943             p_hwfn->p_dev->b_is_emul_full &&
2944             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2945                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2946                     resc_num[ECORE_ILT];
2947 #endif
2948
2949         /* Sanity for ILT */
2950         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2951             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2952                 DP_NOTICE(p_hwfn, true,
2953                           "Can't assign ILT pages [%08x,...,%08x]\n",
2954                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2955                                                                   ECORE_ILT) -
2956                           1);
2957                 return ECORE_INVAL;
2958         }
2959
2960         /* This will also learn the number of SBs from MFW */
2961         if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
2962                 return ECORE_INVAL;
2963
2964         ecore_hw_set_feat(p_hwfn);
2965
2966         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2967                    "The numbers for each resource are:\n");
2968         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2969                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2970                            ecore_hw_get_resc_name(res_id),
2971                            RESC_NUM(p_hwfn, res_id),
2972                            RESC_START(p_hwfn, res_id));
2973
2974         return ECORE_SUCCESS;
2975
2976 unlock_and_exit:
2977         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
2978                 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
2979                                       &resc_unlock_params);
2980         return rc;
2981 }
2982
2983 static enum _ecore_status_t
2984 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2985                       struct ecore_ptt *p_ptt,
2986                       struct ecore_hw_prepare_params *p_params)
2987 {
2988         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
2989         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2990         struct ecore_mcp_link_capabilities *p_caps;
2991         struct ecore_mcp_link_params *link;
2992         enum _ecore_status_t rc;
2993
2994         /* Read global nvm_cfg address */
2995         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2996
2997         /* Verify MCP has initialized it */
2998         if (!nvm_cfg_addr) {
2999                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
3000                 if (p_params->b_relaxed_probe)
3001                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
3002                 return ECORE_INVAL;
3003         }
3004
3005 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
3006
3007         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
3008
3009         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3010             OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
3011                                                        core_cfg);
3012
3013         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
3014
3015         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
3016                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
3017         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
3018                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
3019                 break;
3020         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
3021                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
3022                 break;
3023         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
3024                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
3025                 break;
3026         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
3027                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
3028                 break;
3029         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
3030                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
3031                 break;
3032         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
3033                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
3034                 break;
3035         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
3036                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
3037                 break;
3038         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
3039                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
3040                 break;
3041         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
3042                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
3043                 break;
3044         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
3045                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
3046                 break;
3047         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3048                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
3049                 break;
3050         default:
3051                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
3052                           core_cfg);
3053                 break;
3054         }
3055
3056         /* Read DCBX configuration */
3057         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3058                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3059         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
3060                              port_cfg_addr +
3061                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
3062         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
3063                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
3064         switch (dcbx_mode) {
3065         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
3066                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
3067                 break;
3068         case NVM_CFG1_PORT_DCBX_MODE_CEE:
3069                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
3070                 break;
3071         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
3072                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
3073                 break;
3074         default:
3075                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
3076         }
3077
3078         /* Read default link configuration */
3079         link = &p_hwfn->mcp_info->link_input;
3080         p_caps = &p_hwfn->mcp_info->link_capabilities;
3081         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3082             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3083         link_temp = ecore_rd(p_hwfn, p_ptt,
3084                              port_cfg_addr +
3085                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
3086         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
3087         link->speed.advertised_speeds = link_temp;
3088         p_caps->speed_capabilities = link->speed.advertised_speeds;
3089
3090         link_temp = ecore_rd(p_hwfn, p_ptt,
3091                              port_cfg_addr +
3092                              OFFSETOF(struct nvm_cfg1_port, link_settings));
3093         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
3094                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
3095         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
3096                 link->speed.autoneg = true;
3097                 break;
3098         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
3099                 link->speed.forced_speed = 1000;
3100                 break;
3101         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
3102                 link->speed.forced_speed = 10000;
3103                 break;
3104         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3105                 link->speed.forced_speed = 25000;
3106                 break;
3107         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3108                 link->speed.forced_speed = 40000;
3109                 break;
3110         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3111                 link->speed.forced_speed = 50000;
3112                 break;
3113         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3114                 link->speed.forced_speed = 100000;
3115                 break;
3116         default:
3117                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
3118         }
3119
3120         p_caps->default_speed = link->speed.forced_speed;
3121         p_caps->default_speed_autoneg = link->speed.autoneg;
3122
3123         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3124         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3125         link->pause.autoneg = !!(link_temp &
3126                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3127         link->pause.forced_rx = !!(link_temp &
3128                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3129         link->pause.forced_tx = !!(link_temp &
3130                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3131         link->loopback_mode = 0;
3132
3133         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
3134                 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
3135                                      OFFSETOF(struct nvm_cfg1_port, ext_phy));
3136                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
3137                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
3138                 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
3139                 link->eee.enable = true;
3140                 switch (link_temp) {
3141                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
3142                         p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
3143                         link->eee.enable = false;
3144                         break;
3145                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
3146                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
3147                         break;
3148                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
3149                         p_caps->eee_lpi_timer =
3150                                 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
3151                         break;
3152                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
3153                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
3154                         break;
3155                 }
3156
3157                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
3158                 link->eee.tx_lpi_enable = link->eee.enable;
3159                 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
3160         } else {
3161                 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
3162         }
3163
3164         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3165                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
3166                    link->speed.forced_speed, link->speed.advertised_speeds,
3167                    link->speed.autoneg, link->pause.autoneg,
3168                    p_caps->default_eee, p_caps->eee_lpi_timer);
3169
3170         /* Read Multi-function information from shmem */
3171         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3172             OFFSETOF(struct nvm_cfg1, glob) +
3173             OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3174
3175         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3176
3177         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3178             NVM_CFG1_GLOB_MF_MODE_OFFSET;
3179
3180         switch (mf_mode) {
3181         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3182                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3183                 break;
3184         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3185                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3186                 break;
3187         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3188                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3189                 break;
3190         }
3191         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
3192                 p_hwfn->p_dev->mf_mode);
3193
3194         /* Read Multi-function information from shmem */
3195         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3196             OFFSETOF(struct nvm_cfg1, glob) +
3197             OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3198
3199         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3200         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3201                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3202                              &p_hwfn->hw_info.device_capabilities);
3203         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3204                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3205                              &p_hwfn->hw_info.device_capabilities);
3206         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3207                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3208                              &p_hwfn->hw_info.device_capabilities);
3209         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3210                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3211                              &p_hwfn->hw_info.device_capabilities);
3212         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3213                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3214                              &p_hwfn->hw_info.device_capabilities);
3215
3216         rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3217         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3218                 rc = ECORE_SUCCESS;
3219                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3220         }
3221
3222         return rc;
3223 }
3224
3225 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3226                                 struct ecore_ptt *p_ptt)
3227 {
3228         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3229         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3230         struct ecore_dev *p_dev = p_hwfn->p_dev;
3231
3232         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3233
3234         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3235          * in the other bits are selected.
3236          * Bits 1-15 are for functions 1-15, respectively, and their value is
3237          * '0' only for enabled functions (function 0 always exists and
3238          * enabled).
3239          * In case of CMT in BB, only the "even" functions are enabled, and thus
3240          * the number of functions for both hwfns is learnt from the same bits.
3241          */
3242         if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3243                 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3244                                              MISCS_REG_FUNCTION_HIDE_BB_K2);
3245         } else { /* E5 */
3246                 reg_function_hide = 0;
3247         }
3248
3249         if (reg_function_hide & 0x1) {
3250                 if (ECORE_IS_BB(p_dev)) {
3251                         if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
3252                                 num_funcs = 0;
3253                                 eng_mask = 0xaaaa;
3254                         } else {
3255                                 num_funcs = 1;
3256                                 eng_mask = 0x5554;
3257                         }
3258                 } else {
3259                         num_funcs = 1;
3260                         eng_mask = 0xfffe;
3261                 }
3262
3263                 /* Get the number of the enabled functions on the engine */
3264                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3265                 while (tmp) {
3266                         if (tmp & 0x1)
3267                                 num_funcs++;
3268                         tmp >>= 0x1;
3269                 }
3270
3271                 /* Get the PF index within the enabled functions */
3272                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3273                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3274                 while (tmp) {
3275                         if (tmp & 0x1)
3276                                 enabled_func_idx--;
3277                         tmp >>= 0x1;
3278                 }
3279         }
3280
3281         p_hwfn->num_funcs_on_engine = num_funcs;
3282         p_hwfn->enabled_func_idx = enabled_func_idx;
3283
3284 #ifndef ASIC_ONLY
3285         if (CHIP_REV_IS_FPGA(p_dev)) {
3286                 DP_NOTICE(p_hwfn, false,
3287                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3288                 p_hwfn->num_funcs_on_engine = 4;
3289         }
3290 #endif
3291
3292         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3293                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3294                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3295                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3296 }
3297
3298 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3299                                       struct ecore_ptt *p_ptt)
3300 {
3301         u32 port_mode;
3302
3303 #ifndef ASIC_ONLY
3304         /* Read the port mode */
3305         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
3306                 port_mode = 4;
3307         else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
3308                  (p_hwfn->p_dev->num_hwfns > 1))
3309                 /* In CMT on emulation, assume 1 port */
3310                 port_mode = 1;
3311         else
3312 #endif
3313         port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3314
3315         if (port_mode < 3) {
3316                 p_hwfn->p_dev->num_ports_in_engines = 1;
3317         } else if (port_mode <= 5) {
3318                 p_hwfn->p_dev->num_ports_in_engines = 2;
3319         } else {
3320                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3321                           p_hwfn->p_dev->num_ports_in_engines);
3322
3323                 /* Default num_ports_in_engines to something */
3324                 p_hwfn->p_dev->num_ports_in_engines = 1;
3325         }
3326 }
3327
3328 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3329                                          struct ecore_ptt *p_ptt)
3330 {
3331         u32 port;
3332         int i;
3333
3334         p_hwfn->p_dev->num_ports_in_engines = 0;
3335
3336 #ifndef ASIC_ONLY
3337         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
3338                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3339                 switch ((port & 0xf000) >> 12) {
3340                 case 1:
3341                         p_hwfn->p_dev->num_ports_in_engines = 1;
3342                         break;
3343                 case 3:
3344                         p_hwfn->p_dev->num_ports_in_engines = 2;
3345                         break;
3346                 case 0xf:
3347                         p_hwfn->p_dev->num_ports_in_engines = 4;
3348                         break;
3349                 default:
3350                         DP_NOTICE(p_hwfn, false,
3351                                   "Unknown port mode in ECO_RESERVED %08x\n",
3352                                   port);
3353                 }
3354         } else
3355 #endif
3356                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3357                         port = ecore_rd(p_hwfn, p_ptt,
3358                                         CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3359                                         (i * 4));
3360                         if (port & 1)
3361                                 p_hwfn->p_dev->num_ports_in_engines++;
3362                 }
3363 }
3364
3365 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3366                                    struct ecore_ptt *p_ptt)
3367 {
3368         if (ECORE_IS_BB(p_hwfn->p_dev))
3369                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3370         else
3371                 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3372 }
3373
3374 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
3375                                    struct ecore_ptt *p_ptt)
3376 {
3377         struct ecore_mcp_link_capabilities *p_caps;
3378         u32 eee_status;
3379
3380         p_caps = &p_hwfn->mcp_info->link_capabilities;
3381         if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
3382                 return;
3383
3384         p_caps->eee_speed_caps = 0;
3385         eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
3386                               OFFSETOF(struct public_port, eee_status));
3387         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
3388                         EEE_SUPPORTED_SPEED_OFFSET;
3389         if (eee_status & EEE_1G_SUPPORTED)
3390                 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
3391         if (eee_status & EEE_10G_ADV)
3392                 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
3393 }
3394
3395 static enum _ecore_status_t
3396 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3397                   enum ecore_pci_personality personality,
3398                   struct ecore_hw_prepare_params *p_params)
3399 {
3400         bool drv_resc_alloc = p_params->drv_resc_alloc;
3401         enum _ecore_status_t rc;
3402
3403         /* Since all information is common, only first hwfns should do this */
3404         if (IS_LEAD_HWFN(p_hwfn)) {
3405                 rc = ecore_iov_hw_info(p_hwfn);
3406                 if (rc != ECORE_SUCCESS) {
3407                         if (p_params->b_relaxed_probe)
3408                                 p_params->p_relaxed_res =
3409                                                 ECORE_HW_PREPARE_BAD_IOV;
3410                         else
3411                                 return rc;
3412                 }
3413         }
3414
3415         /* TODO In get_hw_info, amoungst others:
3416          * Get MCP FW revision and determine according to it the supported
3417          * featrues (e.g. DCB)
3418          * Get boot mode
3419          * ecore_get_pcie_width_speed, WOL capability.
3420          * Number of global CQ-s (for storage
3421          */
3422         ecore_hw_info_port_num(p_hwfn, p_ptt);
3423
3424         ecore_mcp_get_capabilities(p_hwfn, p_ptt);
3425
3426 #ifndef ASIC_ONLY
3427         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3428 #endif
3429         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3430         if (rc != ECORE_SUCCESS)
3431                 return rc;
3432 #ifndef ASIC_ONLY
3433         }
3434 #endif
3435
3436         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3437         if (rc != ECORE_SUCCESS) {
3438                 if (p_params->b_relaxed_probe)
3439                         p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3440                 else
3441                         return rc;
3442         }
3443
3444 #ifndef ASIC_ONLY
3445         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3446 #endif
3447                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3448                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3449 #ifndef ASIC_ONLY
3450         } else {
3451                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3452
3453                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3454                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3455         }
3456 #endif
3457
3458         if (ecore_mcp_is_init(p_hwfn)) {
3459                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3460                         p_hwfn->hw_info.ovlan =
3461                             p_hwfn->mcp_info->func_info.ovlan;
3462
3463                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3464
3465                 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
3466         }
3467
3468         if (personality != ECORE_PCI_DEFAULT) {
3469                 p_hwfn->hw_info.personality = personality;
3470         } else if (ecore_mcp_is_init(p_hwfn)) {
3471                 enum ecore_pci_personality protocol;
3472
3473                 protocol = p_hwfn->mcp_info->func_info.protocol;
3474                 p_hwfn->hw_info.personality = protocol;
3475         }
3476
3477 #ifndef ASIC_ONLY
3478         /* To overcome ILT lack for emulation, until at least until we'll have
3479          * a definite answer from system about it, allow only PF0 to be RoCE.
3480          */
3481         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3482                 if (!p_hwfn->rel_pf_id)
3483                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3484                 else
3485                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3486         }
3487 #endif
3488
3489         /* although in BB some constellations may support more than 4 tcs,
3490          * that can result in performance penalty in some cases. 4
3491          * represents a good tradeoff between performance and flexibility.
3492          */
3493         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3494
3495         /* start out with a single active tc. This can be increased either
3496          * by dcbx negotiation or by upper layer driver
3497          */
3498         p_hwfn->hw_info.num_active_tc = 1;
3499
3500         ecore_get_num_funcs(p_hwfn, p_ptt);
3501
3502         if (ecore_mcp_is_init(p_hwfn))
3503                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3504
3505         /* In case of forcing the driver's default resource allocation, calling
3506          * ecore_hw_get_resc() should come after initializing the personality
3507          * and after getting the number of functions, since the calculation of
3508          * the resources/features depends on them.
3509          * This order is not harmful if not forcing.
3510          */
3511         rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
3512         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3513                 rc = ECORE_SUCCESS;
3514                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3515         }
3516
3517         return rc;
3518 }
3519
3520 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
3521                                                struct ecore_ptt *p_ptt)
3522 {
3523         struct ecore_dev *p_dev = p_hwfn->p_dev;
3524         u16 device_id_mask;
3525         u32 tmp;
3526
3527         /* Read Vendor Id / Device Id */
3528         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3529                                   &p_dev->vendor_id);
3530         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3531                                   &p_dev->device_id);
3532
3533         /* Determine type */
3534         device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
3535         switch (device_id_mask) {
3536         case ECORE_DEV_ID_MASK_BB:
3537                 p_dev->type = ECORE_DEV_TYPE_BB;
3538                 break;
3539         case ECORE_DEV_ID_MASK_AH:
3540                 p_dev->type = ECORE_DEV_TYPE_AH;
3541                 break;
3542         default:
3543                 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
3544                           p_dev->device_id);
3545                 return ECORE_ABORTED;
3546         }
3547
3548         p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_ptt,
3549                                                 MISCS_REG_CHIP_NUM);
3550         p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_ptt,
3551                                                 MISCS_REG_CHIP_REV);
3552
3553         MASK_FIELD(CHIP_REV, p_dev->chip_rev);
3554
3555         /* Learn number of HW-functions */
3556         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
3557
3558         if (tmp & (1 << p_hwfn->rel_pf_id)) {
3559                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3560                 p_dev->num_hwfns = 2;
3561         } else {
3562                 p_dev->num_hwfns = 1;
3563         }
3564
3565 #ifndef ASIC_ONLY
3566         if (CHIP_REV_IS_EMUL(p_dev)) {
3567                 /* For some reason we have problems with this register
3568                  * in B0 emulation; Simply assume no CMT
3569                  */
3570                 DP_NOTICE(p_dev->hwfns, false,
3571                           "device on emul - assume no CMT\n");
3572                 p_dev->num_hwfns = 1;
3573         }
3574 #endif
3575
3576         p_dev->chip_bond_id = ecore_rd(p_hwfn, p_ptt,
3577                                        MISCS_REG_CHIP_TEST_REG) >> 4;
3578         MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
3579         p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_ptt,
3580                                            MISCS_REG_CHIP_METAL);
3581         MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
3582         DP_INFO(p_dev->hwfns,
3583                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3584                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3585                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3586                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3587                 p_dev->chip_metal);
3588
3589         if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
3590                 DP_NOTICE(p_dev->hwfns, false,
3591                           "The chip type/rev (BB A0) is not supported!\n");
3592                 return ECORE_ABORTED;
3593         }
3594 #ifndef ASIC_ONLY
3595         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3596                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3597
3598         if (CHIP_REV_IS_EMUL(p_dev)) {
3599                 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3600                 if (tmp & (1 << 29)) {
3601                         DP_NOTICE(p_hwfn, false,
3602                                   "Emulation: Running on a FULL build\n");
3603                         p_dev->b_is_emul_full = true;
3604                 } else {
3605                         DP_NOTICE(p_hwfn, false,
3606                                   "Emulation: Running on a REDUCED build\n");
3607                 }
3608         }
3609 #endif
3610
3611         return ECORE_SUCCESS;
3612 }
3613
3614 #ifndef LINUX_REMOVE
3615 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3616 {
3617         int j;
3618
3619         if (IS_VF(p_dev))
3620                 return;
3621
3622         for_each_hwfn(p_dev, j) {
3623                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3624
3625                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
3626                            "Mark hw/fw uninitialized\n");
3627
3628                 p_hwfn->hw_init_done = false;
3629                 p_hwfn->first_on_engine = false;
3630
3631                 ecore_ptt_invalidate(p_hwfn);
3632         }
3633 }
3634 #endif
3635
3636 static enum _ecore_status_t
3637 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
3638                         void OSAL_IOMEM * p_regview,
3639                         void OSAL_IOMEM * p_doorbells,
3640                         struct ecore_hw_prepare_params *p_params)
3641 {
3642         struct ecore_mdump_retain_data mdump_retain;
3643         struct ecore_dev *p_dev = p_hwfn->p_dev;
3644         struct ecore_mdump_info mdump_info;
3645         enum _ecore_status_t rc = ECORE_SUCCESS;
3646
3647         /* Split PCI bars evenly between hwfns */
3648         p_hwfn->regview = p_regview;
3649         p_hwfn->doorbells = p_doorbells;
3650
3651         if (IS_VF(p_dev))
3652                 return ecore_vf_hw_prepare(p_hwfn);
3653
3654         /* Validate that chip access is feasible */
3655         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3656                 DP_ERR(p_hwfn,
3657                        "Reading the ME register returns all Fs; Preventing further chip access\n");
3658                 if (p_params->b_relaxed_probe)
3659                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
3660                 return ECORE_INVAL;
3661         }
3662
3663         get_function_id(p_hwfn);
3664
3665         /* Allocate PTT pool */
3666         rc = ecore_ptt_pool_alloc(p_hwfn);
3667         if (rc) {
3668                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
3669                 if (p_params->b_relaxed_probe)
3670                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3671                 goto err0;
3672         }
3673
3674         /* Allocate the main PTT */
3675         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3676
3677         /* First hwfn learns basic information, e.g., number of hwfns */
3678         if (!p_hwfn->my_id) {
3679                 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
3680                 if (rc != ECORE_SUCCESS) {
3681                         if (p_params->b_relaxed_probe)
3682                                 p_params->p_relaxed_res =
3683                                         ECORE_HW_PREPARE_FAILED_DEV;
3684                         goto err1;
3685                 }
3686         }
3687
3688         ecore_hw_hwfn_prepare(p_hwfn);
3689
3690         /* Initialize MCP structure */
3691         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3692         if (rc) {
3693                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3694                 if (p_params->b_relaxed_probe)
3695                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3696                 goto err1;
3697         }
3698
3699         /* Read the device configuration information from the HW and SHMEM */
3700         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3701                                p_params->personality, p_params);
3702         if (rc) {
3703                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3704                 goto err2;
3705         }
3706
3707         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3708          * called, since among others it sets the ports number in an engine.
3709          */
3710         if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
3711             !p_dev->recov_in_prog) {
3712                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3713                 if (rc != ECORE_SUCCESS)
3714                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3715         }
3716
3717         /* Check if mdump logs/data are present and update the epoch value */
3718         if (IS_LEAD_HWFN(p_hwfn)) {
3719 #ifndef ASIC_ONLY
3720                 if (!CHIP_REV_IS_EMUL(p_dev)) {
3721 #endif
3722                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3723                                               &mdump_info);
3724                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
3725                         DP_NOTICE(p_hwfn, false,
3726                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3727
3728                 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
3729                                                 &mdump_retain);
3730                 if (rc == ECORE_SUCCESS && mdump_retain.valid)
3731                         DP_NOTICE(p_hwfn, false,
3732                                   "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
3733                                   mdump_retain.epoch, mdump_retain.pf,
3734                                   mdump_retain.status);
3735
3736                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3737                                            p_params->epoch);
3738 #ifndef ASIC_ONLY
3739                 }
3740 #endif
3741         }
3742
3743         /* Allocate the init RT array and initialize the init-ops engine */
3744         rc = ecore_init_alloc(p_hwfn);
3745         if (rc) {
3746                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3747                 if (p_params->b_relaxed_probe)
3748                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3749                 goto err2;
3750         }
3751 #ifndef ASIC_ONLY
3752         if (CHIP_REV_IS_FPGA(p_dev)) {
3753                 DP_NOTICE(p_hwfn, false,
3754                           "FPGA: workaround; Prevent DMAE parities\n");
3755                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
3756                          7);
3757
3758                 DP_NOTICE(p_hwfn, false,
3759                           "FPGA: workaround: Set VF bar0 size\n");
3760                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3761                          PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
3762         }
3763 #endif
3764
3765         return rc;
3766 err2:
3767         if (IS_LEAD_HWFN(p_hwfn))
3768                 ecore_iov_free_hw_info(p_dev);
3769         ecore_mcp_free(p_hwfn);
3770 err1:
3771         ecore_hw_hwfn_free(p_hwfn);
3772 err0:
3773         return rc;
3774 }
3775
3776 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3777                                       struct ecore_hw_prepare_params *p_params)
3778 {
3779         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3780         enum _ecore_status_t rc;
3781
3782         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3783         p_dev->allow_mdump = p_params->allow_mdump;
3784
3785         if (p_params->b_relaxed_probe)
3786                 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
3787
3788         /* Store the precompiled init data ptrs */
3789         if (IS_PF(p_dev))
3790                 ecore_init_iro_array(p_dev);
3791
3792         /* Initialize the first hwfn - will learn number of hwfns */
3793         rc = ecore_hw_prepare_single(p_hwfn,
3794                                      p_dev->regview,
3795                                      p_dev->doorbells, p_params);
3796         if (rc != ECORE_SUCCESS)
3797                 return rc;
3798
3799         p_params->personality = p_hwfn->hw_info.personality;
3800
3801         /* initilalize 2nd hwfn if necessary */
3802         if (p_dev->num_hwfns > 1) {
3803                 void OSAL_IOMEM *p_regview, *p_doorbell;
3804                 u8 OSAL_IOMEM *addr;
3805
3806                 /* adjust bar offset for second engine */
3807                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3808                                         ecore_hw_bar_size(p_hwfn,
3809                                                           p_hwfn->p_main_ptt,
3810                                                           BAR_ID_0) / 2;
3811                 p_regview = (void OSAL_IOMEM *)addr;
3812
3813                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3814                                         ecore_hw_bar_size(p_hwfn,
3815                                                           p_hwfn->p_main_ptt,
3816                                                           BAR_ID_1) / 2;
3817                 p_doorbell = (void OSAL_IOMEM *)addr;
3818
3819                 /* prepare second hw function */
3820                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3821                                              p_doorbell, p_params);
3822
3823                 /* in case of error, need to free the previously
3824                  * initiliazed hwfn 0.
3825                  */
3826                 if (rc != ECORE_SUCCESS) {
3827                         if (p_params->b_relaxed_probe)
3828                                 p_params->p_relaxed_res =
3829                                                 ECORE_HW_PREPARE_FAILED_ENG2;
3830
3831                         if (IS_PF(p_dev)) {
3832                                 ecore_init_free(p_hwfn);
3833                                 ecore_mcp_free(p_hwfn);
3834                                 ecore_hw_hwfn_free(p_hwfn);
3835                         } else {
3836                                 DP_NOTICE(p_dev, true,
3837                                           "What do we need to free when VF hwfn1 init fails\n");
3838                         }
3839                         return rc;
3840                 }
3841         }
3842
3843         return rc;
3844 }
3845
3846 void ecore_hw_remove(struct ecore_dev *p_dev)
3847 {
3848         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3849         int i;
3850
3851         if (IS_PF(p_dev))
3852                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3853                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
3854
3855         for_each_hwfn(p_dev, i) {
3856                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3857
3858                 if (IS_VF(p_dev)) {
3859                         ecore_vf_pf_release(p_hwfn);
3860                         continue;
3861                 }
3862
3863                 ecore_init_free(p_hwfn);
3864                 ecore_hw_hwfn_free(p_hwfn);
3865                 ecore_mcp_free(p_hwfn);
3866
3867 #ifdef CONFIG_ECORE_LOCK_ALLOC
3868                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3869 #endif
3870         }
3871
3872         ecore_iov_free_hw_info(p_dev);
3873 }
3874
3875 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3876                                       struct ecore_chain *p_chain)
3877 {
3878         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3879         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3880         struct ecore_chain_next *p_next;
3881         u32 size, i;
3882
3883         if (!p_virt)
3884                 return;
3885
3886         size = p_chain->elem_size * p_chain->usable_per_page;
3887
3888         for (i = 0; i < p_chain->page_cnt; i++) {
3889                 if (!p_virt)
3890                         break;
3891
3892                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3893                 p_virt_next = p_next->next_virt;
3894                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3895
3896                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3897                                        ECORE_CHAIN_PAGE_SIZE);
3898
3899                 p_virt = p_virt_next;
3900                 p_phys = p_phys_next;
3901         }
3902 }
3903
3904 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3905                                     struct ecore_chain *p_chain)
3906 {
3907         if (!p_chain->p_virt_addr)
3908                 return;
3909
3910         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3911                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3912 }
3913
3914 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3915                                  struct ecore_chain *p_chain)
3916 {
3917         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3918         u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
3919         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3920
3921         if (!pp_virt_addr_tbl)
3922                 return;
3923
3924         if (!p_pbl_virt)
3925                 goto out;
3926
3927         for (i = 0; i < page_cnt; i++) {
3928                 if (!pp_virt_addr_tbl[i])
3929                         break;
3930
3931                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3932                                        *(dma_addr_t *)p_pbl_virt,
3933                                        ECORE_CHAIN_PAGE_SIZE);
3934
3935                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3936         }
3937
3938         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3939
3940         if (!p_chain->b_external_pbl)
3941                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
3942                                        p_chain->pbl_sp.p_phys_table, pbl_size);
3943 out:
3944         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3945 }
3946
3947 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3948 {
3949         switch (p_chain->mode) {
3950         case ECORE_CHAIN_MODE_NEXT_PTR:
3951                 ecore_chain_free_next_ptr(p_dev, p_chain);
3952                 break;
3953         case ECORE_CHAIN_MODE_SINGLE:
3954                 ecore_chain_free_single(p_dev, p_chain);
3955                 break;
3956         case ECORE_CHAIN_MODE_PBL:
3957                 ecore_chain_free_pbl(p_dev, p_chain);
3958                 break;
3959         }
3960 }
3961
3962 static enum _ecore_status_t
3963 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3964                                enum ecore_chain_cnt_type cnt_type,
3965                                osal_size_t elem_size, u32 page_cnt)
3966 {
3967         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3968
3969         /* The actual chain size can be larger than the maximal possible value
3970          * after rounding up the requested elements number to pages, and after
3971          * taking into acount the unusuable elements (next-ptr elements).
3972          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3973          * size/capacity fields are of a u32 type.
3974          */
3975         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3976              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3977             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3978              chain_size > ECORE_U32_MAX)) {
3979                 DP_NOTICE(p_dev, true,
3980                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3981                           (unsigned long)chain_size);
3982                 return ECORE_INVAL;
3983         }
3984
3985         return ECORE_SUCCESS;
3986 }
3987
3988 static enum _ecore_status_t
3989 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3990 {
3991         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3992         dma_addr_t p_phys = 0;
3993         u32 i;
3994
3995         for (i = 0; i < p_chain->page_cnt; i++) {
3996                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3997                                                  ECORE_CHAIN_PAGE_SIZE);
3998                 if (!p_virt) {
3999                         DP_NOTICE(p_dev, true,
4000                                   "Failed to allocate chain memory\n");
4001                         return ECORE_NOMEM;
4002                 }
4003
4004                 if (i == 0) {
4005                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4006                         ecore_chain_reset(p_chain);
4007                 } else {
4008                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4009                                                        p_virt, p_phys);
4010                 }
4011
4012                 p_virt_prev = p_virt;
4013         }
4014         /* Last page's next element should point to the beginning of the
4015          * chain.
4016          */
4017         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4018                                        p_chain->p_virt_addr,
4019                                        p_chain->p_phys_addr);
4020
4021         return ECORE_SUCCESS;
4022 }
4023
4024 static enum _ecore_status_t
4025 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4026 {
4027         dma_addr_t p_phys = 0;
4028         void *p_virt = OSAL_NULL;
4029
4030         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
4031         if (!p_virt) {
4032                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
4033                 return ECORE_NOMEM;
4034         }
4035
4036         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4037         ecore_chain_reset(p_chain);
4038
4039         return ECORE_SUCCESS;
4040 }
4041
4042 static enum _ecore_status_t
4043 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
4044                       struct ecore_chain *p_chain,
4045                       struct ecore_chain_ext_pbl *ext_pbl)
4046 {
4047         void *p_virt = OSAL_NULL;
4048         u8 *p_pbl_virt = OSAL_NULL;
4049         void **pp_virt_addr_tbl = OSAL_NULL;
4050         dma_addr_t p_phys = 0, p_pbl_phys = 0;
4051         u32 page_cnt = p_chain->page_cnt, size, i;
4052
4053         size = page_cnt * sizeof(*pp_virt_addr_tbl);
4054         pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
4055         if (!pp_virt_addr_tbl) {
4056                 DP_NOTICE(p_dev, true,
4057                           "Failed to allocate memory for the chain virtual addresses table\n");
4058                 return ECORE_NOMEM;
4059         }
4060
4061         /* The allocation of the PBL table is done with its full size, since it
4062          * is expected to be successive.
4063          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
4064          * failure, since pp_virt_addr_tbl was previously allocated, and it
4065          * should be saved to allow its freeing during the error flow.
4066          */
4067         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4068
4069         if (ext_pbl == OSAL_NULL) {
4070                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
4071         } else {
4072                 p_pbl_virt = ext_pbl->p_pbl_virt;
4073                 p_pbl_phys = ext_pbl->p_pbl_phys;
4074                 p_chain->b_external_pbl = true;
4075         }
4076
4077         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
4078                                  pp_virt_addr_tbl);
4079         if (!p_pbl_virt) {
4080                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
4081                 return ECORE_NOMEM;
4082         }
4083
4084         for (i = 0; i < page_cnt; i++) {
4085                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4086                                                  ECORE_CHAIN_PAGE_SIZE);
4087                 if (!p_virt) {
4088                         DP_NOTICE(p_dev, true,
4089                                   "Failed to allocate chain memory\n");
4090                         return ECORE_NOMEM;
4091                 }
4092
4093                 if (i == 0) {
4094                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4095                         ecore_chain_reset(p_chain);
4096                 }
4097
4098                 /* Fill the PBL table with the physical address of the page */
4099                 *(dma_addr_t *)p_pbl_virt = p_phys;
4100                 /* Keep the virtual address of the page */
4101                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
4102
4103                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4104         }
4105
4106         return ECORE_SUCCESS;
4107 }
4108
4109 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
4110                                        enum ecore_chain_use_mode intended_use,
4111                                        enum ecore_chain_mode mode,
4112                                        enum ecore_chain_cnt_type cnt_type,
4113                                        u32 num_elems, osal_size_t elem_size,
4114                                        struct ecore_chain *p_chain,
4115                                        struct ecore_chain_ext_pbl *ext_pbl)
4116 {
4117         u32 page_cnt;
4118         enum _ecore_status_t rc = ECORE_SUCCESS;
4119
4120         if (mode == ECORE_CHAIN_MODE_SINGLE)
4121                 page_cnt = 1;
4122         else
4123                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4124
4125         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
4126                                             page_cnt);
4127         if (rc) {
4128                 DP_NOTICE(p_dev, true,
4129                           "Cannot allocate a chain with the given arguments:\n"
4130                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4131                           intended_use, mode, cnt_type, num_elems, elem_size);
4132                 return rc;
4133         }
4134
4135         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
4136                                 mode, cnt_type, p_dev->dp_ctx);
4137
4138         switch (mode) {
4139         case ECORE_CHAIN_MODE_NEXT_PTR:
4140                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
4141                 break;
4142         case ECORE_CHAIN_MODE_SINGLE:
4143                 rc = ecore_chain_alloc_single(p_dev, p_chain);
4144                 break;
4145         case ECORE_CHAIN_MODE_PBL:
4146                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
4147                 break;
4148         }
4149         if (rc)
4150                 goto nomem;
4151
4152         return ECORE_SUCCESS;
4153
4154 nomem:
4155         ecore_chain_free(p_dev, p_chain);
4156         return rc;
4157 }
4158
4159 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
4160                                        u16 src_id, u16 *dst_id)
4161 {
4162         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
4163                 u16 min, max;
4164
4165                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
4166                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
4167                 DP_NOTICE(p_hwfn, true,
4168                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4169                           src_id, min, max);
4170
4171                 return ECORE_INVAL;
4172         }
4173
4174         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
4175
4176         return ECORE_SUCCESS;
4177 }
4178
4179 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
4180                                     u8 src_id, u8 *dst_id)
4181 {
4182         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
4183                 u8 min, max;
4184
4185                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
4186                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
4187                 DP_NOTICE(p_hwfn, true,
4188                           "vport id [%d] is not valid, available indices [%d - %d]\n",
4189                           src_id, min, max);
4190
4191                 return ECORE_INVAL;
4192         }
4193
4194         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
4195
4196         return ECORE_SUCCESS;
4197 }
4198
4199 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
4200                                       u8 src_id, u8 *dst_id)
4201 {
4202         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
4203                 u8 min, max;
4204
4205                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
4206                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
4207                 DP_NOTICE(p_hwfn, true,
4208                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4209                           src_id, min, max);
4210
4211                 return ECORE_INVAL;
4212         }
4213
4214         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
4215
4216         return ECORE_SUCCESS;
4217 }
4218
4219 static enum _ecore_status_t
4220 ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4221                                struct ecore_ptt *p_ptt, u32 high, u32 low,
4222                                u32 *p_entry_num)
4223 {
4224         u32 en;
4225         int i;
4226
4227         /* Find a free entry and utilize it */
4228         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4229                 en = ecore_rd(p_hwfn, p_ptt,
4230                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4231                               i * sizeof(u32));
4232                 if (en)
4233                         continue;
4234                 ecore_wr(p_hwfn, p_ptt,
4235                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4236                          2 * i * sizeof(u32), low);
4237                 ecore_wr(p_hwfn, p_ptt,
4238                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4239                          (2 * i + 1) * sizeof(u32), high);
4240                 ecore_wr(p_hwfn, p_ptt,
4241                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4242                          i * sizeof(u32), 0);
4243                 ecore_wr(p_hwfn, p_ptt,
4244                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4245                          i * sizeof(u32), 0);
4246                 ecore_wr(p_hwfn, p_ptt,
4247                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4248                          i * sizeof(u32), 1);
4249                 break;
4250         }
4251
4252         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4253                 return ECORE_NORESOURCES;
4254
4255         *p_entry_num = i;
4256
4257         return ECORE_SUCCESS;
4258 }
4259
4260 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4261                                           struct ecore_ptt *p_ptt, u8 *p_filter)
4262 {
4263         u32 high, low, entry_num;
4264         enum _ecore_status_t rc;
4265
4266         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4267                 return ECORE_SUCCESS;
4268
4269         high = p_filter[1] | (p_filter[0] << 8);
4270         low = p_filter[5] | (p_filter[4] << 8) |
4271               (p_filter[3] << 16) | (p_filter[2] << 24);
4272
4273         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4274                 rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low,
4275                                                     &entry_num);
4276         if (rc != ECORE_SUCCESS) {
4277                 DP_NOTICE(p_hwfn, false,
4278                           "Failed to find an empty LLH filter to utilize\n");
4279                 return rc;
4280         }
4281
4282         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4283                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n",
4284                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4285                    p_filter[4], p_filter[5], entry_num);
4286
4287         return ECORE_SUCCESS;
4288 }
4289
4290 static enum _ecore_status_t
4291 ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4292                                   struct ecore_ptt *p_ptt, u32 high, u32 low,
4293                                   u32 *p_entry_num)
4294 {
4295         int i;
4296
4297         /* Find the entry and clean it */
4298         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4299                 if (ecore_rd(p_hwfn, p_ptt,
4300                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4301                              2 * i * sizeof(u32)) != low)
4302                         continue;
4303                 if (ecore_rd(p_hwfn, p_ptt,
4304                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4305                              (2 * i + 1) * sizeof(u32)) != high)
4306                         continue;
4307
4308                 ecore_wr(p_hwfn, p_ptt,
4309                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4310                 ecore_wr(p_hwfn, p_ptt,
4311                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4312                          2 * i * sizeof(u32), 0);
4313                 ecore_wr(p_hwfn, p_ptt,
4314                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4315                          (2 * i + 1) * sizeof(u32), 0);
4316                 break;
4317         }
4318
4319         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4320                 return ECORE_INVAL;
4321
4322         *p_entry_num = i;
4323
4324         return ECORE_SUCCESS;
4325 }
4326
4327 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4328                              struct ecore_ptt *p_ptt, u8 *p_filter)
4329 {
4330         u32 high, low, entry_num;
4331         enum _ecore_status_t rc;
4332
4333         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4334                 return;
4335
4336         high = p_filter[1] | (p_filter[0] << 8);
4337         low = p_filter[5] | (p_filter[4] << 8) |
4338               (p_filter[3] << 16) | (p_filter[2] << 24);
4339
4340         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4341                 rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high,
4342                                                        low, &entry_num);
4343         if (rc != ECORE_SUCCESS) {
4344                 DP_NOTICE(p_hwfn, false,
4345                           "Tried to remove a non-configured filter\n");
4346                 return;
4347         }
4348
4349
4350         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4351                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n",
4352                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4353                    p_filter[4], p_filter[5], entry_num);
4354 }
4355
4356 static enum _ecore_status_t
4357 ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4358                                     struct ecore_ptt *p_ptt,
4359                                     enum ecore_llh_port_filter_type_t type,
4360                                     u32 high, u32 low, u32 *p_entry_num)
4361 {
4362         u32 en;
4363         int i;
4364
4365         /* Find a free entry and utilize it */
4366         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4367                 en = ecore_rd(p_hwfn, p_ptt,
4368                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4369                               i * sizeof(u32));
4370                 if (en)
4371                         continue;
4372                 ecore_wr(p_hwfn, p_ptt,
4373                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4374                          2 * i * sizeof(u32), low);
4375                 ecore_wr(p_hwfn, p_ptt,
4376                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4377                          (2 * i + 1) * sizeof(u32), high);
4378                 ecore_wr(p_hwfn, p_ptt,
4379                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4380                          i * sizeof(u32), 1);
4381                 ecore_wr(p_hwfn, p_ptt,
4382                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4383                          i * sizeof(u32), 1 << type);
4384                 ecore_wr(p_hwfn, p_ptt,
4385                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1);
4386                 break;
4387         }
4388
4389         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4390                 return ECORE_NORESOURCES;
4391
4392         *p_entry_num = i;
4393
4394         return ECORE_SUCCESS;
4395 }
4396
4397 enum _ecore_status_t
4398 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4399                               struct ecore_ptt *p_ptt,
4400                               u16 source_port_or_eth_type,
4401                               u16 dest_port,
4402                               enum ecore_llh_port_filter_type_t type)
4403 {
4404         u32 high, low, entry_num;
4405         enum _ecore_status_t rc;
4406
4407         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4408                 return ECORE_SUCCESS;
4409
4410         high = 0;
4411         low = 0;
4412
4413         switch (type) {
4414         case ECORE_LLH_FILTER_ETHERTYPE:
4415                 high = source_port_or_eth_type;
4416                 break;
4417         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4418         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4419                 low = source_port_or_eth_type << 16;
4420                 break;
4421         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4422         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4423                 low = dest_port;
4424                 break;
4425         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4426         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4427                 low = (source_port_or_eth_type << 16) | dest_port;
4428                 break;
4429         default:
4430                 DP_NOTICE(p_hwfn, true,
4431                           "Non valid LLH protocol filter type %d\n", type);
4432                 return ECORE_INVAL;
4433         }
4434
4435         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4436                 rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4437                                                          high, low, &entry_num);
4438         if (rc != ECORE_SUCCESS) {
4439                 DP_NOTICE(p_hwfn, false,
4440                           "Failed to find an empty LLH filter to utilize\n");
4441                 return rc;
4442         }
4443         switch (type) {
4444         case ECORE_LLH_FILTER_ETHERTYPE:
4445                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4446                            "ETH type %x is added at %d\n",
4447                            source_port_or_eth_type, entry_num);
4448                 break;
4449         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4450                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4451                            "TCP src port %x is added at %d\n",
4452                            source_port_or_eth_type, entry_num);
4453                 break;
4454         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4455                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4456                            "UDP src port %x is added at %d\n",
4457                            source_port_or_eth_type, entry_num);
4458                 break;
4459         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4460                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4461                            "TCP dst port %x is added at %d\n", dest_port,
4462                            entry_num);
4463                 break;
4464         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4465                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4466                            "UDP dst port %x is added at %d\n", dest_port,
4467                            entry_num);
4468                 break;
4469         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4470                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4471                            "TCP src/dst ports %x/%x are added at %d\n",
4472                            source_port_or_eth_type, dest_port, entry_num);
4473                 break;
4474         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4475                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4476                            "UDP src/dst ports %x/%x are added at %d\n",
4477                            source_port_or_eth_type, dest_port, entry_num);
4478                 break;
4479         }
4480
4481         return ECORE_SUCCESS;
4482 }
4483
4484 static enum _ecore_status_t
4485 ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4486                                        struct ecore_ptt *p_ptt,
4487                                        enum ecore_llh_port_filter_type_t type,
4488                                        u32 high, u32 low, u32 *p_entry_num)
4489 {
4490         int i;
4491
4492         /* Find the entry and clean it */
4493         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4494                 if (!ecore_rd(p_hwfn, p_ptt,
4495                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4496                               i * sizeof(u32)))
4497                         continue;
4498                 if (!ecore_rd(p_hwfn, p_ptt,
4499                               NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4500                               i * sizeof(u32)))
4501                         continue;
4502                 if (!(ecore_rd(p_hwfn, p_ptt,
4503                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4504                                i * sizeof(u32)) & (1 << type)))
4505                         continue;
4506                 if (ecore_rd(p_hwfn, p_ptt,
4507                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4508                              2 * i * sizeof(u32)) != low)
4509                         continue;
4510                 if (ecore_rd(p_hwfn, p_ptt,
4511                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4512                              (2 * i + 1) * sizeof(u32)) != high)
4513                         continue;
4514
4515                 ecore_wr(p_hwfn, p_ptt,
4516                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4517                 ecore_wr(p_hwfn, p_ptt,
4518                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4519                          i * sizeof(u32), 0);
4520                 ecore_wr(p_hwfn, p_ptt,
4521                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4522                          i * sizeof(u32), 0);
4523                 ecore_wr(p_hwfn, p_ptt,
4524                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4525                          2 * i * sizeof(u32), 0);
4526                 ecore_wr(p_hwfn, p_ptt,
4527                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4528                          (2 * i + 1) * sizeof(u32), 0);
4529                 break;
4530         }
4531
4532         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4533                 return ECORE_INVAL;
4534
4535         *p_entry_num = i;
4536
4537         return ECORE_SUCCESS;
4538 }
4539
4540 void
4541 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4542                                  struct ecore_ptt *p_ptt,
4543                                  u16 source_port_or_eth_type,
4544                                  u16 dest_port,
4545                                  enum ecore_llh_port_filter_type_t type)
4546 {
4547         u32 high, low, entry_num;
4548         enum _ecore_status_t rc;
4549
4550         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4551                 return;
4552
4553         high = 0;
4554         low = 0;
4555
4556         switch (type) {
4557         case ECORE_LLH_FILTER_ETHERTYPE:
4558                 high = source_port_or_eth_type;
4559                 break;
4560         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4561         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4562                 low = source_port_or_eth_type << 16;
4563                 break;
4564         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4565         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4566                 low = dest_port;
4567                 break;
4568         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4569         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4570                 low = (source_port_or_eth_type << 16) | dest_port;
4571                 break;
4572         default:
4573                 DP_NOTICE(p_hwfn, true,
4574                           "Non valid LLH protocol filter type %d\n", type);
4575                 return;
4576         }
4577
4578         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4579                 rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4580                                                             high, low,
4581                                                             &entry_num);
4582         if (rc != ECORE_SUCCESS) {
4583                 DP_NOTICE(p_hwfn, false,
4584                           "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n",
4585                           type, source_port_or_eth_type, dest_port);
4586                 return;
4587         }
4588
4589         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4590                    "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n",
4591                    type, source_port_or_eth_type, dest_port, entry_num);
4592 }
4593
4594 static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn,
4595                                               struct ecore_ptt *p_ptt)
4596 {
4597         int i;
4598
4599         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4600                 return;
4601
4602         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4603                 ecore_wr(p_hwfn, p_ptt,
4604                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2  +
4605                          i * sizeof(u32), 0);
4606                 ecore_wr(p_hwfn, p_ptt,
4607                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4608                          2 * i * sizeof(u32), 0);
4609                 ecore_wr(p_hwfn, p_ptt,
4610                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4611                          (2 * i + 1) * sizeof(u32), 0);
4612         }
4613 }
4614
4615 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4616                              struct ecore_ptt *p_ptt)
4617 {
4618         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4619                 return;
4620
4621         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4622                 ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt);
4623 }
4624
4625 enum _ecore_status_t
4626 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
4627                                   struct ecore_ptt *p_ptt)
4628 {
4629         if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
4630                 ecore_wr(p_hwfn, p_ptt,
4631                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
4632                          1 << p_hwfn->abs_pf_id / 2);
4633                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
4634                 return ECORE_SUCCESS;
4635         }
4636
4637         DP_NOTICE(p_hwfn, false,
4638                   "This function can't be set as default\n");
4639         return ECORE_INVAL;
4640 }
4641
4642 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
4643                                                struct ecore_ptt *p_ptt,
4644                                                u32 hw_addr, void *p_eth_qzone,
4645                                                osal_size_t eth_qzone_size,
4646                                                u8 timeset)
4647 {
4648         struct coalescing_timeset *p_coal_timeset;
4649
4650         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
4651                 DP_NOTICE(p_hwfn, true,
4652                           "Coalescing configuration not enabled\n");
4653                 return ECORE_INVAL;
4654         }
4655
4656         p_coal_timeset = p_eth_qzone;
4657         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
4658         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
4659         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
4660         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
4661
4662         return ECORE_SUCCESS;
4663 }
4664
4665 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
4666                                               u16 rx_coal, u16 tx_coal,
4667                                               void *p_handle)
4668 {
4669         struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
4670         enum _ecore_status_t rc = ECORE_SUCCESS;
4671         struct ecore_ptt *p_ptt;
4672
4673         /* TODO - Configuring a single queue's coalescing but
4674          * claiming all queues are abiding same configuration
4675          * for PF and VF both.
4676          */
4677
4678         if (IS_VF(p_hwfn->p_dev))
4679                 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
4680                                                 tx_coal, p_cid);
4681
4682         p_ptt = ecore_ptt_acquire(p_hwfn);
4683         if (!p_ptt)
4684                 return ECORE_AGAIN;
4685
4686         if (rx_coal) {
4687                 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
4688                 if (rc)
4689                         goto out;
4690                 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
4691         }
4692
4693         if (tx_coal) {
4694                 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
4695                 if (rc)
4696                         goto out;
4697                 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
4698         }
4699 out:
4700         ecore_ptt_release(p_hwfn, p_ptt);
4701
4702         return rc;
4703 }
4704
4705 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
4706                                             struct ecore_ptt *p_ptt,
4707                                             u16 coalesce,
4708                                             struct ecore_queue_cid *p_cid)
4709 {
4710         struct ustorm_eth_queue_zone eth_qzone;
4711         u8 timeset, timer_res;
4712         u32 address;
4713         enum _ecore_status_t rc;
4714
4715         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4716         if (coalesce <= 0x7F) {
4717                 timer_res = 0;
4718         } else if (coalesce <= 0xFF) {
4719                 timer_res = 1;
4720         } else if (coalesce <= 0x1FF) {
4721                 timer_res = 2;
4722         } else {
4723                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4724                 return ECORE_INVAL;
4725         }
4726         timeset = (u8)(coalesce >> timer_res);
4727
4728         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4729                                      p_cid->sb_igu_id, false);
4730         if (rc != ECORE_SUCCESS)
4731                 goto out;
4732
4733         address = BAR0_MAP_REG_USDM_RAM +
4734                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4735
4736         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4737                                 sizeof(struct ustorm_eth_queue_zone), timeset);
4738         if (rc != ECORE_SUCCESS)
4739                 goto out;
4740
4741 out:
4742         return rc;
4743 }
4744
4745 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
4746                                             struct ecore_ptt *p_ptt,
4747                                             u16 coalesce,
4748                                             struct ecore_queue_cid *p_cid)
4749 {
4750         struct xstorm_eth_queue_zone eth_qzone;
4751         u8 timeset, timer_res;
4752         u32 address;
4753         enum _ecore_status_t rc;
4754
4755         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4756         if (coalesce <= 0x7F) {
4757                 timer_res = 0;
4758         } else if (coalesce <= 0xFF) {
4759                 timer_res = 1;
4760         } else if (coalesce <= 0x1FF) {
4761                 timer_res = 2;
4762         } else {
4763                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4764                 return ECORE_INVAL;
4765         }
4766
4767         timeset = (u8)(coalesce >> timer_res);
4768
4769         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4770                                      p_cid->sb_igu_id, true);
4771         if (rc != ECORE_SUCCESS)
4772                 goto out;
4773
4774         address = BAR0_MAP_REG_XSDM_RAM +
4775                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4776
4777         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4778                                 sizeof(struct xstorm_eth_queue_zone), timeset);
4779 out:
4780         return rc;
4781 }
4782
4783 /* Calculate final WFQ values for all vports and configure it.
4784  * After this configuration each vport must have
4785  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
4786  */
4787 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4788                                                struct ecore_ptt *p_ptt,
4789                                                u32 min_pf_rate)
4790 {
4791         struct init_qm_vport_params *vport_params;
4792         int i;
4793
4794         vport_params = p_hwfn->qm_info.qm_vport_params;
4795
4796         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4797                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4798
4799                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
4800                     min_pf_rate;
4801                 ecore_init_vport_wfq(p_hwfn, p_ptt,
4802                                      vport_params[i].first_tx_pq_id,
4803                                      vport_params[i].vport_wfq);
4804         }
4805 }
4806
4807 static void
4808 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
4809 {
4810         int i;
4811
4812         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4813                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4814 }
4815
4816 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4817                                              struct ecore_ptt *p_ptt,
4818                                              u32 min_pf_rate)
4819 {
4820         struct init_qm_vport_params *vport_params;
4821         int i;
4822
4823         vport_params = p_hwfn->qm_info.qm_vport_params;
4824
4825         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4826                 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
4827                 ecore_init_vport_wfq(p_hwfn, p_ptt,
4828                                      vport_params[i].first_tx_pq_id,
4829                                      vport_params[i].vport_wfq);
4830         }
4831 }
4832
4833 /* This function performs several validations for WFQ
4834  * configuration and required min rate for a given vport
4835  * 1. req_rate must be greater than one percent of min_pf_rate.
4836  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4837  *    rates to get less than one percent of min_pf_rate.
4838  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4839  */
4840 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
4841                                                  u16 vport_id, u32 req_rate,
4842                                                  u32 min_pf_rate)
4843 {
4844         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4845         int non_requested_count = 0, req_count = 0, i, num_vports;
4846
4847         num_vports = p_hwfn->qm_info.num_vports;
4848
4849 /* Accounting for the vports which are configured for WFQ explicitly */
4850
4851         for (i = 0; i < num_vports; i++) {
4852                 u32 tmp_speed;
4853
4854                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
4855                         req_count++;
4856                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4857                         total_req_min_rate += tmp_speed;
4858                 }
4859         }
4860
4861         /* Include current vport data as well */
4862         req_count++;
4863         total_req_min_rate += req_rate;
4864         non_requested_count = num_vports - req_count;
4865
4866         /* validate possible error cases */
4867         if (req_rate > min_pf_rate) {
4868                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4869                            "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4870                            vport_id, req_rate, min_pf_rate);
4871                 return ECORE_INVAL;
4872         }
4873
4874         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
4875                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4876                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4877                            vport_id, req_rate, min_pf_rate);
4878                 return ECORE_INVAL;
4879         }
4880
4881         /* TBD - for number of vports greater than 100 */
4882         if (num_vports > ECORE_WFQ_UNIT) {
4883                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4884                            "Number of vports is greater than %d\n",
4885                            ECORE_WFQ_UNIT);
4886                 return ECORE_INVAL;
4887         }
4888
4889         if (total_req_min_rate > min_pf_rate) {
4890                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4891                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4892                            total_req_min_rate, min_pf_rate);
4893                 return ECORE_INVAL;
4894         }
4895
4896         /* Data left for non requested vports */
4897         total_left_rate = min_pf_rate - total_req_min_rate;
4898         left_rate_per_vp = total_left_rate / non_requested_count;
4899
4900         /* validate if non requested get < 1% of min bw */
4901         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4902                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4903                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4904                            left_rate_per_vp, min_pf_rate);
4905                 return ECORE_INVAL;
4906         }
4907
4908         /* now req_rate for given vport passes all scenarios.
4909          * assign final wfq rates to all vports.
4910          */
4911         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4912         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4913
4914         for (i = 0; i < num_vports; i++) {
4915                 if (p_hwfn->qm_info.wfq_data[i].configured)
4916                         continue;
4917
4918                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4919         }
4920
4921         return ECORE_SUCCESS;
4922 }
4923
4924 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4925                                        struct ecore_ptt *p_ptt,
4926                                        u16 vp_id, u32 rate)
4927 {
4928         struct ecore_mcp_link_state *p_link;
4929         int rc = ECORE_SUCCESS;
4930
4931         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4932
4933         if (!p_link->min_pf_rate) {
4934                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4935                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4936                 return rc;
4937         }
4938
4939         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4940
4941         if (rc == ECORE_SUCCESS)
4942                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4943                                                    p_link->min_pf_rate);
4944         else
4945                 DP_NOTICE(p_hwfn, false,
4946                           "Validation failed while configuring min rate\n");
4947
4948         return rc;
4949 }
4950
4951 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4952                                                    struct ecore_ptt *p_ptt,
4953                                                    u32 min_pf_rate)
4954 {
4955         bool use_wfq = false;
4956         int rc = ECORE_SUCCESS;
4957         u16 i;
4958
4959         /* Validate all pre configured vports for wfq */
4960         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4961                 u32 rate;
4962
4963                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4964                         continue;
4965
4966                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4967                 use_wfq = true;
4968
4969                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4970                 if (rc != ECORE_SUCCESS) {
4971                         DP_NOTICE(p_hwfn, false,
4972                                   "WFQ validation failed while configuring min rate\n");
4973                         break;
4974                 }
4975         }
4976
4977         if (rc == ECORE_SUCCESS && use_wfq)
4978                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4979         else
4980                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4981
4982         return rc;
4983 }
4984
4985 /* Main API for ecore clients to configure vport min rate.
4986  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4987  * rate - Speed in Mbps needs to be assigned to a given vport.
4988  */
4989 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4990 {
4991         int i, rc = ECORE_INVAL;
4992
4993         /* TBD - for multiple hardware functions - that is 100 gig */
4994         if (p_dev->num_hwfns > 1) {
4995                 DP_NOTICE(p_dev, false,
4996                           "WFQ configuration is not supported for this device\n");
4997                 return rc;
4998         }
4999
5000         for_each_hwfn(p_dev, i) {
5001                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5002                 struct ecore_ptt *p_ptt;
5003
5004                 p_ptt = ecore_ptt_acquire(p_hwfn);
5005                 if (!p_ptt)
5006                         return ECORE_TIMEOUT;
5007
5008                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5009
5010                 if (rc != ECORE_SUCCESS) {
5011                         ecore_ptt_release(p_hwfn, p_ptt);
5012                         return rc;
5013                 }
5014
5015                 ecore_ptt_release(p_hwfn, p_ptt);
5016         }
5017
5018         return rc;
5019 }
5020
5021 /* API to configure WFQ from mcp link change */
5022 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
5023                                            struct ecore_ptt *p_ptt,
5024                                            u32 min_pf_rate)
5025 {
5026         int i;
5027
5028         /* TBD - for multiple hardware functions - that is 100 gig */
5029         if (p_dev->num_hwfns > 1) {
5030                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
5031                            "WFQ configuration is not supported for this device\n");
5032                 return;
5033         }
5034
5035         for_each_hwfn(p_dev, i) {
5036                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5037
5038                 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5039                                                         min_pf_rate);
5040         }
5041 }
5042
5043 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
5044                                        struct ecore_ptt *p_ptt,
5045                                        struct ecore_mcp_link_state *p_link,
5046                                        u8 max_bw)
5047 {
5048         int rc = ECORE_SUCCESS;
5049
5050         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5051
5052         if (!p_link->line_speed && (max_bw != 100))
5053                 return rc;
5054
5055         p_link->speed = (p_link->line_speed * max_bw) / 100;
5056         p_hwfn->qm_info.pf_rl = p_link->speed;
5057
5058         /* Since the limiter also affects Tx-switched traffic, we don't want it
5059          * to limit such traffic in case there's no actual limit.
5060          * In that case, set limit to imaginary high boundary.
5061          */
5062         if (max_bw == 100)
5063                 p_hwfn->qm_info.pf_rl = 100000;
5064
5065         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5066                               p_hwfn->qm_info.pf_rl);
5067
5068         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5069                    "Configured MAX bandwidth to be %08x Mb/sec\n",
5070                    p_link->speed);
5071
5072         return rc;
5073 }
5074
5075 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5076 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
5077 {
5078         int i, rc = ECORE_INVAL;
5079
5080         if (max_bw < 1 || max_bw > 100) {
5081                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
5082                 return rc;
5083         }
5084
5085         for_each_hwfn(p_dev, i) {
5086                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5087                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5088                 struct ecore_mcp_link_state *p_link;
5089                 struct ecore_ptt *p_ptt;
5090
5091                 p_link = &p_lead->mcp_info->link_output;
5092
5093                 p_ptt = ecore_ptt_acquire(p_hwfn);
5094                 if (!p_ptt)
5095                         return ECORE_TIMEOUT;
5096
5097                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5098                                                         p_link, max_bw);
5099
5100                 ecore_ptt_release(p_hwfn, p_ptt);
5101
5102                 if (rc != ECORE_SUCCESS)
5103                         break;
5104         }
5105
5106         return rc;
5107 }
5108
5109 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
5110                                        struct ecore_ptt *p_ptt,
5111                                        struct ecore_mcp_link_state *p_link,
5112                                        u8 min_bw)
5113 {
5114         int rc = ECORE_SUCCESS;
5115
5116         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5117         p_hwfn->qm_info.pf_wfq = min_bw;
5118
5119         if (!p_link->line_speed)
5120                 return rc;
5121
5122         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5123
5124         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5125
5126         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5127                    "Configured MIN bandwidth to be %d Mb/sec\n",
5128                    p_link->min_pf_rate);
5129
5130         return rc;
5131 }
5132
5133 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5134 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
5135 {
5136         int i, rc = ECORE_INVAL;
5137
5138         if (min_bw < 1 || min_bw > 100) {
5139                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
5140                 return rc;
5141         }
5142
5143         for_each_hwfn(p_dev, i) {
5144                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5145                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5146                 struct ecore_mcp_link_state *p_link;
5147                 struct ecore_ptt *p_ptt;
5148
5149                 p_link = &p_lead->mcp_info->link_output;
5150
5151                 p_ptt = ecore_ptt_acquire(p_hwfn);
5152                 if (!p_ptt)
5153                         return ECORE_TIMEOUT;
5154
5155                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5156                                                         p_link, min_bw);
5157                 if (rc != ECORE_SUCCESS) {
5158                         ecore_ptt_release(p_hwfn, p_ptt);
5159                         return rc;
5160                 }
5161
5162                 if (p_link->min_pf_rate) {
5163                         u32 min_rate = p_link->min_pf_rate;
5164
5165                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
5166                                                                      p_ptt,
5167                                                                      min_rate);
5168                 }
5169
5170                 ecore_ptt_release(p_hwfn, p_ptt);
5171         }
5172
5173         return rc;
5174 }
5175
5176 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
5177 {
5178         struct ecore_mcp_link_state *p_link;
5179
5180         p_link = &p_hwfn->mcp_info->link_output;
5181
5182         if (p_link->min_pf_rate)
5183                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
5184                                                  p_link->min_pf_rate);
5185
5186         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
5187                     sizeof(*p_hwfn->qm_info.wfq_data) *
5188                     p_hwfn->qm_info.num_vports);
5189 }
5190
5191 int ecore_device_num_engines(struct ecore_dev *p_dev)
5192 {
5193         return ECORE_IS_BB(p_dev) ? 2 : 1;
5194 }
5195
5196 int ecore_device_num_ports(struct ecore_dev *p_dev)
5197 {
5198         /* in CMT always only one port */
5199         if (p_dev->num_hwfns > 1)
5200                 return 1;
5201
5202         return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
5203 }
5204
5205 void ecore_set_fw_mac_addr(__le16 *fw_msb,
5206                           __le16 *fw_mid,
5207                           __le16 *fw_lsb,
5208                           u8 *mac)
5209 {
5210         ((u8 *)fw_msb)[0] = mac[1];
5211         ((u8 *)fw_msb)[1] = mac[0];
5212         ((u8 *)fw_mid)[0] = mac[3];
5213         ((u8 *)fw_mid)[1] = mac[2];
5214         ((u8 *)fw_lsb)[0] = mac[5];
5215         ((u8 *)fw_lsb)[1] = mac[4];
5216 }