drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dev_api.h"
  32 #include "ecore_dcbx.h"
  33
  34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  35  * registers involved are not split and thus configuration is a race where
  36  * some of the PFs configuration might be lost.
  37  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  38  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  39  * there's more than a single compiled ecore component in system].
  40  */
  41 static osal_spinlock_t qm_lock;
  42 static bool qm_lock_init;
  43
  44 /* Configurable */
  45 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
  46                                          * load the driver. The number was
  47                                          * arbitrarily set.
  48                                          */
  49
  50 /* Derived */
  51 #define ECORE_MIN_PWM_REGION    ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
  52
  53 enum BAR_ID {
  54         BAR_ID_0,               /* used for GRC */
  55         BAR_ID_1                /* Used for doorbells */
  56 };
  57
  58 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
  59 {
  60         u32 bar_reg = (bar_id == BAR_ID_0 ?
  61                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  62         u32 val;
  63
  64         if (IS_VF(p_hwfn->p_dev)) {
  65                 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
  66                  * read from actual register, but we're currently not using
  67                  * it for actual doorbelling.
  68                  */
  69                 return 1 << 17;
  70         }
  71
  72         val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
  73         if (val)
  74                 return 1 << (val + 15);
  75
  76         /* The above registers were updated in the past only in CMT mode. Since
  77          * they were found to be useful MFW started updating them from 8.7.7.0.
  78          * In older MFW versions they are set to 0 which means disabled.
  79          */
  80         if (p_hwfn->p_dev->num_hwfns > 1) {
  81                 DP_NOTICE(p_hwfn, false,
  82                           "BAR size not configured. Assuming BAR size of 256kB"
  83                           " for GRC and 512kB for DB\n");
  84                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  85         } else {
  86                 DP_NOTICE(p_hwfn, false,
  87                           "BAR size not configured. Assuming BAR size of 512kB"
  88                           " for GRC and 512kB for DB\n");
  89                 val = 512 * 1024;
  90         }
  91
  92         return val;
  93 }
  94
  95 void ecore_init_dp(struct ecore_dev *p_dev,
  96                    u32 dp_module, u8 dp_level, void *dp_ctx)
  97 {
  98         u32 i;
  99
 100         p_dev->dp_level = dp_level;
 101         p_dev->dp_module = dp_module;
 102         p_dev->dp_ctx = dp_ctx;
 103         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 104                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 105
 106                 p_hwfn->dp_level = dp_level;
 107                 p_hwfn->dp_module = dp_module;
 108                 p_hwfn->dp_ctx = dp_ctx;
 109         }
 110 }
 111
 112 void ecore_init_struct(struct ecore_dev *p_dev)
 113 {
 114         u8 i;
 115
 116         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 117                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 118
 119                 p_hwfn->p_dev = p_dev;
 120                 p_hwfn->my_id = i;
 121                 p_hwfn->b_active = false;
 122
 123                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 124                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 125         }
 126
 127         /* hwfn 0 is always active */
 128         p_dev->hwfns[0].b_active = true;
 129
 130         /* set the default cache alignment to 128 (may be overridden later) */
 131         p_dev->cache_shift = 7;
 132 }
 133
 134 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 135 {
 136         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 137
 138         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 139         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 140         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 141         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 142 }
 143
 144 void ecore_resc_free(struct ecore_dev *p_dev)
 145 {
 146         int i;
 147
 148         if (IS_VF(p_dev))
 149                 return;
 150
 151         OSAL_FREE(p_dev, p_dev->fw_data);
 152
 153         OSAL_FREE(p_dev, p_dev->reset_stats);
 154
 155         for_each_hwfn(p_dev, i) {
 156                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 157
 158                 OSAL_FREE(p_dev, p_hwfn->p_tx_cids);
 159                 OSAL_FREE(p_dev, p_hwfn->p_rx_cids);
 160         }
 161
 162         for_each_hwfn(p_dev, i) {
 163                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 164
 165                 ecore_cxt_mngr_free(p_hwfn);
 166                 ecore_qm_info_free(p_hwfn);
 167                 ecore_spq_free(p_hwfn);
 168                 ecore_eq_free(p_hwfn, p_hwfn->p_eq);
 169                 ecore_consq_free(p_hwfn, p_hwfn->p_consq);
 170                 ecore_int_free(p_hwfn);
 171 #ifdef CONFIG_ECORE_LL2
 172                 ecore_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
 173 #endif
 174                 ecore_iov_free(p_hwfn);
 175                 ecore_dmae_info_free(p_hwfn);
 176                 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 177                 /* @@@TBD Flush work-queue ? */
 178         }
 179 }
 180
 181 static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn,
 182                                                bool b_sleepable)
 183 {
 184         u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue;
 185         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 186         struct init_qm_port_params *p_qm_port;
 187         bool init_rdma_offload_pq = false;
 188         bool init_pure_ack_pq = false;
 189         bool init_ooo_pq = false;
 190         u16 num_pqs, protocol_pqs;
 191         u16 num_pf_rls = 0;
 192         u16 num_vfs = 0;
 193         u32 pf_rl;
 194         u8 pf_wfq;
 195
 196         /* @TMP - saving the existing min/max bw config before resetting the
 197          * qm_info to restore them.
 198          */
 199         pf_rl = qm_info->pf_rl;
 200         pf_wfq = qm_info->pf_wfq;
 201
 202 #ifdef CONFIG_ECORE_SRIOV
 203         if (p_hwfn->p_dev->p_iov_info)
 204                 num_vfs = p_hwfn->p_dev->p_iov_info->total_vfs;
 205 #endif
 206         OSAL_MEM_ZERO(qm_info, sizeof(*qm_info));
 207
 208 #ifndef ASIC_ONLY
 209         /* @TMP - Don't allocate QM queues for VFs on emulation */
 210         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 211                 DP_NOTICE(p_hwfn, false,
 212                           "Emulation - skip configuring QM queues for VFs\n");
 213                 num_vfs = 0;
 214         }
 215 #endif
 216
 217         /* ethernet PFs require a pq per tc. Even if only a subset of the TCs
 218          * active, we want physical queues allocated for all of them, since we
 219          * don't have a good recycle flow. Non ethernet PFs require only a
 220          * single physical queue.
 221          */
 222         if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE ||
 223             p_hwfn->hw_info.personality == ECORE_PCI_IWARP ||
 224             p_hwfn->hw_info.personality == ECORE_PCI_ETH)
 225                 protocol_pqs = p_hwfn->hw_info.num_hw_tc;
 226         else
 227                 protocol_pqs = 1;
 228
 229         num_pqs = protocol_pqs + num_vfs + 1;   /* The '1' is for pure-LB */
 230         num_vports = (u8)RESC_NUM(p_hwfn, ECORE_VPORT);
 231
 232         if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
 233                 num_pqs++;      /* for RoCE queue */
 234                 init_rdma_offload_pq = true;
 235                 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn) {
 236                         /* Due to FW assumption that rl==vport, we limit the
 237                          * number of rate limiters by the minimum between its
 238                          * allocated number and the allocated number of vports.
 239                          * Another limitation is the number of supported qps
 240                          * with rate limiters in FW.
 241                          */
 242                         num_pf_rls =
 243                             (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 244                                              RESC_NUM(p_hwfn, ECORE_VPORT));
 245
 246                         /* we subtract num_vfs because each one requires a rate
 247                          * limiter, and one default rate limiter.
 248                          */
 249                         if (num_pf_rls < num_vfs + 1) {
 250                                 DP_ERR(p_hwfn, "No RL for DCQCN");
 251                                 DP_ERR(p_hwfn, "[num_pf_rls %d num_vfs %d]\n",
 252                                        num_pf_rls, num_vfs);
 253                                 return ECORE_INVAL;
 254                         }
 255                         num_pf_rls -= num_vfs + 1;
 256                 }
 257
 258                 num_pqs += num_pf_rls;
 259                 qm_info->num_pf_rls = (u8)num_pf_rls;
 260         }
 261
 262         if (p_hwfn->hw_info.personality == ECORE_PCI_IWARP) {
 263                 num_pqs += 3;   /* for iwarp queue / pure-ack / ooo */
 264                 init_rdma_offload_pq = true;
 265                 init_pure_ack_pq = true;
 266                 init_ooo_pq = true;
 267         }
 268
 269         if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 270                 num_pqs += 2;   /* for iSCSI pure-ACK / OOO queue */
 271                 init_pure_ack_pq = true;
 272                 init_ooo_pq = true;
 273         }
 274
 275         /* Sanity checking that setup requires legal number of resources */
 276         if (num_pqs > RESC_NUM(p_hwfn, ECORE_PQ)) {
 277                 DP_ERR(p_hwfn,
 278                        "Need too many Physical queues - 0x%04x avail %04x",
 279                        num_pqs, RESC_NUM(p_hwfn, ECORE_PQ));
 280                 return ECORE_INVAL;
 281         }
 282
 283         /* PQs will be arranged as follows: First per-TC PQ, then pure-LB queue,
 284          * then special queues (iSCSI pure-ACK / RoCE), then per-VF PQ.
 285          */
 286         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev,
 287                                             b_sleepable ? GFP_KERNEL :
 288                                             GFP_ATOMIC,
 289                                             sizeof(struct init_qm_pq_params) *
 290                                             num_pqs);
 291         if (!qm_info->qm_pq_params)
 292                 goto alloc_err;
 293
 294         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev,
 295                                                b_sleepable ? GFP_KERNEL :
 296                                                GFP_ATOMIC,
 297                                                sizeof(struct
 298                                                       init_qm_vport_params) *
 299                                                num_vports);
 300         if (!qm_info->qm_vport_params)
 301                 goto alloc_err;
 302
 303         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev,
 304                                               b_sleepable ? GFP_KERNEL :
 305                                               GFP_ATOMIC,
 306                                               sizeof(struct init_qm_port_params)
 307                                               * MAX_NUM_PORTS);
 308         if (!qm_info->qm_port_params)
 309                 goto alloc_err;
 310
 311         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev,
 312                                         b_sleepable ? GFP_KERNEL :
 313                                         GFP_ATOMIC,
 314                                         sizeof(struct ecore_wfq_data) *
 315                                         num_vports);
 316
 317         if (!qm_info->wfq_data)
 318                 goto alloc_err;
 319
 320         vport_id = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 321
 322         /* First init rate limited queues ( Due to RoCE assumption of
 323          * qpid=rlid )
 324          */
 325         for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
 326                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
 327                 qm_info->qm_pq_params[curr_queue].tc_id =
 328                     p_hwfn->hw_info.offload_tc;
 329                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 330                 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
 331         };
 332
 333         /* Protocol PQs */
 334         for (i = 0; i < protocol_pqs; i++) {
 335                 struct init_qm_pq_params *params =
 336                     &qm_info->qm_pq_params[curr_queue++];
 337
 338                 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE ||
 339                     p_hwfn->hw_info.personality == ECORE_PCI_IWARP ||
 340                     p_hwfn->hw_info.personality == ECORE_PCI_ETH) {
 341                         params->vport_id = vport_id;
 342                         params->tc_id = i;
 343                         /* Note: this assumes that if we had a configuration
 344                          * with N tcs and subsequently another configuration
 345                          * With Fewer TCs, the in flight traffic (in QM queues,
 346                          * in FW, from driver to FW) will still trickle out and
 347                          * not get "stuck" in the QM. This is determined by the
 348                          * NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ. Unused TCs are
 349                          * supposed to be cleared in this map, allowing traffic
 350                          * to flush out. If this is not the case, we would need
 351                          * to set the TC of unused queues to 0, and reconfigure
 352                          * QM every time num of TCs changes. Unused queues in
 353                          * this context would mean those intended for TCs where
 354                          * tc_id > hw_info.num_active_tcs.
 355                          */
 356                         params->wrr_group = 1;  /* @@@TBD ECORE_WRR_MEDIUM */
 357                 } else {
 358                         params->vport_id = vport_id;
 359                         params->tc_id = p_hwfn->hw_info.offload_tc;
 360                         params->wrr_group = 1;  /* @@@TBD ECORE_WRR_MEDIUM */
 361                 }
 362         }
 363
 364         /* Then init pure-LB PQ */
 365         qm_info->pure_lb_pq = curr_queue;
 366         qm_info->qm_pq_params[curr_queue].vport_id =
 367             (u8)RESC_START(p_hwfn, ECORE_VPORT);
 368         qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
 369         qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 370         curr_queue++;
 371
 372         qm_info->offload_pq = 0;        /* Already initialized for iSCSI/FCoE */
 373         if (init_rdma_offload_pq) {
 374                 qm_info->offload_pq = curr_queue;
 375                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 376                 qm_info->qm_pq_params[curr_queue].tc_id =
 377                     p_hwfn->hw_info.offload_tc;
 378                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 379                 curr_queue++;
 380         }
 381
 382         if (init_pure_ack_pq) {
 383                 qm_info->pure_ack_pq = curr_queue;
 384                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 385                 qm_info->qm_pq_params[curr_queue].tc_id =
 386                     p_hwfn->hw_info.offload_tc;
 387                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 388                 curr_queue++;
 389         }
 390
 391         if (init_ooo_pq) {
 392                 qm_info->ooo_pq = curr_queue;
 393                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 394                 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
 395                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 396                 curr_queue++;
 397         }
 398
 399         /* Then init per-VF PQs */
 400         vf_offset = curr_queue;
 401         for (i = 0; i < num_vfs; i++) {
 402                 /* First vport is used by the PF */
 403                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
 404                 /* @@@TBD VF Multi-cos */
 405                 qm_info->qm_pq_params[curr_queue].tc_id = 0;
 406                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 407                 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
 408                 curr_queue++;
 409         };
 410
 411         qm_info->vf_queues_offset = vf_offset;
 412         qm_info->num_pqs = num_pqs;
 413         qm_info->num_vports = num_vports;
 414
 415         /* Initialize qm port parameters */
 416         num_ports = p_hwfn->p_dev->num_ports_in_engines;
 417         for (i = 0; i < num_ports; i++) {
 418                 p_qm_port = &qm_info->qm_port_params[i];
 419                 p_qm_port->active = 1;
 420                 /* @@@TMP - was NUM_OF_PHYS_TCS; Changed until dcbx will
 421                  * be in place
 422                  */
 423                 if (num_ports == 4)
 424                         p_qm_port->active_phys_tcs = 0xf;
 425                 else
 426                         p_qm_port->active_phys_tcs = 0x9f;
 427                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 428                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 429         }
 430
 431         if (ECORE_IS_AH(p_hwfn->p_dev) && (num_ports == 4))
 432                 qm_info->max_phys_tcs_per_port = NUM_PHYS_TCS_4PORT_K2;
 433         else
 434                 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
 435
 436         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 437
 438         qm_info->num_vf_pqs = num_vfs;
 439         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 440
 441         for (i = 0; i < qm_info->num_vports; i++)
 442                 qm_info->qm_vport_params[i].vport_wfq = 1;
 443
 444         qm_info->vport_rl_en = 1;
 445         qm_info->vport_wfq_en = 1;
 446         qm_info->pf_rl = pf_rl;
 447         qm_info->pf_wfq = pf_wfq;
 448
 449         return ECORE_SUCCESS;
 450
 451  alloc_err:
 452         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
 453         ecore_qm_info_free(p_hwfn);
 454         return ECORE_NOMEM;
 455 }
 456
 457 /* This function reconfigures the QM pf on the fly.
 458  * For this purpose we:
 459  * 1. reconfigure the QM database
 460  * 2. set new values to runtime arrat
 461  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 462  * 4. activate init tool in QM_PF stage
 463  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 464  */
 465 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
 466                                      struct ecore_ptt *p_ptt)
 467 {
 468         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 469         bool b_rc;
 470         enum _ecore_status_t rc;
 471
 472         /* qm_info is allocated in ecore_init_qm_info() which is already called
 473          * from ecore_resc_alloc() or previous call of ecore_qm_reconf().
 474          * The allocated size may change each init, so we free it before next
 475          * allocation.
 476          */
 477         ecore_qm_info_free(p_hwfn);
 478
 479         /* initialize ecore's qm data structure */
 480         rc = ecore_init_qm_info(p_hwfn, false);
 481         if (rc != ECORE_SUCCESS)
 482                 return rc;
 483
 484         /* stop PF's qm queues */
 485         OSAL_SPIN_LOCK(&qm_lock);
 486         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 487                                       qm_info->start_pq, qm_info->num_pqs);
 488         OSAL_SPIN_UNLOCK(&qm_lock);
 489         if (!b_rc)
 490                 return ECORE_INVAL;
 491
 492         /* clear the QM_PF runtime phase leftovers from previous init */
 493         ecore_init_clear_rt_data(p_hwfn);
 494
 495         /* prepare QM portion of runtime array */
 496         ecore_qm_init_pf(p_hwfn);
 497
 498         /* activate init tool on runtime array */
 499         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 500                             p_hwfn->hw_info.hw_mode);
 501         if (rc != ECORE_SUCCESS)
 502                 return rc;
 503
 504         /* start PF's qm queues */
 505         OSAL_SPIN_LOCK(&qm_lock);
 506         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 507                                       qm_info->start_pq, qm_info->num_pqs);
 508         OSAL_SPIN_UNLOCK(&qm_lock);
 509         if (!b_rc)
 510                 return ECORE_INVAL;
 511
 512         return ECORE_SUCCESS;
 513 }
 514
 515 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
 516 {
 517         struct ecore_consq *p_consq;
 518         struct ecore_eq *p_eq;
 519 #ifdef  CONFIG_ECORE_LL2
 520         struct ecore_ll2_info *p_ll2_info;
 521 #endif
 522         enum _ecore_status_t rc = ECORE_SUCCESS;
 523         int i;
 524
 525         if (IS_VF(p_dev))
 526                 return rc;
 527
 528         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 529                                      sizeof(*p_dev->fw_data));
 530         if (!p_dev->fw_data)
 531                 return ECORE_NOMEM;
 532
 533         /* Allocate Memory for the Queue->CID mapping */
 534         for_each_hwfn(p_dev, i) {
 535                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 536                 u32 num_tx_conns = RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 537                 int tx_size, rx_size;
 538
 539                 /* @@@TMP - resc management, change to actual required size */
 540                 if (p_hwfn->pf_params.eth_pf_params.num_cons > num_tx_conns)
 541                         num_tx_conns = p_hwfn->pf_params.eth_pf_params.num_cons;
 542                 tx_size = sizeof(struct ecore_hw_cid_data) * num_tx_conns;
 543                 rx_size = sizeof(struct ecore_hw_cid_data) *
 544                     RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 545
 546                 p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 547                                                 tx_size);
 548                 if (!p_hwfn->p_tx_cids) {
 549                         DP_NOTICE(p_hwfn, true,
 550                                   "Failed to allocate memory for Tx Cids\n");
 551                         goto alloc_no_mem;
 552                 }
 553
 554                 p_hwfn->p_rx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 555                                                 rx_size);
 556                 if (!p_hwfn->p_rx_cids) {
 557                         DP_NOTICE(p_hwfn, true,
 558                                   "Failed to allocate memory for Rx Cids\n");
 559                         goto alloc_no_mem;
 560                 }
 561         }
 562
 563         for_each_hwfn(p_dev, i) {
 564                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 565                 u32 n_eqes, num_cons;
 566
 567                 /* First allocate the context manager structure */
 568                 rc = ecore_cxt_mngr_alloc(p_hwfn);
 569                 if (rc)
 570                         goto alloc_err;
 571
 572                 /* Set the HW cid/tid numbers (in the contest manager)
 573                  * Must be done prior to any further computations.
 574                  */
 575                 rc = ecore_cxt_set_pf_params(p_hwfn);
 576                 if (rc)
 577                         goto alloc_err;
 578
 579                 /* Prepare and process QM requirements */
 580                 rc = ecore_init_qm_info(p_hwfn, true);
 581                 if (rc)
 582                         goto alloc_err;
 583
 584                 /* Compute the ILT client partition */
 585                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
 586                 if (rc)
 587                         goto alloc_err;
 588
 589                 /* CID map / ILT shadow table / T2
 590                  * The talbes sizes are determined by the computations above
 591                  */
 592                 rc = ecore_cxt_tables_alloc(p_hwfn);
 593                 if (rc)
 594                         goto alloc_err;
 595
 596                 /* SPQ, must follow ILT because initializes SPQ context */
 597                 rc = ecore_spq_alloc(p_hwfn);
 598                 if (rc)
 599                         goto alloc_err;
 600
 601                 /* SP status block allocation */
 602                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
 603                                                            RESERVED_PTT_DPC);
 604
 605                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 606                 if (rc)
 607                         goto alloc_err;
 608
 609                 rc = ecore_iov_alloc(p_hwfn);
 610                 if (rc)
 611                         goto alloc_err;
 612
 613                 /* EQ */
 614                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
 615                 if ((p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) ||
 616                     (p_hwfn->hw_info.personality == ECORE_PCI_IWARP)) {
 617                         /* Calculate the EQ size
 618                          * ---------------------
 619                          * Each ICID may generate up to one event at a time i.e.
 620                          * the event must be handled/cleared before a new one
 621                          * can be generated. We calculate the sum of events per
 622                          * protocol and create an EQ deep enough to handle the
 623                          * worst case:
 624                          * - Core - according to SPQ.
 625                          * - RoCE - per QP there are a couple of ICIDs, one
 626                          *          responder and one requester, each can
 627                          *          generate an EQE => n_eqes_qp = 2 * n_qp.
 628                          *          Each CQ can generate an EQE. There are 2 CQs
 629                          *          per QP => n_eqes_cq = 2 * n_qp.
 630                          *          Hence the RoCE total is 4 * n_qp or
 631                          *          2 * num_cons.
 632                          * - ENet - There can be up to two events per VF. One
 633                          *          for VF-PF channel and another for VF FLR
 634                          *          initial cleanup. The number of VFs is
 635                          *          bounded by MAX_NUM_VFS_BB, and is much
 636                          *          smaller than RoCE's so we avoid exact
 637                          *          calculation.
 638                          */
 639                         if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
 640                                 num_cons =
 641                                     ecore_cxt_get_proto_cid_count(
 642                                                 p_hwfn,
 643                                                 PROTOCOLID_ROCE,
 644                                                 0);
 645                                 num_cons *= 2;
 646                         } else {
 647                                 num_cons = ecore_cxt_get_proto_cid_count(
 648                                                 p_hwfn,
 649                                                 PROTOCOLID_IWARP,
 650                                                 0);
 651                         }
 652                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 653                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 654                         num_cons =
 655                             ecore_cxt_get_proto_cid_count(p_hwfn,
 656                                                           PROTOCOLID_ISCSI, 0);
 657                         n_eqes += 2 * num_cons;
 658                 }
 659
 660                 if (n_eqes > 0xFFFF) {
 661                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
 662                                        "The maximum of a u16 chain is 0x%x\n",
 663                                n_eqes, 0xFFFF);
 664                         goto alloc_no_mem;
 665                 }
 666
 667                 p_eq = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
 668                 if (!p_eq)
 669                         goto alloc_no_mem;
 670                 p_hwfn->p_eq = p_eq;
 671
 672                 p_consq = ecore_consq_alloc(p_hwfn);
 673                 if (!p_consq)
 674                         goto alloc_no_mem;
 675                 p_hwfn->p_consq = p_consq;
 676
 677 #ifdef CONFIG_ECORE_LL2
 678                 if (p_hwfn->using_ll2) {
 679                         p_ll2_info = ecore_ll2_alloc(p_hwfn);
 680                         if (!p_ll2_info)
 681                                 goto alloc_no_mem;
 682                         p_hwfn->p_ll2_info = p_ll2_info;
 683                 }
 684 #endif
 685
 686                 /* DMA info initialization */
 687                 rc = ecore_dmae_info_alloc(p_hwfn);
 688                 if (rc) {
 689                         DP_NOTICE(p_hwfn, true,
 690                                   "Failed to allocate memory for dmae_info structure\n");
 691                         goto alloc_err;
 692                 }
 693
 694                 /* DCBX initialization */
 695                 rc = ecore_dcbx_info_alloc(p_hwfn);
 696                 if (rc) {
 697                         DP_NOTICE(p_hwfn, true,
 698                                   "Failed to allocate memory for dcbx structure\n");
 699                         goto alloc_err;
 700                 }
 701         }
 702
 703         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 704                                          sizeof(*p_dev->reset_stats));
 705         if (!p_dev->reset_stats) {
 706                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
 707                 goto alloc_no_mem;
 708         }
 709
 710         return ECORE_SUCCESS;
 711
 712  alloc_no_mem:
 713         rc = ECORE_NOMEM;
 714  alloc_err:
 715         ecore_resc_free(p_dev);
 716         return rc;
 717 }
 718
 719 void ecore_resc_setup(struct ecore_dev *p_dev)
 720 {
 721         int i;
 722
 723         if (IS_VF(p_dev))
 724                 return;
 725
 726         for_each_hwfn(p_dev, i) {
 727                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 728
 729                 ecore_cxt_mngr_setup(p_hwfn);
 730                 ecore_spq_setup(p_hwfn);
 731                 ecore_eq_setup(p_hwfn, p_hwfn->p_eq);
 732                 ecore_consq_setup(p_hwfn, p_hwfn->p_consq);
 733
 734                 /* Read shadow of current MFW mailbox */
 735                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
 736                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
 737                             p_hwfn->mcp_info->mfw_mb_cur,
 738                             p_hwfn->mcp_info->mfw_mb_length);
 739
 740                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
 741
 742                 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
 743 #ifdef CONFIG_ECORE_LL2
 744                 if (p_hwfn->using_ll2)
 745                         ecore_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
 746 #endif
 747         }
 748 }
 749
 750 #define FINAL_CLEANUP_POLL_CNT  (100)
 751 #define FINAL_CLEANUP_POLL_TIME (10)
 752 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
 753                                          struct ecore_ptt *p_ptt,
 754                                          u16 id, bool is_vf)
 755 {
 756         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
 757         enum _ecore_status_t rc = ECORE_TIMEOUT;
 758
 759 #ifndef ASIC_ONLY
 760         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
 761             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 762                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
 763                 return ECORE_SUCCESS;
 764         }
 765 #endif
 766
 767         addr = GTT_BAR0_MAP_REG_USDM_RAM +
 768             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
 769
 770         if (is_vf)
 771                 id += 0x10;
 772
 773         command |= X_FINAL_CLEANUP_AGG_INT <<
 774             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
 775         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
 776         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
 777         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
 778
 779 /* Make sure notification is not set before initiating final cleanup */
 780
 781         if (REG_RD(p_hwfn, addr)) {
 782                 DP_NOTICE(p_hwfn, false,
 783                           "Unexpected; Found final cleanup notification");
 784                 DP_NOTICE(p_hwfn, false,
 785                           " before initiating final cleanup\n");
 786                 REG_WR(p_hwfn, addr, 0);
 787         }
 788
 789         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
 790                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
 791                    id, command);
 792
 793         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
 794
 795         /* Poll until completion */
 796         while (!REG_RD(p_hwfn, addr) && count--)
 797                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
 798
 799         if (REG_RD(p_hwfn, addr))
 800                 rc = ECORE_SUCCESS;
 801         else
 802                 DP_NOTICE(p_hwfn, true,
 803                           "Failed to receive FW final cleanup notification\n");
 804
 805         /* Cleanup afterwards */
 806         REG_WR(p_hwfn, addr, 0);
 807
 808         return rc;
 809 }
 810
 811 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
 812 {
 813         int hw_mode = 0;
 814
 815         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
 816                 hw_mode |= 1 << MODE_BB_B0;
 817         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
 818                 hw_mode |= 1 << MODE_K2;
 819         } else {
 820                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
 821                           p_hwfn->p_dev->type);
 822                 return ECORE_INVAL;
 823         }
 824
 825         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
 826         switch (p_hwfn->p_dev->num_ports_in_engines) {
 827         case 1:
 828                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
 829                 break;
 830         case 2:
 831                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
 832                 break;
 833         case 4:
 834                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
 835                 break;
 836         default:
 837                 DP_NOTICE(p_hwfn, true,
 838                           "num_ports_in_engine = %d not supported\n",
 839                           p_hwfn->p_dev->num_ports_in_engines);
 840                 return ECORE_INVAL;
 841         }
 842
 843         switch (p_hwfn->p_dev->mf_mode) {
 844         case ECORE_MF_DEFAULT:
 845         case ECORE_MF_NPAR:
 846                 hw_mode |= 1 << MODE_MF_SI;
 847                 break;
 848         case ECORE_MF_OVLAN:
 849                 hw_mode |= 1 << MODE_MF_SD;
 850                 break;
 851         default:
 852                 DP_NOTICE(p_hwfn, true,
 853                           "Unsupported MF mode, init as DEFAULT\n");
 854                 hw_mode |= 1 << MODE_MF_SI;
 855         }
 856
 857 #ifndef ASIC_ONLY
 858         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 859                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
 860                         hw_mode |= 1 << MODE_FPGA;
 861                 } else {
 862                         if (p_hwfn->p_dev->b_is_emul_full)
 863                                 hw_mode |= 1 << MODE_EMUL_FULL;
 864                         else
 865                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
 866                 }
 867         } else
 868 #endif
 869                 hw_mode |= 1 << MODE_ASIC;
 870
 871         if (p_hwfn->p_dev->num_hwfns > 1)
 872                 hw_mode |= 1 << MODE_100G;
 873
 874         p_hwfn->hw_info.hw_mode = hw_mode;
 875
 876         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
 877                    "Configuring function for hw_mode: 0x%08x\n",
 878                    p_hwfn->hw_info.hw_mode);
 879
 880         return ECORE_SUCCESS;
 881 }
 882
 883 #ifndef ASIC_ONLY
 884 /* MFW-replacement initializations for non-ASIC */
 885 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
 886                                                struct ecore_ptt *p_ptt)
 887 {
 888         u32 pl_hv = 1;
 889         int i;
 890
 891         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
 892                 pl_hv |= 0x600;
 893
 894         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
 895
 896         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
 897                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2, 0x3ffffff);
 898
 899         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
 900         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
 901         if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))
 902                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0, 4);
 903
 904         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
 905                 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
 906                 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
 907                          (p_hwfn->p_dev->num_ports_in_engines >> 1));
 908
 909                 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
 910                          p_hwfn->p_dev->num_ports_in_engines == 4 ? 0 : 3);
 911         }
 912
 913         /* Poll on RBC */
 914         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
 915         for (i = 0; i < 100; i++) {
 916                 OSAL_UDELAY(50);
 917                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
 918                         break;
 919         }
 920         if (i == 100)
 921                 DP_NOTICE(p_hwfn, true,
 922                           "RBC done failed to complete in PSWRQ2\n");
 923
 924         return ECORE_SUCCESS;
 925 }
 926 #endif
 927
 928 /* Init run time data for all PFs and their VFs on an engine.
 929  * TBD - for VFs - Once we have parent PF info for each VF in
 930  * shmem available as CAU requires knowledge of parent PF for each VF.
 931  */
 932 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
 933 {
 934         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
 935         int i, sb_id;
 936
 937         for_each_hwfn(p_dev, i) {
 938                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 939                 struct ecore_igu_info *p_igu_info;
 940                 struct ecore_igu_block *p_block;
 941                 struct cau_sb_entry sb_entry;
 942
 943                 p_igu_info = p_hwfn->hw_info.p_igu_info;
 944
 945                 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
 946                      sb_id++) {
 947                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
 948
 949                         if (!p_block->is_pf)
 950                                 continue;
 951
 952                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
 953                                                 p_block->function_id, 0, 0);
 954                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
 955                 }
 956         }
 957 }
 958
 959 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
 960                                                  struct ecore_ptt *p_ptt,
 961                                                  int hw_mode)
 962 {
 963         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 964         struct ecore_dev *p_dev = p_hwfn->p_dev;
 965         u8 vf_id, max_num_vfs;
 966         u16 num_pfs, pf_id;
 967         u32 concrete_fid;
 968         enum _ecore_status_t rc = ECORE_SUCCESS;
 969
 970         ecore_init_cau_rt_data(p_dev);
 971
 972         /* Program GTT windows */
 973         ecore_gtt_init(p_hwfn);
 974
 975 #ifndef ASIC_ONLY
 976         if (CHIP_REV_IS_EMUL(p_dev)) {
 977                 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
 978                 if (rc != ECORE_SUCCESS)
 979                         return rc;
 980         }
 981 #endif
 982
 983         if (p_hwfn->mcp_info) {
 984                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
 985                         qm_info->pf_rl_en = 1;
 986                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
 987                         qm_info->pf_wfq_en = 1;
 988         }
 989
 990         ecore_qm_common_rt_init(p_hwfn,
 991                                 p_dev->num_ports_in_engines,
 992                                 qm_info->max_phys_tcs_per_port,
 993                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
 994                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
 995                                 qm_info->qm_port_params);
 996
 997         ecore_cxt_hw_init_common(p_hwfn);
 998
 999         /* Close gate from NIG to BRB/Storm; By default they are open, but
1000          * we close them to prevent NIG from passing data to reset blocks.
1001          * Should have been done in the ENGINE phase, but init-tool lacks
1002          * proper port-pretend capabilities.
1003          */
1004         ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1005         ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1006         ecore_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
1007         ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1008         ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1009         ecore_port_unpretend(p_hwfn, p_ptt);
1010
1011         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1012         if (rc != ECORE_SUCCESS)
1013                 return rc;
1014
1015         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1016          * need to decide with which value, maybe runtime
1017          */
1018         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1019         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1020
1021         if (ECORE_IS_BB(p_dev)) {
1022                 /* Workaround clears ROCE search for all functions to prevent
1023                  * involving non initialized function in processing ROCE packet.
1024                  */
1025                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1026                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1027                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1028                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1029                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1030                 }
1031                 /* pretend to original PF */
1032                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1033         }
1034
1035         /* Workaround for avoiding CCFC execution error when getting packets
1036          * with CRC errors, and allowing instead the invoking of the FW error
1037          * handler.
1038          * This is not done inside the init tool since it currently can't
1039          * perform a pretending to VFs.
1040          */
1041         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1042         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1043                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1044                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1045                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1046                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1047                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1048                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1049         }
1050         /* pretend to original PF */
1051         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1052
1053         return rc;
1054 }
1055
1056 #ifndef ASIC_ONLY
1057 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1058 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1059
1060 #define PMEG_IF_BYTE_COUNT      8
1061
1062 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1063                              struct ecore_ptt *p_ptt,
1064                              u32 addr, u64 data, u8 reg_type, u8 port)
1065 {
1066         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1067                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1068                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) |
1069                    (8 << PMEG_IF_BYTE_COUNT),
1070                    (reg_type << 25) | (addr << 8) | port,
1071                    (u32)((data >> 32) & 0xffffffff),
1072                    (u32)(data & 0xffffffff));
1073
1074         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0,
1075                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) &
1076                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1077         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB_B0,
1078                  (reg_type << 25) | (addr << 8) | port);
1079         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
1080                  data & 0xffffffff);
1081         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
1082                  (data >> 32) & 0xffffffff);
1083 }
1084
1085 #define XLPORT_MODE_REG (0x20a)
1086 #define XLPORT_MAC_CONTROL (0x210)
1087 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1088 #define XLPORT_ENABLE_REG (0x20b)
1089
1090 #define XLMAC_CTRL (0x600)
1091 #define XLMAC_MODE (0x601)
1092 #define XLMAC_RX_MAX_SIZE (0x608)
1093 #define XLMAC_TX_CTRL (0x604)
1094 #define XLMAC_PAUSE_CTRL (0x60d)
1095 #define XLMAC_PFC_CTRL (0x60e)
1096
1097 static void ecore_emul_link_init_ah(struct ecore_hwfn *p_hwfn,
1098                                     struct ecore_ptt *p_ptt)
1099 {
1100         u8 port = p_hwfn->port_id;
1101         u32 mac_base = NWM_REG_MAC0 + (port << 2) * NWM_REG_MAC0_SIZE;
1102
1103         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2 + (port << 2),
1104                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_SHIFT) |
1105                  (port << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_SHIFT)
1106                  | (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_SHIFT));
1107
1108         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE,
1109                  1 << ETH_MAC_REG_XIF_MODE_XGMII_SHIFT);
1110
1111         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH,
1112                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_SHIFT);
1113
1114         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH,
1115                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_SHIFT);
1116
1117         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS,
1118                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_SHIFT);
1119
1120         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS,
1121                  (0xA << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_SHIFT) |
1122                  (8 << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_SHIFT));
1123
1124         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG, 0xa853);
1125 }
1126
1127 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1128                                  struct ecore_ptt *p_ptt)
1129 {
1130         u8 loopback = 0, port = p_hwfn->port_id * 2;
1131
1132         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1133
1134         if (ECORE_IS_AH(p_hwfn->p_dev)) {
1135                 ecore_emul_link_init_ah(p_hwfn, p_ptt);
1136                 return;
1137         }
1138
1139         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1140         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1141                          port);
1142         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1143         /* XLMAC: SOFT RESET */
1144         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1145         /* XLMAC: Port Speed >= 10Gbps */
1146         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1147         /* XLMAC: Max Size */
1148         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1149         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1150                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1151                          0, port);
1152         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1153         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1154                          0x30ffffc000ULL, 0, port);
1155         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1156                          port); /* XLMAC: TX_EN, RX_EN */
1157         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1158         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1159                          0x1003 | (loopback << 2), 0, port);
1160         /* Enabled Parallel PFC interface */
1161         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1162
1163         /* XLPORT port enable */
1164         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1165 }
1166
1167 static void ecore_link_init(struct ecore_hwfn *p_hwfn,
1168                             struct ecore_ptt *p_ptt, u8 port)
1169 {
1170         int port_offset = port ? 0x800 : 0;
1171         u32 xmac_rxctrl = 0;
1172
1173         /* Reset of XMAC */
1174         /* FIXME: move to common start */
1175         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1176                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1177         OSAL_MSLEEP(1);
1178         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1179                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1180
1181         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1182
1183         /* Set the number of ports on the Warp Core to 10G */
1184         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1185
1186         /* Soft reset of XMAC */
1187         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1188                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1189         OSAL_MSLEEP(1);
1190         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1191                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1192
1193         /* FIXME: move to common end */
1194         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1195                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE + port_offset, 0x20);
1196
1197         /* Set Max packet size: initialize XMAC block register for port 0 */
1198         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE + port_offset, 0x2710);
1199
1200         /* CRC append for Tx packets: init XMAC block register for port 1 */
1201         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO + port_offset, 0xC800);
1202
1203         /* Enable TX and RX: initialize XMAC block register for port 1 */
1204         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL + port_offset,
1205                  XMAC_REG_CTRL_TX_EN | XMAC_REG_CTRL_RX_EN);
1206         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset);
1207         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE;
1208         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset, xmac_rxctrl);
1209 }
1210 #endif
1211
1212 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1213                                                struct ecore_ptt *p_ptt,
1214                                                int hw_mode)
1215 {
1216         enum _ecore_status_t rc = ECORE_SUCCESS;
1217
1218         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1219                             hw_mode);
1220         if (rc != ECORE_SUCCESS)
1221                 return rc;
1222 #ifndef ASIC_ONLY
1223         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1224                 return ECORE_SUCCESS;
1225
1226         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1227                 if (ECORE_IS_AH(p_hwfn->p_dev))
1228                         return ECORE_SUCCESS;
1229                 ecore_link_init(p_hwfn, p_ptt, p_hwfn->port_id);
1230         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1231                 if (p_hwfn->p_dev->num_hwfns > 1) {
1232                         /* Activate OPTE in CMT */
1233                         u32 val;
1234
1235                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1236                         val |= 0x10;
1237                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1238                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1239                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1240                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1241                         ecore_wr(p_hwfn, p_ptt,
1242                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1243                         ecore_wr(p_hwfn, p_ptt,
1244                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1245                         ecore_wr(p_hwfn, p_ptt,
1246                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1247                                  0x55555555);
1248                 }
1249
1250                 ecore_emul_link_init(p_hwfn, p_ptt);
1251         } else {
1252                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1253         }
1254 #endif
1255
1256         return rc;
1257 }
1258
1259 static enum _ecore_status_t
1260 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1261                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1262 {
1263         u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1264         u32 dpi_bit_shift, dpi_count;
1265         u32 min_dpis;
1266
1267         /* Calculate DPI size
1268          * ------------------
1269          * The PWM region contains Doorbell Pages. The first is reserverd for
1270          * the kernel for, e.g, L2. The others are free to be used by non-
1271          * trusted applications, typically from user space. Each page, called a
1272          * doorbell page is sectioned into windows that allow doorbells to be
1273          * issued in parallel by the kernel/application. The size of such a
1274          * window (a.k.a. WID) is 1kB.
1275          * Summary:
1276          *    1kB WID x N WIDS = DPI page size
1277          *    DPI page size x N DPIs = PWM region size
1278          * Notes:
1279          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1280          * in order to ensure that two applications won't share the same page.
1281          * It also must contain at least one WID per CPU to allow parallelism.
1282          * It also must be a power of 2, since it is stored as a bit shift.
1283          *
1284          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1285          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1286          * containing 4 WIDs.
1287          */
1288         dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1289         dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1290         dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1291         dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1292         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1293
1294         dpi_count = pwm_region_size / dpi_page_size;
1295
1296         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1297         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1298
1299         /* Update hwfn */
1300         p_hwfn->dpi_size = dpi_page_size;
1301         p_hwfn->dpi_count = dpi_count;
1302
1303         /* Update registers */
1304         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1305
1306         if (dpi_count < min_dpis)
1307                 return ECORE_NORESOURCES;
1308
1309         return ECORE_SUCCESS;
1310 }
1311
1312 enum ECORE_ROCE_EDPM_MODE {
1313         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1314         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1315         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1316 };
1317
1318 static enum _ecore_status_t
1319 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1320                               struct ecore_ptt *p_ptt)
1321 {
1322         u32 pwm_regsize, norm_regsize;
1323         u32 non_pwm_conn, min_addr_reg1;
1324         u32 db_bar_size, n_cpus;
1325         u32 roce_edpm_mode;
1326         u32 pf_dems_shift;
1327         int rc = ECORE_SUCCESS;
1328         u8 cond;
1329
1330         db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1331         if (p_hwfn->p_dev->num_hwfns > 1)
1332                 db_bar_size /= 2;
1333
1334         /* Calculate doorbell regions
1335          * -----------------------------------
1336          * The doorbell BAR is made of two regions. The first is called normal
1337          * region and the second is called PWM region. In the normal region
1338          * each ICID has its own set of addresses so that writing to that
1339          * specific address identifies the ICID. In the Process Window Mode
1340          * region the ICID is given in the data written to the doorbell. The
1341          * above per PF register denotes the offset in the doorbell BAR in which
1342          * the PWM region begins.
1343          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1344          * non-PWM connection. The calculation below computes the total non-PWM
1345          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1346          * in units of 4,096 bytes.
1347          */
1348         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1349             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1350                                           OSAL_NULL) +
1351             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1352         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1353         min_addr_reg1 = norm_regsize / 4096;
1354         pwm_regsize = db_bar_size - norm_regsize;
1355
1356         /* Check that the normal and PWM sizes are valid */
1357         if (db_bar_size < norm_regsize) {
1358                 DP_ERR(p_hwfn->p_dev,
1359                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1360                        db_bar_size, norm_regsize);
1361                 return ECORE_NORESOURCES;
1362         }
1363         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1364                 DP_ERR(p_hwfn->p_dev,
1365                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1366                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1367                        norm_regsize);
1368                 return ECORE_NORESOURCES;
1369         }
1370
1371         /* Calculate number of DPIs */
1372         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1373         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1374             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1375                 /* Either EDPM is mandatory, or we are attempting to allocate a
1376                  * WID per CPU.
1377                  */
1378                 n_cpus = OSAL_NUM_ACTIVE_CPU();
1379                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1380         }
1381
1382         cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1383             (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1384         if (cond || p_hwfn->dcbx_no_edpm) {
1385                 /* Either EDPM is disabled from user configuration, or it is
1386                  * disabled via DCBx, or it is not mandatory and we failed to
1387                  * allocated a WID per CPU.
1388                  */
1389                 n_cpus = 1;
1390                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1391
1392                 /* If we entered this flow due to DCBX then the DPM register is
1393                  * already configured.
1394                  */
1395         }
1396
1397         DP_INFO(p_hwfn,
1398                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1399                 norm_regsize, pwm_regsize);
1400         DP_INFO(p_hwfn,
1401                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1402                 p_hwfn->dpi_size, p_hwfn->dpi_count,
1403                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1404                 "disabled" : "enabled");
1405
1406         /* Check return codes from above calls */
1407         if (rc) {
1408                 DP_ERR(p_hwfn,
1409                        "Failed to allocate enough DPIs\n");
1410                 return ECORE_NORESOURCES;
1411         }
1412
1413         /* Update hwfn */
1414         p_hwfn->dpi_start_offset = norm_regsize;
1415
1416         /* Update registers */
1417         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1418         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1419         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1420         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1421
1422         return ECORE_SUCCESS;
1423 }
1424
1425 static enum _ecore_status_t
1426 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1427                  struct ecore_ptt *p_ptt,
1428                  struct ecore_tunn_start_params *p_tunn,
1429                  int hw_mode,
1430                  bool b_hw_start,
1431                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1432 {
1433         u8 rel_pf_id = p_hwfn->rel_pf_id;
1434         u32 prs_reg;
1435         enum _ecore_status_t rc = ECORE_SUCCESS;
1436         u16 ctrl;
1437         int pos;
1438
1439         if (p_hwfn->mcp_info) {
1440                 struct ecore_mcp_function_info *p_info;
1441
1442                 p_info = &p_hwfn->mcp_info->func_info;
1443                 if (p_info->bandwidth_min)
1444                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1445
1446                 /* Update rate limit once we'll actually have a link */
1447                 p_hwfn->qm_info.pf_rl = 100000;
1448         }
1449         ecore_cxt_hw_init_pf(p_hwfn);
1450
1451         ecore_int_igu_init_rt(p_hwfn);
1452
1453         /* Set VLAN in NIG if needed */
1454         if (hw_mode & (1 << MODE_MF_SD)) {
1455                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1456                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1457                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1458                              p_hwfn->hw_info.ovlan);
1459         }
1460
1461         /* Enable classification by MAC if needed */
1462         if (hw_mode & (1 << MODE_MF_SI)) {
1463                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1464                            "Configuring TAGMAC_CLS_TYPE\n");
1465                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1466                              1);
1467         }
1468
1469         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
1470         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1471                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1472         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1473                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1474         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1475
1476         /* perform debug configuration when chip is out of reset */
1477         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1478
1479         /* Cleanup chip from previous driver if such remains exist */
1480         rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1481         if (rc != ECORE_SUCCESS) {
1482                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1483                 return rc;
1484         }
1485
1486         /* PF Init sequence */
1487         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1488         if (rc)
1489                 return rc;
1490
1491         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1492         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1493         if (rc)
1494                 return rc;
1495
1496         /* Pure runtime initializations - directly to the HW  */
1497         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1498
1499         /* PCI relaxed ordering causes a decrease in the performance on some
1500          * systems. Till a root cause is found, disable this attribute in the
1501          * PCI config space.
1502          */
1503         /* Not in use @DPDK
1504         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1505         * if (!pos) {
1506         *       DP_NOTICE(p_hwfn, true,
1507         *                 "Failed to find the PCIe Cap\n");
1508         *       return ECORE_IO;
1509         * }
1510         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1511         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1512         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1513         */
1514
1515         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1516         if (rc)
1517                 return rc;
1518         if (b_hw_start) {
1519                 /* enable interrupts */
1520                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1521                 if (rc != ECORE_SUCCESS)
1522                         return rc;
1523
1524                 /* send function start command */
1525                 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1526                                        allow_npar_tx_switch);
1527                 if (rc) {
1528                         DP_NOTICE(p_hwfn, true,
1529                                   "Function start ramrod failed\n");
1530                 } else {
1531                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1532                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1533                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1534
1535                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1536                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1537                                          (1 << 2));
1538                                 ecore_wr(p_hwfn, p_ptt,
1539                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1540                                     0x100);
1541                         }
1542                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1543                                    "PRS_REG_SEARCH registers after start PFn\n");
1544                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1545                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1546                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1547                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1548                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1549                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1550                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1551                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1552                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1553                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1554                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1555                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1556                         prs_reg = ecore_rd(p_hwfn, p_ptt,
1557                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
1558                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1559                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1560                                    prs_reg);
1561                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1562                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1563                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1564                 }
1565         }
1566         return rc;
1567 }
1568
1569 static enum _ecore_status_t
1570 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1571                       struct ecore_ptt *p_ptt, u8 enable)
1572 {
1573         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1574
1575         /* Change PF in PXP */
1576         ecore_wr(p_hwfn, p_ptt,
1577                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1578
1579         /* wait until value is set - try for 1 second every 50us */
1580         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1581                 val = ecore_rd(p_hwfn, p_ptt,
1582                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1583                 if (val == set_val)
1584                         break;
1585
1586                 OSAL_UDELAY(50);
1587         }
1588
1589         if (val != set_val) {
1590                 DP_NOTICE(p_hwfn, true,
1591                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1592                 return ECORE_UNKNOWN_ERROR;
1593         }
1594
1595         return ECORE_SUCCESS;
1596 }
1597
1598 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1599                                   struct ecore_ptt *p_main_ptt)
1600 {
1601         /* Read shadow of current MFW mailbox */
1602         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1603         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1604                     p_hwfn->mcp_info->mfw_mb_cur,
1605                     p_hwfn->mcp_info->mfw_mb_length);
1606 }
1607
1608 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1609                                    struct ecore_hw_init_params *p_params)
1610 {
1611         enum _ecore_status_t rc, mfw_rc;
1612         u32 load_code, param;
1613         int i;
1614
1615         if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
1616             (p_dev->num_hwfns > 1)) {
1617                 DP_NOTICE(p_dev, false,
1618                           "MSI mode is not supported for CMT devices\n");
1619                 return ECORE_INVAL;
1620         }
1621
1622         if (IS_PF(p_dev)) {
1623                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1624                 if (rc != ECORE_SUCCESS)
1625                         return rc;
1626         }
1627
1628         for_each_hwfn(p_dev, i) {
1629                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1630
1631                 if (IS_VF(p_dev)) {
1632                         p_hwfn->b_int_enabled = 1;
1633                         continue;
1634                 }
1635
1636                 /* Enable DMAE in PXP */
1637                 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1638                 if (rc != ECORE_SUCCESS)
1639                         return rc;
1640
1641                 rc = ecore_calc_hw_mode(p_hwfn);
1642                 if (rc != ECORE_SUCCESS)
1643                         return rc;
1644
1645                 /* @@@TBD need to add here:
1646                  * Check for fan failure
1647                  * Prev_unload
1648                  */
1649                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1650                 if (rc) {
1651                         DP_NOTICE(p_hwfn, true,
1652                                   "Failed sending LOAD_REQ command\n");
1653                         return rc;
1654                 }
1655
1656                 /* CQ75580:
1657                  * When coming back from hiberbate state, the registers from
1658                  * which shadow is read initially are not initialized. It turns
1659                  * out that these registers get initialized during the call to
1660                  * ecore_mcp_load_req request. So we need to reread them here
1661                  * to get the proper shadow register value.
1662                  * Note: This is a workaround for the missinginig MFW
1663                  * initialization. It may be removed once the implementation
1664                  * is done.
1665                  */
1666                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1667
1668                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1669                            "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1670                            rc, load_code);
1671
1672                 /* Only relevant for recovery:
1673                  * Clear the indication after the LOAD_REQ command is responded
1674                  * by the MFW.
1675                  */
1676                 p_dev->recov_in_prog = false;
1677
1678                 p_hwfn->first_on_engine = (load_code ==
1679                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1680
1681                 if (!qm_lock_init) {
1682                         OSAL_SPIN_LOCK_INIT(&qm_lock);
1683                         qm_lock_init = true;
1684                 }
1685
1686                 switch (load_code) {
1687                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1688                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1689                                                   p_hwfn->hw_info.hw_mode);
1690                         if (rc)
1691                                 break;
1692                         /* Fall into */
1693                 case FW_MSG_CODE_DRV_LOAD_PORT:
1694                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1695                                                 p_hwfn->hw_info.hw_mode);
1696                         if (rc)
1697                                 break;
1698                         /* Fall into */
1699                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1700                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1701                                               p_params->p_tunn,
1702                                               p_hwfn->hw_info.hw_mode,
1703                                               p_params->b_hw_start,
1704                                               p_params->int_mode,
1705                                               p_params->allow_npar_tx_switch);
1706                         break;
1707                 default:
1708                         rc = ECORE_NOTIMPL;
1709                         break;
1710                 }
1711
1712                 if (rc != ECORE_SUCCESS)
1713                         DP_NOTICE(p_hwfn, true,
1714                                   "init phase failed for loadcode 0x%x (rc %d)\n",
1715                                   load_code, rc);
1716
1717                 /* ACK mfw regardless of success or failure of initialization */
1718                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1719                                        DRV_MSG_CODE_LOAD_DONE,
1720                                        0, &load_code, &param);
1721                 if (rc != ECORE_SUCCESS)
1722                         return rc;
1723                 if (mfw_rc != ECORE_SUCCESS) {
1724                         DP_NOTICE(p_hwfn, true,
1725                                   "Failed sending LOAD_DONE command\n");
1726                         return mfw_rc;
1727                 }
1728
1729                 /* send DCBX attention request command */
1730                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1731                            "sending phony dcbx set command to trigger DCBx attention handling\n");
1732                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1733                                        DRV_MSG_CODE_SET_DCBX,
1734                                        1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1735                                        &load_code, &param);
1736                 if (mfw_rc != ECORE_SUCCESS) {
1737                         DP_NOTICE(p_hwfn, true,
1738                                   "Failed to send DCBX attention request\n");
1739                         return mfw_rc;
1740                 }
1741
1742                 p_hwfn->hw_init_done = true;
1743         }
1744
1745         return ECORE_SUCCESS;
1746 }
1747
1748 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
1749 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
1750                                  struct ecore_hwfn *p_hwfn,
1751                                  struct ecore_ptt *p_ptt)
1752 {
1753         int i;
1754
1755         /* close timers */
1756         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1757         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1758         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
1759                                                                         i++) {
1760                 if ((!ecore_rd(p_hwfn, p_ptt,
1761                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1762                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1763                         break;
1764
1765                 /* Dependent on number of connection/tasks, possibly
1766                  * 1ms sleep is required between polls
1767                  */
1768                 OSAL_MSLEEP(1);
1769         }
1770
1771         if (i < ECORE_HW_STOP_RETRY_LIMIT)
1772                 return;
1773
1774         DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
1775                   " [Connection %02x Tasks %02x]\n",
1776                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1777                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1778 }
1779
1780 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
1781 {
1782         int j;
1783
1784         for_each_hwfn(p_dev, j) {
1785                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1786                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1787
1788                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1789         }
1790 }
1791
1792 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
1793 {
1794         enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
1795         int j;
1796
1797         for_each_hwfn(p_dev, j) {
1798                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1799                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1800
1801                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
1802
1803                 if (IS_VF(p_dev)) {
1804                         ecore_vf_pf_int_cleanup(p_hwfn);
1805                         continue;
1806                 }
1807
1808                 /* mark the hw as uninitialized... */
1809                 p_hwfn->hw_init_done = false;
1810
1811                 rc = ecore_sp_pf_stop(p_hwfn);
1812                 if (rc)
1813                         DP_NOTICE(p_hwfn, true,
1814                                   "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
1815
1816                 /* perform debug action after PF stop was sent */
1817                 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
1818
1819                 /* close NIG to BRB gate */
1820                 ecore_wr(p_hwfn, p_ptt,
1821                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1822
1823                 /* close parser */
1824                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1825                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1826                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1827                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1828                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1829
1830                 /* @@@TBD - clean transmission queues (5.b) */
1831                 /* @@@TBD - clean BTB (5.c) */
1832
1833                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1834
1835                 /* @@@TBD - verify DMAE requests are done (8) */
1836
1837                 /* Disable Attention Generation */
1838                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1839                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1840                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1841                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1842                 /* Need to wait 1ms to guarantee SBs are cleared */
1843                 OSAL_MSLEEP(1);
1844         }
1845
1846         if (IS_PF(p_dev)) {
1847                 /* Disable DMAE in PXP - in CMT, this should only be done for
1848                  * first hw-function, and only after all transactions have
1849                  * stopped for all active hw-functions.
1850                  */
1851                 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
1852                                              p_dev->hwfns[0].p_main_ptt, false);
1853                 if (t_rc != ECORE_SUCCESS)
1854                         rc = t_rc;
1855         }
1856
1857         return rc;
1858 }
1859
1860 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
1861 {
1862         int j;
1863
1864         for_each_hwfn(p_dev, j) {
1865                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1866                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1867
1868                 if (IS_VF(p_dev)) {
1869                         ecore_vf_pf_int_cleanup(p_hwfn);
1870                         continue;
1871                 }
1872
1873                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1874                            "Shutting down the fastpath\n");
1875
1876                 ecore_wr(p_hwfn, p_ptt,
1877                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1878
1879                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1880                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1881                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1882                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1883                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1884
1885                 /* @@@TBD - clean transmission queues (5.b) */
1886                 /* @@@TBD - clean BTB (5.c) */
1887
1888                 /* @@@TBD - verify DMAE requests are done (8) */
1889
1890                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1891                 /* Need to wait 1ms to guarantee SBs are cleared */
1892                 OSAL_MSLEEP(1);
1893         }
1894 }
1895
1896 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
1897 {
1898         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1899
1900         if (IS_VF(p_hwfn->p_dev))
1901                 return;
1902
1903         /* If roce info is allocated it means roce is initialized and should
1904          * be enabled in searcher.
1905          */
1906         if (p_hwfn->p_rdma_info) {
1907                 if (p_hwfn->b_rdma_enabled_in_prs)
1908                         ecore_wr(p_hwfn, p_ptt,
1909                                  p_hwfn->rdma_prs_search_reg, 0x1);
1910                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
1911         }
1912
1913         /* Re-open incoming traffic */
1914         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1915                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1916 }
1917
1918 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
1919                                              struct ecore_ptt *p_ptt, u32 reg,
1920                                              bool expected)
1921 {
1922         u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
1923
1924         if (assert_val != expected) {
1925                 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
1926                           reg, expected);
1927                 return ECORE_UNKNOWN_ERROR;
1928         }
1929
1930         return 0;
1931 }
1932
1933 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
1934 {
1935         enum _ecore_status_t rc = ECORE_SUCCESS;
1936         u32 unload_resp, unload_param;
1937         int i;
1938
1939         for_each_hwfn(p_dev, i) {
1940                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1941
1942                 if (IS_VF(p_dev)) {
1943                         rc = ecore_vf_pf_reset(p_hwfn);
1944                         if (rc)
1945                                 return rc;
1946                         continue;
1947                 }
1948
1949                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
1950
1951                 /* Check for incorrect states */
1952                 if (!p_dev->recov_in_prog) {
1953                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1954                                          QM_REG_USG_CNT_PF_TX, 0);
1955                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1956                                          QM_REG_USG_CNT_PF_OTHER, 0);
1957                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
1958                 }
1959
1960                 /* Disable PF in HW blocks */
1961                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1962                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1963
1964                 if (p_dev->recov_in_prog) {
1965                         DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1966                                    "Recovery is in progress -> skip sending unload_req/done\n");
1967                         break;
1968                 }
1969
1970                 /* Send unload command to MCP */
1971                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1972                                    DRV_MSG_CODE_UNLOAD_REQ,
1973                                    DRV_MB_PARAM_UNLOAD_WOL_MCP,
1974                                    &unload_resp, &unload_param);
1975                 if (rc != ECORE_SUCCESS) {
1976                         DP_NOTICE(p_hwfn, true,
1977                                   "ecore_hw_reset: UNLOAD_REQ failed\n");
1978                         /* @@TBD - what to do? for now, assume ENG. */
1979                         unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
1980                 }
1981
1982                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1983                                    DRV_MSG_CODE_UNLOAD_DONE,
1984                                    0, &unload_resp, &unload_param);
1985                 if (rc != ECORE_SUCCESS) {
1986                         DP_NOTICE(p_hwfn,
1987                                   true, "ecore_hw_reset: UNLOAD_DONE failed\n");
1988                         /* @@@TBD - Should it really ASSERT here ? */
1989                         return rc;
1990                 }
1991         }
1992
1993         return rc;
1994 }
1995
1996 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1997 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
1998 {
1999         ecore_ptt_pool_free(p_hwfn);
2000         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2001 }
2002
2003 /* Setup bar access */
2004 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2005 {
2006         /* clear indirect access */
2007         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2008                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2009                          PGLUE_B_REG_PGL_ADDR_E8_F0, 0);
2010                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2011                          PGLUE_B_REG_PGL_ADDR_EC_F0, 0);
2012                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2013                          PGLUE_B_REG_PGL_ADDR_F0_F0, 0);
2014                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2015                          PGLUE_B_REG_PGL_ADDR_F4_F0, 0);
2016         } else {
2017                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2018                          PGLUE_B_REG_PGL_ADDR_88_F0, 0);
2019                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2020                          PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
2021                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2022                          PGLUE_B_REG_PGL_ADDR_90_F0, 0);
2023                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2024                          PGLUE_B_REG_PGL_ADDR_94_F0, 0);
2025         }
2026
2027         /* Clean Previous errors if such exist */
2028         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2029                  PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2030
2031         /* enable internal target-read */
2032         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2033                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2034 }
2035
2036 static void get_function_id(struct ecore_hwfn *p_hwfn)
2037 {
2038         /* ME Register */
2039         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2040                                                   PXP_PF_ME_OPAQUE_ADDR);
2041
2042         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2043
2044         /* Bits 16-19 from the ME registers are the pf_num */
2045         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2046         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2047                                       PXP_CONCRETE_FID_PFID);
2048         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2049                                     PXP_CONCRETE_FID_PORT);
2050
2051         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2052                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2053                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2054 }
2055
2056 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2057 {
2058         u32 *feat_num = p_hwfn->hw_info.feat_num;
2059         struct ecore_sb_cnt_info sb_cnt_info;
2060         int num_features = 1;
2061
2062         /* L2 Queues require each: 1 status block. 1 L2 queue */
2063         feat_num[ECORE_PF_L2_QUE] =
2064             OSAL_MIN_T(u32,
2065                        RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2066                        RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2067
2068         OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2069         ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2070         feat_num[ECORE_VF_L2_QUE] =
2071                 OSAL_MIN_T(u32,
2072                            RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2073                            FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2074                            sb_cnt_info.sb_iov_cnt);
2075
2076         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2077                    "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d num_features=%d\n",
2078                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2079                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2080                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2081                    RESC_NUM(p_hwfn, ECORE_SB),
2082                    num_features);
2083 }
2084
2085 static enum resource_id_enum
2086 ecore_hw_get_mfw_res_id(enum ecore_resources res_id)
2087 {
2088         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2089
2090         switch (res_id) {
2091         case ECORE_SB:
2092                 mfw_res_id = RESOURCE_NUM_SB_E;
2093                 break;
2094         case ECORE_L2_QUEUE:
2095                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2096                 break;
2097         case ECORE_VPORT:
2098                 mfw_res_id = RESOURCE_NUM_VPORT_E;
2099                 break;
2100         case ECORE_RSS_ENG:
2101                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2102                 break;
2103         case ECORE_PQ:
2104                 mfw_res_id = RESOURCE_NUM_PQ_E;
2105                 break;
2106         case ECORE_RL:
2107                 mfw_res_id = RESOURCE_NUM_RL_E;
2108                 break;
2109         case ECORE_MAC:
2110         case ECORE_VLAN:
2111                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2112                 mfw_res_id = RESOURCE_VFC_FILTER_E;
2113                 break;
2114         case ECORE_ILT:
2115                 mfw_res_id = RESOURCE_ILT_E;
2116                 break;
2117         case ECORE_LL2_QUEUE:
2118                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2119                 break;
2120         case ECORE_RDMA_CNQ_RAM:
2121         case ECORE_CMDQS_CQS:
2122                 /* CNQ/CMDQS are the same resource */
2123                 mfw_res_id = RESOURCE_CQS_E;
2124                 break;
2125         case ECORE_RDMA_STATS_QUEUE:
2126                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2127                 break;
2128         default:
2129                 break;
2130         }
2131
2132         return mfw_res_id;
2133 }
2134
2135 static u32 ecore_hw_get_dflt_resc_num(struct ecore_hwfn *p_hwfn,
2136                                       enum ecore_resources res_id)
2137 {
2138         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2139         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2140         struct ecore_sb_cnt_info sb_cnt_info;
2141         u32 dflt_resc_num = 0;
2142
2143         switch (res_id) {
2144         case ECORE_SB:
2145                 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2146                 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2147                 dflt_resc_num = sb_cnt_info.sb_cnt;
2148                 break;
2149         case ECORE_L2_QUEUE:
2150                 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2151                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
2152                 break;
2153         case ECORE_VPORT:
2154                 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2155                                  MAX_NUM_VPORTS_BB) / num_funcs;
2156                 break;
2157         case ECORE_RSS_ENG:
2158                 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2159                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2160                 break;
2161         case ECORE_PQ:
2162                 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2163                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
2164                 break;
2165         case ECORE_RL:
2166                 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2167                 break;
2168         case ECORE_MAC:
2169         case ECORE_VLAN:
2170                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2171                 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2172                 break;
2173         case ECORE_ILT:
2174                 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2175                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2176                 break;
2177         case ECORE_LL2_QUEUE:
2178                 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2179                 break;
2180         case ECORE_RDMA_CNQ_RAM:
2181         case ECORE_CMDQS_CQS:
2182                 /* CNQ/CMDQS are the same resource */
2183                 /* @DPDK */
2184                 dflt_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2185                 break;
2186         case ECORE_RDMA_STATS_QUEUE:
2187                 /* @DPDK */
2188                 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2189                                  MAX_NUM_VPORTS_BB) / num_funcs;
2190                 break;
2191         default:
2192                 break;
2193         }
2194
2195         return dflt_resc_num;
2196 }
2197
2198 static const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2199 {
2200         switch (res_id) {
2201         case ECORE_SB:
2202                 return "SB";
2203         case ECORE_L2_QUEUE:
2204                 return "L2_QUEUE";
2205         case ECORE_VPORT:
2206                 return "VPORT";
2207         case ECORE_RSS_ENG:
2208                 return "RSS_ENG";
2209         case ECORE_PQ:
2210                 return "PQ";
2211         case ECORE_RL:
2212                 return "RL";
2213         case ECORE_MAC:
2214                 return "MAC";
2215         case ECORE_VLAN:
2216                 return "VLAN";
2217         case ECORE_RDMA_CNQ_RAM:
2218                 return "RDMA_CNQ_RAM";
2219         case ECORE_ILT:
2220                 return "ILT";
2221         case ECORE_LL2_QUEUE:
2222                 return "LL2_QUEUE";
2223         case ECORE_CMDQS_CQS:
2224                 return "CMDQS_CQS";
2225         case ECORE_RDMA_STATS_QUEUE:
2226                 return "RDMA_STATS_QUEUE";
2227         default:
2228                 return "UNKNOWN_RESOURCE";
2229         }
2230 }
2231
2232 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2233                                                    enum ecore_resources res_id,
2234                                                    bool drv_resc_alloc)
2235 {
2236         u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
2237         u32 *p_resc_num, *p_resc_start;
2238         struct resource_info resc_info;
2239         enum _ecore_status_t rc;
2240
2241         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2242         p_resc_start = &RESC_START(p_hwfn, res_id);
2243
2244         dflt_resc_num = ecore_hw_get_dflt_resc_num(p_hwfn, res_id);
2245         if (!dflt_resc_num) {
2246                 DP_ERR(p_hwfn,
2247                        "Failed to get default amount for resource %d [%s]\n",
2248                         res_id, ecore_hw_get_resc_name(res_id));
2249                 return ECORE_INVAL;
2250         }
2251         dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
2252
2253 #ifndef ASIC_ONLY
2254         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2255                 *p_resc_num = dflt_resc_num;
2256                 *p_resc_start = dflt_resc_start;
2257                 goto out;
2258         }
2259 #endif
2260
2261         OSAL_MEM_ZERO(&resc_info, sizeof(resc_info));
2262         resc_info.res_id = ecore_hw_get_mfw_res_id(res_id);
2263         if (resc_info.res_id == RESOURCE_NUM_INVALID) {
2264                 DP_ERR(p_hwfn,
2265                        "Failed to match resource %d with MFW resources\n",
2266                        res_id);
2267                 return ECORE_INVAL;
2268         }
2269
2270         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
2271                                      &mcp_resp, &mcp_param);
2272         if (rc != ECORE_SUCCESS) {
2273                 DP_NOTICE(p_hwfn, true,
2274                           "MFW response failure for an allocation request for"
2275                           " resource %d [%s]\n",
2276                           res_id, ecore_hw_get_resc_name(res_id));
2277                 return rc;
2278         }
2279
2280         /* Default driver values are applied in the following cases:
2281          * - The resource allocation MB command is not supported by the MFW
2282          * - There is an internal error in the MFW while processing the request
2283          * - The resource ID is unknown to the MFW
2284          */
2285         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
2286             mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
2287                 /* @DPDK */
2288                 DP_INFO(p_hwfn,
2289                         "Resource %d [%s]: No allocation info was received"
2290                         " [mcp_resp 0x%x]. Applying default values"
2291                         " [num %d, start %d].\n",
2292                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2293                         dflt_resc_num, dflt_resc_start);
2294
2295                 *p_resc_num = dflt_resc_num;
2296                 *p_resc_start = dflt_resc_start;
2297                 goto out;
2298         }
2299
2300         /* TBD - remove this when revising the handling of the SB resource */
2301         if (res_id == ECORE_SB) {
2302                 /* Excluding the slowpath SB */
2303                 resc_info.size -= 1;
2304                 resc_info.offset -= p_hwfn->enabled_func_idx;
2305         }
2306
2307         *p_resc_num = resc_info.size;
2308         *p_resc_start = resc_info.offset;
2309
2310         if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2311                 DP_INFO(p_hwfn,
2312                         "Resource %d [%s]: MFW allocation [num %d, start %d] differs from default values [num %d, start %d]%s\n",
2313                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2314                         *p_resc_start, dflt_resc_num, dflt_resc_start,
2315                         drv_resc_alloc ? " - Applying default values" : "");
2316                 if (drv_resc_alloc) {
2317                         *p_resc_num = dflt_resc_num;
2318                         *p_resc_start = dflt_resc_start;
2319                 }
2320         }
2321  out:
2322         return ECORE_SUCCESS;
2323 }
2324
2325 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2326                                               bool drv_resc_alloc)
2327 {
2328         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2329         enum _ecore_status_t rc;
2330         u8 res_id;
2331 #ifndef ASIC_ONLY
2332         u32 *resc_start = p_hwfn->hw_info.resc_start;
2333         u32 *resc_num = p_hwfn->hw_info.resc_num;
2334         /* For AH, an equal share of the ILT lines between the maximal number of
2335          * PFs is not enough for RoCE. This would be solved by the future
2336          * resource allocation scheme, but isn't currently present for
2337          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2338          * to work - the BB number of ILT lines divided by its max PFs number.
2339          */
2340         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2341 #endif
2342
2343         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2344                 rc = ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2345                 if (rc != ECORE_SUCCESS)
2346                         return rc;
2347         }
2348
2349 #ifndef ASIC_ONLY
2350         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2351                 /* Reduced build contains less PQs */
2352                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2353                         resc_num[ECORE_PQ] = 32;
2354                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2355                             p_hwfn->enabled_func_idx;
2356                 }
2357
2358                 /* For AH emulation, since we have a possible maximal number of
2359                  * 16 enabled PFs, in case there are not enough ILT lines -
2360                  * allocate only first PF as RoCE and have all the other ETH
2361                  * only with less ILT lines.
2362                  */
2363                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2364                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2365                                                          resc_num[ECORE_ILT],
2366                                                          roce_min_ilt_lines);
2367         }
2368
2369         /* Correct the common ILT calculation if PF0 has more */
2370         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2371             p_hwfn->p_dev->b_is_emul_full &&
2372             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2373                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2374                     resc_num[ECORE_ILT];
2375 #endif
2376
2377         /* Sanity for ILT */
2378         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2379             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2380                 DP_NOTICE(p_hwfn, true,
2381                           "Can't assign ILT pages [%08x,...,%08x]\n",
2382                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2383                                                                   ECORE_ILT) -
2384                           1);
2385                 return ECORE_INVAL;
2386         }
2387
2388         ecore_hw_set_feat(p_hwfn);
2389
2390         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2391                    "The numbers for each resource are:\n");
2392         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2393                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2394                            ecore_hw_get_resc_name(res_id),
2395                            RESC_NUM(p_hwfn, res_id),
2396                            RESC_START(p_hwfn, res_id));
2397
2398         return ECORE_SUCCESS;
2399 }
2400
2401 static enum _ecore_status_t ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2402                                                   struct ecore_ptt *p_ptt)
2403 {
2404         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
2405         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2406         struct ecore_mcp_link_params *link;
2407
2408         /* Read global nvm_cfg address */
2409         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2410
2411         /* Verify MCP has initialized it */
2412         if (!nvm_cfg_addr) {
2413                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2414                 return ECORE_INVAL;
2415         }
2416
2417 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2418
2419         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2420
2421         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2422             OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2423                                                        core_cfg);
2424
2425         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2426
2427         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2428                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2429         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2430                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2431                 break;
2432         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2433                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2434                 break;
2435         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2436                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2437                 break;
2438         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2439                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2440                 break;
2441         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2442                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2443                 break;
2444         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2445                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2446                 break;
2447         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2448                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2449                 break;
2450         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2451                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2452                 break;
2453         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2454                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
2455                 break;
2456         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2457                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2458                 break;
2459         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2460                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2461                 break;
2462         default:
2463                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2464                           core_cfg);
2465                 break;
2466         }
2467
2468         /* Read DCBX configuration */
2469         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2470                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2471         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
2472                              port_cfg_addr +
2473                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
2474         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
2475                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
2476         switch (dcbx_mode) {
2477         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
2478                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
2479                 break;
2480         case NVM_CFG1_PORT_DCBX_MODE_CEE:
2481                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
2482                 break;
2483         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
2484                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
2485                 break;
2486         default:
2487                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
2488         }
2489
2490         /* Read default link configuration */
2491         link = &p_hwfn->mcp_info->link_input;
2492         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2493             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2494         link_temp = ecore_rd(p_hwfn, p_ptt,
2495                              port_cfg_addr +
2496                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2497         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2498         link->speed.advertised_speeds = link_temp;
2499
2500         link_temp = link->speed.advertised_speeds;
2501         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2502
2503         link_temp = ecore_rd(p_hwfn, p_ptt,
2504                              port_cfg_addr +
2505                              OFFSETOF(struct nvm_cfg1_port, link_settings));
2506         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2507                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2508         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2509                 link->speed.autoneg = true;
2510                 break;
2511         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2512                 link->speed.forced_speed = 1000;
2513                 break;
2514         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2515                 link->speed.forced_speed = 10000;
2516                 break;
2517         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2518                 link->speed.forced_speed = 25000;
2519                 break;
2520         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2521                 link->speed.forced_speed = 40000;
2522                 break;
2523         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2524                 link->speed.forced_speed = 50000;
2525                 break;
2526         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2527                 link->speed.forced_speed = 100000;
2528                 break;
2529         default:
2530                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
2531         }
2532
2533         p_hwfn->mcp_info->link_capabilities.default_speed =
2534             link->speed.forced_speed;
2535         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2536             link->speed.autoneg;
2537
2538         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2539         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2540         link->pause.autoneg = !!(link_temp &
2541                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2542         link->pause.forced_rx = !!(link_temp &
2543                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2544         link->pause.forced_tx = !!(link_temp &
2545                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2546         link->loopback_mode = 0;
2547
2548         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2549                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2550                    link->speed.forced_speed, link->speed.advertised_speeds,
2551                    link->speed.autoneg, link->pause.autoneg);
2552
2553         /* Read Multi-function information from shmem */
2554         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2555             OFFSETOF(struct nvm_cfg1, glob) +
2556             OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
2557
2558         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
2559
2560         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2561             NVM_CFG1_GLOB_MF_MODE_OFFSET;
2562
2563         switch (mf_mode) {
2564         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2565                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
2566                 break;
2567         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2568                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
2569                 break;
2570         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2571                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
2572                 break;
2573         }
2574         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2575                 p_hwfn->p_dev->mf_mode);
2576
2577         /* Read Multi-function information from shmem */
2578         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2579             OFFSETOF(struct nvm_cfg1, glob) +
2580             OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
2581
2582         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
2583         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2584                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
2585                              &p_hwfn->hw_info.device_capabilities);
2586         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2587                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
2588                              &p_hwfn->hw_info.device_capabilities);
2589         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2590                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
2591                              &p_hwfn->hw_info.device_capabilities);
2592         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2593                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
2594                              &p_hwfn->hw_info.device_capabilities);
2595         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
2596                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
2597                              &p_hwfn->hw_info.device_capabilities);
2598
2599         return ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2600 }
2601
2602 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
2603                                 struct ecore_ptt *p_ptt)
2604 {
2605         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2606         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2607         struct ecore_dev *p_dev = p_hwfn->p_dev;
2608
2609         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2610
2611         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2612          * in the other bits are selected.
2613          * Bits 1-15 are for functions 1-15, respectively, and their value is
2614          * '0' only for enabled functions (function 0 always exists and
2615          * enabled).
2616          * In case of CMT in BB, only the "even" functions are enabled, and thus
2617          * the number of functions for both hwfns is learnt from the same bits.
2618          */
2619         reg_function_hide = ecore_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2620
2621         if (reg_function_hide & 0x1) {
2622                 if (ECORE_IS_BB(p_dev)) {
2623                         if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
2624                                 num_funcs = 0;
2625                                 eng_mask = 0xaaaa;
2626                         } else {
2627                                 num_funcs = 1;
2628                                 eng_mask = 0x5554;
2629                         }
2630                 } else {
2631                         num_funcs = 1;
2632                         eng_mask = 0xfffe;
2633                 }
2634
2635                 /* Get the number of the enabled functions on the engine */
2636                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2637                 while (tmp) {
2638                         if (tmp & 0x1)
2639                                 num_funcs++;
2640                         tmp >>= 0x1;
2641                 }
2642
2643                 /* Get the PF index within the enabled functions */
2644                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2645                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2646                 while (tmp) {
2647                         if (tmp & 0x1)
2648                                 enabled_func_idx--;
2649                         tmp >>= 0x1;
2650                 }
2651         }
2652
2653         p_hwfn->num_funcs_on_engine = num_funcs;
2654         p_hwfn->enabled_func_idx = enabled_func_idx;
2655
2656 #ifndef ASIC_ONLY
2657         if (CHIP_REV_IS_FPGA(p_dev)) {
2658                 DP_NOTICE(p_hwfn, false,
2659                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
2660                 p_hwfn->num_funcs_on_engine = 4;
2661         }
2662 #endif
2663
2664         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2665                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2666                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
2667                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2668 }
2669
2670 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
2671                                       struct ecore_ptt *p_ptt)
2672 {
2673         u32 port_mode;
2674
2675 #ifndef ASIC_ONLY
2676         /* Read the port mode */
2677         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
2678                 port_mode = 4;
2679         else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
2680                  (p_hwfn->p_dev->num_hwfns > 1))
2681                 /* In CMT on emulation, assume 1 port */
2682                 port_mode = 1;
2683         else
2684 #endif
2685                 port_mode = ecore_rd(p_hwfn, p_ptt,
2686                                      CNIG_REG_NW_PORT_MODE_BB_B0);
2687
2688         if (port_mode < 3) {
2689                 p_hwfn->p_dev->num_ports_in_engines = 1;
2690         } else if (port_mode <= 5) {
2691                 p_hwfn->p_dev->num_ports_in_engines = 2;
2692         } else {
2693                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
2694                           p_hwfn->p_dev->num_ports_in_engines);
2695
2696                 /* Default num_ports_in_engines to something */
2697                 p_hwfn->p_dev->num_ports_in_engines = 1;
2698         }
2699 }
2700
2701 static void ecore_hw_info_port_num_ah(struct ecore_hwfn *p_hwfn,
2702                                       struct ecore_ptt *p_ptt)
2703 {
2704         u32 port;
2705         int i;
2706
2707         p_hwfn->p_dev->num_ports_in_engines = 0;
2708
2709 #ifndef ASIC_ONLY
2710         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2711                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
2712                 switch ((port & 0xf000) >> 12) {
2713                 case 1:
2714                         p_hwfn->p_dev->num_ports_in_engines = 1;
2715                         break;
2716                 case 3:
2717                         p_hwfn->p_dev->num_ports_in_engines = 2;
2718                         break;
2719                 case 0xf:
2720                         p_hwfn->p_dev->num_ports_in_engines = 4;
2721                         break;
2722                 default:
2723                         DP_NOTICE(p_hwfn, false,
2724                                   "Unknown port mode in ECO_RESERVED %08x\n",
2725                                   port);
2726                 }
2727         } else
2728 #endif
2729                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2730                         port = ecore_rd(p_hwfn, p_ptt,
2731                                         CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2732                         if (port & 1)
2733                                 p_hwfn->p_dev->num_ports_in_engines++;
2734                 }
2735 }
2736
2737 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
2738                                    struct ecore_ptt *p_ptt)
2739 {
2740         if (ECORE_IS_BB(p_hwfn->p_dev))
2741                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
2742         else
2743                 ecore_hw_info_port_num_ah(p_hwfn, p_ptt);
2744 }
2745
2746 static enum _ecore_status_t
2747 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2748                   enum ecore_pci_personality personality, bool drv_resc_alloc)
2749 {
2750         enum _ecore_status_t rc;
2751
2752         /* Since all information is common, only first hwfns should do this */
2753         if (IS_LEAD_HWFN(p_hwfn)) {
2754                 rc = ecore_iov_hw_info(p_hwfn);
2755                 if (rc != ECORE_SUCCESS)
2756                         return rc;
2757         }
2758
2759         /* TODO In get_hw_info, amoungst others:
2760          * Get MCP FW revision and determine according to it the supported
2761          * featrues (e.g. DCB)
2762          * Get boot mode
2763          * ecore_get_pcie_width_speed, WOL capability.
2764          * Number of global CQ-s (for storage
2765          */
2766         ecore_hw_info_port_num(p_hwfn, p_ptt);
2767
2768 #ifndef ASIC_ONLY
2769         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
2770 #endif
2771         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt);
2772         if (rc != ECORE_SUCCESS)
2773                 return rc;
2774 #ifndef ASIC_ONLY
2775         }
2776 #endif
2777
2778         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
2779         if (rc != ECORE_SUCCESS)
2780                 return rc;
2781
2782 #ifndef ASIC_ONLY
2783         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
2784 #endif
2785                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
2786                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
2787 #ifndef ASIC_ONLY
2788         } else {
2789                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
2790
2791                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
2792                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
2793         }
2794 #endif
2795
2796         if (ecore_mcp_is_init(p_hwfn)) {
2797                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
2798                         p_hwfn->hw_info.ovlan =
2799                             p_hwfn->mcp_info->func_info.ovlan;
2800
2801                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
2802         }
2803
2804         if (personality != ECORE_PCI_DEFAULT) {
2805                 p_hwfn->hw_info.personality = personality;
2806         } else if (ecore_mcp_is_init(p_hwfn)) {
2807                 enum ecore_pci_personality protocol;
2808
2809                 protocol = p_hwfn->mcp_info->func_info.protocol;
2810                 p_hwfn->hw_info.personality = protocol;
2811         }
2812
2813 #ifndef ASIC_ONLY
2814         /* To overcome ILT lack for emulation, until at least until we'll have
2815          * a definite answer from system about it, allow only PF0 to be RoCE.
2816          */
2817         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
2818                 if (!p_hwfn->rel_pf_id)
2819                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
2820                 else
2821                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
2822         }
2823 #endif
2824
2825         /* although in BB some constellations may support more than 4 tcs,
2826          * that can result in performance penalty in some cases. 4
2827          * represents a good tradeoff between performance and flexibility.
2828          */
2829         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2830
2831         /* start out with a single active tc. This can be increased either
2832          * by dcbx negotiation or by upper layer driver
2833          */
2834         p_hwfn->hw_info.num_active_tc = 1;
2835
2836         ecore_get_num_funcs(p_hwfn, p_ptt);
2837
2838         /* In case of forcing the driver's default resource allocation, calling
2839          * ecore_hw_get_resc() should come after initializing the personality
2840          * and after getting the number of functions, since the calculation of
2841          * the resources/features depends on them.
2842          * This order is not harmful if not forcing.
2843          */
2844         return ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
2845 }
2846
2847 #define ECORE_DEV_ID_MASK       0xff00
2848 #define ECORE_DEV_ID_MASK_BB    0x1600
2849 #define ECORE_DEV_ID_MASK_AH    0x8000
2850
2851 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
2852 {
2853         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2854         u32 tmp;
2855
2856         /* Read Vendor Id / Device Id */
2857         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
2858                                   &p_dev->vendor_id);
2859         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
2860                                   &p_dev->device_id);
2861
2862         /* Determine type */
2863         if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
2864                 p_dev->type = ECORE_DEV_TYPE_AH;
2865         else
2866                 p_dev->type = ECORE_DEV_TYPE_BB;
2867
2868         p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2869                                          MISCS_REG_CHIP_NUM);
2870         p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2871                                          MISCS_REG_CHIP_REV);
2872
2873         MASK_FIELD(CHIP_REV, p_dev->chip_rev);
2874
2875         /* Learn number of HW-functions */
2876         tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2877                        MISCS_REG_CMT_ENABLED_FOR_PAIR);
2878
2879         if (tmp & (1 << p_hwfn->rel_pf_id)) {
2880                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
2881                 p_dev->num_hwfns = 2;
2882         } else {
2883                 p_dev->num_hwfns = 1;
2884         }
2885
2886 #ifndef ASIC_ONLY
2887         if (CHIP_REV_IS_EMUL(p_dev)) {
2888                 /* For some reason we have problems with this register
2889                  * in B0 emulation; Simply assume no CMT
2890                  */
2891                 DP_NOTICE(p_dev->hwfns, false,
2892                           "device on emul - assume no CMT\n");
2893                 p_dev->num_hwfns = 1;
2894         }
2895 #endif
2896
2897         p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2898                                        MISCS_REG_CHIP_TEST_REG) >> 4;
2899         MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
2900         p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2901                                            MISCS_REG_CHIP_METAL);
2902         MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
2903         DP_INFO(p_dev->hwfns,
2904                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2905                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
2906                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
2907                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
2908                 p_dev->chip_metal);
2909
2910         if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
2911                 DP_NOTICE(p_dev->hwfns, false,
2912                           "The chip type/rev (BB A0) is not supported!\n");
2913                 return ECORE_ABORTED;
2914         }
2915 #ifndef ASIC_ONLY
2916         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
2917                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2918                          MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
2919
2920         if (CHIP_REV_IS_EMUL(p_dev)) {
2921                 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2922                                MISCS_REG_ECO_RESERVED);
2923                 if (tmp & (1 << 29)) {
2924                         DP_NOTICE(p_hwfn, false,
2925                                   "Emulation: Running on a FULL build\n");
2926                         p_dev->b_is_emul_full = true;
2927                 } else {
2928                         DP_NOTICE(p_hwfn, false,
2929                                   "Emulation: Running on a REDUCED build\n");
2930                 }
2931         }
2932 #endif
2933
2934         return ECORE_SUCCESS;
2935 }
2936
2937 #ifndef LINUX_REMOVE
2938 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
2939 {
2940         int j;
2941
2942         if (IS_VF(p_dev))
2943                 return;
2944
2945         for_each_hwfn(p_dev, j) {
2946                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2947
2948                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2949                            "Mark hw/fw uninitialized\n");
2950
2951                 p_hwfn->hw_init_done = false;
2952                 p_hwfn->first_on_engine = false;
2953
2954                 ecore_ptt_invalidate(p_hwfn);
2955         }
2956 }
2957 #endif
2958
2959 static enum _ecore_status_t
2960 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
2961                         void OSAL_IOMEM * p_regview,
2962                         void OSAL_IOMEM * p_doorbells,
2963                         struct ecore_hw_prepare_params *p_params)
2964 {
2965         struct ecore_dev *p_dev = p_hwfn->p_dev;
2966         struct ecore_mdump_info mdump_info;
2967         enum _ecore_status_t rc = ECORE_SUCCESS;
2968
2969         /* Split PCI bars evenly between hwfns */
2970         p_hwfn->regview = p_regview;
2971         p_hwfn->doorbells = p_doorbells;
2972
2973         if (IS_VF(p_dev))
2974                 return ecore_vf_hw_prepare(p_hwfn);
2975
2976         /* Validate that chip access is feasible */
2977         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2978                 DP_ERR(p_hwfn,
2979                        "Reading the ME register returns all Fs; Preventing further chip access\n");
2980                 return ECORE_INVAL;
2981         }
2982
2983         get_function_id(p_hwfn);
2984
2985         /* Allocate PTT pool */
2986         rc = ecore_ptt_pool_alloc(p_hwfn);
2987         if (rc) {
2988                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
2989                 goto err0;
2990         }
2991
2992         /* Allocate the main PTT */
2993         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2994
2995         /* First hwfn learns basic information, e.g., number of hwfns */
2996         if (!p_hwfn->my_id) {
2997                 rc = ecore_get_dev_info(p_dev);
2998                 if (rc != ECORE_SUCCESS)
2999                         goto err1;
3000         }
3001
3002         ecore_hw_hwfn_prepare(p_hwfn);
3003
3004         /* Initialize MCP structure */
3005         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3006         if (rc) {
3007                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3008                 goto err1;
3009         }
3010
3011         /* Read the device configuration information from the HW and SHMEM */
3012         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3013                                p_params->personality, p_params->drv_resc_alloc);
3014         if (rc) {
3015                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3016                 goto err2;
3017         }
3018
3019         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3020          * called, since among others it sets the ports number in an engine.
3021          */
3022         if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3023             !p_dev->recov_in_prog) {
3024                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3025                 if (rc != ECORE_SUCCESS)
3026                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3027         }
3028
3029         /* Check if mdump logs are present and update the epoch value */
3030         if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) {
3031                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3032                                               &mdump_info);
3033                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) {
3034                         DP_NOTICE(p_hwfn, false,
3035                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3036                 }
3037
3038                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3039                                            p_params->epoch);
3040         }
3041
3042         /* Allocate the init RT array and initialize the init-ops engine */
3043         rc = ecore_init_alloc(p_hwfn);
3044         if (rc) {
3045                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3046                 goto err2;
3047         }
3048 #ifndef ASIC_ONLY
3049         if (CHIP_REV_IS_FPGA(p_dev)) {
3050                 DP_NOTICE(p_hwfn, false,
3051                           "FPGA: workaround; Prevent DMAE parities\n");
3052                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK, 7);
3053
3054                 DP_NOTICE(p_hwfn, false,
3055                           "FPGA: workaround: Set VF bar0 size\n");
3056                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3057                          PGLUE_B_REG_VF_BAR0_SIZE, 4);
3058         }
3059 #endif
3060
3061         return rc;
3062  err2:
3063         if (IS_LEAD_HWFN(p_hwfn))
3064                 ecore_iov_free_hw_info(p_dev);
3065         ecore_mcp_free(p_hwfn);
3066  err1:
3067         ecore_hw_hwfn_free(p_hwfn);
3068  err0:
3069         return rc;
3070 }
3071
3072 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3073                                       struct ecore_hw_prepare_params *p_params)
3074 {
3075         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3076         enum _ecore_status_t rc;
3077
3078         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3079
3080         /* Store the precompiled init data ptrs */
3081         if (IS_PF(p_dev))
3082                 ecore_init_iro_array(p_dev);
3083
3084         /* Initialize the first hwfn - will learn number of hwfns */
3085         rc = ecore_hw_prepare_single(p_hwfn,
3086                                      p_dev->regview,
3087                                      p_dev->doorbells, p_params);
3088         if (rc != ECORE_SUCCESS)
3089                 return rc;
3090
3091         p_params->personality = p_hwfn->hw_info.personality;
3092
3093         /* initilalize 2nd hwfn if necessary */
3094         if (p_dev->num_hwfns > 1) {
3095                 void OSAL_IOMEM *p_regview, *p_doorbell;
3096                 u8 OSAL_IOMEM *addr;
3097
3098                 /* adjust bar offset for second engine */
3099                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3100                     ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3101                 p_regview = (void OSAL_IOMEM *)addr;
3102
3103                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3104                     ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3105                 p_doorbell = (void OSAL_IOMEM *)addr;
3106
3107                 /* prepare second hw function */
3108                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3109                                              p_doorbell, p_params);
3110
3111                 /* in case of error, need to free the previously
3112                  * initiliazed hwfn 0.
3113                  */
3114                 if (rc != ECORE_SUCCESS) {
3115                         if (IS_PF(p_dev)) {
3116                                 ecore_init_free(p_hwfn);
3117                                 ecore_mcp_free(p_hwfn);
3118                                 ecore_hw_hwfn_free(p_hwfn);
3119                         } else {
3120                                 DP_NOTICE(p_dev, true,
3121                                           "What do we need to free when VF hwfn1 init fails\n");
3122                         }
3123                         return rc;
3124                 }
3125         }
3126
3127         return rc;
3128 }
3129
3130 void ecore_hw_remove(struct ecore_dev *p_dev)
3131 {
3132         int i;
3133
3134         for_each_hwfn(p_dev, i) {
3135                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3136
3137                 if (IS_VF(p_dev)) {
3138                         ecore_vf_pf_release(p_hwfn);
3139                         continue;
3140                 }
3141
3142                 ecore_init_free(p_hwfn);
3143                 ecore_hw_hwfn_free(p_hwfn);
3144                 ecore_mcp_free(p_hwfn);
3145
3146                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3147         }
3148
3149         ecore_iov_free_hw_info(p_dev);
3150 }
3151
3152 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3153                                       struct ecore_chain *p_chain)
3154 {
3155         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3156         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3157         struct ecore_chain_next *p_next;
3158         u32 size, i;
3159
3160         if (!p_virt)
3161                 return;
3162
3163         size = p_chain->elem_size * p_chain->usable_per_page;
3164
3165         for (i = 0; i < p_chain->page_cnt; i++) {
3166                 if (!p_virt)
3167                         break;
3168
3169                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3170                 p_virt_next = p_next->next_virt;
3171                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3172
3173                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3174                                        ECORE_CHAIN_PAGE_SIZE);
3175
3176                 p_virt = p_virt_next;
3177                 p_phys = p_phys_next;
3178         }
3179 }
3180
3181 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3182                                     struct ecore_chain *p_chain)
3183 {
3184         if (!p_chain->p_virt_addr)
3185                 return;
3186
3187         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3188                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3189 }
3190
3191 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3192                                  struct ecore_chain *p_chain)
3193 {
3194         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3195         u8 *p_pbl_virt = (u8 *)p_chain->pbl.p_virt_table;
3196         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3197
3198         if (!pp_virt_addr_tbl)
3199                 return;
3200
3201         if (!p_chain->pbl.p_virt_table)
3202                 goto out;
3203
3204         for (i = 0; i < page_cnt; i++) {
3205                 if (!pp_virt_addr_tbl[i])
3206                         break;
3207
3208                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3209                                        *(dma_addr_t *)p_pbl_virt,
3210                                        ECORE_CHAIN_PAGE_SIZE);
3211
3212                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3213         }
3214
3215         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3216
3217         if (!p_chain->pbl.external)
3218                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table,
3219                                        p_chain->pbl.p_phys_table, pbl_size);
3220  out:
3221         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3222 }
3223
3224 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3225 {
3226         switch (p_chain->mode) {
3227         case ECORE_CHAIN_MODE_NEXT_PTR:
3228                 ecore_chain_free_next_ptr(p_dev, p_chain);
3229                 break;
3230         case ECORE_CHAIN_MODE_SINGLE:
3231                 ecore_chain_free_single(p_dev, p_chain);
3232                 break;
3233         case ECORE_CHAIN_MODE_PBL:
3234                 ecore_chain_free_pbl(p_dev, p_chain);
3235                 break;
3236         }
3237 }
3238
3239 static enum _ecore_status_t
3240 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3241                                enum ecore_chain_cnt_type cnt_type,
3242                                osal_size_t elem_size, u32 page_cnt)
3243 {
3244         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3245
3246         /* The actual chain size can be larger than the maximal possible value
3247          * after rounding up the requested elements number to pages, and after
3248          * taking into acount the unusuable elements (next-ptr elements).
3249          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3250          * size/capacity fields are of a u32 type.
3251          */
3252         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3253              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3254             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3255              chain_size > ECORE_U32_MAX)) {
3256                 DP_NOTICE(p_dev, true,
3257                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3258                           (unsigned long)chain_size);
3259                 return ECORE_INVAL;
3260         }
3261
3262         return ECORE_SUCCESS;
3263 }
3264
3265 static enum _ecore_status_t
3266 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3267 {
3268         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3269         dma_addr_t p_phys = 0;
3270         u32 i;
3271
3272         for (i = 0; i < p_chain->page_cnt; i++) {
3273                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3274                                                  ECORE_CHAIN_PAGE_SIZE);
3275                 if (!p_virt) {
3276                         DP_NOTICE(p_dev, true,
3277                                   "Failed to allocate chain memory\n");
3278                         return ECORE_NOMEM;
3279                 }
3280
3281                 if (i == 0) {
3282                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3283                         ecore_chain_reset(p_chain);
3284                 } else {
3285                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3286                                                        p_virt, p_phys);
3287                 }
3288
3289                 p_virt_prev = p_virt;
3290         }
3291         /* Last page's next element should point to the beginning of the
3292          * chain.
3293          */
3294         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3295                                        p_chain->p_virt_addr,
3296                                        p_chain->p_phys_addr);
3297
3298         return ECORE_SUCCESS;
3299 }
3300
3301 static enum _ecore_status_t
3302 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3303 {
3304         dma_addr_t p_phys = 0;
3305         void *p_virt = OSAL_NULL;
3306
3307         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3308         if (!p_virt) {
3309                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3310                 return ECORE_NOMEM;
3311         }
3312
3313         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3314         ecore_chain_reset(p_chain);
3315
3316         return ECORE_SUCCESS;
3317 }
3318
3319 static enum _ecore_status_t
3320 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3321                       struct ecore_chain *p_chain,
3322                       struct ecore_chain_ext_pbl *ext_pbl)
3323 {
3324         void *p_virt = OSAL_NULL;
3325         u8 *p_pbl_virt = OSAL_NULL;
3326         void **pp_virt_addr_tbl = OSAL_NULL;
3327         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3328         u32 page_cnt = p_chain->page_cnt, size, i;
3329
3330         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3331         pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
3332         if (!pp_virt_addr_tbl) {
3333                 DP_NOTICE(p_dev, true,
3334                           "Failed to allocate memory for the chain virtual addresses table\n");
3335                 return ECORE_NOMEM;
3336         }
3337         OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
3338
3339         /* The allocation of the PBL table is done with its full size, since it
3340          * is expected to be successive.
3341          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3342          * failure, since pp_virt_addr_tbl was previously allocated, and it
3343          * should be saved to allow its freeing during the error flow.
3344          */
3345         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3346
3347         if (ext_pbl == OSAL_NULL) {
3348                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3349         } else {
3350                 p_pbl_virt = ext_pbl->p_pbl_virt;
3351                 p_pbl_phys = ext_pbl->p_pbl_phys;
3352                 p_chain->pbl.external = true;
3353         }
3354
3355         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3356                                  pp_virt_addr_tbl);
3357         if (!p_pbl_virt) {
3358                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3359                 return ECORE_NOMEM;
3360         }
3361
3362         for (i = 0; i < page_cnt; i++) {
3363                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3364                                                  ECORE_CHAIN_PAGE_SIZE);
3365                 if (!p_virt) {
3366                         DP_NOTICE(p_dev, true,
3367                                   "Failed to allocate chain memory\n");
3368                         return ECORE_NOMEM;
3369                 }
3370
3371                 if (i == 0) {
3372                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3373                         ecore_chain_reset(p_chain);
3374                 }
3375
3376                 /* Fill the PBL table with the physical address of the page */
3377                 *(dma_addr_t *)p_pbl_virt = p_phys;
3378                 /* Keep the virtual address of the page */
3379                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3380
3381                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3382         }
3383
3384         return ECORE_SUCCESS;
3385 }
3386
3387 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3388                                        enum ecore_chain_use_mode intended_use,
3389                                        enum ecore_chain_mode mode,
3390                                        enum ecore_chain_cnt_type cnt_type,
3391                                        u32 num_elems, osal_size_t elem_size,
3392                                        struct ecore_chain *p_chain,
3393                                        struct ecore_chain_ext_pbl *ext_pbl)
3394 {
3395         u32 page_cnt;
3396         enum _ecore_status_t rc = ECORE_SUCCESS;
3397
3398         if (mode == ECORE_CHAIN_MODE_SINGLE)
3399                 page_cnt = 1;
3400         else
3401                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3402
3403         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3404                                             page_cnt);
3405         if (rc) {
3406                 DP_NOTICE(p_dev, true,
3407                           "Cannot allocate a chain with the given arguments:\n"
3408                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3409                           intended_use, mode, cnt_type, num_elems, elem_size);
3410                 return rc;
3411         }
3412
3413         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3414                                 mode, cnt_type, p_dev->dp_ctx);
3415
3416         switch (mode) {
3417         case ECORE_CHAIN_MODE_NEXT_PTR:
3418                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3419                 break;
3420         case ECORE_CHAIN_MODE_SINGLE:
3421                 rc = ecore_chain_alloc_single(p_dev, p_chain);
3422                 break;
3423         case ECORE_CHAIN_MODE_PBL:
3424                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
3425                 break;
3426         }
3427         if (rc)
3428                 goto nomem;
3429
3430         return ECORE_SUCCESS;
3431
3432  nomem:
3433         ecore_chain_free(p_dev, p_chain);
3434         return rc;
3435 }
3436
3437 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3438                                        u16 src_id, u16 *dst_id)
3439 {
3440         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3441                 u16 min, max;
3442
3443                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3444                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3445                 DP_NOTICE(p_hwfn, true,
3446                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3447                           src_id, min, max);
3448
3449                 return ECORE_INVAL;
3450         }
3451
3452         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3453
3454         return ECORE_SUCCESS;
3455 }
3456
3457 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3458                                     u8 src_id, u8 *dst_id)
3459 {
3460         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3461                 u8 min, max;
3462
3463                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3464                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3465                 DP_NOTICE(p_hwfn, true,
3466                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3467                           src_id, min, max);
3468
3469                 return ECORE_INVAL;
3470         }
3471
3472         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3473
3474         return ECORE_SUCCESS;
3475 }
3476
3477 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
3478                                       u8 src_id, u8 *dst_id)
3479 {
3480         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
3481                 u8 min, max;
3482
3483                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
3484                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
3485                 DP_NOTICE(p_hwfn, true,
3486                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3487                           src_id, min, max);
3488
3489                 return ECORE_INVAL;
3490         }
3491
3492         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
3493
3494         return ECORE_SUCCESS;
3495 }
3496
3497 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
3498                                               struct ecore_ptt *p_ptt,
3499                                               u8 *p_filter)
3500 {
3501         u32 high, low, en;
3502         int i;
3503
3504         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3505                 return ECORE_SUCCESS;
3506
3507         high = p_filter[1] | (p_filter[0] << 8);
3508         low = p_filter[5] | (p_filter[4] << 8) |
3509             (p_filter[3] << 16) | (p_filter[2] << 24);
3510
3511         /* Find a free entry and utilize it */
3512         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3513                 en = ecore_rd(p_hwfn, p_ptt,
3514                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3515                 if (en)
3516                         continue;
3517                 ecore_wr(p_hwfn, p_ptt,
3518                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3519                          2 * i * sizeof(u32), low);
3520                 ecore_wr(p_hwfn, p_ptt,
3521                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3522                          (2 * i + 1) * sizeof(u32), high);
3523                 ecore_wr(p_hwfn, p_ptt,
3524                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3525                 ecore_wr(p_hwfn, p_ptt,
3526                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3527                          i * sizeof(u32), 0);
3528                 ecore_wr(p_hwfn, p_ptt,
3529                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3530                 break;
3531         }
3532         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3533                 DP_NOTICE(p_hwfn, false,
3534                           "Failed to find an empty LLH filter to utilize\n");
3535                 return ECORE_INVAL;
3536         }
3537
3538         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3539                    "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
3540                    p_filter[0], p_filter[1], p_filter[2],
3541                    p_filter[3], p_filter[4], p_filter[5], i);
3542
3543         return ECORE_SUCCESS;
3544 }
3545
3546 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
3547                                  struct ecore_ptt *p_ptt, u8 *p_filter)
3548 {
3549         u32 high, low;
3550         int i;
3551
3552         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3553                 return;
3554
3555         high = p_filter[1] | (p_filter[0] << 8);
3556         low = p_filter[5] | (p_filter[4] << 8) |
3557             (p_filter[3] << 16) | (p_filter[2] << 24);
3558
3559         /* Find the entry and clean it */
3560         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3561                 if (ecore_rd(p_hwfn, p_ptt,
3562                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3563                              2 * i * sizeof(u32)) != low)
3564                         continue;
3565                 if (ecore_rd(p_hwfn, p_ptt,
3566                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3567                              (2 * i + 1) * sizeof(u32)) != high)
3568                         continue;
3569
3570                 ecore_wr(p_hwfn, p_ptt,
3571                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3572                 ecore_wr(p_hwfn, p_ptt,
3573                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3574                          2 * i * sizeof(u32), 0);
3575                 ecore_wr(p_hwfn, p_ptt,
3576                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3577                          (2 * i + 1) * sizeof(u32), 0);
3578                 break;
3579         }
3580         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3581                 DP_NOTICE(p_hwfn, false,
3582                           "Tried to remove a non-configured filter\n");
3583 }
3584
3585 enum _ecore_status_t
3586 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
3587                               struct ecore_ptt *p_ptt,
3588                               u16 source_port_or_eth_type,
3589                               u16 dest_port,
3590                               enum ecore_llh_port_filter_type_t type)
3591 {
3592         u32 high, low, en;
3593         int i;
3594
3595         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3596                 return ECORE_SUCCESS;
3597
3598         high = 0;
3599         low = 0;
3600         switch (type) {
3601         case ECORE_LLH_FILTER_ETHERTYPE:
3602                 high = source_port_or_eth_type;
3603                 break;
3604         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3605         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3606                 low = source_port_or_eth_type << 16;
3607                 break;
3608         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3609         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3610                 low = dest_port;
3611                 break;
3612         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3613         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3614                 low = (source_port_or_eth_type << 16) | dest_port;
3615                 break;
3616         default:
3617                 DP_NOTICE(p_hwfn, true,
3618                           "Non valid LLH protocol filter type %d\n", type);
3619                 return ECORE_INVAL;
3620         }
3621         /* Find a free entry and utilize it */
3622         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3623                 en = ecore_rd(p_hwfn, p_ptt,
3624                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3625                 if (en)
3626                         continue;
3627                 ecore_wr(p_hwfn, p_ptt,
3628                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3629                          2 * i * sizeof(u32), low);
3630                 ecore_wr(p_hwfn, p_ptt,
3631                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3632                          (2 * i + 1) * sizeof(u32), high);
3633                 ecore_wr(p_hwfn, p_ptt,
3634                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3635                 ecore_wr(p_hwfn, p_ptt,
3636                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3637                          i * sizeof(u32), 1 << type);
3638                 ecore_wr(p_hwfn, p_ptt,
3639                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3640                 break;
3641         }
3642         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3643                 DP_NOTICE(p_hwfn, false,
3644                           "Failed to find an empty LLH filter to utilize\n");
3645                 return ECORE_NORESOURCES;
3646         }
3647         switch (type) {
3648         case ECORE_LLH_FILTER_ETHERTYPE:
3649                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3650                            "ETH type %x is added at %d\n",
3651                            source_port_or_eth_type, i);
3652                 break;
3653         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3654                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3655                            "TCP src port %x is added at %d\n",
3656                            source_port_or_eth_type, i);
3657                 break;
3658         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3659                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3660                            "UDP src port %x is added at %d\n",
3661                            source_port_or_eth_type, i);
3662                 break;
3663         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3664                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3665                            "TCP dst port %x is added at %d\n", dest_port, i);
3666                 break;
3667         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3668                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3669                            "UDP dst port %x is added at %d\n", dest_port, i);
3670                 break;
3671         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3672                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3673                            "TCP src/dst ports %x/%x are added at %d\n",
3674                            source_port_or_eth_type, dest_port, i);
3675                 break;
3676         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3677                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3678                            "UDP src/dst ports %x/%x are added at %d\n",
3679                            source_port_or_eth_type, dest_port, i);
3680                 break;
3681         }
3682         return ECORE_SUCCESS;
3683 }
3684
3685 void
3686 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
3687                                  struct ecore_ptt *p_ptt,
3688                                  u16 source_port_or_eth_type,
3689                                  u16 dest_port,
3690                                  enum ecore_llh_port_filter_type_t type)
3691 {
3692         u32 high, low;
3693         int i;
3694
3695         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3696                 return;
3697
3698         high = 0;
3699         low = 0;
3700         switch (type) {
3701         case ECORE_LLH_FILTER_ETHERTYPE:
3702                 high = source_port_or_eth_type;
3703                 break;
3704         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3705         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3706                 low = source_port_or_eth_type << 16;
3707                 break;
3708         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3709         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3710                 low = dest_port;
3711                 break;
3712         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3713         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3714                 low = (source_port_or_eth_type << 16) | dest_port;
3715                 break;
3716         default:
3717                 DP_NOTICE(p_hwfn, true,
3718                           "Non valid LLH protocol filter type %d\n", type);
3719                 return;
3720         }
3721
3722         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3723                 if (!ecore_rd(p_hwfn, p_ptt,
3724                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3725                         continue;
3726                 if (!ecore_rd(p_hwfn, p_ptt,
3727                               NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3728                         continue;
3729                 if (!(ecore_rd(p_hwfn, p_ptt,
3730                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3731                                i * sizeof(u32)) & (1 << type)))
3732                         continue;
3733                 if (ecore_rd(p_hwfn, p_ptt,
3734                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3735                              2 * i * sizeof(u32)) != low)
3736                         continue;
3737                 if (ecore_rd(p_hwfn, p_ptt,
3738                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3739                              (2 * i + 1) * sizeof(u32)) != high)
3740                         continue;
3741
3742                 ecore_wr(p_hwfn, p_ptt,
3743                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3744                 ecore_wr(p_hwfn, p_ptt,
3745                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3746                 ecore_wr(p_hwfn, p_ptt,
3747                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3748                          i * sizeof(u32), 0);
3749                 ecore_wr(p_hwfn, p_ptt,
3750                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3751                          2 * i * sizeof(u32), 0);
3752                 ecore_wr(p_hwfn, p_ptt,
3753                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3754                          (2 * i + 1) * sizeof(u32), 0);
3755                 break;
3756         }
3757
3758         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3759                 DP_NOTICE(p_hwfn, false,
3760                           "Tried to remove a non-configured filter\n");
3761 }
3762
3763 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
3764                                  struct ecore_ptt *p_ptt)
3765 {
3766         int i;
3767
3768         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3769                 return;
3770
3771         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3772                 ecore_wr(p_hwfn, p_ptt,
3773                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3774                 ecore_wr(p_hwfn, p_ptt,
3775                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3776                          2 * i * sizeof(u32), 0);
3777                 ecore_wr(p_hwfn, p_ptt,
3778                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3779                          (2 * i + 1) * sizeof(u32), 0);
3780         }
3781 }
3782
3783 enum _ecore_status_t
3784 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
3785                                   struct ecore_ptt *p_ptt)
3786 {
3787         if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
3788                 ecore_wr(p_hwfn, p_ptt,
3789                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
3790                          1 << p_hwfn->abs_pf_id / 2);
3791                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
3792                 return ECORE_SUCCESS;
3793         }
3794
3795         DP_NOTICE(p_hwfn, false,
3796                   "This function can't be set as default\n");
3797         return ECORE_INVAL;
3798 }
3799
3800 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
3801                                                struct ecore_ptt *p_ptt,
3802                                                u32 hw_addr, void *p_eth_qzone,
3803                                                osal_size_t eth_qzone_size,
3804                                                u8 timeset)
3805 {
3806         struct coalescing_timeset *p_coal_timeset;
3807
3808         if (IS_VF(p_hwfn->p_dev)) {
3809                 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n");
3810                 return ECORE_INVAL;
3811         }
3812
3813         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
3814                 DP_NOTICE(p_hwfn, true,
3815                           "Coalescing configuration not enabled\n");
3816                 return ECORE_INVAL;
3817         }
3818
3819         p_coal_timeset = p_eth_qzone;
3820         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
3821         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3822         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3823         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3824
3825         return ECORE_SUCCESS;
3826 }
3827
3828 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
3829                                             struct ecore_ptt *p_ptt,
3830                                             u16 coalesce, u8 qid, u16 sb_id)
3831 {
3832         struct ustorm_eth_queue_zone eth_qzone;
3833         u8 timeset, timer_res;
3834         u16 fw_qid = 0;
3835         u32 address;
3836         enum _ecore_status_t rc;
3837
3838         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3839         if (coalesce <= 0x7F) {
3840                 timer_res = 0;
3841         } else if (coalesce <= 0xFF) {
3842                 timer_res = 1;
3843         } else if (coalesce <= 0x1FF) {
3844                 timer_res = 2;
3845         } else {
3846                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3847                 return ECORE_INVAL;
3848         }
3849         timeset = (u8)(coalesce >> timer_res);
3850
3851         rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3852         if (rc != ECORE_SUCCESS)
3853                 return rc;
3854
3855         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
3856         if (rc != ECORE_SUCCESS)
3857                 goto out;
3858
3859         address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3860
3861         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3862                                 sizeof(struct ustorm_eth_queue_zone), timeset);
3863         if (rc != ECORE_SUCCESS)
3864                 goto out;
3865
3866         p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
3867  out:
3868         return rc;
3869 }
3870
3871 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
3872                                             struct ecore_ptt *p_ptt,
3873                                             u16 coalesce, u8 qid, u16 sb_id)
3874 {
3875         struct xstorm_eth_queue_zone eth_qzone;
3876         u8 timeset, timer_res;
3877         u16 fw_qid = 0;
3878         u32 address;
3879         enum _ecore_status_t rc;
3880
3881         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3882         if (coalesce <= 0x7F) {
3883                 timer_res = 0;
3884         } else if (coalesce <= 0xFF) {
3885                 timer_res = 1;
3886         } else if (coalesce <= 0x1FF) {
3887                 timer_res = 2;
3888         } else {
3889                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3890                 return ECORE_INVAL;
3891         }
3892
3893         timeset = (u8)(coalesce >> timer_res);
3894
3895         rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3896         if (rc != ECORE_SUCCESS)
3897                 return rc;
3898
3899         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
3900         if (rc != ECORE_SUCCESS)
3901                 goto out;
3902
3903         address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3904
3905         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3906                                 sizeof(struct xstorm_eth_queue_zone), timeset);
3907         if (rc != ECORE_SUCCESS)
3908                 goto out;
3909
3910         p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
3911  out:
3912         return rc;
3913 }
3914
3915 /* Calculate final WFQ values for all vports and configure it.
3916  * After this configuration each vport must have
3917  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
3918  */
3919 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3920                                                struct ecore_ptt *p_ptt,
3921                                                u32 min_pf_rate)
3922 {
3923         struct init_qm_vport_params *vport_params;
3924         int i;
3925
3926         vport_params = p_hwfn->qm_info.qm_vport_params;
3927
3928         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3929                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3930
3931                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
3932                     min_pf_rate;
3933                 ecore_init_vport_wfq(p_hwfn, p_ptt,
3934                                      vport_params[i].first_tx_pq_id,
3935                                      vport_params[i].vport_wfq);
3936         }
3937 }
3938
3939 static void
3940 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
3941 {
3942         int i;
3943
3944         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3945                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3946 }
3947
3948 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3949                                              struct ecore_ptt *p_ptt,
3950                                              u32 min_pf_rate)
3951 {
3952         struct init_qm_vport_params *vport_params;
3953         int i;
3954
3955         vport_params = p_hwfn->qm_info.qm_vport_params;
3956
3957         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3958                 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
3959                 ecore_init_vport_wfq(p_hwfn, p_ptt,
3960                                      vport_params[i].first_tx_pq_id,
3961                                      vport_params[i].vport_wfq);
3962         }
3963 }
3964
3965 /* This function performs several validations for WFQ
3966  * configuration and required min rate for a given vport
3967  * 1. req_rate must be greater than one percent of min_pf_rate.
3968  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
3969  *    rates to get less than one percent of min_pf_rate.
3970  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
3971  */
3972 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
3973                                                  u16 vport_id, u32 req_rate,
3974                                                  u32 min_pf_rate)
3975 {
3976         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3977         int non_requested_count = 0, req_count = 0, i, num_vports;
3978
3979         num_vports = p_hwfn->qm_info.num_vports;
3980
3981 /* Accounting for the vports which are configured for WFQ explicitly */
3982
3983         for (i = 0; i < num_vports; i++) {
3984                 u32 tmp_speed;
3985
3986                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
3987                         req_count++;
3988                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3989                         total_req_min_rate += tmp_speed;
3990                 }
3991         }
3992
3993         /* Include current vport data as well */
3994         req_count++;
3995         total_req_min_rate += req_rate;
3996         non_requested_count = num_vports - req_count;
3997
3998         /* validate possible error cases */
3999         if (req_rate > min_pf_rate) {
4000                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4001                            "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4002                            vport_id, req_rate, min_pf_rate);
4003                 return ECORE_INVAL;
4004         }
4005
4006         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
4007                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4008                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4009                            vport_id, req_rate, min_pf_rate);
4010                 return ECORE_INVAL;
4011         }
4012
4013         /* TBD - for number of vports greater than 100 */
4014         if (num_vports > ECORE_WFQ_UNIT) {
4015                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4016                            "Number of vports is greater than %d\n",
4017                            ECORE_WFQ_UNIT);
4018                 return ECORE_INVAL;
4019         }
4020
4021         if (total_req_min_rate > min_pf_rate) {
4022                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4023                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4024                            total_req_min_rate, min_pf_rate);
4025                 return ECORE_INVAL;
4026         }
4027
4028         /* Data left for non requested vports */
4029         total_left_rate = min_pf_rate - total_req_min_rate;
4030         left_rate_per_vp = total_left_rate / non_requested_count;
4031
4032         /* validate if non requested get < 1% of min bw */
4033         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4034                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4035                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4036                            left_rate_per_vp, min_pf_rate);
4037                 return ECORE_INVAL;
4038         }
4039
4040         /* now req_rate for given vport passes all scenarios.
4041          * assign final wfq rates to all vports.
4042          */
4043         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4044         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4045
4046         for (i = 0; i < num_vports; i++) {
4047                 if (p_hwfn->qm_info.wfq_data[i].configured)
4048                         continue;
4049
4050                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4051         }
4052
4053         return ECORE_SUCCESS;
4054 }
4055
4056 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4057                                        struct ecore_ptt *p_ptt,
4058                                        u16 vp_id, u32 rate)
4059 {
4060         struct ecore_mcp_link_state *p_link;
4061         int rc = ECORE_SUCCESS;
4062
4063         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4064
4065         if (!p_link->min_pf_rate) {
4066                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4067                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4068                 return rc;
4069         }
4070
4071         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4072
4073         if (rc == ECORE_SUCCESS)
4074                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4075                                                    p_link->min_pf_rate);
4076         else
4077                 DP_NOTICE(p_hwfn, false,
4078                           "Validation failed while configuring min rate\n");
4079
4080         return rc;
4081 }
4082
4083 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4084                                                    struct ecore_ptt *p_ptt,
4085                                                    u32 min_pf_rate)
4086 {
4087         bool use_wfq = false;
4088         int rc = ECORE_SUCCESS;
4089         u16 i;
4090
4091         /* Validate all pre configured vports for wfq */
4092         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4093                 u32 rate;
4094
4095                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4096                         continue;
4097
4098                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4099                 use_wfq = true;
4100
4101                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4102                 if (rc != ECORE_SUCCESS) {
4103                         DP_NOTICE(p_hwfn, false,
4104                                   "WFQ validation failed while configuring min rate\n");
4105                         break;
4106                 }
4107         }
4108
4109         if (rc == ECORE_SUCCESS && use_wfq)
4110                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4111         else
4112                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4113
4114         return rc;
4115 }
4116
4117 /* Main API for ecore clients to configure vport min rate.
4118  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4119  * rate - Speed in Mbps needs to be assigned to a given vport.
4120  */
4121 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4122 {
4123         int i, rc = ECORE_INVAL;
4124
4125         /* TBD - for multiple hardware functions - that is 100 gig */
4126         if (p_dev->num_hwfns > 1) {
4127                 DP_NOTICE(p_dev, false,
4128                           "WFQ configuration is not supported for this device\n");
4129                 return rc;
4130         }
4131
4132         for_each_hwfn(p_dev, i) {
4133                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4134                 struct ecore_ptt *p_ptt;
4135
4136                 p_ptt = ecore_ptt_acquire(p_hwfn);
4137                 if (!p_ptt)
4138                         return ECORE_TIMEOUT;
4139
4140                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4141
4142                 if (rc != ECORE_SUCCESS) {
4143                         ecore_ptt_release(p_hwfn, p_ptt);
4144                         return rc;
4145                 }
4146
4147                 ecore_ptt_release(p_hwfn, p_ptt);
4148         }
4149
4150         return rc;
4151 }
4152
4153 /* API to configure WFQ from mcp link change */
4154 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4155                                            u32 min_pf_rate)
4156 {
4157         int i;
4158
4159         /* TBD - for multiple hardware functions - that is 100 gig */
4160         if (p_dev->num_hwfns > 1) {
4161                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4162                            "WFQ configuration is not supported for this device\n");
4163                 return;
4164         }
4165
4166         for_each_hwfn(p_dev, i) {
4167                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4168
4169                 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4170                                                         p_hwfn->p_dpc_ptt,
4171                                                         min_pf_rate);
4172         }
4173 }
4174
4175 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4176                                        struct ecore_ptt *p_ptt,
4177                                        struct ecore_mcp_link_state *p_link,
4178                                        u8 max_bw)
4179 {
4180         int rc = ECORE_SUCCESS;
4181
4182         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4183
4184         if (!p_link->line_speed && (max_bw != 100))
4185                 return rc;
4186
4187         p_link->speed = (p_link->line_speed * max_bw) / 100;
4188         p_hwfn->qm_info.pf_rl = p_link->speed;
4189
4190         /* Since the limiter also affects Tx-switched traffic, we don't want it
4191          * to limit such traffic in case there's no actual limit.
4192          * In that case, set limit to imaginary high boundary.
4193          */
4194         if (max_bw == 100)
4195                 p_hwfn->qm_info.pf_rl = 100000;
4196
4197         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4198                               p_hwfn->qm_info.pf_rl);
4199
4200         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4201                    "Configured MAX bandwidth to be %08x Mb/sec\n",
4202                    p_link->speed);
4203
4204         return rc;
4205 }
4206
4207 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4208 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4209 {
4210         int i, rc = ECORE_INVAL;
4211
4212         if (max_bw < 1 || max_bw > 100) {
4213                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4214                 return rc;
4215         }
4216
4217         for_each_hwfn(p_dev, i) {
4218                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4219                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4220                 struct ecore_mcp_link_state *p_link;
4221                 struct ecore_ptt *p_ptt;
4222
4223                 p_link = &p_lead->mcp_info->link_output;
4224
4225                 p_ptt = ecore_ptt_acquire(p_hwfn);
4226                 if (!p_ptt)
4227                         return ECORE_TIMEOUT;
4228
4229                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4230                                                         p_link, max_bw);
4231
4232                 ecore_ptt_release(p_hwfn, p_ptt);
4233
4234                 if (rc != ECORE_SUCCESS)
4235                         break;
4236         }
4237
4238         return rc;
4239 }
4240
4241 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4242                                        struct ecore_ptt *p_ptt,
4243                                        struct ecore_mcp_link_state *p_link,
4244                                        u8 min_bw)
4245 {
4246         int rc = ECORE_SUCCESS;
4247
4248         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4249         p_hwfn->qm_info.pf_wfq = min_bw;
4250
4251         if (!p_link->line_speed)
4252                 return rc;
4253
4254         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4255
4256         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4257
4258         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4259                    "Configured MIN bandwidth to be %d Mb/sec\n",
4260                    p_link->min_pf_rate);
4261
4262         return rc;
4263 }
4264
4265 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4266 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4267 {
4268         int i, rc = ECORE_INVAL;
4269
4270         if (min_bw < 1 || min_bw > 100) {
4271                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4272                 return rc;
4273         }
4274
4275         for_each_hwfn(p_dev, i) {
4276                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4277                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4278                 struct ecore_mcp_link_state *p_link;
4279                 struct ecore_ptt *p_ptt;
4280
4281                 p_link = &p_lead->mcp_info->link_output;
4282
4283                 p_ptt = ecore_ptt_acquire(p_hwfn);
4284                 if (!p_ptt)
4285                         return ECORE_TIMEOUT;
4286
4287                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4288                                                         p_link, min_bw);
4289                 if (rc != ECORE_SUCCESS) {
4290                         ecore_ptt_release(p_hwfn, p_ptt);
4291                         return rc;
4292                 }
4293
4294                 if (p_link->min_pf_rate) {
4295                         u32 min_rate = p_link->min_pf_rate;
4296
4297                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4298                                                                      p_ptt,
4299                                                                      min_rate);
4300                 }
4301
4302                 ecore_ptt_release(p_hwfn, p_ptt);
4303         }
4304
4305         return rc;
4306 }
4307
4308 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4309 {
4310         struct ecore_mcp_link_state *p_link;
4311
4312         p_link = &p_hwfn->mcp_info->link_output;
4313
4314         if (p_link->min_pf_rate)
4315                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4316                                                  p_link->min_pf_rate);
4317
4318         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4319                     sizeof(*p_hwfn->qm_info.wfq_data) *
4320                     p_hwfn->qm_info.num_vports);
4321 }
4322
4323 int ecore_device_num_engines(struct ecore_dev *p_dev)
4324 {
4325         return ECORE_IS_BB(p_dev) ? 2 : 1;
4326 }
4327
4328 int ecore_device_num_ports(struct ecore_dev *p_dev)
4329 {
4330         /* in CMT always only one port */
4331         if (p_dev->num_hwfns > 1)
4332                 return 1;
4333
4334         return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
4335 }
4336
4337 void ecore_set_fw_mac_addr(__le16 *fw_msb,
4338                           __le16 *fw_mid,
4339                           __le16 *fw_lsb,
4340                           u8 *mac)
4341 {
4342         ((u8 *)fw_msb)[0] = mac[1];
4343         ((u8 *)fw_msb)[1] = mac[0];
4344         ((u8 *)fw_mid)[0] = mac[3];
4345         ((u8 *)fw_mid)[1] = mac[2];
4346         ((u8 *)fw_lsb)[0] = mac[5];
4347         ((u8 *)fw_lsb)[1] = mac[4];
4348 }