1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
9 #include "ecore_gtt_reg_addr.h"
11 #include "ecore_chain.h"
12 #include "ecore_status.h"
14 #include "ecore_rt_defs.h"
15 #include "ecore_init_ops.h"
16 #include "ecore_int.h"
17 #include "ecore_cxt.h"
18 #include "ecore_spq.h"
19 #include "ecore_init_fw_funcs.h"
20 #include "ecore_sp_commands.h"
21 #include "ecore_dev_api.h"
22 #include "ecore_sriov.h"
24 #include "ecore_mcp.h"
25 #include "ecore_hw_defs.h"
26 #include "mcp_public.h"
27 #include "ecore_iro.h"
29 #include "ecore_dcbx.h"
32 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
33 * registers involved are not split and thus configuration is a race where
34 * some of the PFs configuration might be lost.
35 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
36 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
37 * there's more than a single compiled ecore component in system].
39 static osal_spinlock_t qm_lock;
40 static u32 qm_lock_ref_cnt;
42 /******************** Doorbell Recovery *******************/
43 /* The doorbell recovery mechanism consists of a list of entries which represent
44 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
45 * entity needs to register with the mechanism and provide the parameters
46 * describing it's doorbell, including a location where last used doorbell data
47 * can be found. The doorbell execute function will traverse the list and
48 * doorbell all of the registered entries.
50 struct ecore_db_recovery_entry {
51 osal_list_entry_t list_entry;
52 void OSAL_IOMEM *db_addr;
54 enum ecore_db_rec_width db_width;
55 enum ecore_db_rec_space db_space;
59 /* display a single doorbell recovery entry */
60 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
61 struct ecore_db_recovery_entry *db_entry,
64 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
65 action, db_entry, db_entry->db_addr, db_entry->db_data,
66 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
67 db_entry->db_space == DB_REC_USER ? "user" : "kernel",
71 /* doorbell address sanity (address within doorbell bar range) */
72 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
75 /* make sure doorbell address is within the doorbell bar */
76 if (db_addr < p_dev->doorbells || (u8 *)db_addr >
77 (u8 *)p_dev->doorbells + p_dev->db_size) {
79 "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
80 db_addr, p_dev->doorbells,
81 (u8 *)p_dev->doorbells + p_dev->db_size);
85 /* make sure doorbell data pointer is not null */
87 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
94 /* find hwfn according to the doorbell address */
95 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
96 void OSAL_IOMEM *db_addr)
98 struct ecore_hwfn *p_hwfn;
100 /* In CMT doorbell bar is split down the middle between engine 0 and
103 if (ECORE_IS_CMT(p_dev))
104 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
105 &p_dev->hwfns[0] : &p_dev->hwfns[1];
107 p_hwfn = ECORE_LEADING_HWFN(p_dev);
112 /* add a new entry to the doorbell recovery mechanism */
113 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
114 void OSAL_IOMEM *db_addr,
116 enum ecore_db_rec_width db_width,
117 enum ecore_db_rec_space db_space)
119 struct ecore_db_recovery_entry *db_entry;
120 struct ecore_hwfn *p_hwfn;
122 /* shortcircuit VFs, for now */
124 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
125 return ECORE_SUCCESS;
128 /* sanitize doorbell address */
129 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
132 /* obtain hwfn from doorbell address */
133 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
136 db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
138 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
143 db_entry->db_addr = db_addr;
144 db_entry->db_data = db_data;
145 db_entry->db_width = db_width;
146 db_entry->db_space = db_space;
147 db_entry->hwfn_idx = p_hwfn->my_id;
150 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
152 /* protect the list */
153 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
154 OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
155 &p_hwfn->db_recovery_info.list);
156 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
158 return ECORE_SUCCESS;
161 /* remove an entry from the doorbell recovery mechanism */
162 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
163 void OSAL_IOMEM *db_addr,
166 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
167 enum _ecore_status_t rc = ECORE_INVAL;
168 struct ecore_hwfn *p_hwfn;
170 /* shortcircuit VFs, for now */
172 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
173 return ECORE_SUCCESS;
176 /* sanitize doorbell address */
177 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
180 /* obtain hwfn from doorbell address */
181 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
183 /* protect the list */
184 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
185 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
186 &p_hwfn->db_recovery_info.list,
188 struct ecore_db_recovery_entry) {
189 /* search according to db_data addr since db_addr is not unique
192 if (db_entry->db_data == db_data) {
193 ecore_db_recovery_dp_entry(p_hwfn, db_entry,
195 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
196 &p_hwfn->db_recovery_info.list);
202 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
204 if (rc == ECORE_INVAL)
206 DP_NOTICE(p_hwfn, false,
207 "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
210 OSAL_FREE(p_dev, db_entry);
215 /* initialize the doorbell recovery mechanism */
216 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
218 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
220 /* make sure db_size was set in p_dev */
221 if (!p_hwfn->p_dev->db_size) {
222 DP_ERR(p_hwfn->p_dev, "db_size not set\n");
226 OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
227 #ifdef CONFIG_ECORE_LOCK_ALLOC
228 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock))
231 OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
232 p_hwfn->db_recovery_info.db_recovery_counter = 0;
234 return ECORE_SUCCESS;
237 /* destroy the doorbell recovery mechanism */
238 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
240 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
242 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
243 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
244 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
245 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
246 db_entry = OSAL_LIST_FIRST_ENTRY(
247 &p_hwfn->db_recovery_info.list,
248 struct ecore_db_recovery_entry,
250 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
251 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
252 &p_hwfn->db_recovery_info.list);
253 OSAL_FREE(p_hwfn->p_dev, db_entry);
256 #ifdef CONFIG_ECORE_LOCK_ALLOC
257 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
259 p_hwfn->db_recovery_info.db_recovery_counter = 0;
262 /* print the content of the doorbell recovery mechanism */
263 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
265 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
267 DP_NOTICE(p_hwfn, false,
268 "Dispalying doorbell recovery database. Counter was %d\n",
269 p_hwfn->db_recovery_info.db_recovery_counter);
271 /* protect the list */
272 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
273 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
274 &p_hwfn->db_recovery_info.list,
276 struct ecore_db_recovery_entry) {
277 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
280 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
283 /* ring the doorbell of a single doorbell recovery entry */
284 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
285 struct ecore_db_recovery_entry *db_entry,
286 enum ecore_db_rec_exec db_exec)
288 /* Print according to width */
289 if (db_entry->db_width == DB_REC_WIDTH_32B)
290 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
291 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
292 db_entry->db_addr, *(u32 *)db_entry->db_data);
294 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n",
295 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
297 *(unsigned long *)(db_entry->db_data));
300 if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
304 /* Flush the write combined buffer. Since there are multiple doorbelling
305 * entities using the same address, if we don't flush, a transaction
308 OSAL_WMB(p_hwfn->p_dev);
310 /* Ring the doorbell */
311 if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
312 if (db_entry->db_width == DB_REC_WIDTH_32B)
313 DIRECT_REG_WR(p_hwfn, db_entry->db_addr,
314 *(u32 *)(db_entry->db_data));
316 DIRECT_REG_WR64(p_hwfn, db_entry->db_addr,
317 *(u64 *)(db_entry->db_data));
320 /* Flush the write combined buffer. Next doorbell may come from a
321 * different entity to the same address...
323 OSAL_WMB(p_hwfn->p_dev);
326 /* traverse the doorbell recovery entry list and ring all the doorbells */
327 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
328 enum ecore_db_rec_exec db_exec)
330 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
332 if (db_exec != DB_REC_ONCE) {
333 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
334 p_hwfn->db_recovery_info.db_recovery_counter);
336 /* track amount of times recovery was executed */
337 p_hwfn->db_recovery_info.db_recovery_counter++;
340 /* protect the list */
341 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
342 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
343 &p_hwfn->db_recovery_info.list,
345 struct ecore_db_recovery_entry) {
346 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
347 if (db_exec == DB_REC_ONCE)
351 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
353 /******************** Doorbell Recovery end ****************/
356 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to
357 * load the driver. The number was
362 #define ECORE_MIN_PWM_REGION (ECORE_WID_SIZE * ECORE_MIN_DPIS)
364 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
365 struct ecore_ptt *p_ptt,
368 u32 bar_reg = (bar_id == BAR_ID_0 ?
369 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
372 if (IS_VF(p_hwfn->p_dev))
373 return ecore_vf_hw_bar_size(p_hwfn, bar_id);
375 val = ecore_rd(p_hwfn, p_ptt, bar_reg);
377 return 1 << (val + 15);
379 /* The above registers were updated in the past only in CMT mode. Since
380 * they were found to be useful MFW started updating them from 8.7.7.0.
381 * In older MFW versions they are set to 0 which means disabled.
383 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
385 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
386 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
389 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
396 void ecore_init_dp(struct ecore_dev *p_dev,
397 u32 dp_module, u8 dp_level, void *dp_ctx)
401 p_dev->dp_level = dp_level;
402 p_dev->dp_module = dp_module;
403 p_dev->dp_ctx = dp_ctx;
404 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
405 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
407 p_hwfn->dp_level = dp_level;
408 p_hwfn->dp_module = dp_module;
409 p_hwfn->dp_ctx = dp_ctx;
413 enum _ecore_status_t ecore_init_struct(struct ecore_dev *p_dev)
417 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
418 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
420 p_hwfn->p_dev = p_dev;
422 p_hwfn->b_active = false;
424 #ifdef CONFIG_ECORE_LOCK_ALLOC
425 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->dmae_info.lock))
428 OSAL_SPIN_LOCK_INIT(&p_hwfn->dmae_info.lock);
431 /* hwfn 0 is always active */
432 p_dev->hwfns[0].b_active = true;
434 /* set the default cache alignment to 128 (may be overridden later) */
435 p_dev->cache_shift = 7;
436 return ECORE_SUCCESS;
437 #ifdef CONFIG_ECORE_LOCK_ALLOC
440 struct ecore_hwfn *p_hwfn = OSAL_NULL;
442 p_hwfn = &p_dev->hwfns[i];
443 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
449 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
451 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
453 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
454 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
455 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
456 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
459 static void ecore_dbg_user_data_free(struct ecore_hwfn *p_hwfn)
461 OSAL_FREE(p_hwfn->p_dev, p_hwfn->dbg_user_info);
462 p_hwfn->dbg_user_info = OSAL_NULL;
465 void ecore_resc_free(struct ecore_dev *p_dev)
470 for_each_hwfn(p_dev, i)
471 ecore_l2_free(&p_dev->hwfns[i]);
475 OSAL_FREE(p_dev, p_dev->fw_data);
477 OSAL_FREE(p_dev, p_dev->reset_stats);
479 for_each_hwfn(p_dev, i) {
480 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
482 ecore_cxt_mngr_free(p_hwfn);
483 ecore_qm_info_free(p_hwfn);
484 ecore_spq_free(p_hwfn);
485 ecore_eq_free(p_hwfn);
486 ecore_consq_free(p_hwfn);
487 ecore_int_free(p_hwfn);
488 ecore_iov_free(p_hwfn);
489 ecore_l2_free(p_hwfn);
490 ecore_dmae_info_free(p_hwfn);
491 ecore_dcbx_info_free(p_hwfn);
492 ecore_dbg_user_data_free(p_hwfn);
493 /* @@@TBD Flush work-queue ? */
495 /* destroy doorbell recovery mechanism */
496 ecore_db_recovery_teardown(p_hwfn);
500 /******************** QM initialization *******************/
502 /* bitmaps for indicating active traffic classes.
503 * Special case for Arrowhead 4 port
505 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
506 #define ACTIVE_TCS_BMAP 0x9f
507 /* 0..3 actually used, OOO and high priority stuff all use 3 */
508 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
510 /* determines the physical queue flags for a given PF. */
511 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
519 if (IS_ECORE_SRIOV(p_hwfn->p_dev))
520 flags |= PQ_FLAGS_VFS;
521 if (IS_ECORE_PACING(p_hwfn))
522 flags |= PQ_FLAGS_RLS;
525 switch (p_hwfn->hw_info.personality) {
527 if (!IS_ECORE_PACING(p_hwfn))
528 flags |= PQ_FLAGS_MCOS;
531 flags |= PQ_FLAGS_OFLD;
533 case ECORE_PCI_ISCSI:
534 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
536 case ECORE_PCI_ETH_ROCE:
537 flags |= PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
538 if (!IS_ECORE_PACING(p_hwfn))
539 flags |= PQ_FLAGS_MCOS;
541 case ECORE_PCI_ETH_IWARP:
542 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
543 if (!IS_ECORE_PACING(p_hwfn))
544 flags |= PQ_FLAGS_MCOS;
547 DP_ERR(p_hwfn, "unknown personality %d\n",
548 p_hwfn->hw_info.personality);
554 /* Getters for resource amounts necessary for qm initialization */
555 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
557 return p_hwfn->hw_info.num_hw_tc;
560 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
562 return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
563 p_hwfn->p_dev->p_iov_info->total_vfs : 0;
566 #define NUM_DEFAULT_RLS 1
568 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
570 u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
573 /* num RLs can't exceed resource amount of rls or vports or the
576 num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
577 (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
579 /* make sure after we reserve the default and VF rls we'll have
582 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
583 DP_NOTICE(p_hwfn, false,
584 "no rate limiters left for PF rate limiting"
585 " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
589 /* subtract rls necessary for VFs and one default one for the PF */
590 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
595 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
597 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
599 /* all pqs share the same vport (hence the 1 below), except for vfs
602 return (!!(PQ_FLAGS_RLS & pq_flags)) *
603 ecore_init_qm_get_num_pf_rls(p_hwfn) +
604 (!!(PQ_FLAGS_VFS & pq_flags)) *
605 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
608 /* calc amount of PQs according to the requested flags */
609 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
611 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
613 return (!!(PQ_FLAGS_RLS & pq_flags)) *
614 ecore_init_qm_get_num_pf_rls(p_hwfn) +
615 (!!(PQ_FLAGS_MCOS & pq_flags)) *
616 ecore_init_qm_get_num_tcs(p_hwfn) +
617 (!!(PQ_FLAGS_LB & pq_flags)) +
618 (!!(PQ_FLAGS_OOO & pq_flags)) +
619 (!!(PQ_FLAGS_ACK & pq_flags)) +
620 (!!(PQ_FLAGS_OFLD & pq_flags)) +
621 (!!(PQ_FLAGS_VFS & pq_flags)) *
622 ecore_init_qm_get_num_vfs(p_hwfn);
625 /* initialize the top level QM params */
626 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
628 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
631 /* pq and vport bases for this PF */
632 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
633 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
635 /* rate limiting and weighted fair queueing are always enabled */
636 qm_info->vport_rl_en = 1;
637 qm_info->vport_wfq_en = 1;
639 /* TC config is different for AH 4 port */
640 four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;
642 /* in AH 4 port we have fewer TCs per port */
643 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
646 /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
649 if (!qm_info->ooo_tc)
650 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
654 /* initialize qm vport params */
655 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
657 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
660 /* all vports participate in weighted fair queueing */
661 for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
662 qm_info->qm_vport_params[i].vport_wfq = 1;
665 /* initialize qm port params */
666 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
668 /* Initialize qm port parameters */
669 u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
671 /* indicate how ooo and high pri traffic is dealt with */
672 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
673 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
675 for (i = 0; i < num_ports; i++) {
676 struct init_qm_port_params *p_qm_port =
677 &p_hwfn->qm_info.qm_port_params[i];
679 p_qm_port->active = 1;
680 p_qm_port->active_phys_tcs = active_phys_tcs;
681 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES_E4 / num_ports;
682 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
686 /* Reset the params which must be reset for qm init. QM init may be called as
687 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
688 * params may be affected by the init but would simply recalculate to the same
689 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
690 * affected as these amounts stay the same.
692 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
694 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
696 qm_info->num_pqs = 0;
697 qm_info->num_vports = 0;
698 qm_info->num_pf_rls = 0;
699 qm_info->num_vf_pqs = 0;
700 qm_info->first_vf_pq = 0;
701 qm_info->first_mcos_pq = 0;
702 qm_info->first_rl_pq = 0;
705 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
707 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
709 qm_info->num_vports++;
711 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
713 "vport overflow! qm_info->num_vports %d,"
714 " qm_init_get_num_vports() %d\n",
716 ecore_init_qm_get_num_vports(p_hwfn));
719 /* initialize a single pq and manage qm_info resources accounting.
720 * The pq_init_flags param determines whether the PQ is rate limited
722 * and whether a new vport is allocated to the pq or not (i.e. vport will be
726 /* flags for pq init */
727 #define PQ_INIT_SHARE_VPORT (1 << 0)
728 #define PQ_INIT_PF_RL (1 << 1)
729 #define PQ_INIT_VF_RL (1 << 2)
731 /* defines for pq init */
732 #define PQ_INIT_DEFAULT_WRR_GROUP 1
733 #define PQ_INIT_DEFAULT_TC 0
734 #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc)
736 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
737 struct ecore_qm_info *qm_info,
738 u8 tc, u32 pq_init_flags)
740 u16 pq_idx = qm_info->num_pqs, max_pq =
741 ecore_init_qm_get_num_pqs(p_hwfn);
745 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
748 qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
749 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
751 qm_info->qm_pq_params[pq_idx].tc_id = tc;
752 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
753 qm_info->qm_pq_params[pq_idx].rl_valid =
754 (pq_init_flags & PQ_INIT_PF_RL ||
755 pq_init_flags & PQ_INIT_VF_RL);
757 /* qm params accounting */
759 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
760 qm_info->num_vports++;
762 if (pq_init_flags & PQ_INIT_PF_RL)
763 qm_info->num_pf_rls++;
765 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
767 "vport overflow! qm_info->num_vports %d,"
768 " qm_init_get_num_vports() %d\n",
770 ecore_init_qm_get_num_vports(p_hwfn));
772 if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
773 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
774 " qm_init_get_num_pf_rls() %d\n",
776 ecore_init_qm_get_num_pf_rls(p_hwfn));
779 /* get pq index according to PQ_FLAGS */
780 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
783 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
785 /* Can't have multiple flags set here */
786 if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
787 sizeof(pq_flags)) > 1)
792 return &qm_info->first_rl_pq;
794 return &qm_info->first_mcos_pq;
796 return &qm_info->pure_lb_pq;
798 return &qm_info->ooo_pq;
800 return &qm_info->pure_ack_pq;
802 return &qm_info->offload_pq;
804 return &qm_info->first_vf_pq;
810 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
814 /* save pq index in qm info */
815 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
816 u32 pq_flags, u16 pq_val)
818 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
820 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
823 /* get tx pq index, with the PQ TX base already set (ready for context init) */
824 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
826 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
828 return *base_pq_idx + CM_TX_PQ_BASE;
831 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
833 u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
836 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
838 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
841 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
843 u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
846 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
848 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
851 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
853 u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
856 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
858 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
861 u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
863 u16 start_pq, pq, qm_pq_idx;
865 pq = ecore_get_cm_pq_idx_rl(p_hwfn, rl);
866 start_pq = p_hwfn->qm_info.start_pq;
867 qm_pq_idx = pq - start_pq - CM_TX_PQ_BASE;
869 if (qm_pq_idx > p_hwfn->qm_info.num_pqs) {
871 "qm_pq_idx %d must be smaller than %d\n",
872 qm_pq_idx, p_hwfn->qm_info.num_pqs);
875 return p_hwfn->qm_info.qm_pq_params[qm_pq_idx].vport_id;
878 /* Functions for creating specific types of pqs */
879 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
881 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
883 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
886 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
887 ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
890 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
892 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
894 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
897 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
898 ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
901 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
903 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
905 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
908 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
909 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
912 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
914 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
916 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
919 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
920 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
923 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
925 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
928 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
931 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
932 for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
933 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
936 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
938 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
939 u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
941 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
944 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
946 qm_info->num_vf_pqs = num_vfs;
947 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
948 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
952 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
954 u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
955 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
957 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
960 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
961 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
962 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
966 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
968 /* rate limited pqs, must come first (FW assumption) */
969 ecore_init_qm_rl_pqs(p_hwfn);
971 /* pqs for multi cos */
972 ecore_init_qm_mcos_pqs(p_hwfn);
974 /* pure loopback pq */
975 ecore_init_qm_lb_pq(p_hwfn);
977 /* out of order pq */
978 ecore_init_qm_ooo_pq(p_hwfn);
981 ecore_init_qm_pure_ack_pq(p_hwfn);
983 /* pq for offloaded protocol */
984 ecore_init_qm_offload_pq(p_hwfn);
986 /* done sharing vports */
987 ecore_init_qm_advance_vport(p_hwfn);
990 ecore_init_qm_vf_pqs(p_hwfn);
993 /* compare values of getters against resources amounts */
994 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
996 if (ecore_init_qm_get_num_vports(p_hwfn) >
997 RESC_NUM(p_hwfn, ECORE_VPORT)) {
998 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
1002 if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
1003 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
1007 return ECORE_SUCCESS;
1011 * Function for verbose printing of the qm initialization results
1013 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
1015 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1016 struct init_qm_vport_params *vport;
1017 struct init_qm_port_params *port;
1018 struct init_qm_pq_params *pq;
1021 /* top level params */
1022 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1023 "qm init top level params: start_pq %d, start_vport %d,"
1024 " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
1025 qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
1026 qm_info->offload_pq, qm_info->pure_ack_pq);
1027 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1028 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
1029 " num_vports %d, max_phys_tcs_per_port %d\n",
1030 qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
1031 qm_info->num_vf_pqs, qm_info->num_vports,
1032 qm_info->max_phys_tcs_per_port);
1033 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1034 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
1035 " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
1036 qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
1037 qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
1038 qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
1041 for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
1042 port = &qm_info->qm_port_params[i];
1043 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1044 "port idx %d, active %d, active_phys_tcs %d,"
1045 " num_pbf_cmd_lines %d, num_btb_blocks %d,"
1047 i, port->active, port->active_phys_tcs,
1048 port->num_pbf_cmd_lines, port->num_btb_blocks,
1053 for (i = 0; i < qm_info->num_vports; i++) {
1054 vport = &qm_info->qm_vport_params[i];
1055 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1056 "vport idx %d, vport_rl %d, wfq %d,"
1057 " first_tx_pq_id [ ",
1058 qm_info->start_vport + i, vport->vport_rl,
1060 for (tc = 0; tc < NUM_OF_TCS; tc++)
1061 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
1062 vport->first_tx_pq_id[tc]);
1063 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
1067 for (i = 0; i < qm_info->num_pqs; i++) {
1068 pq = &qm_info->qm_pq_params[i];
1069 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1070 "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
1071 qm_info->start_pq + i, pq->port_id, pq->vport_id,
1072 pq->tc_id, pq->wrr_group, pq->rl_valid);
1076 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
1078 /* reset params required for init run */
1079 ecore_init_qm_reset_params(p_hwfn);
1081 /* init QM top level params */
1082 ecore_init_qm_params(p_hwfn);
1084 /* init QM port params */
1085 ecore_init_qm_port_params(p_hwfn);
1087 /* init QM vport params */
1088 ecore_init_qm_vport_params(p_hwfn);
1090 /* init QM physical queue params */
1091 ecore_init_qm_pq_params(p_hwfn);
1093 /* display all that init */
1094 ecore_dp_init_qm_params(p_hwfn);
1097 /* This function reconfigures the QM pf on the fly.
1098 * For this purpose we:
1099 * 1. reconfigure the QM database
1100 * 2. set new values to runtime array
1101 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
1102 * 4. activate init tool in QM_PF stage
1103 * 5. send an sdm_qm_cmd through rbc interface to release the QM
1105 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
1106 struct ecore_ptt *p_ptt)
1108 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1110 enum _ecore_status_t rc;
1112 /* initialize ecore's qm data structure */
1113 ecore_init_qm_info(p_hwfn);
1115 /* stop PF's qm queues */
1116 OSAL_SPIN_LOCK(&qm_lock);
1117 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
1118 qm_info->start_pq, qm_info->num_pqs);
1119 OSAL_SPIN_UNLOCK(&qm_lock);
1123 /* clear the QM_PF runtime phase leftovers from previous init */
1124 ecore_init_clear_rt_data(p_hwfn);
1126 /* prepare QM portion of runtime array */
1127 ecore_qm_init_pf(p_hwfn, p_ptt, false);
1129 /* activate init tool on runtime array */
1130 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
1131 p_hwfn->hw_info.hw_mode);
1132 if (rc != ECORE_SUCCESS)
1135 /* start PF's qm queues */
1136 OSAL_SPIN_LOCK(&qm_lock);
1137 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
1138 qm_info->start_pq, qm_info->num_pqs);
1139 OSAL_SPIN_UNLOCK(&qm_lock);
1143 return ECORE_SUCCESS;
1146 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
1148 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1149 enum _ecore_status_t rc;
1151 rc = ecore_init_qm_sanity(p_hwfn);
1152 if (rc != ECORE_SUCCESS)
1155 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1156 sizeof(struct init_qm_pq_params) *
1157 ecore_init_qm_get_num_pqs(p_hwfn));
1158 if (!qm_info->qm_pq_params)
1161 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1162 sizeof(struct init_qm_vport_params) *
1163 ecore_init_qm_get_num_vports(p_hwfn));
1164 if (!qm_info->qm_vport_params)
1167 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1168 sizeof(struct init_qm_port_params) *
1169 p_hwfn->p_dev->num_ports_in_engine);
1170 if (!qm_info->qm_port_params)
1173 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1174 sizeof(struct ecore_wfq_data) *
1175 ecore_init_qm_get_num_vports(p_hwfn));
1176 if (!qm_info->wfq_data)
1179 return ECORE_SUCCESS;
1182 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
1183 ecore_qm_info_free(p_hwfn);
1186 /******************** End QM initialization ***************/
1188 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
1190 enum _ecore_status_t rc = ECORE_SUCCESS;
1194 for_each_hwfn(p_dev, i) {
1195 rc = ecore_l2_alloc(&p_dev->hwfns[i]);
1196 if (rc != ECORE_SUCCESS)
1202 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1203 sizeof(*p_dev->fw_data));
1204 if (!p_dev->fw_data)
1207 for_each_hwfn(p_dev, i) {
1208 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1209 u32 n_eqes, num_cons;
1211 /* initialize the doorbell recovery mechanism */
1212 rc = ecore_db_recovery_setup(p_hwfn);
1216 /* First allocate the context manager structure */
1217 rc = ecore_cxt_mngr_alloc(p_hwfn);
1221 /* Set the HW cid/tid numbers (in the context manager)
1222 * Must be done prior to any further computations.
1224 rc = ecore_cxt_set_pf_params(p_hwfn);
1228 rc = ecore_alloc_qm_data(p_hwfn);
1233 ecore_init_qm_info(p_hwfn);
1235 /* Compute the ILT client partition */
1236 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
1240 /* CID map / ILT shadow table / T2
1241 * The talbes sizes are determined by the computations above
1243 rc = ecore_cxt_tables_alloc(p_hwfn);
1247 /* SPQ, must follow ILT because initializes SPQ context */
1248 rc = ecore_spq_alloc(p_hwfn);
1252 /* SP status block allocation */
1253 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
1256 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1260 rc = ecore_iov_alloc(p_hwfn);
1265 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
1266 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
1267 /* Calculate the EQ size
1268 * ---------------------
1269 * Each ICID may generate up to one event at a time i.e.
1270 * the event must be handled/cleared before a new one
1271 * can be generated. We calculate the sum of events per
1272 * protocol and create an EQ deep enough to handle the
1274 * - Core - according to SPQ.
1275 * - RoCE - per QP there are a couple of ICIDs, one
1276 * responder and one requester, each can
1277 * generate an EQE => n_eqes_qp = 2 * n_qp.
1278 * Each CQ can generate an EQE. There are 2 CQs
1279 * per QP => n_eqes_cq = 2 * n_qp.
1280 * Hence the RoCE total is 4 * n_qp or
1282 * - ENet - There can be up to two events per VF. One
1283 * for VF-PF channel and another for VF FLR
1284 * initial cleanup. The number of VFs is
1285 * bounded by MAX_NUM_VFS_BB, and is much
1286 * smaller than RoCE's so we avoid exact
1289 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
1291 ecore_cxt_get_proto_cid_count(
1297 num_cons = ecore_cxt_get_proto_cid_count(
1302 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1303 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
1305 ecore_cxt_get_proto_cid_count(p_hwfn,
1308 n_eqes += 2 * num_cons;
1311 if (n_eqes > 0xFFFF) {
1312 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
1313 "The maximum of a u16 chain is 0x%x\n",
1318 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
1322 rc = ecore_consq_alloc(p_hwfn);
1326 rc = ecore_l2_alloc(p_hwfn);
1327 if (rc != ECORE_SUCCESS)
1330 /* DMA info initialization */
1331 rc = ecore_dmae_info_alloc(p_hwfn);
1333 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for dmae_info structure\n");
1337 /* DCBX initialization */
1338 rc = ecore_dcbx_info_alloc(p_hwfn);
1340 DP_NOTICE(p_hwfn, false,
1341 "Failed to allocate memory for dcbx structure\n");
1345 rc = OSAL_DBG_ALLOC_USER_DATA(p_hwfn, &p_hwfn->dbg_user_info);
1347 DP_NOTICE(p_hwfn, false,
1348 "Failed to allocate dbg user info structure\n");
1353 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1354 sizeof(*p_dev->reset_stats));
1355 if (!p_dev->reset_stats) {
1356 DP_NOTICE(p_dev, false, "Failed to allocate reset statistics\n");
1360 return ECORE_SUCCESS;
1365 ecore_resc_free(p_dev);
1369 void ecore_resc_setup(struct ecore_dev *p_dev)
1374 for_each_hwfn(p_dev, i)
1375 ecore_l2_setup(&p_dev->hwfns[i]);
1379 for_each_hwfn(p_dev, i) {
1380 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1382 ecore_cxt_mngr_setup(p_hwfn);
1383 ecore_spq_setup(p_hwfn);
1384 ecore_eq_setup(p_hwfn);
1385 ecore_consq_setup(p_hwfn);
1387 /* Read shadow of current MFW mailbox */
1388 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1389 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1390 p_hwfn->mcp_info->mfw_mb_cur,
1391 p_hwfn->mcp_info->mfw_mb_length);
1393 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1395 ecore_l2_setup(p_hwfn);
1396 ecore_iov_setup(p_hwfn);
1400 #define FINAL_CLEANUP_POLL_CNT (100)
1401 #define FINAL_CLEANUP_POLL_TIME (10)
1402 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1403 struct ecore_ptt *p_ptt,
1406 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1407 enum _ecore_status_t rc = ECORE_TIMEOUT;
1410 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1411 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1412 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1413 return ECORE_SUCCESS;
1417 addr = GTT_BAR0_MAP_REG_USDM_RAM +
1418 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1423 command |= X_FINAL_CLEANUP_AGG_INT <<
1424 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1425 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1426 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1427 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1429 /* Make sure notification is not set before initiating final cleanup */
1431 if (REG_RD(p_hwfn, addr)) {
1432 DP_NOTICE(p_hwfn, false,
1433 "Unexpected; Found final cleanup notification");
1434 DP_NOTICE(p_hwfn, false,
1435 " before initiating final cleanup\n");
1436 REG_WR(p_hwfn, addr, 0);
1439 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1440 "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1443 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1445 /* Poll until completion */
1446 while (!REG_RD(p_hwfn, addr) && count--)
1447 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1449 if (REG_RD(p_hwfn, addr))
1452 DP_NOTICE(p_hwfn, true,
1453 "Failed to receive FW final cleanup notification\n");
1455 /* Cleanup afterwards */
1456 REG_WR(p_hwfn, addr, 0);
1461 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1465 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1466 hw_mode |= 1 << MODE_BB;
1467 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1468 hw_mode |= 1 << MODE_K2;
1470 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1471 p_hwfn->p_dev->type);
1475 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1476 switch (p_hwfn->p_dev->num_ports_in_engine) {
1478 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1481 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1484 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1487 DP_NOTICE(p_hwfn, true,
1488 "num_ports_in_engine = %d not supported\n",
1489 p_hwfn->p_dev->num_ports_in_engine);
1493 if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS,
1494 &p_hwfn->p_dev->mf_bits))
1495 hw_mode |= 1 << MODE_MF_SD;
1497 hw_mode |= 1 << MODE_MF_SI;
1500 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1501 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1502 hw_mode |= 1 << MODE_FPGA;
1504 if (p_hwfn->p_dev->b_is_emul_full)
1505 hw_mode |= 1 << MODE_EMUL_FULL;
1507 hw_mode |= 1 << MODE_EMUL_REDUCED;
1511 hw_mode |= 1 << MODE_ASIC;
1513 if (ECORE_IS_CMT(p_hwfn->p_dev))
1514 hw_mode |= 1 << MODE_100G;
1516 p_hwfn->hw_info.hw_mode = hw_mode;
1518 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1519 "Configuring function for hw_mode: 0x%08x\n",
1520 p_hwfn->hw_info.hw_mode);
1522 return ECORE_SUCCESS;
1526 /* MFW-replacement initializations for non-ASIC */
1527 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1528 struct ecore_ptt *p_ptt)
1530 struct ecore_dev *p_dev = p_hwfn->p_dev;
1534 if (CHIP_REV_IS_EMUL(p_dev)) {
1535 if (ECORE_IS_AH(p_dev))
1539 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1541 if (CHIP_REV_IS_EMUL(p_dev) &&
1542 (ECORE_IS_AH(p_dev)))
1543 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1546 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1547 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1548 if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1549 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1551 if (CHIP_REV_IS_EMUL(p_dev)) {
1552 if (ECORE_IS_AH(p_dev)) {
1553 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1554 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1555 (p_dev->num_ports_in_engine >> 1));
1557 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1558 p_dev->num_ports_in_engine == 4 ? 0 : 3);
1563 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1564 for (i = 0; i < 100; i++) {
1566 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1570 DP_NOTICE(p_hwfn, true,
1571 "RBC done failed to complete in PSWRQ2\n");
1573 return ECORE_SUCCESS;
1577 /* Init run time data for all PFs and their VFs on an engine.
1578 * TBD - for VFs - Once we have parent PF info for each VF in
1579 * shmem available as CAU requires knowledge of parent PF for each VF.
1581 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1583 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1586 for_each_hwfn(p_dev, i) {
1587 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1588 struct ecore_igu_info *p_igu_info;
1589 struct ecore_igu_block *p_block;
1590 struct cau_sb_entry sb_entry;
1592 p_igu_info = p_hwfn->hw_info.p_igu_info;
1595 igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1597 p_block = &p_igu_info->entry[igu_sb_id];
1599 if (!p_block->is_pf)
1602 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1603 p_block->function_id, 0, 0);
1604 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1610 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
1611 struct ecore_ptt *p_ptt)
1613 u32 val, wr_mbs, cache_line_size;
1615 val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1628 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1633 cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
1634 switch (cache_line_size) {
1649 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1653 if (wr_mbs < OSAL_CACHE_LINE_SIZE)
1655 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1656 OSAL_CACHE_LINE_SIZE, wr_mbs);
1658 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1660 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1661 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1665 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1666 struct ecore_ptt *p_ptt,
1669 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1670 struct ecore_dev *p_dev = p_hwfn->p_dev;
1671 u8 vf_id, max_num_vfs;
1674 enum _ecore_status_t rc = ECORE_SUCCESS;
1676 ecore_init_cau_rt_data(p_dev);
1678 /* Program GTT windows */
1679 ecore_gtt_init(p_hwfn, p_ptt);
1682 if (CHIP_REV_IS_EMUL(p_dev)) {
1683 rc = ecore_hw_init_chip(p_hwfn, p_ptt);
1684 if (rc != ECORE_SUCCESS)
1689 if (p_hwfn->mcp_info) {
1690 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1691 qm_info->pf_rl_en = 1;
1692 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1693 qm_info->pf_wfq_en = 1;
1696 ecore_qm_common_rt_init(p_hwfn,
1697 p_dev->num_ports_in_engine,
1698 qm_info->max_phys_tcs_per_port,
1699 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1700 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1701 qm_info->qm_port_params);
1703 ecore_cxt_hw_init_common(p_hwfn);
1705 ecore_init_cache_line_size(p_hwfn, p_ptt);
1707 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ECORE_PATH_ID(p_hwfn),
1709 if (rc != ECORE_SUCCESS)
1712 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1713 * need to decide with which value, maybe runtime
1715 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1716 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1718 if (ECORE_IS_BB(p_dev)) {
1719 /* Workaround clears ROCE search for all functions to prevent
1720 * involving non initialized function in processing ROCE packet.
1722 num_pfs = NUM_OF_ENG_PFS(p_dev);
1723 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1724 ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1725 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1726 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1728 /* pretend to original PF */
1729 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1732 /* Workaround for avoiding CCFC execution error when getting packets
1733 * with CRC errors, and allowing instead the invoking of the FW error
1735 * This is not done inside the init tool since it currently can't
1736 * perform a pretending to VFs.
1738 max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1739 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1740 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1741 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1742 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1743 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1744 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1745 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1747 /* pretend to original PF */
1748 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1754 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1755 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1757 #define PMEG_IF_BYTE_COUNT 8
1759 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1760 struct ecore_ptt *p_ptt,
1761 u32 addr, u64 data, u8 reg_type, u8 port)
1763 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1764 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1765 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1766 (8 << PMEG_IF_BYTE_COUNT),
1767 (reg_type << 25) | (addr << 8) | port,
1768 (u32)((data >> 32) & 0xffffffff),
1769 (u32)(data & 0xffffffff));
1771 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1772 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1773 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1774 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1775 (reg_type << 25) | (addr << 8) | port);
1776 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1777 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1778 (data >> 32) & 0xffffffff);
1781 #define XLPORT_MODE_REG (0x20a)
1782 #define XLPORT_MAC_CONTROL (0x210)
1783 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1784 #define XLPORT_ENABLE_REG (0x20b)
1786 #define XLMAC_CTRL (0x600)
1787 #define XLMAC_MODE (0x601)
1788 #define XLMAC_RX_MAX_SIZE (0x608)
1789 #define XLMAC_TX_CTRL (0x604)
1790 #define XLMAC_PAUSE_CTRL (0x60d)
1791 #define XLMAC_PFC_CTRL (0x60e)
1793 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1794 struct ecore_ptt *p_ptt)
1796 u8 loopback = 0, port = p_hwfn->port_id * 2;
1798 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1800 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1801 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1803 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1804 /* XLMAC: SOFT RESET */
1805 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1806 /* XLMAC: Port Speed >= 10Gbps */
1807 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1808 /* XLMAC: Max Size */
1809 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1810 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1811 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1813 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1814 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1815 0x30ffffc000ULL, 0, port);
1816 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1817 port); /* XLMAC: TX_EN, RX_EN */
1818 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1819 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1820 0x1003 | (loopback << 2), 0, port);
1821 /* Enabled Parallel PFC interface */
1822 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1824 /* XLPORT port enable */
1825 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1828 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1829 struct ecore_ptt *p_ptt)
1831 u8 port = p_hwfn->port_id;
1832 u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1834 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1836 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1837 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1839 CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1840 (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1842 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1843 1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1845 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1846 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1848 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1849 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1851 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1852 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1854 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1856 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1858 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1860 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1864 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1865 struct ecore_ptt *p_ptt)
1867 if (ECORE_IS_AH(p_hwfn->p_dev))
1868 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1870 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1873 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1874 struct ecore_ptt *p_ptt, u8 port)
1876 int port_offset = port ? 0x800 : 0;
1877 u32 xmac_rxctrl = 0;
1880 /* FIXME: move to common start */
1881 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1882 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
1884 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1885 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
1887 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1889 /* Set the number of ports on the Warp Core to 10G */
1890 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1892 /* Soft reset of XMAC */
1893 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1894 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1896 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1897 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1899 /* FIXME: move to common end */
1900 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1901 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1903 /* Set Max packet size: initialize XMAC block register for port 0 */
1904 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1906 /* CRC append for Tx packets: init XMAC block register for port 1 */
1907 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1909 /* Enable TX and RX: initialize XMAC block register for port 1 */
1910 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1911 XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1912 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1913 XMAC_REG_RX_CTRL_BB + port_offset);
1914 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1915 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1919 static enum _ecore_status_t
1920 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1921 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1923 u32 dpi_bit_shift, dpi_count, dpi_page_size;
1927 /* Calculate DPI size
1928 * ------------------
1929 * The PWM region contains Doorbell Pages. The first is reserverd for
1930 * the kernel for, e.g, L2. The others are free to be used by non-
1931 * trusted applications, typically from user space. Each page, called a
1932 * doorbell page is sectioned into windows that allow doorbells to be
1933 * issued in parallel by the kernel/application. The size of such a
1934 * window (a.k.a. WID) is 1kB.
1936 * 1kB WID x N WIDS = DPI page size
1937 * DPI page size x N DPIs = PWM region size
1939 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1940 * in order to ensure that two applications won't share the same page.
1941 * It also must contain at least one WID per CPU to allow parallelism.
1942 * It also must be a power of 2, since it is stored as a bit shift.
1944 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1945 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1946 * containing 4 WIDs.
1948 n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus);
1949 dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids);
1950 dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) &
1951 ~(OSAL_PAGE_SIZE - 1);
1952 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1953 dpi_count = pwm_region_size / dpi_page_size;
1955 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1956 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1959 p_hwfn->dpi_size = dpi_page_size;
1960 p_hwfn->dpi_count = dpi_count;
1962 /* Update registers */
1963 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1965 if (dpi_count < min_dpis)
1966 return ECORE_NORESOURCES;
1968 return ECORE_SUCCESS;
1971 enum ECORE_ROCE_EDPM_MODE {
1972 ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1973 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1974 ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1977 static enum _ecore_status_t
1978 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1979 struct ecore_ptt *p_ptt)
1981 u32 pwm_regsize, norm_regsize;
1982 u32 non_pwm_conn, min_addr_reg1;
1983 u32 db_bar_size, n_cpus;
1986 enum _ecore_status_t rc = ECORE_SUCCESS;
1989 db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1990 if (ECORE_IS_CMT(p_hwfn->p_dev))
1993 /* Calculate doorbell regions
1994 * -----------------------------------
1995 * The doorbell BAR is made of two regions. The first is called normal
1996 * region and the second is called PWM region. In the normal region
1997 * each ICID has its own set of addresses so that writing to that
1998 * specific address identifies the ICID. In the Process Window Mode
1999 * region the ICID is given in the data written to the doorbell. The
2000 * above per PF register denotes the offset in the doorbell BAR in which
2001 * the PWM region begins.
2002 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
2003 * non-PWM connection. The calculation below computes the total non-PWM
2004 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
2005 * in units of 4,096 bytes.
2007 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
2008 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
2010 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
2011 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn,
2013 min_addr_reg1 = norm_regsize / 4096;
2014 pwm_regsize = db_bar_size - norm_regsize;
2016 /* Check that the normal and PWM sizes are valid */
2017 if (db_bar_size < norm_regsize) {
2018 DP_ERR(p_hwfn->p_dev,
2019 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
2020 db_bar_size, norm_regsize);
2021 return ECORE_NORESOURCES;
2023 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
2024 DP_ERR(p_hwfn->p_dev,
2025 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
2026 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
2028 return ECORE_NORESOURCES;
2031 /* Calculate number of DPIs */
2032 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
2033 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
2034 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
2035 /* Either EDPM is mandatory, or we are attempting to allocate a
2038 n_cpus = OSAL_NUM_CPUS();
2039 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2042 cond = ((rc != ECORE_SUCCESS) &&
2043 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
2044 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
2045 if (cond || p_hwfn->dcbx_no_edpm) {
2046 /* Either EDPM is disabled from user configuration, or it is
2047 * disabled via DCBx, or it is not mandatory and we failed to
2048 * allocated a WID per CPU.
2051 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2053 /* If we entered this flow due to DCBX then the DPM register is
2054 * already configured.
2059 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
2060 norm_regsize, pwm_regsize);
2062 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
2063 p_hwfn->dpi_size, p_hwfn->dpi_count,
2064 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
2065 "disabled" : "enabled");
2067 /* Check return codes from above calls */
2068 if (rc != ECORE_SUCCESS) {
2070 "Failed to allocate enough DPIs\n");
2071 return ECORE_NORESOURCES;
2075 p_hwfn->dpi_start_offset = norm_regsize;
2077 /* Update registers */
2078 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2079 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
2080 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2081 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2083 return ECORE_SUCCESS;
2086 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
2087 struct ecore_ptt *p_ptt,
2090 u32 ppf_to_eng_sel[NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE];
2092 enum _ecore_status_t rc = ECORE_SUCCESS;
2095 /* In CMT for non-RoCE packets - use connection based classification */
2096 val = ECORE_IS_CMT(p_hwfn->p_dev) ? 0x8 : 0x0;
2097 for (i = 0; i < NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE; i++)
2098 ppf_to_eng_sel[i] = val;
2099 STORE_RT_REG_AGG(p_hwfn, NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET,
2102 /* In CMT the gate should be cleared by the 2nd hwfn */
2103 if (!ECORE_IS_CMT(p_hwfn->p_dev) || !IS_LEAD_HWFN(p_hwfn))
2104 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
2106 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
2108 if (rc != ECORE_SUCCESS)
2111 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2114 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2115 return ECORE_SUCCESS;
2117 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2118 if (ECORE_IS_AH(p_hwfn->p_dev))
2119 return ECORE_SUCCESS;
2120 else if (ECORE_IS_BB(p_hwfn->p_dev))
2121 ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
2122 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2123 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
2124 /* Activate OPTE in CMT */
2127 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
2129 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
2130 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
2131 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
2132 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
2133 ecore_wr(p_hwfn, p_ptt,
2134 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
2135 ecore_wr(p_hwfn, p_ptt,
2136 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
2137 ecore_wr(p_hwfn, p_ptt,
2138 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
2142 ecore_emul_link_init(p_hwfn, p_ptt);
2144 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
2151 static enum _ecore_status_t
2152 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
2153 struct ecore_ptt *p_ptt,
2154 struct ecore_tunnel_info *p_tunn,
2157 enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
2159 u8 rel_pf_id = p_hwfn->rel_pf_id;
2161 enum _ecore_status_t rc = ECORE_SUCCESS;
2165 if (p_hwfn->mcp_info) {
2166 struct ecore_mcp_function_info *p_info;
2168 p_info = &p_hwfn->mcp_info->func_info;
2169 if (p_info->bandwidth_min)
2170 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2172 /* Update rate limit once we'll actually have a link */
2173 p_hwfn->qm_info.pf_rl = 100000;
2175 ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
2177 ecore_int_igu_init_rt(p_hwfn);
2179 /* Set VLAN in NIG if needed */
2180 if (hw_mode & (1 << MODE_MF_SD)) {
2181 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2182 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2183 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2184 p_hwfn->hw_info.ovlan);
2186 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2187 "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
2188 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
2192 /* Enable classification by MAC if needed */
2193 if (hw_mode & (1 << MODE_MF_SI)) {
2194 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2195 "Configuring TAGMAC_CLS_TYPE\n");
2196 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
2200 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
2201 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2202 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
2203 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2204 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
2205 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2207 /* perform debug configuration when chip is out of reset */
2208 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
2210 /* Sanity check before the PF init sequence that uses DMAE */
2211 rc = ecore_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
2215 /* PF Init sequence */
2216 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2220 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2221 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2225 /* Pure runtime initializations - directly to the HW */
2226 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2228 /* PCI relaxed ordering causes a decrease in the performance on some
2229 * systems. Till a root cause is found, disable this attribute in the
2233 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
2235 * DP_NOTICE(p_hwfn, true,
2236 * "Failed to find the PCIe Cap\n");
2239 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
2240 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
2241 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
2244 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2248 /* enable interrupts */
2249 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
2250 if (rc != ECORE_SUCCESS)
2253 /* send function start command */
2254 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2255 allow_npar_tx_switch);
2257 DP_NOTICE(p_hwfn, true,
2258 "Function start ramrod failed\n");
2262 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2263 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2264 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2266 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
2267 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
2269 ecore_wr(p_hwfn, p_ptt,
2270 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2273 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2274 "PRS_REG_SEARCH registers after start PFn\n");
2275 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
2276 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2277 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
2278 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
2279 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2280 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
2281 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
2282 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2283 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
2284 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
2285 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2286 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
2287 prs_reg = ecore_rd(p_hwfn, p_ptt,
2288 PRS_REG_SEARCH_TCP_FIRST_FRAG);
2289 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2290 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
2292 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2293 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2294 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2296 return ECORE_SUCCESS;
2299 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
2300 struct ecore_ptt *p_ptt,
2303 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2305 /* Configure the PF's internal FID_enable for master transactions */
2306 ecore_wr(p_hwfn, p_ptt,
2307 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2309 /* Wait until value is set - try for 1 second every 50us */
2310 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2311 val = ecore_rd(p_hwfn, p_ptt,
2312 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2319 if (val != set_val) {
2320 DP_NOTICE(p_hwfn, true,
2321 "PFID_ENABLE_MASTER wasn't changed after a second\n");
2322 return ECORE_UNKNOWN_ERROR;
2325 return ECORE_SUCCESS;
2328 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
2329 struct ecore_ptt *p_main_ptt)
2331 /* Read shadow of current MFW mailbox */
2332 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
2333 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
2334 p_hwfn->mcp_info->mfw_mb_cur,
2335 p_hwfn->mcp_info->mfw_mb_length);
2338 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
2339 struct ecore_ptt *p_ptt)
2341 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
2342 1 << p_hwfn->abs_pf_id);
2345 static enum _ecore_status_t
2346 ecore_fill_load_req_params(struct ecore_hwfn *p_hwfn,
2347 struct ecore_load_req_params *p_load_req,
2348 struct ecore_drv_load_params *p_drv_load)
2350 /* Make sure that if ecore-client didn't provide inputs, all the
2351 * expected defaults are indeed zero.
2353 OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
2354 OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
2355 OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
2357 OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
2359 if (p_drv_load == OSAL_NULL)
2362 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2363 ECORE_DRV_ROLE_KDUMP :
2365 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2366 p_load_req->override_force_load = p_drv_load->override_force_load;
2368 /* Old MFW versions don't support timeout values other than default and
2369 * none, so these values are replaced according to the fall-back action.
2372 if (p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT ||
2373 p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_NONE ||
2374 (p_hwfn->mcp_info->capabilities &
2375 FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO)) {
2376 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2380 switch (p_drv_load->mfw_timeout_fallback) {
2381 case ECORE_TO_FALLBACK_TO_NONE:
2382 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_NONE;
2384 case ECORE_TO_FALLBACK_TO_DEFAULT:
2385 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_DEFAULT;
2387 case ECORE_TO_FALLBACK_FAIL_LOAD:
2388 DP_NOTICE(p_hwfn, false,
2389 "Received %d as a value for MFW timeout while the MFW supports only default [%d] or none [%d]. Abort.\n",
2390 p_drv_load->mfw_timeout_val,
2391 ECORE_LOAD_REQ_LOCK_TO_DEFAULT,
2392 ECORE_LOAD_REQ_LOCK_TO_NONE);
2393 return ECORE_ABORTED;
2397 "Modified the MFW timeout value from %d to %s [%d] due to lack of MFW support\n",
2398 p_drv_load->mfw_timeout_val,
2399 (p_load_req->timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT) ?
2401 p_load_req->timeout_val);
2403 return ECORE_SUCCESS;
2406 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
2407 struct ecore_hw_init_params *p_params)
2409 if (p_params->p_tunn) {
2410 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2411 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2414 p_hwfn->b_int_enabled = 1;
2416 return ECORE_SUCCESS;
2419 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
2420 struct ecore_hw_init_params *p_params)
2422 struct ecore_load_req_params load_req_params;
2423 u32 load_code, resp, param, drv_mb_param;
2424 bool b_default_mtu = true;
2425 struct ecore_hwfn *p_hwfn;
2426 enum _ecore_status_t rc = ECORE_SUCCESS;
2430 if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) {
2431 DP_NOTICE(p_dev, false,
2432 "MSI mode is not supported for CMT devices\n");
2437 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
2438 if (rc != ECORE_SUCCESS)
2442 for_each_hwfn(p_dev, i) {
2443 p_hwfn = &p_dev->hwfns[i];
2445 /* If management didn't provide a default, set one of our own */
2446 if (!p_hwfn->hw_info.mtu) {
2447 p_hwfn->hw_info.mtu = 1500;
2448 b_default_mtu = false;
2452 ecore_vf_start(p_hwfn, p_params);
2456 rc = ecore_calc_hw_mode(p_hwfn);
2457 if (rc != ECORE_SUCCESS)
2460 if (IS_PF(p_dev) && (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
2462 OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING,
2463 &p_dev->mf_bits))) {
2464 if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
2466 ether_type = ETHER_TYPE_VLAN;
2468 ether_type = ETHER_TYPE_QINQ;
2469 STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
2471 STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
2473 STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
2475 STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
2479 ecore_set_spq_block_timeout(p_hwfn, p_params->spq_timeout_ms);
2481 rc = ecore_fill_load_req_params(p_hwfn, &load_req_params,
2482 p_params->p_drv_load_params);
2483 if (rc != ECORE_SUCCESS)
2486 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
2488 if (rc != ECORE_SUCCESS) {
2489 DP_NOTICE(p_hwfn, false,
2490 "Failed sending a LOAD_REQ command\n");
2494 load_code = load_req_params.load_code;
2495 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2496 "Load request was sent. Load code: 0x%x\n",
2499 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
2502 * When coming back from hiberbate state, the registers from
2503 * which shadow is read initially are not initialized. It turns
2504 * out that these registers get initialized during the call to
2505 * ecore_mcp_load_req request. So we need to reread them here
2506 * to get the proper shadow register value.
2507 * Note: This is a workaround for the missing MFW
2508 * initialization. It may be removed once the implementation
2511 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2513 /* Only relevant for recovery:
2514 * Clear the indication after the LOAD_REQ command is responded
2517 p_dev->recov_in_prog = false;
2519 p_hwfn->first_on_engine = (load_code ==
2520 FW_MSG_CODE_DRV_LOAD_ENGINE);
2522 if (!qm_lock_ref_cnt) {
2523 #ifdef CONFIG_ECORE_LOCK_ALLOC
2524 rc = OSAL_SPIN_LOCK_ALLOC(p_hwfn, &qm_lock);
2526 DP_ERR(p_hwfn, "qm_lock allocation failed\n");
2530 OSAL_SPIN_LOCK_INIT(&qm_lock);
2534 /* Clean up chip from previous driver if such remains exist.
2535 * This is not needed when the PF is the first one on the
2536 * engine, since afterwards we are going to init the FW.
2538 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2539 rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2540 p_hwfn->rel_pf_id, false);
2541 if (rc != ECORE_SUCCESS) {
2542 ecore_hw_err_notify(p_hwfn,
2543 ECORE_HW_ERR_RAMROD_FAIL);
2548 /* Log and clear previous pglue_b errors if such exist */
2549 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt, true);
2551 /* Enable the PF's internal FID_enable in the PXP */
2552 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2554 if (rc != ECORE_SUCCESS)
2557 /* Clear the pglue_b was_error indication.
2558 * In E4 it must be done after the BME and the internal
2559 * FID_enable for the PF are set, since VDMs may cause the
2560 * indication to be set again.
2562 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2564 switch (load_code) {
2565 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2566 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2567 p_hwfn->hw_info.hw_mode);
2568 if (rc != ECORE_SUCCESS)
2571 case FW_MSG_CODE_DRV_LOAD_PORT:
2572 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2573 p_hwfn->hw_info.hw_mode);
2574 if (rc != ECORE_SUCCESS)
2577 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2578 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2580 p_hwfn->hw_info.hw_mode,
2581 p_params->b_hw_start,
2583 p_params->allow_npar_tx_switch);
2586 DP_NOTICE(p_hwfn, false,
2587 "Unexpected load code [0x%08x]", load_code);
2592 if (rc != ECORE_SUCCESS) {
2593 DP_NOTICE(p_hwfn, false,
2594 "init phase failed for loadcode 0x%x (rc %d)\n",
2599 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2600 if (rc != ECORE_SUCCESS) {
2601 DP_NOTICE(p_hwfn, false,
2602 "Sending load done failed, rc = %d\n", rc);
2603 if (rc == ECORE_NOMEM) {
2604 DP_NOTICE(p_hwfn, false,
2605 "Sending load done was failed due to memory allocation failure\n");
2611 /* send DCBX attention request command */
2612 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2613 "sending phony dcbx set command to trigger DCBx attention handling\n");
2614 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2615 DRV_MSG_CODE_SET_DCBX,
2616 1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
2618 if (rc != ECORE_SUCCESS) {
2619 DP_NOTICE(p_hwfn, false,
2620 "Failed to send DCBX attention request\n");
2624 p_hwfn->hw_init_done = true;
2628 /* Get pre-negotiated values for stag, bandwidth etc. */
2629 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2630 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
2631 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
2632 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2633 DRV_MSG_CODE_GET_OEM_UPDATES,
2634 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET,
2636 if (rc != ECORE_SUCCESS)
2637 DP_NOTICE(p_hwfn, false,
2638 "Failed to send GET_OEM_UPDATES attention request\n");
2642 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2643 drv_mb_param = STORM_FW_VERSION;
2644 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2645 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2646 drv_mb_param, &resp, ¶m);
2647 if (rc != ECORE_SUCCESS)
2648 DP_INFO(p_hwfn, "Failed to update firmware version\n");
2650 if (!b_default_mtu) {
2651 rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2652 p_hwfn->hw_info.mtu);
2653 if (rc != ECORE_SUCCESS)
2654 DP_INFO(p_hwfn, "Failed to update default mtu\n");
2657 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2659 ECORE_OV_DRIVER_STATE_DISABLED);
2660 if (rc != ECORE_SUCCESS)
2661 DP_INFO(p_hwfn, "Failed to update driver state\n");
2663 rc = ecore_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
2664 ECORE_OV_ESWITCH_NONE);
2665 if (rc != ECORE_SUCCESS)
2666 DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
2673 #ifdef CONFIG_ECORE_LOCK_ALLOC
2674 if (!qm_lock_ref_cnt)
2675 OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
2678 /* The MFW load lock should be released regardless of success or failure
2679 * of initialization.
2680 * TODO: replace this with an attempt to send cancel_load.
2682 ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2686 #define ECORE_HW_STOP_RETRY_LIMIT (10)
2687 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2688 struct ecore_hwfn *p_hwfn,
2689 struct ecore_ptt *p_ptt)
2694 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2695 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2696 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2698 if ((!ecore_rd(p_hwfn, p_ptt,
2699 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2700 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2703 /* Dependent on number of connection/tasks, possibly
2704 * 1ms sleep is required between polls
2709 if (i < ECORE_HW_STOP_RETRY_LIMIT)
2712 DP_NOTICE(p_hwfn, false,
2713 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
2714 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2715 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2718 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2722 for_each_hwfn(p_dev, j) {
2723 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2724 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2726 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2730 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
2731 struct ecore_ptt *p_ptt,
2732 u32 addr, u32 expected_val)
2734 u32 val = ecore_rd(p_hwfn, p_ptt, addr);
2736 if (val != expected_val) {
2737 DP_NOTICE(p_hwfn, true,
2738 "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
2739 addr, val, expected_val);
2740 return ECORE_UNKNOWN_ERROR;
2743 return ECORE_SUCCESS;
2746 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2748 struct ecore_hwfn *p_hwfn;
2749 struct ecore_ptt *p_ptt;
2750 enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
2753 for_each_hwfn(p_dev, j) {
2754 p_hwfn = &p_dev->hwfns[j];
2755 p_ptt = p_hwfn->p_main_ptt;
2757 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2760 ecore_vf_pf_int_cleanup(p_hwfn);
2761 rc = ecore_vf_pf_reset(p_hwfn);
2762 if (rc != ECORE_SUCCESS) {
2763 DP_NOTICE(p_hwfn, true,
2764 "ecore_vf_pf_reset failed. rc = %d.\n",
2766 rc2 = ECORE_UNKNOWN_ERROR;
2771 /* mark the hw as uninitialized... */
2772 p_hwfn->hw_init_done = false;
2774 /* Send unload command to MCP */
2775 if (!p_dev->recov_in_prog) {
2776 rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
2777 if (rc != ECORE_SUCCESS) {
2778 DP_NOTICE(p_hwfn, false,
2779 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2781 rc2 = ECORE_UNKNOWN_ERROR;
2785 OSAL_DPC_SYNC(p_hwfn);
2787 /* After this point no MFW attentions are expected, e.g. prevent
2788 * race between pf stop and dcbx pf update.
2791 rc = ecore_sp_pf_stop(p_hwfn);
2792 if (rc != ECORE_SUCCESS) {
2793 DP_NOTICE(p_hwfn, false,
2794 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2796 rc2 = ECORE_UNKNOWN_ERROR;
2799 /* perform debug action after PF stop was sent */
2800 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
2802 /* close NIG to BRB gate */
2803 ecore_wr(p_hwfn, p_ptt,
2804 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2807 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2808 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2809 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2810 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2811 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2813 /* @@@TBD - clean transmission queues (5.b) */
2814 /* @@@TBD - clean BTB (5.c) */
2816 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2818 /* @@@TBD - verify DMAE requests are done (8) */
2820 /* Disable Attention Generation */
2821 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2822 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2823 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2824 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2825 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
2826 if (rc != ECORE_SUCCESS) {
2827 DP_NOTICE(p_hwfn, true,
2828 "Failed to return IGU CAM to default\n");
2829 rc2 = ECORE_UNKNOWN_ERROR;
2832 /* Need to wait 1ms to guarantee SBs are cleared */
2835 if (!p_dev->recov_in_prog) {
2836 ecore_verify_reg_val(p_hwfn, p_ptt,
2837 QM_REG_USG_CNT_PF_TX, 0);
2838 ecore_verify_reg_val(p_hwfn, p_ptt,
2839 QM_REG_USG_CNT_PF_OTHER, 0);
2840 /* @@@TBD - assert on incorrect xCFC values (10.b) */
2843 /* Disable PF in HW blocks */
2844 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2845 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2848 #ifdef CONFIG_ECORE_LOCK_ALLOC
2849 if (!qm_lock_ref_cnt)
2850 OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
2853 if (!p_dev->recov_in_prog) {
2854 rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
2855 if (rc == ECORE_NOMEM) {
2856 DP_NOTICE(p_hwfn, false,
2857 "Failed sending an UNLOAD_DONE command due to a memory allocation failure. Resending.\n");
2858 rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
2860 if (rc != ECORE_SUCCESS) {
2861 DP_NOTICE(p_hwfn, false,
2862 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2864 rc2 = ECORE_UNKNOWN_ERROR;
2869 if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
2870 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2871 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2873 /* Clear the PF's internal FID_enable in the PXP.
2874 * In CMT this should only be done for first hw-function, and
2875 * only after all transactions have stopped for all active
2878 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2880 if (rc != ECORE_SUCCESS) {
2881 DP_NOTICE(p_hwfn, true,
2882 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2884 rc2 = ECORE_UNKNOWN_ERROR;
2891 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2895 for_each_hwfn(p_dev, j) {
2896 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2897 struct ecore_ptt *p_ptt;
2900 ecore_vf_pf_int_cleanup(p_hwfn);
2903 p_ptt = ecore_ptt_acquire(p_hwfn);
2907 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2908 "Shutting down the fastpath\n");
2910 ecore_wr(p_hwfn, p_ptt,
2911 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2913 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2914 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2915 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2916 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2917 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2919 /* @@@TBD - clean transmission queues (5.b) */
2920 /* @@@TBD - clean BTB (5.c) */
2922 /* @@@TBD - verify DMAE requests are done (8) */
2924 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2925 /* Need to wait 1ms to guarantee SBs are cleared */
2927 ecore_ptt_release(p_hwfn, p_ptt);
2930 return ECORE_SUCCESS;
2933 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2935 struct ecore_ptt *p_ptt;
2937 if (IS_VF(p_hwfn->p_dev))
2938 return ECORE_SUCCESS;
2940 p_ptt = ecore_ptt_acquire(p_hwfn);
2944 /* If roce info is allocated it means roce is initialized and should
2945 * be enabled in searcher.
2947 if (p_hwfn->p_rdma_info) {
2948 if (p_hwfn->b_rdma_enabled_in_prs)
2949 ecore_wr(p_hwfn, p_ptt,
2950 p_hwfn->rdma_prs_search_reg, 0x1);
2951 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2954 /* Re-open incoming traffic */
2955 ecore_wr(p_hwfn, p_ptt,
2956 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2957 ecore_ptt_release(p_hwfn, p_ptt);
2959 return ECORE_SUCCESS;
2962 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2963 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2965 ecore_ptt_pool_free(p_hwfn);
2966 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2969 /* Setup bar access */
2970 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2972 /* clear indirect access */
2973 if (ECORE_IS_AH(p_hwfn->p_dev)) {
2974 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2975 PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2976 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2977 PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2978 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2979 PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2980 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2981 PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2983 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2984 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2985 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2986 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2987 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2988 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2989 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2990 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2993 /* Clean previous pglue_b errors if such exist */
2994 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2996 /* enable internal target-read */
2997 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2998 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
3001 static void get_function_id(struct ecore_hwfn *p_hwfn)
3004 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
3005 PXP_PF_ME_OPAQUE_ADDR);
3007 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
3009 /* Bits 16-19 from the ME registers are the pf_num */
3010 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
3011 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
3012 PXP_CONCRETE_FID_PFID);
3013 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
3014 PXP_CONCRETE_FID_PORT);
3016 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3017 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
3018 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
3021 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
3023 u32 *feat_num = p_hwfn->hw_info.feat_num;
3024 struct ecore_sb_cnt_info sb_cnt;
3027 OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
3028 ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
3030 /* L2 Queues require each: 1 status block. 1 L2 queue */
3031 if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
3032 /* Start by allocating VF queues, then PF's */
3033 feat_num[ECORE_VF_L2_QUE] =
3035 RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
3037 feat_num[ECORE_PF_L2_QUE] =
3039 sb_cnt.cnt - non_l2_sbs,
3040 RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
3041 FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
3044 if (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
3045 ECORE_IS_ISCSI_PERSONALITY(p_hwfn)) {
3046 u32 *p_storage_feat = ECORE_IS_FCOE_PERSONALITY(p_hwfn) ?
3047 &feat_num[ECORE_FCOE_CQ] :
3048 &feat_num[ECORE_ISCSI_CQ];
3049 u32 limit = sb_cnt.cnt;
3051 /* The number of queues should not exceed the number of FP SBs.
3052 * In storage target, the queues are divided into pairs of a CQ
3053 * and a CmdQ, and each pair uses a single SB. The limit in
3054 * this case should allow a max ratio of 2:1 instead of 1:1.
3056 if (p_hwfn->p_dev->b_is_target)
3058 *p_storage_feat = OSAL_MIN_T(u32, limit,
3059 RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
3062 /* The size of "cq_cmdq_sb_num_arr" in the fcoe/iscsi init
3063 * ramrod is limited to "NUM_OF_GLOBAL_QUEUES / 2".
3065 *p_storage_feat = OSAL_MIN_T(u32, *p_storage_feat,
3066 (NUM_OF_GLOBAL_QUEUES / 2));
3069 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3070 "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
3071 (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
3072 (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
3073 (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
3074 (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
3075 (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
3079 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
3082 case ECORE_L2_QUEUE:
3096 case ECORE_RDMA_CNQ_RAM:
3097 return "RDMA_CNQ_RAM";
3100 case ECORE_LL2_QUEUE:
3102 case ECORE_CMDQS_CQS:
3104 case ECORE_RDMA_STATS_QUEUE:
3105 return "RDMA_STATS_QUEUE";
3111 return "UNKNOWN_RESOURCE";
3115 static enum _ecore_status_t
3116 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
3117 struct ecore_ptt *p_ptt,
3118 enum ecore_resources res_id,
3122 enum _ecore_status_t rc;
3124 rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
3125 resc_max_val, p_mcp_resp);
3126 if (rc != ECORE_SUCCESS) {
3127 DP_NOTICE(p_hwfn, false,
3128 "MFW response failure for a max value setting of resource %d [%s]\n",
3129 res_id, ecore_hw_get_resc_name(res_id));
3133 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
3135 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
3136 res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
3138 return ECORE_SUCCESS;
3141 static enum _ecore_status_t
3142 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
3143 struct ecore_ptt *p_ptt)
3145 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3146 u32 resc_max_val, mcp_resp;
3148 enum _ecore_status_t rc;
3150 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3153 case ECORE_LL2_QUEUE:
3154 case ECORE_RDMA_CNQ_RAM:
3155 case ECORE_RDMA_STATS_QUEUE:
3163 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
3164 resc_max_val, &mcp_resp);
3165 if (rc != ECORE_SUCCESS)
3168 /* There's no point to continue to the next resource if the
3169 * command is not supported by the MFW.
3170 * We do continue if the command is supported but the resource
3171 * is unknown to the MFW. Such a resource will be later
3172 * configured with the default allocation values.
3174 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
3175 return ECORE_NOTIMPL;
3178 return ECORE_SUCCESS;
3182 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
3183 enum ecore_resources res_id,
3184 u32 *p_resc_num, u32 *p_resc_start)
3186 u8 num_funcs = p_hwfn->num_funcs_on_engine;
3187 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3190 case ECORE_L2_QUEUE:
3191 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
3192 MAX_NUM_L2_QUEUES_BB) / num_funcs;
3195 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3196 MAX_NUM_VPORTS_BB) / num_funcs;
3199 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
3200 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
3203 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
3204 MAX_QM_TX_QUEUES_BB) / num_funcs;
3207 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
3211 /* Each VFC resource can accommodate both a MAC and a VLAN */
3212 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3215 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
3216 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
3218 case ECORE_LL2_QUEUE:
3219 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
3221 case ECORE_RDMA_CNQ_RAM:
3222 case ECORE_CMDQS_CQS:
3223 /* CNQ/CMDQS are the same resource */
3225 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
3227 case ECORE_RDMA_STATS_QUEUE:
3229 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3230 MAX_NUM_VPORTS_BB) / num_funcs;
3247 /* Since we want its value to reflect whether MFW supports
3248 * the new scheme, have a default of 0.
3253 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3257 return ECORE_SUCCESS;
3260 static enum _ecore_status_t
3261 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
3262 bool drv_resc_alloc)
3264 u32 dflt_resc_num = 0, dflt_resc_start = 0;
3265 u32 mcp_resp, *p_resc_num, *p_resc_start;
3266 enum _ecore_status_t rc;
3268 p_resc_num = &RESC_NUM(p_hwfn, res_id);
3269 p_resc_start = &RESC_START(p_hwfn, res_id);
3271 rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3273 if (rc != ECORE_SUCCESS) {
3275 "Failed to get default amount for resource %d [%s]\n",
3276 res_id, ecore_hw_get_resc_name(res_id));
3281 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3282 *p_resc_num = dflt_resc_num;
3283 *p_resc_start = dflt_resc_start;
3288 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3289 &mcp_resp, p_resc_num, p_resc_start);
3290 if (rc != ECORE_SUCCESS) {
3291 DP_NOTICE(p_hwfn, true,
3292 "MFW response failure for an allocation request for"
3293 " resource %d [%s]\n",
3294 res_id, ecore_hw_get_resc_name(res_id));
3298 /* Default driver values are applied in the following cases:
3299 * - The resource allocation MB command is not supported by the MFW
3300 * - There is an internal error in the MFW while processing the request
3301 * - The resource ID is unknown to the MFW
3303 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3305 "Failed to receive allocation info for resource %d [%s]."
3306 " mcp_resp = 0x%x. Applying default values"
3308 res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
3309 dflt_resc_num, dflt_resc_start);
3311 *p_resc_num = dflt_resc_num;
3312 *p_resc_start = dflt_resc_start;
3316 if ((*p_resc_num != dflt_resc_num ||
3317 *p_resc_start != dflt_resc_start) &&
3318 res_id != ECORE_SB) {
3320 "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
3321 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
3322 *p_resc_start, dflt_resc_num, dflt_resc_start,
3323 drv_resc_alloc ? " - Applying default values" : "");
3324 if (drv_resc_alloc) {
3325 *p_resc_num = dflt_resc_num;
3326 *p_resc_start = dflt_resc_start;
3330 return ECORE_SUCCESS;
3333 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
3334 bool drv_resc_alloc)
3336 enum _ecore_status_t rc;
3339 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3340 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
3341 if (rc != ECORE_SUCCESS)
3345 return ECORE_SUCCESS;
3348 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
3349 struct ecore_ptt *p_ptt,
3350 bool drv_resc_alloc)
3352 struct ecore_resc_unlock_params resc_unlock_params;
3353 struct ecore_resc_lock_params resc_lock_params;
3354 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3356 enum _ecore_status_t rc;
3358 u32 *resc_start = p_hwfn->hw_info.resc_start;
3359 u32 *resc_num = p_hwfn->hw_info.resc_num;
3360 /* For AH, an equal share of the ILT lines between the maximal number of
3361 * PFs is not enough for RoCE. This would be solved by the future
3362 * resource allocation scheme, but isn't currently present for
3363 * FPGA/emulation. For now we keep a number that is sufficient for RoCE
3364 * to work - the BB number of ILT lines divided by its max PFs number.
3366 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
3369 /* Setting the max values of the soft resources and the following
3370 * resources allocation queries should be atomic. Since several PFs can
3371 * run in parallel - a resource lock is needed.
3372 * If either the resource lock or resource set value commands are not
3373 * supported - skip the max values setting, release the lock if
3374 * needed, and proceed to the queries. Other failures, including a
3375 * failure to acquire the lock, will cause this function to fail.
3376 * Old drivers that don't acquire the lock can run in parallel, and
3377 * their allocation values won't be affected by the updated max values.
3379 ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3380 ECORE_RESC_LOCK_RESC_ALLOC, false);
3382 rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3383 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3385 } else if (rc == ECORE_NOTIMPL) {
3387 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3388 } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
3389 DP_NOTICE(p_hwfn, false,
3390 "Failed to acquire the resource lock for the resource allocation commands\n");
3392 goto unlock_and_exit;
3394 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
3395 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3396 DP_NOTICE(p_hwfn, false,
3397 "Failed to set the max values of the soft resources\n");
3398 goto unlock_and_exit;
3399 } else if (rc == ECORE_NOTIMPL) {
3401 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3402 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3403 &resc_unlock_params);
3404 if (rc != ECORE_SUCCESS)
3406 "Failed to release the resource lock for the resource allocation commands\n");
3410 rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
3411 if (rc != ECORE_SUCCESS)
3412 goto unlock_and_exit;
3414 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3415 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3416 &resc_unlock_params);
3417 if (rc != ECORE_SUCCESS)
3419 "Failed to release the resource lock for the resource allocation commands\n");
3423 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3424 /* Reduced build contains less PQs */
3425 if (!(p_hwfn->p_dev->b_is_emul_full)) {
3426 resc_num[ECORE_PQ] = 32;
3427 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
3428 p_hwfn->enabled_func_idx;
3431 /* For AH emulation, since we have a possible maximal number of
3432 * 16 enabled PFs, in case there are not enough ILT lines -
3433 * allocate only first PF as RoCE and have all the other ETH
3434 * only with less ILT lines.
3436 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
3437 resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
3438 resc_num[ECORE_ILT],
3439 roce_min_ilt_lines);
3442 /* Correct the common ILT calculation if PF0 has more */
3443 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
3444 p_hwfn->p_dev->b_is_emul_full &&
3445 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
3446 resc_start[ECORE_ILT] += roce_min_ilt_lines -
3447 resc_num[ECORE_ILT];
3450 /* Sanity for ILT */
3451 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3452 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3453 DP_NOTICE(p_hwfn, true,
3454 "Can't assign ILT pages [%08x,...,%08x]\n",
3455 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
3461 /* This will also learn the number of SBs from MFW */
3462 if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
3465 ecore_hw_set_feat(p_hwfn);
3467 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3468 "The numbers for each resource are:\n");
3469 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
3470 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
3471 ecore_hw_get_resc_name(res_id),
3472 RESC_NUM(p_hwfn, res_id),
3473 RESC_START(p_hwfn, res_id));
3475 return ECORE_SUCCESS;
3478 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3479 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3480 &resc_unlock_params);
3484 static enum _ecore_status_t
3485 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
3486 struct ecore_ptt *p_ptt,
3487 struct ecore_hw_prepare_params *p_params)
3489 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
3490 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
3491 struct ecore_mcp_link_capabilities *p_caps;
3492 struct ecore_mcp_link_params *link;
3493 enum _ecore_status_t rc;
3495 /* Read global nvm_cfg address */
3496 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
3498 /* Verify MCP has initialized it */
3499 if (!nvm_cfg_addr) {
3500 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
3501 if (p_params->b_relaxed_probe)
3502 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
3506 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
3508 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
3510 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3511 OFFSETOF(struct nvm_cfg1, glob) +
3512 OFFSETOF(struct nvm_cfg1_glob, core_cfg);
3514 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
3516 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
3517 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
3518 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
3519 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
3521 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
3522 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
3524 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
3525 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
3527 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
3528 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
3530 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
3531 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
3533 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
3534 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
3536 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
3537 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
3539 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
3540 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
3542 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
3543 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
3545 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
3546 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
3548 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3549 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
3552 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
3557 /* Read DCBX configuration */
3558 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3559 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3560 dcbx_mode = ecore_rd(p_hwfn, p_ptt,
3562 OFFSETOF(struct nvm_cfg1_port, generic_cont0));
3563 dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
3564 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
3565 switch (dcbx_mode) {
3566 case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
3567 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
3569 case NVM_CFG1_PORT_DCBX_MODE_CEE:
3570 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
3572 case NVM_CFG1_PORT_DCBX_MODE_IEEE:
3573 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
3576 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
3579 /* Read default link configuration */
3580 link = &p_hwfn->mcp_info->link_input;
3581 p_caps = &p_hwfn->mcp_info->link_capabilities;
3582 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3583 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3584 link_temp = ecore_rd(p_hwfn, p_ptt,
3586 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
3587 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
3588 link->speed.advertised_speeds = link_temp;
3589 p_caps->speed_capabilities = link->speed.advertised_speeds;
3591 link_temp = ecore_rd(p_hwfn, p_ptt,
3593 OFFSETOF(struct nvm_cfg1_port, link_settings));
3594 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
3595 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
3596 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
3597 link->speed.autoneg = true;
3599 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
3600 link->speed.forced_speed = 1000;
3602 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
3603 link->speed.forced_speed = 10000;
3605 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3606 link->speed.forced_speed = 25000;
3608 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3609 link->speed.forced_speed = 40000;
3611 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3612 link->speed.forced_speed = 50000;
3614 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3615 link->speed.forced_speed = 100000;
3618 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
3621 p_caps->default_speed = link->speed.forced_speed;
3622 p_caps->default_speed_autoneg = link->speed.autoneg;
3624 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3625 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3626 link->pause.autoneg = !!(link_temp &
3627 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3628 link->pause.forced_rx = !!(link_temp &
3629 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3630 link->pause.forced_tx = !!(link_temp &
3631 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3632 link->loopback_mode = 0;
3634 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
3635 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
3636 OFFSETOF(struct nvm_cfg1_port, ext_phy));
3637 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
3638 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
3639 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
3640 link->eee.enable = true;
3641 switch (link_temp) {
3642 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
3643 p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
3644 link->eee.enable = false;
3646 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
3647 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
3649 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
3650 p_caps->eee_lpi_timer =
3651 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
3653 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
3654 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
3658 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
3659 link->eee.tx_lpi_enable = link->eee.enable;
3660 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
3662 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
3665 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3666 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
3667 link->speed.forced_speed, link->speed.advertised_speeds,
3668 link->speed.autoneg, link->pause.autoneg,
3669 p_caps->default_eee, p_caps->eee_lpi_timer);
3671 /* Read Multi-function information from shmem */
3672 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3673 OFFSETOF(struct nvm_cfg1, glob) +
3674 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3676 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3678 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3679 NVM_CFG1_GLOB_MF_MODE_OFFSET;
3682 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3683 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS;
3685 case NVM_CFG1_GLOB_MF_MODE_UFP:
3686 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
3687 1 << ECORE_MF_UFP_SPECIFIC |
3688 1 << ECORE_MF_8021Q_TAGGING;
3690 case NVM_CFG1_GLOB_MF_MODE_BD:
3691 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
3692 1 << ECORE_MF_LLH_PROTO_CLSS |
3693 1 << ECORE_MF_8021AD_TAGGING;
3695 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3696 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3697 1 << ECORE_MF_LLH_PROTO_CLSS |
3698 1 << ECORE_MF_LL2_NON_UNICAST |
3699 1 << ECORE_MF_INTER_PF_SWITCH |
3700 1 << ECORE_MF_DISABLE_ARFS;
3702 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3703 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3704 1 << ECORE_MF_LLH_PROTO_CLSS |
3705 1 << ECORE_MF_LL2_NON_UNICAST;
3706 if (ECORE_IS_BB(p_hwfn->p_dev))
3707 p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
3710 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
3711 p_hwfn->p_dev->mf_bits);
3713 if (ECORE_IS_CMT(p_hwfn->p_dev))
3714 p_hwfn->p_dev->mf_bits |= (1 << ECORE_MF_DISABLE_ARFS);
3716 /* It's funny since we have another switch, but it's easier
3717 * to throw this away in linux this way. Long term, it might be
3718 * better to have have getters for needed ECORE_MF_* fields,
3719 * convert client code and eliminate this.
3722 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3723 case NVM_CFG1_GLOB_MF_MODE_BD:
3724 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3726 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3727 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3729 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3730 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3732 case NVM_CFG1_GLOB_MF_MODE_UFP:
3733 p_hwfn->p_dev->mf_mode = ECORE_MF_UFP;
3737 /* Read Multi-function information from shmem */
3738 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3739 OFFSETOF(struct nvm_cfg1, glob) +
3740 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3742 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3743 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3744 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3745 &p_hwfn->hw_info.device_capabilities);
3746 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3747 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3748 &p_hwfn->hw_info.device_capabilities);
3749 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3750 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3751 &p_hwfn->hw_info.device_capabilities);
3752 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3753 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3754 &p_hwfn->hw_info.device_capabilities);
3755 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3756 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3757 &p_hwfn->hw_info.device_capabilities);
3759 rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3760 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3762 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3768 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3769 struct ecore_ptt *p_ptt)
3771 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3772 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3773 struct ecore_dev *p_dev = p_hwfn->p_dev;
3775 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3777 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3778 * in the other bits are selected.
3779 * Bits 1-15 are for functions 1-15, respectively, and their value is
3780 * '0' only for enabled functions (function 0 always exists and
3782 * In case of CMT in BB, only the "even" functions are enabled, and thus
3783 * the number of functions for both hwfns is learnt from the same bits.
3785 if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3786 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3787 MISCS_REG_FUNCTION_HIDE_BB_K2);
3789 reg_function_hide = 0;
3792 if (reg_function_hide & 0x1) {
3793 if (ECORE_IS_BB(p_dev)) {
3794 if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) {
3806 /* Get the number of the enabled functions on the engine */
3807 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3814 /* Get the PF index within the enabled functions */
3815 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3816 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3824 p_hwfn->num_funcs_on_engine = num_funcs;
3825 p_hwfn->enabled_func_idx = enabled_func_idx;
3828 if (CHIP_REV_IS_FPGA(p_dev)) {
3829 DP_NOTICE(p_hwfn, false,
3830 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3831 p_hwfn->num_funcs_on_engine = 4;
3835 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3836 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3837 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3838 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3841 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3842 struct ecore_ptt *p_ptt)
3844 struct ecore_dev *p_dev = p_hwfn->p_dev;
3848 /* Read the port mode */
3849 if (CHIP_REV_IS_FPGA(p_dev))
3851 else if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_CMT(p_dev))
3852 /* In CMT on emulation, assume 1 port */
3856 port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3858 if (port_mode < 3) {
3859 p_dev->num_ports_in_engine = 1;
3860 } else if (port_mode <= 5) {
3861 p_dev->num_ports_in_engine = 2;
3863 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3864 p_dev->num_ports_in_engine);
3866 /* Default num_ports_in_engine to something */
3867 p_dev->num_ports_in_engine = 1;
3871 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3872 struct ecore_ptt *p_ptt)
3874 struct ecore_dev *p_dev = p_hwfn->p_dev;
3878 p_dev->num_ports_in_engine = 0;
3881 if (CHIP_REV_IS_EMUL(p_dev)) {
3882 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3883 switch ((port & 0xf000) >> 12) {
3885 p_dev->num_ports_in_engine = 1;
3888 p_dev->num_ports_in_engine = 2;
3891 p_dev->num_ports_in_engine = 4;
3894 DP_NOTICE(p_hwfn, false,
3895 "Unknown port mode in ECO_RESERVED %08x\n",
3900 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3901 port = ecore_rd(p_hwfn, p_ptt,
3902 CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3905 p_dev->num_ports_in_engine++;
3908 if (!p_dev->num_ports_in_engine) {
3909 DP_NOTICE(p_hwfn, true, "All NIG ports are inactive\n");
3911 /* Default num_ports_in_engine to something */
3912 p_dev->num_ports_in_engine = 1;
3916 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3917 struct ecore_ptt *p_ptt)
3919 struct ecore_dev *p_dev = p_hwfn->p_dev;
3921 /* Determine the number of ports per engine */
3922 if (ECORE_IS_BB(p_dev))
3923 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3925 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3927 /* Get the total number of ports of the device */
3928 if (ECORE_IS_CMT(p_dev)) {
3929 /* In CMT there is always only one port */
3930 p_dev->num_ports = 1;
3932 } else if (CHIP_REV_IS_EMUL(p_dev) || CHIP_REV_IS_TEDIBEAR(p_dev)) {
3933 p_dev->num_ports = p_dev->num_ports_in_engine *
3934 ecore_device_num_engines(p_dev);
3937 u32 addr, global_offsize, global_addr;
3939 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
3941 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
3942 global_addr = SECTION_ADDR(global_offsize, 0);
3943 addr = global_addr + OFFSETOF(struct public_global, max_ports);
3944 p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
3948 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
3949 struct ecore_ptt *p_ptt)
3951 struct ecore_mcp_link_capabilities *p_caps;
3954 p_caps = &p_hwfn->mcp_info->link_capabilities;
3955 if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
3958 p_caps->eee_speed_caps = 0;
3959 eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
3960 OFFSETOF(struct public_port, eee_status));
3961 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
3962 EEE_SUPPORTED_SPEED_OFFSET;
3963 if (eee_status & EEE_1G_SUPPORTED)
3964 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
3965 if (eee_status & EEE_10G_ADV)
3966 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
3969 static enum _ecore_status_t
3970 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3971 enum ecore_pci_personality personality,
3972 struct ecore_hw_prepare_params *p_params)
3974 bool drv_resc_alloc = p_params->drv_resc_alloc;
3975 enum _ecore_status_t rc;
3977 if (IS_ECORE_PACING(p_hwfn)) {
3978 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_IOV,
3979 "Skipping IOV as packet pacing is requested\n");
3982 /* Since all information is common, only first hwfns should do this */
3983 if (IS_LEAD_HWFN(p_hwfn) && !IS_ECORE_PACING(p_hwfn)) {
3984 rc = ecore_iov_hw_info(p_hwfn);
3985 if (rc != ECORE_SUCCESS) {
3986 if (p_params->b_relaxed_probe)
3987 p_params->p_relaxed_res =
3988 ECORE_HW_PREPARE_BAD_IOV;
3994 if (IS_LEAD_HWFN(p_hwfn))
3995 ecore_hw_info_port_num(p_hwfn, p_ptt);
3997 ecore_mcp_get_capabilities(p_hwfn, p_ptt);
4000 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
4002 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
4003 if (rc != ECORE_SUCCESS)
4009 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
4010 if (rc != ECORE_SUCCESS) {
4011 if (p_params->b_relaxed_probe)
4012 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
4018 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
4020 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
4021 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
4024 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
4026 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
4027 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
4031 if (ecore_mcp_is_init(p_hwfn)) {
4032 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
4033 p_hwfn->hw_info.ovlan =
4034 p_hwfn->mcp_info->func_info.ovlan;
4036 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
4038 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
4040 ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
4043 if (personality != ECORE_PCI_DEFAULT) {
4044 p_hwfn->hw_info.personality = personality;
4045 } else if (ecore_mcp_is_init(p_hwfn)) {
4046 enum ecore_pci_personality protocol;
4048 protocol = p_hwfn->mcp_info->func_info.protocol;
4049 p_hwfn->hw_info.personality = protocol;
4053 /* To overcome ILT lack for emulation, until at least until we'll have
4054 * a definite answer from system about it, allow only PF0 to be RoCE.
4056 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
4057 if (!p_hwfn->rel_pf_id)
4058 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
4060 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
4064 /* although in BB some constellations may support more than 4 tcs,
4065 * that can result in performance penalty in some cases. 4
4066 * represents a good tradeoff between performance and flexibility.
4068 if (IS_ECORE_PACING(p_hwfn))
4069 p_hwfn->hw_info.num_hw_tc = 1;
4071 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
4073 /* start out with a single active tc. This can be increased either
4074 * by dcbx negotiation or by upper layer driver
4076 p_hwfn->hw_info.num_active_tc = 1;
4078 ecore_get_num_funcs(p_hwfn, p_ptt);
4080 if (ecore_mcp_is_init(p_hwfn))
4081 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
4083 /* In case of forcing the driver's default resource allocation, calling
4084 * ecore_hw_get_resc() should come after initializing the personality
4085 * and after getting the number of functions, since the calculation of
4086 * the resources/features depends on them.
4087 * This order is not harmful if not forcing.
4089 rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
4090 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
4092 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
4098 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
4099 struct ecore_ptt *p_ptt)
4101 struct ecore_dev *p_dev = p_hwfn->p_dev;
4105 /* Read Vendor Id / Device Id */
4106 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
4108 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
4111 /* Determine type */
4112 device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
4113 switch (device_id_mask) {
4114 case ECORE_DEV_ID_MASK_BB:
4115 p_dev->type = ECORE_DEV_TYPE_BB;
4117 case ECORE_DEV_ID_MASK_AH:
4118 p_dev->type = ECORE_DEV_TYPE_AH;
4121 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
4123 return ECORE_ABORTED;
4126 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
4127 p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM);
4128 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
4129 p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV);
4131 /* Learn number of HW-functions */
4132 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
4134 if (tmp & (1 << p_hwfn->rel_pf_id)) {
4135 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
4136 p_dev->num_hwfns = 2;
4138 p_dev->num_hwfns = 1;
4142 if (CHIP_REV_IS_EMUL(p_dev)) {
4143 /* For some reason we have problems with this register
4144 * in B0 emulation; Simply assume no CMT
4146 DP_NOTICE(p_dev->hwfns, false,
4147 "device on emul - assume no CMT\n");
4148 p_dev->num_hwfns = 1;
4152 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG);
4153 p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID);
4154 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
4155 p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL);
4157 DP_INFO(p_dev->hwfns,
4158 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n",
4159 ECORE_IS_BB(p_dev) ? "BB" : "AH",
4160 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
4161 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
4164 if (ECORE_IS_BB_A0(p_dev)) {
4165 DP_NOTICE(p_dev->hwfns, false,
4166 "The chip type/rev (BB A0) is not supported!\n");
4167 return ECORE_ABORTED;
4170 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
4171 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
4173 if (CHIP_REV_IS_EMUL(p_dev)) {
4174 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
4175 if (tmp & (1 << 29)) {
4176 DP_NOTICE(p_hwfn, false,
4177 "Emulation: Running on a FULL build\n");
4178 p_dev->b_is_emul_full = true;
4180 DP_NOTICE(p_hwfn, false,
4181 "Emulation: Running on a REDUCED build\n");
4186 return ECORE_SUCCESS;
4189 #ifndef LINUX_REMOVE
4190 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
4197 for_each_hwfn(p_dev, j) {
4198 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
4200 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
4201 "Mark hw/fw uninitialized\n");
4203 p_hwfn->hw_init_done = false;
4205 ecore_ptt_invalidate(p_hwfn);
4210 static enum _ecore_status_t
4211 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
4212 void OSAL_IOMEM * p_regview,
4213 void OSAL_IOMEM * p_doorbells,
4214 struct ecore_hw_prepare_params *p_params)
4216 struct ecore_mdump_retain_data mdump_retain;
4217 struct ecore_dev *p_dev = p_hwfn->p_dev;
4218 struct ecore_mdump_info mdump_info;
4219 enum _ecore_status_t rc = ECORE_SUCCESS;
4221 /* Split PCI bars evenly between hwfns */
4222 p_hwfn->regview = p_regview;
4223 p_hwfn->doorbells = p_doorbells;
4226 return ecore_vf_hw_prepare(p_hwfn);
4228 /* Validate that chip access is feasible */
4229 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
4231 "Reading the ME register returns all Fs; Preventing further chip access\n");
4232 if (p_params->b_relaxed_probe)
4233 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
4237 get_function_id(p_hwfn);
4239 /* Allocate PTT pool */
4240 rc = ecore_ptt_pool_alloc(p_hwfn);
4242 DP_NOTICE(p_hwfn, false, "Failed to prepare hwfn's hw\n");
4243 if (p_params->b_relaxed_probe)
4244 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4248 /* Allocate the main PTT */
4249 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4251 /* First hwfn learns basic information, e.g., number of hwfns */
4252 if (!p_hwfn->my_id) {
4253 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
4254 if (rc != ECORE_SUCCESS) {
4255 if (p_params->b_relaxed_probe)
4256 p_params->p_relaxed_res =
4257 ECORE_HW_PREPARE_FAILED_DEV;
4262 ecore_hw_hwfn_prepare(p_hwfn);
4264 /* Initialize MCP structure */
4265 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4267 DP_NOTICE(p_hwfn, false, "Failed initializing mcp command\n");
4268 if (p_params->b_relaxed_probe)
4269 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4273 /* Read the device configuration information from the HW and SHMEM */
4274 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
4275 p_params->personality, p_params);
4277 DP_NOTICE(p_hwfn, false, "Failed to get HW information\n");
4281 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
4282 * called, since among others it sets the ports number in an engine.
4284 if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
4285 !p_dev->recov_in_prog) {
4286 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4287 if (rc != ECORE_SUCCESS)
4288 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
4290 /* Workaround for MFW issue where PF FLR does not cleanup
4293 if (!(p_hwfn->mcp_info->capabilities &
4294 FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP))
4295 ecore_pf_flr_igu_cleanup(p_hwfn);
4298 /* Check if mdump logs/data are present and update the epoch value */
4299 if (IS_LEAD_HWFN(p_hwfn)) {
4301 if (!CHIP_REV_IS_EMUL(p_dev)) {
4303 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
4305 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
4306 DP_NOTICE(p_hwfn, false,
4307 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
4309 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
4311 if (rc == ECORE_SUCCESS && mdump_retain.valid)
4312 DP_NOTICE(p_hwfn, false,
4313 "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
4314 mdump_retain.epoch, mdump_retain.pf,
4315 mdump_retain.status);
4317 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
4324 /* Allocate the init RT array and initialize the init-ops engine */
4325 rc = ecore_init_alloc(p_hwfn);
4327 DP_NOTICE(p_hwfn, false, "Failed to allocate the init array\n");
4328 if (p_params->b_relaxed_probe)
4329 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4333 if (CHIP_REV_IS_FPGA(p_dev)) {
4334 DP_NOTICE(p_hwfn, false,
4335 "FPGA: workaround; Prevent DMAE parities\n");
4336 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
4339 DP_NOTICE(p_hwfn, false,
4340 "FPGA: workaround: Set VF bar0 size\n");
4341 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4342 PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
4348 if (IS_LEAD_HWFN(p_hwfn))
4349 ecore_iov_free_hw_info(p_dev);
4350 ecore_mcp_free(p_hwfn);
4352 ecore_hw_hwfn_free(p_hwfn);
4357 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
4358 struct ecore_hw_prepare_params *p_params)
4360 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4361 enum _ecore_status_t rc;
4363 p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
4364 p_dev->allow_mdump = p_params->allow_mdump;
4365 p_hwfn->b_en_pacing = p_params->b_en_pacing;
4366 p_dev->b_is_target = p_params->b_is_target;
4368 if (p_params->b_relaxed_probe)
4369 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
4371 /* Store the precompiled init data ptrs */
4373 ecore_init_iro_array(p_dev);
4375 /* Initialize the first hwfn - will learn number of hwfns */
4376 rc = ecore_hw_prepare_single(p_hwfn,
4378 p_dev->doorbells, p_params);
4379 if (rc != ECORE_SUCCESS)
4382 p_params->personality = p_hwfn->hw_info.personality;
4384 /* initilalize 2nd hwfn if necessary */
4385 if (ECORE_IS_CMT(p_dev)) {
4386 void OSAL_IOMEM *p_regview, *p_doorbell;
4387 u8 OSAL_IOMEM *addr;
4389 /* adjust bar offset for second engine */
4390 addr = (u8 OSAL_IOMEM *)p_dev->regview +
4391 ecore_hw_bar_size(p_hwfn,
4394 p_regview = (void OSAL_IOMEM *)addr;
4396 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
4397 ecore_hw_bar_size(p_hwfn,
4400 p_doorbell = (void OSAL_IOMEM *)addr;
4402 p_dev->hwfns[1].b_en_pacing = p_params->b_en_pacing;
4403 /* prepare second hw function */
4404 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
4405 p_doorbell, p_params);
4407 /* in case of error, need to free the previously
4408 * initiliazed hwfn 0.
4410 if (rc != ECORE_SUCCESS) {
4411 if (p_params->b_relaxed_probe)
4412 p_params->p_relaxed_res =
4413 ECORE_HW_PREPARE_FAILED_ENG2;
4416 ecore_init_free(p_hwfn);
4417 ecore_mcp_free(p_hwfn);
4418 ecore_hw_hwfn_free(p_hwfn);
4420 DP_NOTICE(p_dev, false, "What do we need to free when VF hwfn1 init fails\n");
4429 void ecore_hw_remove(struct ecore_dev *p_dev)
4431 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4435 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4436 ECORE_OV_DRIVER_STATE_NOT_LOADED);
4438 for_each_hwfn(p_dev, i) {
4439 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4442 ecore_vf_pf_release(p_hwfn);
4446 ecore_init_free(p_hwfn);
4447 ecore_hw_hwfn_free(p_hwfn);
4448 ecore_mcp_free(p_hwfn);
4450 #ifdef CONFIG_ECORE_LOCK_ALLOC
4451 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
4455 ecore_iov_free_hw_info(p_dev);
4458 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
4459 struct ecore_chain *p_chain)
4461 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
4462 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
4463 struct ecore_chain_next *p_next;
4469 size = p_chain->elem_size * p_chain->usable_per_page;
4471 for (i = 0; i < p_chain->page_cnt; i++) {
4475 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
4476 p_virt_next = p_next->next_virt;
4477 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
4479 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
4480 ECORE_CHAIN_PAGE_SIZE);
4482 p_virt = p_virt_next;
4483 p_phys = p_phys_next;
4487 static void ecore_chain_free_single(struct ecore_dev *p_dev,
4488 struct ecore_chain *p_chain)
4490 if (!p_chain->p_virt_addr)
4493 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
4494 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
4497 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
4498 struct ecore_chain *p_chain)
4500 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
4501 u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
4502 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
4504 if (!pp_virt_addr_tbl)
4510 for (i = 0; i < page_cnt; i++) {
4511 if (!pp_virt_addr_tbl[i])
4514 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
4515 *(dma_addr_t *)p_pbl_virt,
4516 ECORE_CHAIN_PAGE_SIZE);
4518 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4521 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4523 if (!p_chain->b_external_pbl)
4524 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
4525 p_chain->pbl_sp.p_phys_table, pbl_size);
4527 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
4530 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4532 switch (p_chain->mode) {
4533 case ECORE_CHAIN_MODE_NEXT_PTR:
4534 ecore_chain_free_next_ptr(p_dev, p_chain);
4536 case ECORE_CHAIN_MODE_SINGLE:
4537 ecore_chain_free_single(p_dev, p_chain);
4539 case ECORE_CHAIN_MODE_PBL:
4540 ecore_chain_free_pbl(p_dev, p_chain);
4545 static enum _ecore_status_t
4546 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
4547 enum ecore_chain_cnt_type cnt_type,
4548 osal_size_t elem_size, u32 page_cnt)
4550 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
4552 /* The actual chain size can be larger than the maximal possible value
4553 * after rounding up the requested elements number to pages, and after
4554 * taking into acount the unusuable elements (next-ptr elements).
4555 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
4556 * size/capacity fields are of a u32 type.
4558 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
4559 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
4560 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
4561 chain_size > ECORE_U32_MAX)) {
4562 DP_NOTICE(p_dev, true,
4563 "The actual chain size (0x%lx) is larger than the maximal possible value\n",
4564 (unsigned long)chain_size);
4568 return ECORE_SUCCESS;
4571 static enum _ecore_status_t
4572 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4574 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
4575 dma_addr_t p_phys = 0;
4578 for (i = 0; i < p_chain->page_cnt; i++) {
4579 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4580 ECORE_CHAIN_PAGE_SIZE);
4582 DP_NOTICE(p_dev, false,
4583 "Failed to allocate chain memory\n");
4588 ecore_chain_init_mem(p_chain, p_virt, p_phys);
4589 ecore_chain_reset(p_chain);
4591 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4595 p_virt_prev = p_virt;
4597 /* Last page's next element should point to the beginning of the
4600 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4601 p_chain->p_virt_addr,
4602 p_chain->p_phys_addr);
4604 return ECORE_SUCCESS;
4607 static enum _ecore_status_t
4608 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4610 dma_addr_t p_phys = 0;
4611 void *p_virt = OSAL_NULL;
4613 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
4615 DP_NOTICE(p_dev, false, "Failed to allocate chain memory\n");
4619 ecore_chain_init_mem(p_chain, p_virt, p_phys);
4620 ecore_chain_reset(p_chain);
4622 return ECORE_SUCCESS;
4625 static enum _ecore_status_t
4626 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
4627 struct ecore_chain *p_chain,
4628 struct ecore_chain_ext_pbl *ext_pbl)
4630 u32 page_cnt = p_chain->page_cnt, size, i;
4631 dma_addr_t p_phys = 0, p_pbl_phys = 0;
4632 void **pp_virt_addr_tbl = OSAL_NULL;
4633 u8 *p_pbl_virt = OSAL_NULL;
4634 void *p_virt = OSAL_NULL;
4636 size = page_cnt * sizeof(*pp_virt_addr_tbl);
4637 pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
4638 if (!pp_virt_addr_tbl) {
4639 DP_NOTICE(p_dev, false,
4640 "Failed to allocate memory for the chain virtual addresses table\n");
4644 /* The allocation of the PBL table is done with its full size, since it
4645 * is expected to be successive.
4646 * ecore_chain_init_pbl_mem() is called even in a case of an allocation
4647 * failure, since pp_virt_addr_tbl was previously allocated, and it
4648 * should be saved to allow its freeing during the error flow.
4650 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4652 if (ext_pbl == OSAL_NULL) {
4653 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
4655 p_pbl_virt = ext_pbl->p_pbl_virt;
4656 p_pbl_phys = ext_pbl->p_pbl_phys;
4657 p_chain->b_external_pbl = true;
4660 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
4663 DP_NOTICE(p_dev, false, "Failed to allocate chain pbl memory\n");
4667 for (i = 0; i < page_cnt; i++) {
4668 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4669 ECORE_CHAIN_PAGE_SIZE);
4671 DP_NOTICE(p_dev, false,
4672 "Failed to allocate chain memory\n");
4677 ecore_chain_init_mem(p_chain, p_virt, p_phys);
4678 ecore_chain_reset(p_chain);
4681 /* Fill the PBL table with the physical address of the page */
4682 *(dma_addr_t *)p_pbl_virt = p_phys;
4683 /* Keep the virtual address of the page */
4684 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
4686 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4689 return ECORE_SUCCESS;
4692 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
4693 enum ecore_chain_use_mode intended_use,
4694 enum ecore_chain_mode mode,
4695 enum ecore_chain_cnt_type cnt_type,
4696 u32 num_elems, osal_size_t elem_size,
4697 struct ecore_chain *p_chain,
4698 struct ecore_chain_ext_pbl *ext_pbl)
4701 enum _ecore_status_t rc = ECORE_SUCCESS;
4703 if (mode == ECORE_CHAIN_MODE_SINGLE)
4706 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4708 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
4711 DP_NOTICE(p_dev, false,
4712 "Cannot allocate a chain with the given arguments:\n"
4713 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4714 intended_use, mode, cnt_type, num_elems, elem_size);
4718 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
4719 mode, cnt_type, p_dev->dp_ctx);
4722 case ECORE_CHAIN_MODE_NEXT_PTR:
4723 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
4725 case ECORE_CHAIN_MODE_SINGLE:
4726 rc = ecore_chain_alloc_single(p_dev, p_chain);
4728 case ECORE_CHAIN_MODE_PBL:
4729 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
4735 return ECORE_SUCCESS;
4738 ecore_chain_free(p_dev, p_chain);
4742 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
4743 u16 src_id, u16 *dst_id)
4745 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
4748 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
4749 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
4750 DP_NOTICE(p_hwfn, true,
4751 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4757 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
4759 return ECORE_SUCCESS;
4762 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
4763 u8 src_id, u8 *dst_id)
4765 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
4768 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
4769 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
4770 DP_NOTICE(p_hwfn, true,
4771 "vport id [%d] is not valid, available indices [%d - %d]\n",
4777 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
4779 return ECORE_SUCCESS;
4782 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
4783 u8 src_id, u8 *dst_id)
4785 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
4788 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
4789 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
4790 DP_NOTICE(p_hwfn, true,
4791 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4797 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
4799 return ECORE_SUCCESS;
4802 static enum _ecore_status_t
4803 ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4804 struct ecore_ptt *p_ptt, u32 high, u32 low,
4810 /* Find a free entry and utilize it */
4811 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4812 en = ecore_rd(p_hwfn, p_ptt,
4813 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4817 ecore_wr(p_hwfn, p_ptt,
4818 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4819 2 * i * sizeof(u32), low);
4820 ecore_wr(p_hwfn, p_ptt,
4821 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4822 (2 * i + 1) * sizeof(u32), high);
4823 ecore_wr(p_hwfn, p_ptt,
4824 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4825 i * sizeof(u32), 0);
4826 ecore_wr(p_hwfn, p_ptt,
4827 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4828 i * sizeof(u32), 0);
4829 ecore_wr(p_hwfn, p_ptt,
4830 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4831 i * sizeof(u32), 1);
4835 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4836 return ECORE_NORESOURCES;
4840 return ECORE_SUCCESS;
4843 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4844 struct ecore_ptt *p_ptt, u8 *p_filter)
4846 u32 high, low, entry_num;
4847 enum _ecore_status_t rc = ECORE_SUCCESS;
4849 if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4850 &p_hwfn->p_dev->mf_bits))
4851 return ECORE_SUCCESS;
4853 high = p_filter[1] | (p_filter[0] << 8);
4854 low = p_filter[5] | (p_filter[4] << 8) |
4855 (p_filter[3] << 16) | (p_filter[2] << 24);
4857 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4858 rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low,
4860 if (rc != ECORE_SUCCESS) {
4861 DP_NOTICE(p_hwfn, false,
4862 "Failed to find an empty LLH filter to utilize\n");
4866 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4867 "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n",
4868 p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4869 p_filter[4], p_filter[5], entry_num);
4874 static enum _ecore_status_t
4875 ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4876 struct ecore_ptt *p_ptt, u32 high, u32 low,
4881 /* Find the entry and clean it */
4882 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4883 if (ecore_rd(p_hwfn, p_ptt,
4884 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4885 2 * i * sizeof(u32)) != low)
4887 if (ecore_rd(p_hwfn, p_ptt,
4888 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4889 (2 * i + 1) * sizeof(u32)) != high)
4892 ecore_wr(p_hwfn, p_ptt,
4893 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4894 ecore_wr(p_hwfn, p_ptt,
4895 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4896 2 * i * sizeof(u32), 0);
4897 ecore_wr(p_hwfn, p_ptt,
4898 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4899 (2 * i + 1) * sizeof(u32), 0);
4903 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4908 return ECORE_SUCCESS;
4911 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4912 struct ecore_ptt *p_ptt, u8 *p_filter)
4914 u32 high, low, entry_num;
4915 enum _ecore_status_t rc = ECORE_SUCCESS;
4917 if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4918 &p_hwfn->p_dev->mf_bits))
4921 high = p_filter[1] | (p_filter[0] << 8);
4922 low = p_filter[5] | (p_filter[4] << 8) |
4923 (p_filter[3] << 16) | (p_filter[2] << 24);
4925 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4926 rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high,
4928 if (rc != ECORE_SUCCESS) {
4929 DP_NOTICE(p_hwfn, false,
4930 "Tried to remove a non-configured filter\n");
4935 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4936 "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n",
4937 p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4938 p_filter[4], p_filter[5], entry_num);
4941 static enum _ecore_status_t
4942 ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4943 struct ecore_ptt *p_ptt,
4944 enum ecore_llh_port_filter_type_t type,
4945 u32 high, u32 low, u32 *p_entry_num)
4950 /* Find a free entry and utilize it */
4951 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4952 en = ecore_rd(p_hwfn, p_ptt,
4953 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4957 ecore_wr(p_hwfn, p_ptt,
4958 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4959 2 * i * sizeof(u32), low);
4960 ecore_wr(p_hwfn, p_ptt,
4961 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4962 (2 * i + 1) * sizeof(u32), high);
4963 ecore_wr(p_hwfn, p_ptt,
4964 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4965 i * sizeof(u32), 1);
4966 ecore_wr(p_hwfn, p_ptt,
4967 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4968 i * sizeof(u32), 1 << type);
4969 ecore_wr(p_hwfn, p_ptt,
4970 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1);
4974 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4975 return ECORE_NORESOURCES;
4979 return ECORE_SUCCESS;
4982 enum _ecore_status_t
4983 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4984 struct ecore_ptt *p_ptt,
4985 u16 source_port_or_eth_type,
4987 enum ecore_llh_port_filter_type_t type)
4989 u32 high, low, entry_num;
4990 enum _ecore_status_t rc = ECORE_SUCCESS;
4992 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
4993 &p_hwfn->p_dev->mf_bits))
5000 case ECORE_LLH_FILTER_ETHERTYPE:
5001 high = source_port_or_eth_type;
5003 case ECORE_LLH_FILTER_TCP_SRC_PORT:
5004 case ECORE_LLH_FILTER_UDP_SRC_PORT:
5005 low = source_port_or_eth_type << 16;
5007 case ECORE_LLH_FILTER_TCP_DEST_PORT:
5008 case ECORE_LLH_FILTER_UDP_DEST_PORT:
5011 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
5012 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
5013 low = (source_port_or_eth_type << 16) | dest_port;
5016 DP_NOTICE(p_hwfn, true,
5017 "Non valid LLH protocol filter type %d\n", type);
5021 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5022 rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
5023 high, low, &entry_num);
5024 if (rc != ECORE_SUCCESS) {
5025 DP_NOTICE(p_hwfn, false,
5026 "Failed to find an empty LLH filter to utilize\n");
5030 case ECORE_LLH_FILTER_ETHERTYPE:
5031 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5032 "ETH type %x is added at %d\n",
5033 source_port_or_eth_type, entry_num);
5035 case ECORE_LLH_FILTER_TCP_SRC_PORT:
5036 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5037 "TCP src port %x is added at %d\n",
5038 source_port_or_eth_type, entry_num);
5040 case ECORE_LLH_FILTER_UDP_SRC_PORT:
5041 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5042 "UDP src port %x is added at %d\n",
5043 source_port_or_eth_type, entry_num);
5045 case ECORE_LLH_FILTER_TCP_DEST_PORT:
5046 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5047 "TCP dst port %x is added at %d\n", dest_port,
5050 case ECORE_LLH_FILTER_UDP_DEST_PORT:
5051 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5052 "UDP dst port %x is added at %d\n", dest_port,
5055 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
5056 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5057 "TCP src/dst ports %x/%x are added at %d\n",
5058 source_port_or_eth_type, dest_port, entry_num);
5060 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
5061 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5062 "UDP src/dst ports %x/%x are added at %d\n",
5063 source_port_or_eth_type, dest_port, entry_num);
5070 static enum _ecore_status_t
5071 ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
5072 struct ecore_ptt *p_ptt,
5073 enum ecore_llh_port_filter_type_t type,
5074 u32 high, u32 low, u32 *p_entry_num)
5078 /* Find the entry and clean it */
5079 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
5080 if (!ecore_rd(p_hwfn, p_ptt,
5081 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
5084 if (!ecore_rd(p_hwfn, p_ptt,
5085 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
5088 if (!(ecore_rd(p_hwfn, p_ptt,
5089 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
5090 i * sizeof(u32)) & (1 << type)))
5092 if (ecore_rd(p_hwfn, p_ptt,
5093 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5094 2 * i * sizeof(u32)) != low)
5096 if (ecore_rd(p_hwfn, p_ptt,
5097 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5098 (2 * i + 1) * sizeof(u32)) != high)
5101 ecore_wr(p_hwfn, p_ptt,
5102 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
5103 ecore_wr(p_hwfn, p_ptt,
5104 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
5105 i * sizeof(u32), 0);
5106 ecore_wr(p_hwfn, p_ptt,
5107 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
5108 i * sizeof(u32), 0);
5109 ecore_wr(p_hwfn, p_ptt,
5110 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5111 2 * i * sizeof(u32), 0);
5112 ecore_wr(p_hwfn, p_ptt,
5113 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5114 (2 * i + 1) * sizeof(u32), 0);
5118 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
5123 return ECORE_SUCCESS;
5127 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
5128 struct ecore_ptt *p_ptt,
5129 u16 source_port_or_eth_type,
5131 enum ecore_llh_port_filter_type_t type)
5133 u32 high, low, entry_num;
5134 enum _ecore_status_t rc = ECORE_SUCCESS;
5136 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
5137 &p_hwfn->p_dev->mf_bits))
5144 case ECORE_LLH_FILTER_ETHERTYPE:
5145 high = source_port_or_eth_type;
5147 case ECORE_LLH_FILTER_TCP_SRC_PORT:
5148 case ECORE_LLH_FILTER_UDP_SRC_PORT:
5149 low = source_port_or_eth_type << 16;
5151 case ECORE_LLH_FILTER_TCP_DEST_PORT:
5152 case ECORE_LLH_FILTER_UDP_DEST_PORT:
5155 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
5156 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
5157 low = (source_port_or_eth_type << 16) | dest_port;
5160 DP_NOTICE(p_hwfn, true,
5161 "Non valid LLH protocol filter type %d\n", type);
5165 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5166 rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
5169 if (rc != ECORE_SUCCESS) {
5170 DP_NOTICE(p_hwfn, false,
5171 "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n",
5172 type, source_port_or_eth_type, dest_port);
5176 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5177 "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n",
5178 type, source_port_or_eth_type, dest_port, entry_num);
5181 static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn,
5182 struct ecore_ptt *p_ptt)
5186 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
5189 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
5190 ecore_wr(p_hwfn, p_ptt,
5191 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
5192 i * sizeof(u32), 0);
5193 ecore_wr(p_hwfn, p_ptt,
5194 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5195 2 * i * sizeof(u32), 0);
5196 ecore_wr(p_hwfn, p_ptt,
5197 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5198 (2 * i + 1) * sizeof(u32), 0);
5202 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
5203 struct ecore_ptt *p_ptt)
5205 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
5206 &p_hwfn->p_dev->mf_bits) &&
5207 !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
5208 &p_hwfn->p_dev->mf_bits))
5211 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5212 ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt);
5215 enum _ecore_status_t
5216 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
5217 struct ecore_ptt *p_ptt)
5219 if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
5220 ecore_wr(p_hwfn, p_ptt,
5221 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
5222 1 << p_hwfn->abs_pf_id / 2);
5223 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
5224 return ECORE_SUCCESS;
5227 DP_NOTICE(p_hwfn, false,
5228 "This function can't be set as default\n");
5232 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
5233 struct ecore_ptt *p_ptt,
5234 u32 hw_addr, void *p_eth_qzone,
5235 osal_size_t eth_qzone_size,
5238 struct coalescing_timeset *p_coal_timeset;
5240 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
5241 DP_NOTICE(p_hwfn, true,
5242 "Coalescing configuration not enabled\n");
5246 p_coal_timeset = p_eth_qzone;
5247 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
5248 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
5249 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
5250 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
5252 return ECORE_SUCCESS;
5255 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
5256 u16 rx_coal, u16 tx_coal,
5259 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
5260 enum _ecore_status_t rc = ECORE_SUCCESS;
5261 struct ecore_ptt *p_ptt;
5263 /* TODO - Configuring a single queue's coalescing but
5264 * claiming all queues are abiding same configuration
5265 * for PF and VF both.
5268 if (IS_VF(p_hwfn->p_dev))
5269 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
5272 p_ptt = ecore_ptt_acquire(p_hwfn);
5277 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
5280 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
5284 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
5287 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
5290 ecore_ptt_release(p_hwfn, p_ptt);
5295 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
5296 struct ecore_ptt *p_ptt,
5298 struct ecore_queue_cid *p_cid)
5300 struct ustorm_eth_queue_zone eth_qzone;
5301 u8 timeset, timer_res;
5303 enum _ecore_status_t rc;
5305 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5306 if (coalesce <= 0x7F) {
5308 } else if (coalesce <= 0xFF) {
5310 } else if (coalesce <= 0x1FF) {
5313 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5316 timeset = (u8)(coalesce >> timer_res);
5318 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5319 p_cid->sb_igu_id, false);
5320 if (rc != ECORE_SUCCESS)
5323 address = BAR0_MAP_REG_USDM_RAM +
5324 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5326 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
5327 sizeof(struct ustorm_eth_queue_zone), timeset);
5328 if (rc != ECORE_SUCCESS)
5335 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
5336 struct ecore_ptt *p_ptt,
5338 struct ecore_queue_cid *p_cid)
5340 struct xstorm_eth_queue_zone eth_qzone;
5341 u8 timeset, timer_res;
5343 enum _ecore_status_t rc;
5345 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5346 if (coalesce <= 0x7F) {
5348 } else if (coalesce <= 0xFF) {
5350 } else if (coalesce <= 0x1FF) {
5353 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5357 timeset = (u8)(coalesce >> timer_res);
5359 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5360 p_cid->sb_igu_id, true);
5361 if (rc != ECORE_SUCCESS)
5364 address = BAR0_MAP_REG_XSDM_RAM +
5365 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5367 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
5368 sizeof(struct xstorm_eth_queue_zone), timeset);
5373 /* Calculate final WFQ values for all vports and configure it.
5374 * After this configuration each vport must have
5375 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
5377 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5378 struct ecore_ptt *p_ptt,
5381 struct init_qm_vport_params *vport_params;
5384 vport_params = p_hwfn->qm_info.qm_vport_params;
5386 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5387 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5389 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
5391 ecore_init_vport_wfq(p_hwfn, p_ptt,
5392 vport_params[i].first_tx_pq_id,
5393 vport_params[i].vport_wfq);
5397 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn)
5401 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5402 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
5405 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5406 struct ecore_ptt *p_ptt)
5408 struct init_qm_vport_params *vport_params;
5411 vport_params = p_hwfn->qm_info.qm_vport_params;
5413 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5414 ecore_init_wfq_default_param(p_hwfn);
5415 ecore_init_vport_wfq(p_hwfn, p_ptt,
5416 vport_params[i].first_tx_pq_id,
5417 vport_params[i].vport_wfq);
5421 /* This function performs several validations for WFQ
5422 * configuration and required min rate for a given vport
5423 * 1. req_rate must be greater than one percent of min_pf_rate.
5424 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
5425 * rates to get less than one percent of min_pf_rate.
5426 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
5428 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
5429 u16 vport_id, u32 req_rate,
5432 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
5433 int non_requested_count = 0, req_count = 0, i, num_vports;
5435 num_vports = p_hwfn->qm_info.num_vports;
5437 /* Accounting for the vports which are configured for WFQ explicitly */
5439 for (i = 0; i < num_vports; i++) {
5442 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
5444 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5445 total_req_min_rate += tmp_speed;
5449 /* Include current vport data as well */
5451 total_req_min_rate += req_rate;
5452 non_requested_count = num_vports - req_count;
5454 /* validate possible error cases */
5455 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
5456 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5457 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5458 vport_id, req_rate, min_pf_rate);
5462 /* TBD - for number of vports greater than 100 */
5463 if (num_vports > ECORE_WFQ_UNIT) {
5464 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5465 "Number of vports is greater than %d\n",
5470 if (total_req_min_rate > min_pf_rate) {
5471 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5472 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5473 total_req_min_rate, min_pf_rate);
5477 /* Data left for non requested vports */
5478 total_left_rate = min_pf_rate - total_req_min_rate;
5479 left_rate_per_vp = total_left_rate / non_requested_count;
5481 /* validate if non requested get < 1% of min bw */
5482 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
5483 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5484 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5485 left_rate_per_vp, min_pf_rate);
5489 /* now req_rate for given vport passes all scenarios.
5490 * assign final wfq rates to all vports.
5492 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5493 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5495 for (i = 0; i < num_vports; i++) {
5496 if (p_hwfn->qm_info.wfq_data[i].configured)
5499 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5502 return ECORE_SUCCESS;
5505 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
5506 struct ecore_ptt *p_ptt,
5507 u16 vp_id, u32 rate)
5509 struct ecore_mcp_link_state *p_link;
5510 int rc = ECORE_SUCCESS;
5512 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
5514 if (!p_link->min_pf_rate) {
5515 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5516 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5520 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5522 if (rc == ECORE_SUCCESS)
5523 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5524 p_link->min_pf_rate);
5526 DP_NOTICE(p_hwfn, false,
5527 "Validation failed while configuring min rate\n");
5532 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
5533 struct ecore_ptt *p_ptt,
5536 bool use_wfq = false;
5537 int rc = ECORE_SUCCESS;
5540 /* Validate all pre configured vports for wfq */
5541 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5544 if (!p_hwfn->qm_info.wfq_data[i].configured)
5547 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5550 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5551 if (rc != ECORE_SUCCESS) {
5552 DP_NOTICE(p_hwfn, false,
5553 "WFQ validation failed while configuring min rate\n");
5558 if (rc == ECORE_SUCCESS && use_wfq)
5559 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5561 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5566 /* Main API for ecore clients to configure vport min rate.
5567 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5568 * rate - Speed in Mbps needs to be assigned to a given vport.
5570 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
5572 int i, rc = ECORE_INVAL;
5574 /* TBD - for multiple hardware functions - that is 100 gig */
5575 if (ECORE_IS_CMT(p_dev)) {
5576 DP_NOTICE(p_dev, false,
5577 "WFQ configuration is not supported for this device\n");
5581 for_each_hwfn(p_dev, i) {
5582 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5583 struct ecore_ptt *p_ptt;
5585 p_ptt = ecore_ptt_acquire(p_hwfn);
5587 return ECORE_TIMEOUT;
5589 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5591 if (rc != ECORE_SUCCESS) {
5592 ecore_ptt_release(p_hwfn, p_ptt);
5596 ecore_ptt_release(p_hwfn, p_ptt);
5602 /* API to configure WFQ from mcp link change */
5603 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
5604 struct ecore_ptt *p_ptt,
5609 /* TBD - for multiple hardware functions - that is 100 gig */
5610 if (ECORE_IS_CMT(p_dev)) {
5611 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
5612 "WFQ configuration is not supported for this device\n");
5616 for_each_hwfn(p_dev, i) {
5617 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5619 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5624 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
5625 struct ecore_ptt *p_ptt,
5626 struct ecore_mcp_link_state *p_link,
5629 int rc = ECORE_SUCCESS;
5631 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5633 if (!p_link->line_speed && (max_bw != 100))
5636 p_link->speed = (p_link->line_speed * max_bw) / 100;
5637 p_hwfn->qm_info.pf_rl = p_link->speed;
5639 /* Since the limiter also affects Tx-switched traffic, we don't want it
5640 * to limit such traffic in case there's no actual limit.
5641 * In that case, set limit to imaginary high boundary.
5644 p_hwfn->qm_info.pf_rl = 100000;
5646 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5647 p_hwfn->qm_info.pf_rl);
5649 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5650 "Configured MAX bandwidth to be %08x Mb/sec\n",
5656 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5657 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
5659 int i, rc = ECORE_INVAL;
5661 if (max_bw < 1 || max_bw > 100) {
5662 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
5666 for_each_hwfn(p_dev, i) {
5667 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5668 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5669 struct ecore_mcp_link_state *p_link;
5670 struct ecore_ptt *p_ptt;
5672 p_link = &p_lead->mcp_info->link_output;
5674 p_ptt = ecore_ptt_acquire(p_hwfn);
5676 return ECORE_TIMEOUT;
5678 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5681 ecore_ptt_release(p_hwfn, p_ptt);
5683 if (rc != ECORE_SUCCESS)
5690 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
5691 struct ecore_ptt *p_ptt,
5692 struct ecore_mcp_link_state *p_link,
5695 int rc = ECORE_SUCCESS;
5697 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5698 p_hwfn->qm_info.pf_wfq = min_bw;
5700 if (!p_link->line_speed)
5703 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5705 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5707 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5708 "Configured MIN bandwidth to be %d Mb/sec\n",
5709 p_link->min_pf_rate);
5714 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5715 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
5717 int i, rc = ECORE_INVAL;
5719 if (min_bw < 1 || min_bw > 100) {
5720 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
5724 for_each_hwfn(p_dev, i) {
5725 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5726 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5727 struct ecore_mcp_link_state *p_link;
5728 struct ecore_ptt *p_ptt;
5730 p_link = &p_lead->mcp_info->link_output;
5732 p_ptt = ecore_ptt_acquire(p_hwfn);
5734 return ECORE_TIMEOUT;
5736 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5738 if (rc != ECORE_SUCCESS) {
5739 ecore_ptt_release(p_hwfn, p_ptt);
5743 if (p_link->min_pf_rate) {
5744 u32 min_rate = p_link->min_pf_rate;
5746 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
5751 ecore_ptt_release(p_hwfn, p_ptt);
5757 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
5759 struct ecore_mcp_link_state *p_link;
5761 p_link = &p_hwfn->mcp_info->link_output;
5763 if (p_link->min_pf_rate)
5764 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5766 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
5767 sizeof(*p_hwfn->qm_info.wfq_data) *
5768 p_hwfn->qm_info.num_vports);
5771 int ecore_device_num_engines(struct ecore_dev *p_dev)
5773 return ECORE_IS_BB(p_dev) ? 2 : 1;
5776 int ecore_device_num_ports(struct ecore_dev *p_dev)
5778 return p_dev->num_ports;
5781 void ecore_set_fw_mac_addr(__le16 *fw_msb,
5786 ((u8 *)fw_msb)[0] = mac[1];
5787 ((u8 *)fw_msb)[1] = mac[0];
5788 ((u8 *)fw_mid)[0] = mac[3];
5789 ((u8 *)fw_mid)[1] = mac[2];
5790 ((u8 *)fw_lsb)[0] = mac[5];
5791 ((u8 *)fw_lsb)[1] = mac[4];