drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dev_api.h"
  32 #include "ecore_dcbx.h"
  33 #include "ecore_l2.h"
  34
  35 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  36  * registers involved are not split and thus configuration is a race where
  37  * some of the PFs configuration might be lost.
  38  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  39  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  40  * there's more than a single compiled ecore component in system].
  41  */
  42 static osal_spinlock_t qm_lock;
  43 static bool qm_lock_init;
  44
  45 /******************** Doorbell Recovery *******************/
  46 /* The doorbell recovery mechanism consists of a list of entries which represent
  47  * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
  48  * entity needs to register with the mechanism and provide the parameters
  49  * describing it's doorbell, including a location where last used doorbell data
  50  * can be found. The doorbell execute function will traverse the list and
  51  * doorbell all of the registered entries.
  52  */
  53 struct ecore_db_recovery_entry {
  54         osal_list_entry_t       list_entry;
  55         void OSAL_IOMEM         *db_addr;
  56         void                    *db_data;
  57         enum ecore_db_rec_width db_width;
  58         enum ecore_db_rec_space db_space;
  59         u8                      hwfn_idx;
  60 };
  61
  62 /* display a single doorbell recovery entry */
  63 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
  64                                 struct ecore_db_recovery_entry *db_entry,
  65                                 const char *action)
  66 {
  67         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
  68                    action, db_entry, db_entry->db_addr, db_entry->db_data,
  69                    db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
  70                    db_entry->db_space == DB_REC_USER ? "user" : "kernel",
  71                    db_entry->hwfn_idx);
  72 }
  73
  74 /* doorbell address sanity (address within doorbell bar range) */
  75 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
  76                          void *db_data)
  77 {
  78         /* make sure doorbell address  is within the doorbell bar */
  79         if (db_addr < p_dev->doorbells || (u8 *)db_addr >
  80                         (u8 *)p_dev->doorbells + p_dev->db_size) {
  81                 OSAL_WARN(true,
  82                           "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
  83                           db_addr, p_dev->doorbells,
  84                           (u8 *)p_dev->doorbells + p_dev->db_size);
  85                 return false;
  86         }
  87
  88         /* make sure doorbell data pointer is not null */
  89         if (!db_data) {
  90                 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
  91                 return false;
  92         }
  93
  94         return true;
  95 }
  96
  97 /* find hwfn according to the doorbell address */
  98 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
  99                                           void OSAL_IOMEM *db_addr)
 100 {
 101         struct ecore_hwfn *p_hwfn;
 102
 103         /* In CMT doorbell bar is split down the middle between engine 0 and
 104          * enigne 1
 105          */
 106         if (ECORE_IS_CMT(p_dev))
 107                 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
 108                         &p_dev->hwfns[0] : &p_dev->hwfns[1];
 109         else
 110                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
 111
 112         return p_hwfn;
 113 }
 114
 115 /* add a new entry to the doorbell recovery mechanism */
 116 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
 117                                            void OSAL_IOMEM *db_addr,
 118                                            void *db_data,
 119                                            enum ecore_db_rec_width db_width,
 120                                            enum ecore_db_rec_space db_space)
 121 {
 122         struct ecore_db_recovery_entry *db_entry;
 123         struct ecore_hwfn *p_hwfn;
 124
 125         /* shortcircuit VFs, for now */
 126         if (IS_VF(p_dev)) {
 127                 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
 128                 return ECORE_SUCCESS;
 129         }
 130
 131         /* sanitize doorbell address */
 132         if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
 133                 return ECORE_INVAL;
 134
 135         /* obtain hwfn from doorbell address */
 136         p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
 137
 138         /* create entry */
 139         db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
 140         if (!db_entry) {
 141                 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
 142                 return ECORE_NOMEM;
 143         }
 144
 145         /* populate entry */
 146         db_entry->db_addr = db_addr;
 147         db_entry->db_data = db_data;
 148         db_entry->db_width = db_width;
 149         db_entry->db_space = db_space;
 150         db_entry->hwfn_idx = p_hwfn->my_id;
 151
 152         /* display */
 153         ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
 154
 155         /* protect the list */
 156         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 157         OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
 158                             &p_hwfn->db_recovery_info.list);
 159         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 160
 161         return ECORE_SUCCESS;
 162 }
 163
 164 /* remove an entry from the doorbell recovery mechanism */
 165 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
 166                                            void OSAL_IOMEM *db_addr,
 167                                            void *db_data)
 168 {
 169         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 170         enum _ecore_status_t rc = ECORE_INVAL;
 171         struct ecore_hwfn *p_hwfn;
 172
 173         /* shortcircuit VFs, for now */
 174         if (IS_VF(p_dev)) {
 175                 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
 176                 return ECORE_SUCCESS;
 177         }
 178
 179         /* sanitize doorbell address */
 180         if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
 181                 return ECORE_INVAL;
 182
 183         /* obtain hwfn from doorbell address */
 184         p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
 185
 186         /* protect the list */
 187         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 188         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 189                                  &p_hwfn->db_recovery_info.list,
 190                                  list_entry,
 191                                  struct ecore_db_recovery_entry) {
 192                 /* search according to db_data addr since db_addr is not unique
 193                  * (roce)
 194                  */
 195                 if (db_entry->db_data == db_data) {
 196                         ecore_db_recovery_dp_entry(p_hwfn, db_entry,
 197                                                    "Deleting");
 198                         OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
 199                                                &p_hwfn->db_recovery_info.list);
 200                         rc = ECORE_SUCCESS;
 201                         break;
 202                 }
 203         }
 204
 205         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 206
 207         if (rc == ECORE_INVAL)
 208                 /*OSAL_WARN(true,*/
 209                 DP_NOTICE(p_hwfn, false,
 210                           "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
 211                           db_data, db_addr);
 212         else
 213                 OSAL_FREE(p_dev, db_entry);
 214
 215         return rc;
 216 }
 217
 218 /* initialize the doorbell recovery mechanism */
 219 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
 220 {
 221         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
 222
 223         /* make sure db_size was set in p_dev */
 224         if (!p_hwfn->p_dev->db_size) {
 225                 DP_ERR(p_hwfn->p_dev, "db_size not set\n");
 226                 return ECORE_INVAL;
 227         }
 228
 229         OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
 230 #ifdef CONFIG_ECORE_LOCK_ALLOC
 231         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock);
 232 #endif
 233         OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
 234         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 235
 236         return ECORE_SUCCESS;
 237 }
 238
 239 /* destroy the doorbell recovery mechanism */
 240 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
 241 {
 242         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 243
 244         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
 245         if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
 246                 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
 247                 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
 248                         db_entry = OSAL_LIST_FIRST_ENTRY(
 249                                                 &p_hwfn->db_recovery_info.list,
 250                                                 struct ecore_db_recovery_entry,
 251                                                 list_entry);
 252                         ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
 253                         OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
 254                                                &p_hwfn->db_recovery_info.list);
 255                         OSAL_FREE(p_hwfn->p_dev, db_entry);
 256                 }
 257         }
 258 #ifdef CONFIG_ECORE_LOCK_ALLOC
 259         OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
 260 #endif
 261         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 262 }
 263
 264 /* print the content of the doorbell recovery mechanism */
 265 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
 266 {
 267         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 268
 269         DP_NOTICE(p_hwfn, false,
 270                   "Dispalying doorbell recovery database. Counter was %d\n",
 271                   p_hwfn->db_recovery_info.db_recovery_counter);
 272
 273         /* protect the list */
 274         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 275         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 276                                  &p_hwfn->db_recovery_info.list,
 277                                  list_entry,
 278                                  struct ecore_db_recovery_entry) {
 279                 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
 280         }
 281
 282         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 283 }
 284
 285 /* ring the doorbell of a single doorbell recovery entry */
 286 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
 287                             struct ecore_db_recovery_entry *db_entry,
 288                             enum ecore_db_rec_exec db_exec)
 289 {
 290         /* Print according to width */
 291         if (db_entry->db_width == DB_REC_WIDTH_32B)
 292                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
 293                            db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
 294                            db_entry->db_addr, *(u32 *)db_entry->db_data);
 295         else
 296                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n",
 297                            db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
 298                            db_entry->db_addr,
 299                            *(unsigned long *)(db_entry->db_data));
 300
 301         /* Sanity */
 302         if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
 303                                  db_entry->db_data))
 304                 return;
 305
 306         /* Flush the write combined buffer. Since there are multiple doorbelling
 307          * entities using the same address, if we don't flush, a transaction
 308          * could be lost.
 309          */
 310         OSAL_WMB(p_hwfn->p_dev);
 311
 312         /* Ring the doorbell */
 313         if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
 314                 if (db_entry->db_width == DB_REC_WIDTH_32B)
 315                         DIRECT_REG_WR(p_hwfn, db_entry->db_addr,
 316                                       *(u32 *)(db_entry->db_data));
 317                 else
 318                         DIRECT_REG_WR64(p_hwfn, db_entry->db_addr,
 319                                         *(u64 *)(db_entry->db_data));
 320         }
 321
 322         /* Flush the write combined buffer. Next doorbell may come from a
 323          * different entity to the same address...
 324          */
 325         OSAL_WMB(p_hwfn->p_dev);
 326 }
 327
 328 /* traverse the doorbell recovery entry list and ring all the doorbells */
 329 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
 330                                enum ecore_db_rec_exec db_exec)
 331 {
 332         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 333
 334         if (db_exec != DB_REC_ONCE) {
 335                 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
 336                           p_hwfn->db_recovery_info.db_recovery_counter);
 337
 338                 /* track amount of times recovery was executed */
 339                 p_hwfn->db_recovery_info.db_recovery_counter++;
 340         }
 341
 342         /* protect the list */
 343         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 344         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 345                                  &p_hwfn->db_recovery_info.list,
 346                                  list_entry,
 347                                  struct ecore_db_recovery_entry) {
 348                 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
 349                 if (db_exec == DB_REC_ONCE)
 350                         break;
 351         }
 352
 353         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 354 }
 355 /******************** Doorbell Recovery end ****************/
 356
 357 /* Configurable */
 358 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
 359                                          * load the driver. The number was
 360                                          * arbitrarily set.
 361                                          */
 362
 363 /* Derived */
 364 #define ECORE_MIN_PWM_REGION    (ECORE_WID_SIZE * ECORE_MIN_DPIS)
 365
 366 enum BAR_ID {
 367         BAR_ID_0,               /* used for GRC */
 368         BAR_ID_1                /* Used for doorbells */
 369 };
 370
 371 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
 372                              struct ecore_ptt *p_ptt,
 373                              enum BAR_ID bar_id)
 374 {
 375         u32 bar_reg = (bar_id == BAR_ID_0 ?
 376                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
 377         u32 val;
 378
 379         if (IS_VF(p_hwfn->p_dev)) {
 380                 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
 381                  * read from actual register, but we're currently not using
 382                  * it for actual doorbelling.
 383                  */
 384                 return 1 << 17;
 385         }
 386
 387         val = ecore_rd(p_hwfn, p_ptt, bar_reg);
 388         if (val)
 389                 return 1 << (val + 15);
 390
 391         /* The above registers were updated in the past only in CMT mode. Since
 392          * they were found to be useful MFW started updating them from 8.7.7.0.
 393          * In older MFW versions they are set to 0 which means disabled.
 394          */
 395         if (ECORE_IS_CMT(p_hwfn->p_dev)) {
 396                 DP_INFO(p_hwfn,
 397                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
 398                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
 399         } else {
 400                 DP_INFO(p_hwfn,
 401                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
 402                 val = 512 * 1024;
 403         }
 404
 405         return val;
 406 }
 407
 408 void ecore_init_dp(struct ecore_dev *p_dev,
 409                    u32 dp_module, u8 dp_level, void *dp_ctx)
 410 {
 411         u32 i;
 412
 413         p_dev->dp_level = dp_level;
 414         p_dev->dp_module = dp_module;
 415         p_dev->dp_ctx = dp_ctx;
 416         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 417                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 418
 419                 p_hwfn->dp_level = dp_level;
 420                 p_hwfn->dp_module = dp_module;
 421                 p_hwfn->dp_ctx = dp_ctx;
 422         }
 423 }
 424
 425 void ecore_init_struct(struct ecore_dev *p_dev)
 426 {
 427         u8 i;
 428
 429         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 430                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 431
 432                 p_hwfn->p_dev = p_dev;
 433                 p_hwfn->my_id = i;
 434                 p_hwfn->b_active = false;
 435
 436 #ifdef CONFIG_ECORE_LOCK_ALLOC
 437                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 438 #endif
 439                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 440         }
 441
 442         /* hwfn 0 is always active */
 443         p_dev->hwfns[0].b_active = true;
 444
 445         /* set the default cache alignment to 128 (may be overridden later) */
 446         p_dev->cache_shift = 7;
 447 }
 448
 449 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 450 {
 451         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 452
 453         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 454         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 455         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 456         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 457 }
 458
 459 void ecore_resc_free(struct ecore_dev *p_dev)
 460 {
 461         int i;
 462
 463         if (IS_VF(p_dev)) {
 464                 for_each_hwfn(p_dev, i)
 465                         ecore_l2_free(&p_dev->hwfns[i]);
 466                 return;
 467         }
 468
 469         OSAL_FREE(p_dev, p_dev->fw_data);
 470
 471         OSAL_FREE(p_dev, p_dev->reset_stats);
 472
 473         for_each_hwfn(p_dev, i) {
 474                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 475
 476                 ecore_cxt_mngr_free(p_hwfn);
 477                 ecore_qm_info_free(p_hwfn);
 478                 ecore_spq_free(p_hwfn);
 479                 ecore_eq_free(p_hwfn);
 480                 ecore_consq_free(p_hwfn);
 481                 ecore_int_free(p_hwfn);
 482                 ecore_iov_free(p_hwfn);
 483                 ecore_l2_free(p_hwfn);
 484                 ecore_dmae_info_free(p_hwfn);
 485                 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 486                 /* @@@TBD Flush work-queue ? */
 487
 488                 /* destroy doorbell recovery mechanism */
 489                 ecore_db_recovery_teardown(p_hwfn);
 490         }
 491 }
 492
 493 /******************** QM initialization *******************/
 494
 495 /* bitmaps for indicating active traffic classes.
 496  * Special case for Arrowhead 4 port
 497  */
 498 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
 499 #define ACTIVE_TCS_BMAP 0x9f
 500 /* 0..3 actually used, OOO and high priority stuff all use 3 */
 501 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 502
 503 /* determines the physical queue flags for a given PF. */
 504 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
 505 {
 506         u32 flags;
 507
 508         /* common flags */
 509         flags = PQ_FLAGS_LB;
 510
 511         /* feature flags */
 512         if (IS_ECORE_SRIOV(p_hwfn->p_dev))
 513                 flags |= PQ_FLAGS_VFS;
 514
 515         /* protocol flags */
 516         switch (p_hwfn->hw_info.personality) {
 517         case ECORE_PCI_ETH:
 518                 flags |= PQ_FLAGS_MCOS;
 519                 break;
 520         case ECORE_PCI_FCOE:
 521                 flags |= PQ_FLAGS_OFLD;
 522                 break;
 523         case ECORE_PCI_ISCSI:
 524                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 525                 break;
 526         case ECORE_PCI_ETH_ROCE:
 527                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
 528                 break;
 529         case ECORE_PCI_ETH_IWARP:
 530                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 531                          PQ_FLAGS_OFLD;
 532                 break;
 533         default:
 534                 DP_ERR(p_hwfn, "unknown personality %d\n",
 535                        p_hwfn->hw_info.personality);
 536                 return 0;
 537         }
 538         return flags;
 539 }
 540
 541 /* Getters for resource amounts necessary for qm initialization */
 542 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
 543 {
 544         return p_hwfn->hw_info.num_hw_tc;
 545 }
 546
 547 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
 548 {
 549         return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
 550                         p_hwfn->p_dev->p_iov_info->total_vfs : 0;
 551 }
 552
 553 #define NUM_DEFAULT_RLS 1
 554
 555 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
 556 {
 557         u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 558
 559         /* @DPDK */
 560         /* num RLs can't exceed resource amount of rls or vports or the
 561          * dcqcn qps
 562          */
 563         num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 564                                      (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
 565
 566         /* make sure after we reserve the default and VF rls we'll have
 567          * something left
 568          */
 569         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
 570                 DP_NOTICE(p_hwfn, false,
 571                           "no rate limiters left for PF rate limiting"
 572                           " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
 573                 return 0;
 574         }
 575
 576         /* subtract rls necessary for VFs and one default one for the PF */
 577         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 578
 579         return num_pf_rls;
 580 }
 581
 582 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
 583 {
 584         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 585
 586         /* all pqs share the same vport (hence the 1 below), except for vfs
 587          * and pf_rl pqs
 588          */
 589         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 590                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 591                (!!(PQ_FLAGS_VFS & pq_flags)) *
 592                 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
 593 }
 594
 595 /* calc amount of PQs according to the requested flags */
 596 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
 597 {
 598         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 599
 600         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 601                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 602                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 603                 ecore_init_qm_get_num_tcs(p_hwfn) +
 604                (!!(PQ_FLAGS_LB & pq_flags)) +
 605                (!!(PQ_FLAGS_OOO & pq_flags)) +
 606                (!!(PQ_FLAGS_ACK & pq_flags)) +
 607                (!!(PQ_FLAGS_OFLD & pq_flags)) +
 608                (!!(PQ_FLAGS_VFS & pq_flags)) *
 609                 ecore_init_qm_get_num_vfs(p_hwfn);
 610 }
 611
 612 /* initialize the top level QM params */
 613 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
 614 {
 615         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 616         bool four_port;
 617
 618         /* pq and vport bases for this PF */
 619         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 620         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 621
 622         /* rate limiting and weighted fair queueing are always enabled */
 623         qm_info->vport_rl_en = 1;
 624         qm_info->vport_wfq_en = 1;
 625
 626         /* TC config is different for AH 4 port */
 627         four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;
 628
 629         /* in AH 4 port we have fewer TCs per port */
 630         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 631                                                      NUM_OF_PHYS_TCS;
 632
 633         /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
 634          * 4 otherwise
 635          */
 636         if (!qm_info->ooo_tc)
 637                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 638                                               DCBX_TCP_OOO_TC;
 639 }
 640
 641 /* initialize qm vport params */
 642 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
 643 {
 644         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 645         u8 i;
 646
 647         /* all vports participate in weighted fair queueing */
 648         for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
 649                 qm_info->qm_vport_params[i].vport_wfq = 1;
 650 }
 651
 652 /* initialize qm port params */
 653 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
 654 {
 655         /* Initialize qm port parameters */
 656         u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
 657
 658         /* indicate how ooo and high pri traffic is dealt with */
 659         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 660                 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
 661
 662         for (i = 0; i < num_ports; i++) {
 663                 struct init_qm_port_params *p_qm_port =
 664                         &p_hwfn->qm_info.qm_port_params[i];
 665
 666                 p_qm_port->active = 1;
 667                 p_qm_port->active_phys_tcs = active_phys_tcs;
 668                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES_E4 / num_ports;
 669                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 670         }
 671 }
 672
 673 /* Reset the params which must be reset for qm init. QM init may be called as
 674  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 675  * params may be affected by the init but would simply recalculate to the same
 676  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 677  * affected as these amounts stay the same.
 678  */
 679 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
 680 {
 681         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 682
 683         qm_info->num_pqs = 0;
 684         qm_info->num_vports = 0;
 685         qm_info->num_pf_rls = 0;
 686         qm_info->num_vf_pqs = 0;
 687         qm_info->first_vf_pq = 0;
 688         qm_info->first_mcos_pq = 0;
 689         qm_info->first_rl_pq = 0;
 690 }
 691
 692 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
 693 {
 694         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 695
 696         qm_info->num_vports++;
 697
 698         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 699                 DP_ERR(p_hwfn,
 700                        "vport overflow! qm_info->num_vports %d,"
 701                        " qm_init_get_num_vports() %d\n",
 702                        qm_info->num_vports,
 703                        ecore_init_qm_get_num_vports(p_hwfn));
 704 }
 705
 706 /* initialize a single pq and manage qm_info resources accounting.
 707  * The pq_init_flags param determines whether the PQ is rate limited
 708  * (for VF or PF)
 709  * and whether a new vport is allocated to the pq or not (i.e. vport will be
 710  * shared)
 711  */
 712
 713 /* flags for pq init */
 714 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 715 #define PQ_INIT_PF_RL           (1 << 1)
 716 #define PQ_INIT_VF_RL           (1 << 2)
 717
 718 /* defines for pq init */
 719 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 720 #define PQ_INIT_DEFAULT_TC              0
 721 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 722
 723 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
 724                              struct ecore_qm_info *qm_info,
 725                              u8 tc, u32 pq_init_flags)
 726 {
 727         u16 pq_idx = qm_info->num_pqs, max_pq =
 728                                         ecore_init_qm_get_num_pqs(p_hwfn);
 729
 730         if (pq_idx > max_pq)
 731                 DP_ERR(p_hwfn,
 732                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 733
 734         /* init pq params */
 735         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 736                                                  qm_info->num_vports;
 737         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 738         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 739         qm_info->qm_pq_params[pq_idx].rl_valid =
 740                 (pq_init_flags & PQ_INIT_PF_RL ||
 741                  pq_init_flags & PQ_INIT_VF_RL);
 742
 743         /* qm params accounting */
 744         qm_info->num_pqs++;
 745         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 746                 qm_info->num_vports++;
 747
 748         if (pq_init_flags & PQ_INIT_PF_RL)
 749                 qm_info->num_pf_rls++;
 750
 751         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 752                 DP_ERR(p_hwfn,
 753                        "vport overflow! qm_info->num_vports %d,"
 754                        " qm_init_get_num_vports() %d\n",
 755                        qm_info->num_vports,
 756                        ecore_init_qm_get_num_vports(p_hwfn));
 757
 758         if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
 759                 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
 760                        " qm_init_get_num_pf_rls() %d\n",
 761                        qm_info->num_pf_rls,
 762                        ecore_init_qm_get_num_pf_rls(p_hwfn));
 763 }
 764
 765 /* get pq index according to PQ_FLAGS */
 766 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
 767                                              u32 pq_flags)
 768 {
 769         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 770
 771         /* Can't have multiple flags set here */
 772         if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
 773                                 sizeof(pq_flags)) > 1)
 774                 goto err;
 775
 776         switch (pq_flags) {
 777         case PQ_FLAGS_RLS:
 778                 return &qm_info->first_rl_pq;
 779         case PQ_FLAGS_MCOS:
 780                 return &qm_info->first_mcos_pq;
 781         case PQ_FLAGS_LB:
 782                 return &qm_info->pure_lb_pq;
 783         case PQ_FLAGS_OOO:
 784                 return &qm_info->ooo_pq;
 785         case PQ_FLAGS_ACK:
 786                 return &qm_info->pure_ack_pq;
 787         case PQ_FLAGS_OFLD:
 788                 return &qm_info->offload_pq;
 789         case PQ_FLAGS_VFS:
 790                 return &qm_info->first_vf_pq;
 791         default:
 792                 goto err;
 793         }
 794
 795 err:
 796         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 797         return OSAL_NULL;
 798 }
 799
 800 /* save pq index in qm info */
 801 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
 802                                   u32 pq_flags, u16 pq_val)
 803 {
 804         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 805
 806         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 807 }
 808
 809 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 810 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
 811 {
 812         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 813
 814         return *base_pq_idx + CM_TX_PQ_BASE;
 815 }
 816
 817 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
 818 {
 819         u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
 820
 821         if (tc > max_tc)
 822                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 823
 824         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 825 }
 826
 827 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
 828 {
 829         u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
 830
 831         if (vf > max_vf)
 832                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 833
 834         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 835 }
 836
 837 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
 838 {
 839         u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
 840
 841         if (rl > max_rl)
 842                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 843
 844         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 845 }
 846
 847 /* Functions for creating specific types of pqs */
 848 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
 849 {
 850         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 851
 852         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 853                 return;
 854
 855         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 856         ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 857 }
 858
 859 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
 860 {
 861         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 862
 863         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 864                 return;
 865
 866         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 867         ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 868 }
 869
 870 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
 871 {
 872         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 873
 874         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 875                 return;
 876
 877         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 878         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 879 }
 880
 881 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
 882 {
 883         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 884
 885         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 886                 return;
 887
 888         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 889         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 890 }
 891
 892 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
 893 {
 894         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 895         u8 tc_idx;
 896
 897         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 898                 return;
 899
 900         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 901         for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 902                 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 903 }
 904
 905 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
 906 {
 907         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 908         u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 909
 910         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 911                 return;
 912
 913         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 914
 915         qm_info->num_vf_pqs = num_vfs;
 916         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 917                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
 918                                  PQ_INIT_VF_RL);
 919 }
 920
 921 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
 922 {
 923         u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
 924         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 925
 926         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 927                 return;
 928
 929         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 930         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 931                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
 932                                  PQ_INIT_PF_RL);
 933 }
 934
 935 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
 936 {
 937         /* rate limited pqs, must come first (FW assumption) */
 938         ecore_init_qm_rl_pqs(p_hwfn);
 939
 940         /* pqs for multi cos */
 941         ecore_init_qm_mcos_pqs(p_hwfn);
 942
 943         /* pure loopback pq */
 944         ecore_init_qm_lb_pq(p_hwfn);
 945
 946         /* out of order pq */
 947         ecore_init_qm_ooo_pq(p_hwfn);
 948
 949         /* pure ack pq */
 950         ecore_init_qm_pure_ack_pq(p_hwfn);
 951
 952         /* pq for offloaded protocol */
 953         ecore_init_qm_offload_pq(p_hwfn);
 954
 955         /* done sharing vports */
 956         ecore_init_qm_advance_vport(p_hwfn);
 957
 958         /* pqs for vfs */
 959         ecore_init_qm_vf_pqs(p_hwfn);
 960 }
 961
 962 /* compare values of getters against resources amounts */
 963 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
 964 {
 965         if (ecore_init_qm_get_num_vports(p_hwfn) >
 966             RESC_NUM(p_hwfn, ECORE_VPORT)) {
 967                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 968                 return ECORE_INVAL;
 969         }
 970
 971         if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
 972                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 973                 return ECORE_INVAL;
 974         }
 975
 976         return ECORE_SUCCESS;
 977 }
 978
 979 /*
 980  * Function for verbose printing of the qm initialization results
 981  */
 982 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
 983 {
 984         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 985         struct init_qm_vport_params *vport;
 986         struct init_qm_port_params *port;
 987         struct init_qm_pq_params *pq;
 988         int i, tc;
 989
 990         /* top level params */
 991         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 992                    "qm init top level params: start_pq %d, start_vport %d,"
 993                    " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 994                    qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
 995                    qm_info->offload_pq, qm_info->pure_ack_pq);
 996         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 997                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
 998                    " num_vports %d, max_phys_tcs_per_port %d\n",
 999                    qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
1000                    qm_info->num_vf_pqs, qm_info->num_vports,
1001                    qm_info->max_phys_tcs_per_port);
1002         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1003                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
1004                    " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
1005                    qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
1006                    qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
1007                    qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
1008
1009         /* port table */
1010         for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
1011                 port = &qm_info->qm_port_params[i];
1012                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1013                            "port idx %d, active %d, active_phys_tcs %d,"
1014                            " num_pbf_cmd_lines %d, num_btb_blocks %d,"
1015                            " reserved %d\n",
1016                            i, port->active, port->active_phys_tcs,
1017                            port->num_pbf_cmd_lines, port->num_btb_blocks,
1018                            port->reserved);
1019         }
1020
1021         /* vport table */
1022         for (i = 0; i < qm_info->num_vports; i++) {
1023                 vport = &qm_info->qm_vport_params[i];
1024                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1025                            "vport idx %d, vport_rl %d, wfq %d,"
1026                            " first_tx_pq_id [ ",
1027                            qm_info->start_vport + i, vport->vport_rl,
1028                            vport->vport_wfq);
1029                 for (tc = 0; tc < NUM_OF_TCS; tc++)
1030                         DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
1031                                    vport->first_tx_pq_id[tc]);
1032                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
1033         }
1034
1035         /* pq table */
1036         for (i = 0; i < qm_info->num_pqs; i++) {
1037                 pq = &qm_info->qm_pq_params[i];
1038                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1039                            "pq idx %d, vport_id %d, tc %d, wrr_grp %d,"
1040                            " rl_valid %d\n",
1041                            qm_info->start_pq + i, pq->vport_id, pq->tc_id,
1042                            pq->wrr_group, pq->rl_valid);
1043         }
1044 }
1045
1046 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
1047 {
1048         /* reset params required for init run */
1049         ecore_init_qm_reset_params(p_hwfn);
1050
1051         /* init QM top level params */
1052         ecore_init_qm_params(p_hwfn);
1053
1054         /* init QM port params */
1055         ecore_init_qm_port_params(p_hwfn);
1056
1057         /* init QM vport params */
1058         ecore_init_qm_vport_params(p_hwfn);
1059
1060         /* init QM physical queue params */
1061         ecore_init_qm_pq_params(p_hwfn);
1062
1063         /* display all that init */
1064         ecore_dp_init_qm_params(p_hwfn);
1065 }
1066
1067 /* This function reconfigures the QM pf on the fly.
1068  * For this purpose we:
1069  * 1. reconfigure the QM database
1070  * 2. set new values to runtime array
1071  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
1072  * 4. activate init tool in QM_PF stage
1073  * 5. send an sdm_qm_cmd through rbc interface to release the QM
1074  */
1075 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
1076                                      struct ecore_ptt *p_ptt)
1077 {
1078         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1079         bool b_rc;
1080         enum _ecore_status_t rc;
1081
1082         /* initialize ecore's qm data structure */
1083         ecore_init_qm_info(p_hwfn);
1084
1085         /* stop PF's qm queues */
1086         OSAL_SPIN_LOCK(&qm_lock);
1087         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
1088                                       qm_info->start_pq, qm_info->num_pqs);
1089         OSAL_SPIN_UNLOCK(&qm_lock);
1090         if (!b_rc)
1091                 return ECORE_INVAL;
1092
1093         /* clear the QM_PF runtime phase leftovers from previous init */
1094         ecore_init_clear_rt_data(p_hwfn);
1095
1096         /* prepare QM portion of runtime array */
1097         ecore_qm_init_pf(p_hwfn, p_ptt);
1098
1099         /* activate init tool on runtime array */
1100         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
1101                             p_hwfn->hw_info.hw_mode);
1102         if (rc != ECORE_SUCCESS)
1103                 return rc;
1104
1105         /* start PF's qm queues */
1106         OSAL_SPIN_LOCK(&qm_lock);
1107         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
1108                                       qm_info->start_pq, qm_info->num_pqs);
1109         OSAL_SPIN_UNLOCK(&qm_lock);
1110         if (!b_rc)
1111                 return ECORE_INVAL;
1112
1113         return ECORE_SUCCESS;
1114 }
1115
1116 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
1117 {
1118         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1119         enum _ecore_status_t rc;
1120
1121         rc = ecore_init_qm_sanity(p_hwfn);
1122         if (rc != ECORE_SUCCESS)
1123                 goto alloc_err;
1124
1125         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1126                                             sizeof(struct init_qm_pq_params) *
1127                                             ecore_init_qm_get_num_pqs(p_hwfn));
1128         if (!qm_info->qm_pq_params)
1129                 goto alloc_err;
1130
1131         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1132                                        sizeof(struct init_qm_vport_params) *
1133                                        ecore_init_qm_get_num_vports(p_hwfn));
1134         if (!qm_info->qm_vport_params)
1135                 goto alloc_err;
1136
1137         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1138                                       sizeof(struct init_qm_port_params) *
1139                                       p_hwfn->p_dev->num_ports_in_engine);
1140         if (!qm_info->qm_port_params)
1141                 goto alloc_err;
1142
1143         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1144                                         sizeof(struct ecore_wfq_data) *
1145                                         ecore_init_qm_get_num_vports(p_hwfn));
1146         if (!qm_info->wfq_data)
1147                 goto alloc_err;
1148
1149         return ECORE_SUCCESS;
1150
1151 alloc_err:
1152         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
1153         ecore_qm_info_free(p_hwfn);
1154         return ECORE_NOMEM;
1155 }
1156 /******************** End QM initialization ***************/
1157
1158 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
1159 {
1160         enum _ecore_status_t rc = ECORE_SUCCESS;
1161         int i;
1162
1163         if (IS_VF(p_dev)) {
1164                 for_each_hwfn(p_dev, i) {
1165                         rc = ecore_l2_alloc(&p_dev->hwfns[i]);
1166                         if (rc != ECORE_SUCCESS)
1167                                 return rc;
1168                 }
1169                 return rc;
1170         }
1171
1172         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1173                                      sizeof(*p_dev->fw_data));
1174         if (!p_dev->fw_data)
1175                 return ECORE_NOMEM;
1176
1177         for_each_hwfn(p_dev, i) {
1178                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1179                 u32 n_eqes, num_cons;
1180
1181                 /* initialize the doorbell recovery mechanism */
1182                 rc = ecore_db_recovery_setup(p_hwfn);
1183                 if (rc)
1184                         goto alloc_err;
1185
1186                 /* First allocate the context manager structure */
1187                 rc = ecore_cxt_mngr_alloc(p_hwfn);
1188                 if (rc)
1189                         goto alloc_err;
1190
1191                 /* Set the HW cid/tid numbers (in the context manager)
1192                  * Must be done prior to any further computations.
1193                  */
1194                 rc = ecore_cxt_set_pf_params(p_hwfn);
1195                 if (rc)
1196                         goto alloc_err;
1197
1198                 rc = ecore_alloc_qm_data(p_hwfn);
1199                 if (rc)
1200                         goto alloc_err;
1201
1202                 /* init qm info */
1203                 ecore_init_qm_info(p_hwfn);
1204
1205                 /* Compute the ILT client partition */
1206                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
1207                 if (rc)
1208                         goto alloc_err;
1209
1210                 /* CID map / ILT shadow table / T2
1211                  * The talbes sizes are determined by the computations above
1212                  */
1213                 rc = ecore_cxt_tables_alloc(p_hwfn);
1214                 if (rc)
1215                         goto alloc_err;
1216
1217                 /* SPQ, must follow ILT because initializes SPQ context */
1218                 rc = ecore_spq_alloc(p_hwfn);
1219                 if (rc)
1220                         goto alloc_err;
1221
1222                 /* SP status block allocation */
1223                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
1224                                                            RESERVED_PTT_DPC);
1225
1226                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1227                 if (rc)
1228                         goto alloc_err;
1229
1230                 rc = ecore_iov_alloc(p_hwfn);
1231                 if (rc)
1232                         goto alloc_err;
1233
1234                 /* EQ */
1235                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
1236                 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
1237                         /* Calculate the EQ size
1238                          * ---------------------
1239                          * Each ICID may generate up to one event at a time i.e.
1240                          * the event must be handled/cleared before a new one
1241                          * can be generated. We calculate the sum of events per
1242                          * protocol and create an EQ deep enough to handle the
1243                          * worst case:
1244                          * - Core - according to SPQ.
1245                          * - RoCE - per QP there are a couple of ICIDs, one
1246                          *        responder and one requester, each can
1247                          *        generate an EQE => n_eqes_qp = 2 * n_qp.
1248                          *        Each CQ can generate an EQE. There are 2 CQs
1249                          *        per QP => n_eqes_cq = 2 * n_qp.
1250                          *        Hence the RoCE total is 4 * n_qp or
1251                          *        2 * num_cons.
1252                          * - ENet - There can be up to two events per VF. One
1253                          *        for VF-PF channel and another for VF FLR
1254                          *        initial cleanup. The number of VFs is
1255                          *        bounded by MAX_NUM_VFS_BB, and is much
1256                          *        smaller than RoCE's so we avoid exact
1257                          *        calculation.
1258                          */
1259                         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
1260                                 num_cons =
1261                                     ecore_cxt_get_proto_cid_count(
1262                                                 p_hwfn,
1263                                                 PROTOCOLID_ROCE,
1264                                                 OSAL_NULL);
1265                                 num_cons *= 2;
1266                         } else {
1267                                 num_cons = ecore_cxt_get_proto_cid_count(
1268                                                 p_hwfn,
1269                                                 PROTOCOLID_IWARP,
1270                                                 OSAL_NULL);
1271                         }
1272                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1273                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
1274                         num_cons =
1275                             ecore_cxt_get_proto_cid_count(p_hwfn,
1276                                                           PROTOCOLID_ISCSI,
1277                                                           OSAL_NULL);
1278                         n_eqes += 2 * num_cons;
1279                 }
1280
1281                 if (n_eqes > 0xFFFF) {
1282                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
1283                                        "The maximum of a u16 chain is 0x%x\n",
1284                                n_eqes, 0xFFFF);
1285                         goto alloc_no_mem;
1286                 }
1287
1288                 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
1289                 if (rc)
1290                         goto alloc_err;
1291
1292                 rc = ecore_consq_alloc(p_hwfn);
1293                 if (rc)
1294                         goto alloc_err;
1295
1296                 rc = ecore_l2_alloc(p_hwfn);
1297                 if (rc != ECORE_SUCCESS)
1298                         goto alloc_err;
1299
1300                 /* DMA info initialization */
1301                 rc = ecore_dmae_info_alloc(p_hwfn);
1302                 if (rc) {
1303                         DP_NOTICE(p_hwfn, true,
1304                                   "Failed to allocate memory for dmae_info"
1305                                   " structure\n");
1306                         goto alloc_err;
1307                 }
1308
1309                 /* DCBX initialization */
1310                 rc = ecore_dcbx_info_alloc(p_hwfn);
1311                 if (rc) {
1312                         DP_NOTICE(p_hwfn, true,
1313                                   "Failed to allocate memory for dcbx structure\n");
1314                         goto alloc_err;
1315                 }
1316         }
1317
1318         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1319                                          sizeof(*p_dev->reset_stats));
1320         if (!p_dev->reset_stats) {
1321                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
1322                 goto alloc_no_mem;
1323         }
1324
1325         return ECORE_SUCCESS;
1326
1327 alloc_no_mem:
1328         rc = ECORE_NOMEM;
1329 alloc_err:
1330         ecore_resc_free(p_dev);
1331         return rc;
1332 }
1333
1334 void ecore_resc_setup(struct ecore_dev *p_dev)
1335 {
1336         int i;
1337
1338         if (IS_VF(p_dev)) {
1339                 for_each_hwfn(p_dev, i)
1340                         ecore_l2_setup(&p_dev->hwfns[i]);
1341                 return;
1342         }
1343
1344         for_each_hwfn(p_dev, i) {
1345                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1346
1347                 ecore_cxt_mngr_setup(p_hwfn);
1348                 ecore_spq_setup(p_hwfn);
1349                 ecore_eq_setup(p_hwfn);
1350                 ecore_consq_setup(p_hwfn);
1351
1352                 /* Read shadow of current MFW mailbox */
1353                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1354                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1355                             p_hwfn->mcp_info->mfw_mb_cur,
1356                             p_hwfn->mcp_info->mfw_mb_length);
1357
1358                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1359
1360                 ecore_l2_setup(p_hwfn);
1361                 ecore_iov_setup(p_hwfn);
1362         }
1363 }
1364
1365 #define FINAL_CLEANUP_POLL_CNT  (100)
1366 #define FINAL_CLEANUP_POLL_TIME (10)
1367 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1368                                          struct ecore_ptt *p_ptt,
1369                                          u16 id, bool is_vf)
1370 {
1371         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1372         enum _ecore_status_t rc = ECORE_TIMEOUT;
1373
1374 #ifndef ASIC_ONLY
1375         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1376             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1377                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1378                 return ECORE_SUCCESS;
1379         }
1380 #endif
1381
1382         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1383             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1384
1385         if (is_vf)
1386                 id += 0x10;
1387
1388         command |= X_FINAL_CLEANUP_AGG_INT <<
1389             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1390         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1391         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1392         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1393
1394 /* Make sure notification is not set before initiating final cleanup */
1395
1396         if (REG_RD(p_hwfn, addr)) {
1397                 DP_NOTICE(p_hwfn, false,
1398                           "Unexpected; Found final cleanup notification");
1399                 DP_NOTICE(p_hwfn, false,
1400                           " before initiating final cleanup\n");
1401                 REG_WR(p_hwfn, addr, 0);
1402         }
1403
1404         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1405                    "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1406                    id, command);
1407
1408         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1409
1410         /* Poll until completion */
1411         while (!REG_RD(p_hwfn, addr) && count--)
1412                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1413
1414         if (REG_RD(p_hwfn, addr))
1415                 rc = ECORE_SUCCESS;
1416         else
1417                 DP_NOTICE(p_hwfn, true,
1418                           "Failed to receive FW final cleanup notification\n");
1419
1420         /* Cleanup afterwards */
1421         REG_WR(p_hwfn, addr, 0);
1422
1423         return rc;
1424 }
1425
1426 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1427 {
1428         int hw_mode = 0;
1429
1430         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1431                 hw_mode |= 1 << MODE_BB;
1432         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1433                 hw_mode |= 1 << MODE_K2;
1434         } else {
1435                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1436                           p_hwfn->p_dev->type);
1437                 return ECORE_INVAL;
1438         }
1439
1440         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1441         switch (p_hwfn->p_dev->num_ports_in_engine) {
1442         case 1:
1443                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1444                 break;
1445         case 2:
1446                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1447                 break;
1448         case 4:
1449                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1450                 break;
1451         default:
1452                 DP_NOTICE(p_hwfn, true,
1453                           "num_ports_in_engine = %d not supported\n",
1454                           p_hwfn->p_dev->num_ports_in_engine);
1455                 return ECORE_INVAL;
1456         }
1457
1458         if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS,
1459                           &p_hwfn->p_dev->mf_bits))
1460                 hw_mode |= 1 << MODE_MF_SD;
1461         else
1462                 hw_mode |= 1 << MODE_MF_SI;
1463
1464 #ifndef ASIC_ONLY
1465         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1466                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1467                         hw_mode |= 1 << MODE_FPGA;
1468                 } else {
1469                         if (p_hwfn->p_dev->b_is_emul_full)
1470                                 hw_mode |= 1 << MODE_EMUL_FULL;
1471                         else
1472                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
1473                 }
1474         } else
1475 #endif
1476                 hw_mode |= 1 << MODE_ASIC;
1477
1478         if (ECORE_IS_CMT(p_hwfn->p_dev))
1479                 hw_mode |= 1 << MODE_100G;
1480
1481         p_hwfn->hw_info.hw_mode = hw_mode;
1482
1483         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1484                    "Configuring function for hw_mode: 0x%08x\n",
1485                    p_hwfn->hw_info.hw_mode);
1486
1487         return ECORE_SUCCESS;
1488 }
1489
1490 #ifndef ASIC_ONLY
1491 /* MFW-replacement initializations for non-ASIC */
1492 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1493                                                struct ecore_ptt *p_ptt)
1494 {
1495         struct ecore_dev *p_dev = p_hwfn->p_dev;
1496         u32 pl_hv = 1;
1497         int i;
1498
1499         if (CHIP_REV_IS_EMUL(p_dev)) {
1500                 if (ECORE_IS_AH(p_dev))
1501                         pl_hv |= 0x600;
1502         }
1503
1504         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1505
1506         if (CHIP_REV_IS_EMUL(p_dev) &&
1507             (ECORE_IS_AH(p_dev)))
1508                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1509                          0x3ffffff);
1510
1511         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1512         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1513         if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1514                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1515
1516         if (CHIP_REV_IS_EMUL(p_dev)) {
1517                 if (ECORE_IS_AH(p_dev)) {
1518                         /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1519                         ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1520                                  (p_dev->num_ports_in_engine >> 1));
1521
1522                         ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1523                                  p_dev->num_ports_in_engine == 4 ? 0 : 3);
1524                 }
1525         }
1526
1527         /* Poll on RBC */
1528         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1529         for (i = 0; i < 100; i++) {
1530                 OSAL_UDELAY(50);
1531                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1532                         break;
1533         }
1534         if (i == 100)
1535                 DP_NOTICE(p_hwfn, true,
1536                           "RBC done failed to complete in PSWRQ2\n");
1537
1538         return ECORE_SUCCESS;
1539 }
1540 #endif
1541
1542 /* Init run time data for all PFs and their VFs on an engine.
1543  * TBD - for VFs - Once we have parent PF info for each VF in
1544  * shmem available as CAU requires knowledge of parent PF for each VF.
1545  */
1546 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1547 {
1548         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1549         int i, igu_sb_id;
1550
1551         for_each_hwfn(p_dev, i) {
1552                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1553                 struct ecore_igu_info *p_igu_info;
1554                 struct ecore_igu_block *p_block;
1555                 struct cau_sb_entry sb_entry;
1556
1557                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1558
1559                 for (igu_sb_id = 0;
1560                      igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1561                      igu_sb_id++) {
1562                         p_block = &p_igu_info->entry[igu_sb_id];
1563
1564                         if (!p_block->is_pf)
1565                                 continue;
1566
1567                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1568                                                 p_block->function_id, 0, 0);
1569                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1570                                          sb_entry);
1571                 }
1572         }
1573 }
1574
1575 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
1576                                        struct ecore_ptt *p_ptt)
1577 {
1578         u32 val, wr_mbs, cache_line_size;
1579
1580         val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1581         switch (val) {
1582         case 0:
1583                 wr_mbs = 128;
1584                 break;
1585         case 1:
1586                 wr_mbs = 256;
1587                 break;
1588         case 2:
1589                 wr_mbs = 512;
1590                 break;
1591         default:
1592                 DP_INFO(p_hwfn,
1593                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1594                         val);
1595                 return;
1596         }
1597
1598         cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
1599         switch (cache_line_size) {
1600         case 32:
1601                 val = 0;
1602                 break;
1603         case 64:
1604                 val = 1;
1605                 break;
1606         case 128:
1607                 val = 2;
1608                 break;
1609         case 256:
1610                 val = 3;
1611                 break;
1612         default:
1613                 DP_INFO(p_hwfn,
1614                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1615                         cache_line_size);
1616         }
1617
1618         if (wr_mbs < OSAL_CACHE_LINE_SIZE)
1619                 DP_INFO(p_hwfn,
1620                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1621                         OSAL_CACHE_LINE_SIZE, wr_mbs);
1622
1623         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1624         if (val > 0) {
1625                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1626                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1627         }
1628 }
1629
1630 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1631                                                  struct ecore_ptt *p_ptt,
1632                                                  int hw_mode)
1633 {
1634         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1635         struct ecore_dev *p_dev = p_hwfn->p_dev;
1636         u8 vf_id, max_num_vfs;
1637         u16 num_pfs, pf_id;
1638         u32 concrete_fid;
1639         enum _ecore_status_t rc = ECORE_SUCCESS;
1640
1641         ecore_init_cau_rt_data(p_dev);
1642
1643         /* Program GTT windows */
1644         ecore_gtt_init(p_hwfn, p_ptt);
1645
1646 #ifndef ASIC_ONLY
1647         if (CHIP_REV_IS_EMUL(p_dev)) {
1648                 rc = ecore_hw_init_chip(p_hwfn, p_ptt);
1649                 if (rc != ECORE_SUCCESS)
1650                         return rc;
1651         }
1652 #endif
1653
1654         if (p_hwfn->mcp_info) {
1655                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1656                         qm_info->pf_rl_en = 1;
1657                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1658                         qm_info->pf_wfq_en = 1;
1659         }
1660
1661         ecore_qm_common_rt_init(p_hwfn,
1662                                 p_dev->num_ports_in_engine,
1663                                 qm_info->max_phys_tcs_per_port,
1664                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1665                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1666                                 qm_info->qm_port_params);
1667
1668         ecore_cxt_hw_init_common(p_hwfn);
1669
1670         ecore_init_cache_line_size(p_hwfn, p_ptt);
1671
1672         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1673         if (rc != ECORE_SUCCESS)
1674                 return rc;
1675
1676         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1677          * need to decide with which value, maybe runtime
1678          */
1679         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1680         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1681
1682         if (ECORE_IS_BB(p_dev)) {
1683                 /* Workaround clears ROCE search for all functions to prevent
1684                  * involving non initialized function in processing ROCE packet.
1685                  */
1686                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1687                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1688                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1689                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1690                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1691                 }
1692                 /* pretend to original PF */
1693                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1694         }
1695
1696         /* Workaround for avoiding CCFC execution error when getting packets
1697          * with CRC errors, and allowing instead the invoking of the FW error
1698          * handler.
1699          * This is not done inside the init tool since it currently can't
1700          * perform a pretending to VFs.
1701          */
1702         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1703         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1704                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1705                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1706                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1707                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1708                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1709                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1710         }
1711         /* pretend to original PF */
1712         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1713
1714         return rc;
1715 }
1716
1717 #ifndef ASIC_ONLY
1718 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1719 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1720
1721 #define PMEG_IF_BYTE_COUNT      8
1722
1723 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1724                              struct ecore_ptt *p_ptt,
1725                              u32 addr, u64 data, u8 reg_type, u8 port)
1726 {
1727         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1728                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1729                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1730                    (8 << PMEG_IF_BYTE_COUNT),
1731                    (reg_type << 25) | (addr << 8) | port,
1732                    (u32)((data >> 32) & 0xffffffff),
1733                    (u32)(data & 0xffffffff));
1734
1735         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1736                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1737                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1738         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1739                  (reg_type << 25) | (addr << 8) | port);
1740         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1741         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1742                  (data >> 32) & 0xffffffff);
1743 }
1744
1745 #define XLPORT_MODE_REG (0x20a)
1746 #define XLPORT_MAC_CONTROL (0x210)
1747 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1748 #define XLPORT_ENABLE_REG (0x20b)
1749
1750 #define XLMAC_CTRL (0x600)
1751 #define XLMAC_MODE (0x601)
1752 #define XLMAC_RX_MAX_SIZE (0x608)
1753 #define XLMAC_TX_CTRL (0x604)
1754 #define XLMAC_PAUSE_CTRL (0x60d)
1755 #define XLMAC_PFC_CTRL (0x60e)
1756
1757 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1758                                     struct ecore_ptt *p_ptt)
1759 {
1760         u8 loopback = 0, port = p_hwfn->port_id * 2;
1761
1762         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1763
1764         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1765         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1766                          port);
1767         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1768         /* XLMAC: SOFT RESET */
1769         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1770         /* XLMAC: Port Speed >= 10Gbps */
1771         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1772         /* XLMAC: Max Size */
1773         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1774         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1775                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1776                          0, port);
1777         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1778         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1779                          0x30ffffc000ULL, 0, port);
1780         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1781                          port); /* XLMAC: TX_EN, RX_EN */
1782         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1783         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1784                          0x1003 | (loopback << 2), 0, port);
1785         /* Enabled Parallel PFC interface */
1786         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1787
1788         /* XLPORT port enable */
1789         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1790 }
1791
1792 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1793                                        struct ecore_ptt *p_ptt)
1794 {
1795         u8 port = p_hwfn->port_id;
1796         u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1797
1798         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1799
1800         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1801                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1802                  (port <<
1803                   CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1804                  (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1805
1806         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1807                  1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1808
1809         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1810                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1811
1812         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1813                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1814
1815         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1816                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1817
1818         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1819                  (0xA <<
1820                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1821                  (8 <<
1822                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1823
1824         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1825                  0xa853);
1826 }
1827
1828 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1829                                  struct ecore_ptt *p_ptt)
1830 {
1831         if (ECORE_IS_AH(p_hwfn->p_dev))
1832                 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1833         else /* BB */
1834                 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1835 }
1836
1837 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1838                                struct ecore_ptt *p_ptt,  u8 port)
1839 {
1840         int port_offset = port ? 0x800 : 0;
1841         u32 xmac_rxctrl = 0;
1842
1843         /* Reset of XMAC */
1844         /* FIXME: move to common start */
1845         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1846                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1847         OSAL_MSLEEP(1);
1848         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1849                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1850
1851         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1852
1853         /* Set the number of ports on the Warp Core to 10G */
1854         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1855
1856         /* Soft reset of XMAC */
1857         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1858                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1859         OSAL_MSLEEP(1);
1860         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1861                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1862
1863         /* FIXME: move to common end */
1864         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1865                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1866
1867         /* Set Max packet size: initialize XMAC block register for port 0 */
1868         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1869
1870         /* CRC append for Tx packets: init XMAC block register for port 1 */
1871         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1872
1873         /* Enable TX and RX: initialize XMAC block register for port 1 */
1874         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1875                  XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1876         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1877                                XMAC_REG_RX_CTRL_BB + port_offset);
1878         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1879         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1880 }
1881 #endif
1882
1883 static enum _ecore_status_t
1884 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1885                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1886 {
1887         u32 dpi_bit_shift, dpi_count, dpi_page_size;
1888         u32 min_dpis;
1889         u32 n_wids;
1890
1891         /* Calculate DPI size
1892          * ------------------
1893          * The PWM region contains Doorbell Pages. The first is reserverd for
1894          * the kernel for, e.g, L2. The others are free to be used by non-
1895          * trusted applications, typically from user space. Each page, called a
1896          * doorbell page is sectioned into windows that allow doorbells to be
1897          * issued in parallel by the kernel/application. The size of such a
1898          * window (a.k.a. WID) is 1kB.
1899          * Summary:
1900          *    1kB WID x N WIDS = DPI page size
1901          *    DPI page size x N DPIs = PWM region size
1902          * Notes:
1903          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1904          * in order to ensure that two applications won't share the same page.
1905          * It also must contain at least one WID per CPU to allow parallelism.
1906          * It also must be a power of 2, since it is stored as a bit shift.
1907          *
1908          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1909          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1910          * containing 4 WIDs.
1911          */
1912         n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus);
1913         dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids);
1914         dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) &
1915                         ~(OSAL_PAGE_SIZE - 1);
1916         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1917         dpi_count = pwm_region_size / dpi_page_size;
1918
1919         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1920         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1921
1922         /* Update hwfn */
1923         p_hwfn->dpi_size = dpi_page_size;
1924         p_hwfn->dpi_count = dpi_count;
1925
1926         /* Update registers */
1927         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1928
1929         if (dpi_count < min_dpis)
1930                 return ECORE_NORESOURCES;
1931
1932         return ECORE_SUCCESS;
1933 }
1934
1935 enum ECORE_ROCE_EDPM_MODE {
1936         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1937         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1938         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1939 };
1940
1941 static enum _ecore_status_t
1942 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1943                               struct ecore_ptt *p_ptt)
1944 {
1945         u32 pwm_regsize, norm_regsize;
1946         u32 non_pwm_conn, min_addr_reg1;
1947         u32 db_bar_size, n_cpus;
1948         u32 roce_edpm_mode;
1949         u32 pf_dems_shift;
1950         enum _ecore_status_t rc = ECORE_SUCCESS;
1951         u8 cond;
1952
1953         db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1954         if (ECORE_IS_CMT(p_hwfn->p_dev))
1955                 db_bar_size /= 2;
1956
1957         /* Calculate doorbell regions
1958          * -----------------------------------
1959          * The doorbell BAR is made of two regions. The first is called normal
1960          * region and the second is called PWM region. In the normal region
1961          * each ICID has its own set of addresses so that writing to that
1962          * specific address identifies the ICID. In the Process Window Mode
1963          * region the ICID is given in the data written to the doorbell. The
1964          * above per PF register denotes the offset in the doorbell BAR in which
1965          * the PWM region begins.
1966          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1967          * non-PWM connection. The calculation below computes the total non-PWM
1968          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1969          * in units of 4,096 bytes.
1970          */
1971         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1972             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1973                                           OSAL_NULL) +
1974             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1975         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn,
1976                                OSAL_PAGE_SIZE);
1977         min_addr_reg1 = norm_regsize / 4096;
1978         pwm_regsize = db_bar_size - norm_regsize;
1979
1980         /* Check that the normal and PWM sizes are valid */
1981         if (db_bar_size < norm_regsize) {
1982                 DP_ERR(p_hwfn->p_dev,
1983                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1984                        db_bar_size, norm_regsize);
1985                 return ECORE_NORESOURCES;
1986         }
1987         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1988                 DP_ERR(p_hwfn->p_dev,
1989                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1990                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1991                        norm_regsize);
1992                 return ECORE_NORESOURCES;
1993         }
1994
1995         /* Calculate number of DPIs */
1996         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1997         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1998             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1999                 /* Either EDPM is mandatory, or we are attempting to allocate a
2000                  * WID per CPU.
2001                  */
2002                 n_cpus = OSAL_NUM_ACTIVE_CPU();
2003                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2004         }
2005
2006         cond = ((rc != ECORE_SUCCESS) &&
2007                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
2008                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
2009         if (cond || p_hwfn->dcbx_no_edpm) {
2010                 /* Either EDPM is disabled from user configuration, or it is
2011                  * disabled via DCBx, or it is not mandatory and we failed to
2012                  * allocated a WID per CPU.
2013                  */
2014                 n_cpus = 1;
2015                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2016
2017                 /* If we entered this flow due to DCBX then the DPM register is
2018                  * already configured.
2019                  */
2020         }
2021
2022         DP_INFO(p_hwfn,
2023                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
2024                 norm_regsize, pwm_regsize);
2025         DP_INFO(p_hwfn,
2026                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
2027                 p_hwfn->dpi_size, p_hwfn->dpi_count,
2028                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
2029                 "disabled" : "enabled");
2030
2031         /* Check return codes from above calls */
2032         if (rc != ECORE_SUCCESS) {
2033                 DP_ERR(p_hwfn,
2034                        "Failed to allocate enough DPIs\n");
2035                 return ECORE_NORESOURCES;
2036         }
2037
2038         /* Update hwfn */
2039         p_hwfn->dpi_start_offset = norm_regsize;
2040
2041         /* Update registers */
2042         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2043         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
2044         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2045         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2046
2047         return ECORE_SUCCESS;
2048 }
2049
2050 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
2051                                                struct ecore_ptt *p_ptt,
2052                                                int hw_mode)
2053 {
2054         u32 ppf_to_eng_sel[NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE];
2055         u32 val;
2056         enum _ecore_status_t rc = ECORE_SUCCESS;
2057         u8 i;
2058
2059         /* In CMT for non-RoCE packets - use connection based classification */
2060         val = ECORE_IS_CMT(p_hwfn->p_dev) ? 0x8 : 0x0;
2061         for (i = 0; i < NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE; i++)
2062                 ppf_to_eng_sel[i] = val;
2063         STORE_RT_REG_AGG(p_hwfn, NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET,
2064                          ppf_to_eng_sel);
2065
2066         /* In CMT the gate should be cleared by the 2nd hwfn */
2067         if (!ECORE_IS_CMT(p_hwfn->p_dev) || !IS_LEAD_HWFN(p_hwfn))
2068                 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
2069
2070         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
2071                             hw_mode);
2072         if (rc != ECORE_SUCCESS)
2073                 return rc;
2074
2075         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2076
2077 #ifndef ASIC_ONLY
2078         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2079                 return ECORE_SUCCESS;
2080
2081         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2082                 if (ECORE_IS_AH(p_hwfn->p_dev))
2083                         return ECORE_SUCCESS;
2084                 else if (ECORE_IS_BB(p_hwfn->p_dev))
2085                         ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
2086         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2087                 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
2088                         /* Activate OPTE in CMT */
2089                         u32 val;
2090
2091                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
2092                         val |= 0x10;
2093                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
2094                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
2095                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
2096                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
2097                         ecore_wr(p_hwfn, p_ptt,
2098                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
2099                         ecore_wr(p_hwfn, p_ptt,
2100                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
2101                         ecore_wr(p_hwfn, p_ptt,
2102                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
2103                                  0x55555555);
2104                 }
2105
2106                 ecore_emul_link_init(p_hwfn, p_ptt);
2107         } else {
2108                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
2109         }
2110 #endif
2111
2112         return rc;
2113 }
2114
2115 static enum _ecore_status_t
2116 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
2117                  struct ecore_ptt *p_ptt,
2118                  struct ecore_tunnel_info *p_tunn,
2119                  int hw_mode,
2120                  bool b_hw_start,
2121                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
2122 {
2123         u8 rel_pf_id = p_hwfn->rel_pf_id;
2124         u32 prs_reg;
2125         enum _ecore_status_t rc = ECORE_SUCCESS;
2126         u16 ctrl;
2127         int pos;
2128
2129         if (p_hwfn->mcp_info) {
2130                 struct ecore_mcp_function_info *p_info;
2131
2132                 p_info = &p_hwfn->mcp_info->func_info;
2133                 if (p_info->bandwidth_min)
2134                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2135
2136                 /* Update rate limit once we'll actually have a link */
2137                 p_hwfn->qm_info.pf_rl = 100000;
2138         }
2139         ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
2140
2141         ecore_int_igu_init_rt(p_hwfn);
2142
2143         /* Set VLAN in NIG if needed */
2144         if (hw_mode & (1 << MODE_MF_SD)) {
2145                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2146                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2147                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2148                              p_hwfn->hw_info.ovlan);
2149
2150                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2151                            "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
2152                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
2153                              1);
2154         }
2155
2156         /* Enable classification by MAC if needed */
2157         if (hw_mode & (1 << MODE_MF_SI)) {
2158                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2159                            "Configuring TAGMAC_CLS_TYPE\n");
2160                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
2161                              1);
2162         }
2163
2164         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
2165         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2166                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
2167         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2168                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
2169         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2170
2171         /* perform debug configuration when chip is out of reset */
2172         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
2173
2174         /* PF Init sequence */
2175         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2176         if (rc)
2177                 return rc;
2178
2179         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2180         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2181         if (rc)
2182                 return rc;
2183
2184         /* Pure runtime initializations - directly to the HW  */
2185         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2186
2187         /* PCI relaxed ordering causes a decrease in the performance on some
2188          * systems. Till a root cause is found, disable this attribute in the
2189          * PCI config space.
2190          */
2191         /* Not in use @DPDK
2192         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
2193         * if (!pos) {
2194         *       DP_NOTICE(p_hwfn, true,
2195         *                 "Failed to find the PCIe Cap\n");
2196         *       return ECORE_IO;
2197         * }
2198         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
2199         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
2200         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
2201         */
2202
2203         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2204         if (rc)
2205                 return rc;
2206         if (b_hw_start) {
2207                 /* enable interrupts */
2208                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
2209                 if (rc != ECORE_SUCCESS)
2210                         return rc;
2211
2212                 /* send function start command */
2213                 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2214                                        allow_npar_tx_switch);
2215                 if (rc) {
2216                         DP_NOTICE(p_hwfn, true,
2217                                   "Function start ramrod failed\n");
2218                 } else {
2219                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2220                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2221                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2222
2223                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
2224                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
2225                                          (1 << 2));
2226                                 ecore_wr(p_hwfn, p_ptt,
2227                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2228                                     0x100);
2229                         }
2230                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2231                                    "PRS_REG_SEARCH registers after start PFn\n");
2232                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
2233                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2234                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
2235                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
2236                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2237                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
2238                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
2239                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2240                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
2241                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
2242                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2243                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
2244                         prs_reg = ecore_rd(p_hwfn, p_ptt,
2245                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
2246                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2247                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
2248                                    prs_reg);
2249                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2250                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2251                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2252                 }
2253         }
2254         return rc;
2255 }
2256
2257 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
2258                                                   struct ecore_ptt *p_ptt,
2259                                                   bool b_enable)
2260 {
2261         u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2262
2263         /* Configure the PF's internal FID_enable for master transactions */
2264         ecore_wr(p_hwfn, p_ptt,
2265                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2266
2267         /* Wait until value is set - try for 1 second every 50us */
2268         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2269                 val = ecore_rd(p_hwfn, p_ptt,
2270                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2271                 if (val == set_val)
2272                         break;
2273
2274                 OSAL_UDELAY(50);
2275         }
2276
2277         if (val != set_val) {
2278                 DP_NOTICE(p_hwfn, true,
2279                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
2280                 return ECORE_UNKNOWN_ERROR;
2281         }
2282
2283         return ECORE_SUCCESS;
2284 }
2285
2286 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
2287                                   struct ecore_ptt *p_main_ptt)
2288 {
2289         /* Read shadow of current MFW mailbox */
2290         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
2291         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
2292                     p_hwfn->mcp_info->mfw_mb_cur,
2293                     p_hwfn->mcp_info->mfw_mb_length);
2294 }
2295
2296 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
2297                                     struct ecore_hw_init_params *p_params)
2298 {
2299         if (p_params->p_tunn) {
2300                 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2301                 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2302         }
2303
2304         p_hwfn->b_int_enabled = 1;
2305
2306         return ECORE_SUCCESS;
2307 }
2308
2309 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
2310                                      struct ecore_ptt *p_ptt)
2311 {
2312         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
2313                  1 << p_hwfn->abs_pf_id);
2314 }
2315
2316 static void
2317 ecore_fill_load_req_params(struct ecore_load_req_params *p_load_req,
2318                            struct ecore_drv_load_params *p_drv_load)
2319 {
2320         /* Make sure that if ecore-client didn't provide inputs, all the
2321          * expected defaults are indeed zero.
2322          */
2323         OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
2324         OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
2325         OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
2326
2327         OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
2328
2329         if (p_drv_load != OSAL_NULL) {
2330                 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2331                                        ECORE_DRV_ROLE_KDUMP :
2332                                        ECORE_DRV_ROLE_OS;
2333                 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2334                 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2335                 p_load_req->override_force_load =
2336                         p_drv_load->override_force_load;
2337         }
2338 }
2339
2340 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
2341                                    struct ecore_hw_init_params *p_params)
2342 {
2343         struct ecore_load_req_params load_req_params;
2344         u32 load_code, resp, param, drv_mb_param;
2345         bool b_default_mtu = true;
2346         struct ecore_hwfn *p_hwfn;
2347         enum _ecore_status_t rc = ECORE_SUCCESS;
2348         int i;
2349
2350         if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) {
2351                 DP_NOTICE(p_dev, false,
2352                           "MSI mode is not supported for CMT devices\n");
2353                 return ECORE_INVAL;
2354         }
2355
2356         if (IS_PF(p_dev)) {
2357                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
2358                 if (rc != ECORE_SUCCESS)
2359                         return rc;
2360         }
2361
2362         for_each_hwfn(p_dev, i) {
2363                 p_hwfn = &p_dev->hwfns[i];
2364
2365                 /* If management didn't provide a default, set one of our own */
2366                 if (!p_hwfn->hw_info.mtu) {
2367                         p_hwfn->hw_info.mtu = 1500;
2368                         b_default_mtu = false;
2369                 }
2370
2371                 if (IS_VF(p_dev)) {
2372                         ecore_vf_start(p_hwfn, p_params);
2373                         continue;
2374                 }
2375
2376                 rc = ecore_calc_hw_mode(p_hwfn);
2377                 if (rc != ECORE_SUCCESS)
2378                         return rc;
2379
2380                 ecore_fill_load_req_params(&load_req_params,
2381                                            p_params->p_drv_load_params);
2382                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
2383                                         &load_req_params);
2384                 if (rc != ECORE_SUCCESS) {
2385                         DP_NOTICE(p_hwfn, true,
2386                                   "Failed sending a LOAD_REQ command\n");
2387                         return rc;
2388                 }
2389
2390                 load_code = load_req_params.load_code;
2391                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2392                            "Load request was sent. Load code: 0x%x\n",
2393                            load_code);
2394
2395                 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
2396
2397                 /* CQ75580:
2398                  * When coming back from hiberbate state, the registers from
2399                  * which shadow is read initially are not initialized. It turns
2400                  * out that these registers get initialized during the call to
2401                  * ecore_mcp_load_req request. So we need to reread them here
2402                  * to get the proper shadow register value.
2403                  * Note: This is a workaround for the missing MFW
2404                  * initialization. It may be removed once the implementation
2405                  * is done.
2406                  */
2407                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2408
2409                 /* Only relevant for recovery:
2410                  * Clear the indication after the LOAD_REQ command is responded
2411                  * by the MFW.
2412                  */
2413                 p_dev->recov_in_prog = false;
2414
2415                 p_hwfn->first_on_engine = (load_code ==
2416                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
2417
2418                 if (!qm_lock_init) {
2419                         OSAL_SPIN_LOCK_INIT(&qm_lock);
2420                         qm_lock_init = true;
2421                 }
2422
2423                 /* Clean up chip from previous driver if such remains exist.
2424                  * This is not needed when the PF is the first one on the
2425                  * engine, since afterwards we are going to init the FW.
2426                  */
2427                 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2428                         rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2429                                                  p_hwfn->rel_pf_id, false);
2430                         if (rc != ECORE_SUCCESS) {
2431                                 ecore_hw_err_notify(p_hwfn,
2432                                                     ECORE_HW_ERR_RAMROD_FAIL);
2433                                 goto load_err;
2434                         }
2435                 }
2436
2437                 /* Log and clean previous pglue_b errors if such exist */
2438                 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
2439                 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2440
2441                 /* Enable the PF's internal FID_enable in the PXP */
2442                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2443                                                   true);
2444                 if (rc != ECORE_SUCCESS)
2445                         goto load_err;
2446
2447                 switch (load_code) {
2448                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2449                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2450                                                   p_hwfn->hw_info.hw_mode);
2451                         if (rc != ECORE_SUCCESS)
2452                                 break;
2453                         /* Fall into */
2454                 case FW_MSG_CODE_DRV_LOAD_PORT:
2455                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2456                                                 p_hwfn->hw_info.hw_mode);
2457                         if (rc != ECORE_SUCCESS)
2458                                 break;
2459                         /* Fall into */
2460                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2461                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2462                                               p_params->p_tunn,
2463                                               p_hwfn->hw_info.hw_mode,
2464                                               p_params->b_hw_start,
2465                                               p_params->int_mode,
2466                                               p_params->allow_npar_tx_switch);
2467                         break;
2468                 default:
2469                         DP_NOTICE(p_hwfn, false,
2470                                   "Unexpected load code [0x%08x]", load_code);
2471                         rc = ECORE_NOTIMPL;
2472                         break;
2473                 }
2474
2475                 if (rc != ECORE_SUCCESS) {
2476                         DP_NOTICE(p_hwfn, true,
2477                                   "init phase failed for loadcode 0x%x (rc %d)\n",
2478                                   load_code, rc);
2479                         goto load_err;
2480                 }
2481
2482                 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2483                 if (rc != ECORE_SUCCESS)
2484                         return rc;
2485
2486                 /* send DCBX attention request command */
2487                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2488                            "sending phony dcbx set command to trigger DCBx attention handling\n");
2489                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2490                                    DRV_MSG_CODE_SET_DCBX,
2491                                    1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
2492                                    &param);
2493                 if (rc != ECORE_SUCCESS) {
2494                         DP_NOTICE(p_hwfn, true,
2495                                   "Failed to send DCBX attention request\n");
2496                         return rc;
2497                 }
2498
2499                 p_hwfn->hw_init_done = true;
2500         }
2501
2502         if (IS_PF(p_dev)) {
2503                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2504                 drv_mb_param = STORM_FW_VERSION;
2505                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2506                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2507                                    drv_mb_param, &resp, &param);
2508                 if (rc != ECORE_SUCCESS)
2509                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
2510
2511                 if (!b_default_mtu)
2512                         rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2513                                                       p_hwfn->hw_info.mtu);
2514                 if (rc != ECORE_SUCCESS)
2515                         DP_INFO(p_hwfn, "Failed to update default mtu\n");
2516
2517                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2518                                                       p_hwfn->p_main_ptt,
2519                                                 ECORE_OV_DRIVER_STATE_DISABLED);
2520                 if (rc != ECORE_SUCCESS)
2521                         DP_INFO(p_hwfn, "Failed to update driver state\n");
2522         }
2523
2524         return rc;
2525
2526 load_err:
2527         /* The MFW load lock should be released regardless of success or failure
2528          * of initialization.
2529          * TODO: replace this with an attempt to send cancel_load.
2530          */
2531         ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2532         return rc;
2533 }
2534
2535 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
2536 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2537                                  struct ecore_hwfn *p_hwfn,
2538                                  struct ecore_ptt *p_ptt)
2539 {
2540         int i;
2541
2542         /* close timers */
2543         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2544         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2545         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2546                                                                         i++) {
2547                 if ((!ecore_rd(p_hwfn, p_ptt,
2548                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2549                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2550                         break;
2551
2552                 /* Dependent on number of connection/tasks, possibly
2553                  * 1ms sleep is required between polls
2554                  */
2555                 OSAL_MSLEEP(1);
2556         }
2557
2558         if (i < ECORE_HW_STOP_RETRY_LIMIT)
2559                 return;
2560
2561         DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2562                   " [Connection %02x Tasks %02x]\n",
2563                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2564                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2565 }
2566
2567 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2568 {
2569         int j;
2570
2571         for_each_hwfn(p_dev, j) {
2572                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2573                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2574
2575                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2576         }
2577 }
2578
2579 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
2580                                                  struct ecore_ptt *p_ptt,
2581                                                  u32 addr, u32 expected_val)
2582 {
2583         u32 val = ecore_rd(p_hwfn, p_ptt, addr);
2584
2585         if (val != expected_val) {
2586                 DP_NOTICE(p_hwfn, true,
2587                           "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
2588                           addr, val, expected_val);
2589                 return ECORE_UNKNOWN_ERROR;
2590         }
2591
2592         return ECORE_SUCCESS;
2593 }
2594
2595 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2596 {
2597         struct ecore_hwfn *p_hwfn;
2598         struct ecore_ptt *p_ptt;
2599         enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
2600         int j;
2601
2602         for_each_hwfn(p_dev, j) {
2603                 p_hwfn = &p_dev->hwfns[j];
2604                 p_ptt = p_hwfn->p_main_ptt;
2605
2606                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2607
2608                 if (IS_VF(p_dev)) {
2609                         ecore_vf_pf_int_cleanup(p_hwfn);
2610                         rc = ecore_vf_pf_reset(p_hwfn);
2611                         if (rc != ECORE_SUCCESS) {
2612                                 DP_NOTICE(p_hwfn, true,
2613                                           "ecore_vf_pf_reset failed. rc = %d.\n",
2614                                           rc);
2615                                 rc2 = ECORE_UNKNOWN_ERROR;
2616                         }
2617                         continue;
2618                 }
2619
2620                 /* mark the hw as uninitialized... */
2621                 p_hwfn->hw_init_done = false;
2622
2623                 /* Send unload command to MCP */
2624                 if (!p_dev->recov_in_prog) {
2625                         rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
2626                         if (rc != ECORE_SUCCESS) {
2627                                 DP_NOTICE(p_hwfn, true,
2628                                           "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2629                                           rc);
2630                                 rc2 = ECORE_UNKNOWN_ERROR;
2631                         }
2632                 }
2633
2634                 OSAL_DPC_SYNC(p_hwfn);
2635
2636                 /* After this point no MFW attentions are expected, e.g. prevent
2637                  * race between pf stop and dcbx pf update.
2638                  */
2639
2640                 rc = ecore_sp_pf_stop(p_hwfn);
2641                 if (rc != ECORE_SUCCESS) {
2642                         DP_NOTICE(p_hwfn, true,
2643                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2644                                   rc);
2645                         rc2 = ECORE_UNKNOWN_ERROR;
2646                 }
2647
2648                 /* perform debug action after PF stop was sent */
2649                 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
2650
2651                 /* close NIG to BRB gate */
2652                 ecore_wr(p_hwfn, p_ptt,
2653                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2654
2655                 /* close parser */
2656                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2657                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2658                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2659                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2660                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2661
2662                 /* @@@TBD - clean transmission queues (5.b) */
2663                 /* @@@TBD - clean BTB (5.c) */
2664
2665                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2666
2667                 /* @@@TBD - verify DMAE requests are done (8) */
2668
2669                 /* Disable Attention Generation */
2670                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2671                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2672                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2673                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2674                 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
2675                 if (rc != ECORE_SUCCESS) {
2676                         DP_NOTICE(p_hwfn, true,
2677                                   "Failed to return IGU CAM to default\n");
2678                         rc2 = ECORE_UNKNOWN_ERROR;
2679                 }
2680
2681                 /* Need to wait 1ms to guarantee SBs are cleared */
2682                 OSAL_MSLEEP(1);
2683
2684                 if (!p_dev->recov_in_prog) {
2685                         ecore_verify_reg_val(p_hwfn, p_ptt,
2686                                              QM_REG_USG_CNT_PF_TX, 0);
2687                         ecore_verify_reg_val(p_hwfn, p_ptt,
2688                                              QM_REG_USG_CNT_PF_OTHER, 0);
2689                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
2690                 }
2691
2692                 /* Disable PF in HW blocks */
2693                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2694                 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2695
2696                 if (!p_dev->recov_in_prog) {
2697                         ecore_mcp_unload_done(p_hwfn, p_ptt);
2698                         if (rc != ECORE_SUCCESS) {
2699                                 DP_NOTICE(p_hwfn, true,
2700                                           "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2701                                           rc);
2702                                 rc2 = ECORE_UNKNOWN_ERROR;
2703                         }
2704                 }
2705         } /* hwfn loop */
2706
2707         if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
2708                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2709                 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2710
2711                  /* Clear the PF's internal FID_enable in the PXP.
2712                   * In CMT this should only be done for first hw-function, and
2713                   * only after all transactions have stopped for all active
2714                   * hw-functions.
2715                   */
2716                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2717                                                   false);
2718                 if (rc != ECORE_SUCCESS) {
2719                         DP_NOTICE(p_hwfn, true,
2720                                   "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2721                                   rc);
2722                         rc2 = ECORE_UNKNOWN_ERROR;
2723                 }
2724         }
2725
2726         return rc2;
2727 }
2728
2729 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2730 {
2731         int j;
2732
2733         for_each_hwfn(p_dev, j) {
2734                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2735                 struct ecore_ptt *p_ptt;
2736
2737                 if (IS_VF(p_dev)) {
2738                         ecore_vf_pf_int_cleanup(p_hwfn);
2739                         continue;
2740                 }
2741                 p_ptt = ecore_ptt_acquire(p_hwfn);
2742                 if (!p_ptt)
2743                         return ECORE_AGAIN;
2744
2745                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2746                            "Shutting down the fastpath\n");
2747
2748                 ecore_wr(p_hwfn, p_ptt,
2749                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2750
2751                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2752                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2753                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2754                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2755                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2756
2757                 /* @@@TBD - clean transmission queues (5.b) */
2758                 /* @@@TBD - clean BTB (5.c) */
2759
2760                 /* @@@TBD - verify DMAE requests are done (8) */
2761
2762                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2763                 /* Need to wait 1ms to guarantee SBs are cleared */
2764                 OSAL_MSLEEP(1);
2765                 ecore_ptt_release(p_hwfn, p_ptt);
2766         }
2767
2768         return ECORE_SUCCESS;
2769 }
2770
2771 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2772 {
2773         struct ecore_ptt *p_ptt;
2774
2775         if (IS_VF(p_hwfn->p_dev))
2776                 return ECORE_SUCCESS;
2777
2778         p_ptt = ecore_ptt_acquire(p_hwfn);
2779         if (!p_ptt)
2780                 return ECORE_AGAIN;
2781
2782         /* If roce info is allocated it means roce is initialized and should
2783          * be enabled in searcher.
2784          */
2785         if (p_hwfn->p_rdma_info) {
2786                 if (p_hwfn->b_rdma_enabled_in_prs)
2787                         ecore_wr(p_hwfn, p_ptt,
2788                                  p_hwfn->rdma_prs_search_reg, 0x1);
2789                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2790         }
2791
2792         /* Re-open incoming traffic */
2793         ecore_wr(p_hwfn, p_ptt,
2794                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2795         ecore_ptt_release(p_hwfn, p_ptt);
2796
2797         return ECORE_SUCCESS;
2798 }
2799
2800 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2801 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2802 {
2803         ecore_ptt_pool_free(p_hwfn);
2804         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2805 }
2806
2807 /* Setup bar access */
2808 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2809 {
2810         /* clear indirect access */
2811         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2812                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2813                          PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2814                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2815                          PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2816                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2817                          PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2818                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2819                          PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2820         } else {
2821                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2822                          PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2823                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2824                          PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2825                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2826                          PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2827                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2828                          PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2829         }
2830
2831         /* Clean previous pglue_b errors if such exist */
2832         ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2833
2834         /* enable internal target-read */
2835         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2836                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2837 }
2838
2839 static void get_function_id(struct ecore_hwfn *p_hwfn)
2840 {
2841         /* ME Register */
2842         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2843                                                   PXP_PF_ME_OPAQUE_ADDR);
2844
2845         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2846
2847         /* Bits 16-19 from the ME registers are the pf_num */
2848         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2849         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2850                                       PXP_CONCRETE_FID_PFID);
2851         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2852                                     PXP_CONCRETE_FID_PORT);
2853
2854         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2855                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2856                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2857 }
2858
2859 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2860 {
2861         u32 *feat_num = p_hwfn->hw_info.feat_num;
2862         struct ecore_sb_cnt_info sb_cnt;
2863         u32 non_l2_sbs = 0;
2864
2865         OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
2866         ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
2867
2868         /* L2 Queues require each: 1 status block. 1 L2 queue */
2869         if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
2870                 /* Start by allocating VF queues, then PF's */
2871                 feat_num[ECORE_VF_L2_QUE] =
2872                         OSAL_MIN_T(u32,
2873                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
2874                                    sb_cnt.iov_cnt);
2875                 feat_num[ECORE_PF_L2_QUE] =
2876                         OSAL_MIN_T(u32,
2877                                    sb_cnt.cnt - non_l2_sbs,
2878                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2879                                    FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
2880         }
2881
2882         feat_num[ECORE_FCOE_CQ] = OSAL_MIN_T(u32, sb_cnt.cnt,
2883                                              RESC_NUM(p_hwfn,
2884                                                       ECORE_CMDQS_CQS));
2885         feat_num[ECORE_ISCSI_CQ] = OSAL_MIN_T(u32, sb_cnt.cnt,
2886                                               RESC_NUM(p_hwfn,
2887                                                        ECORE_CMDQS_CQS));
2888
2889         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2890                    "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2891                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2892                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2893                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2894                    (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2895                    (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2896                    (int)sb_cnt.cnt);
2897 }
2898
2899 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2900 {
2901         switch (res_id) {
2902         case ECORE_L2_QUEUE:
2903                 return "L2_QUEUE";
2904         case ECORE_VPORT:
2905                 return "VPORT";
2906         case ECORE_RSS_ENG:
2907                 return "RSS_ENG";
2908         case ECORE_PQ:
2909                 return "PQ";
2910         case ECORE_RL:
2911                 return "RL";
2912         case ECORE_MAC:
2913                 return "MAC";
2914         case ECORE_VLAN:
2915                 return "VLAN";
2916         case ECORE_RDMA_CNQ_RAM:
2917                 return "RDMA_CNQ_RAM";
2918         case ECORE_ILT:
2919                 return "ILT";
2920         case ECORE_LL2_QUEUE:
2921                 return "LL2_QUEUE";
2922         case ECORE_CMDQS_CQS:
2923                 return "CMDQS_CQS";
2924         case ECORE_RDMA_STATS_QUEUE:
2925                 return "RDMA_STATS_QUEUE";
2926         case ECORE_BDQ:
2927                 return "BDQ";
2928         case ECORE_SB:
2929                 return "SB";
2930         default:
2931                 return "UNKNOWN_RESOURCE";
2932         }
2933 }
2934
2935 static enum _ecore_status_t
2936 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2937                               struct ecore_ptt *p_ptt,
2938                               enum ecore_resources res_id,
2939                               u32 resc_max_val,
2940                               u32 *p_mcp_resp)
2941 {
2942         enum _ecore_status_t rc;
2943
2944         rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2945                                         resc_max_val, p_mcp_resp);
2946         if (rc != ECORE_SUCCESS) {
2947                 DP_NOTICE(p_hwfn, true,
2948                           "MFW response failure for a max value setting of resource %d [%s]\n",
2949                           res_id, ecore_hw_get_resc_name(res_id));
2950                 return rc;
2951         }
2952
2953         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2954                 DP_INFO(p_hwfn,
2955                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2956                         res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
2957
2958         return ECORE_SUCCESS;
2959 }
2960
2961 static enum _ecore_status_t
2962 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2963                             struct ecore_ptt *p_ptt)
2964 {
2965         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2966         u32 resc_max_val, mcp_resp;
2967         u8 res_id;
2968         enum _ecore_status_t rc;
2969
2970         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2971                 /* @DPDK */
2972                 switch (res_id) {
2973                 case ECORE_LL2_QUEUE:
2974                 case ECORE_RDMA_CNQ_RAM:
2975                 case ECORE_RDMA_STATS_QUEUE:
2976                 case ECORE_BDQ:
2977                         resc_max_val = 0;
2978                         break;
2979                 default:
2980                         continue;
2981                 }
2982
2983                 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2984                                                    resc_max_val, &mcp_resp);
2985                 if (rc != ECORE_SUCCESS)
2986                         return rc;
2987
2988                 /* There's no point to continue to the next resource if the
2989                  * command is not supported by the MFW.
2990                  * We do continue if the command is supported but the resource
2991                  * is unknown to the MFW. Such a resource will be later
2992                  * configured with the default allocation values.
2993                  */
2994                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2995                         return ECORE_NOTIMPL;
2996         }
2997
2998         return ECORE_SUCCESS;
2999 }
3000
3001 static
3002 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
3003                                             enum ecore_resources res_id,
3004                                             u32 *p_resc_num, u32 *p_resc_start)
3005 {
3006         u8 num_funcs = p_hwfn->num_funcs_on_engine;
3007         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3008
3009         switch (res_id) {
3010         case ECORE_L2_QUEUE:
3011                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
3012                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
3013                 break;
3014         case ECORE_VPORT:
3015                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3016                                  MAX_NUM_VPORTS_BB) / num_funcs;
3017                 break;
3018         case ECORE_RSS_ENG:
3019                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
3020                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
3021                 break;
3022         case ECORE_PQ:
3023                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
3024                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
3025                 break;
3026         case ECORE_RL:
3027                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
3028                 break;
3029         case ECORE_MAC:
3030         case ECORE_VLAN:
3031                 /* Each VFC resource can accommodate both a MAC and a VLAN */
3032                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3033                 break;
3034         case ECORE_ILT:
3035                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
3036                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
3037                 break;
3038         case ECORE_LL2_QUEUE:
3039                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
3040                 break;
3041         case ECORE_RDMA_CNQ_RAM:
3042         case ECORE_CMDQS_CQS:
3043                 /* CNQ/CMDQS are the same resource */
3044                 /* @DPDK */
3045                 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
3046                 break;
3047         case ECORE_RDMA_STATS_QUEUE:
3048                 /* @DPDK */
3049                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3050                                  MAX_NUM_VPORTS_BB) / num_funcs;
3051                 break;
3052         case ECORE_BDQ:
3053                 /* @DPDK */
3054                 *p_resc_num = 0;
3055                 break;
3056         default:
3057                 break;
3058         }
3059
3060
3061         switch (res_id) {
3062         case ECORE_BDQ:
3063                 if (!*p_resc_num)
3064                         *p_resc_start = 0;
3065                 break;
3066         case ECORE_SB:
3067                 /* Since we want its value to reflect whether MFW supports
3068                  * the new scheme, have a default of 0.
3069                  */
3070                 *p_resc_num = 0;
3071                 break;
3072         default:
3073                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3074                 break;
3075         }
3076
3077         return ECORE_SUCCESS;
3078 }
3079
3080 static enum _ecore_status_t
3081 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
3082                          bool drv_resc_alloc)
3083 {
3084         u32 dflt_resc_num = 0, dflt_resc_start = 0;
3085         u32 mcp_resp, *p_resc_num, *p_resc_start;
3086         enum _ecore_status_t rc;
3087
3088         p_resc_num = &RESC_NUM(p_hwfn, res_id);
3089         p_resc_start = &RESC_START(p_hwfn, res_id);
3090
3091         rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3092                                     &dflt_resc_start);
3093         if (rc != ECORE_SUCCESS) {
3094                 DP_ERR(p_hwfn,
3095                        "Failed to get default amount for resource %d [%s]\n",
3096                         res_id, ecore_hw_get_resc_name(res_id));
3097                 return rc;
3098         }
3099
3100 #ifndef ASIC_ONLY
3101         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3102                 *p_resc_num = dflt_resc_num;
3103                 *p_resc_start = dflt_resc_start;
3104                 goto out;
3105         }
3106 #endif
3107
3108         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3109                                      &mcp_resp, p_resc_num, p_resc_start);
3110         if (rc != ECORE_SUCCESS) {
3111                 DP_NOTICE(p_hwfn, true,
3112                           "MFW response failure for an allocation request for"
3113                           " resource %d [%s]\n",
3114                           res_id, ecore_hw_get_resc_name(res_id));
3115                 return rc;
3116         }
3117
3118         /* Default driver values are applied in the following cases:
3119          * - The resource allocation MB command is not supported by the MFW
3120          * - There is an internal error in the MFW while processing the request
3121          * - The resource ID is unknown to the MFW
3122          */
3123         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3124                 DP_INFO(p_hwfn,
3125                         "Failed to receive allocation info for resource %d [%s]."
3126                         " mcp_resp = 0x%x. Applying default values"
3127                         " [%d,%d].\n",
3128                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
3129                         dflt_resc_num, dflt_resc_start);
3130
3131                 *p_resc_num = dflt_resc_num;
3132                 *p_resc_start = dflt_resc_start;
3133                 goto out;
3134         }
3135
3136         if ((*p_resc_num != dflt_resc_num ||
3137              *p_resc_start != dflt_resc_start) &&
3138             res_id != ECORE_SB) {
3139                 DP_INFO(p_hwfn,
3140                         "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
3141                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
3142                         *p_resc_start, dflt_resc_num, dflt_resc_start,
3143                         drv_resc_alloc ? " - Applying default values" : "");
3144                 if (drv_resc_alloc) {
3145                         *p_resc_num = dflt_resc_num;
3146                         *p_resc_start = dflt_resc_start;
3147                 }
3148         }
3149 out:
3150         return ECORE_SUCCESS;
3151 }
3152
3153 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
3154                                                    bool drv_resc_alloc)
3155 {
3156         enum _ecore_status_t rc;
3157         u8 res_id;
3158
3159         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3160                 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
3161                 if (rc != ECORE_SUCCESS)
3162                         return rc;
3163         }
3164
3165         return ECORE_SUCCESS;
3166 }
3167
3168 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
3169                                               struct ecore_ptt *p_ptt,
3170                                               bool drv_resc_alloc)
3171 {
3172         struct ecore_resc_unlock_params resc_unlock_params;
3173         struct ecore_resc_lock_params resc_lock_params;
3174         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3175         u8 res_id;
3176         enum _ecore_status_t rc;
3177 #ifndef ASIC_ONLY
3178         u32 *resc_start = p_hwfn->hw_info.resc_start;
3179         u32 *resc_num = p_hwfn->hw_info.resc_num;
3180         /* For AH, an equal share of the ILT lines between the maximal number of
3181          * PFs is not enough for RoCE. This would be solved by the future
3182          * resource allocation scheme, but isn't currently present for
3183          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
3184          * to work - the BB number of ILT lines divided by its max PFs number.
3185          */
3186         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
3187 #endif
3188
3189         /* Setting the max values of the soft resources and the following
3190          * resources allocation queries should be atomic. Since several PFs can
3191          * run in parallel - a resource lock is needed.
3192          * If either the resource lock or resource set value commands are not
3193          * supported - skip the the max values setting, release the lock if
3194          * needed, and proceed to the queries. Other failures, including a
3195          * failure to acquire the lock, will cause this function to fail.
3196          * Old drivers that don't acquire the lock can run in parallel, and
3197          * their allocation values won't be affected by the updated max values.
3198          */
3199         ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3200                                          ECORE_RESC_LOCK_RESC_ALLOC, false);
3201
3202         rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3203         if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3204                 return rc;
3205         } else if (rc == ECORE_NOTIMPL) {
3206                 DP_INFO(p_hwfn,
3207                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3208         } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
3209                 DP_NOTICE(p_hwfn, false,
3210                           "Failed to acquire the resource lock for the resource allocation commands\n");
3211                 rc = ECORE_BUSY;
3212                 goto unlock_and_exit;
3213         } else {
3214                 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
3215                 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3216                         DP_NOTICE(p_hwfn, false,
3217                                   "Failed to set the max values of the soft resources\n");
3218                         goto unlock_and_exit;
3219                 } else if (rc == ECORE_NOTIMPL) {
3220                         DP_INFO(p_hwfn,
3221                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3222                         rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3223                                                    &resc_unlock_params);
3224                         if (rc != ECORE_SUCCESS)
3225                                 DP_INFO(p_hwfn,
3226                                         "Failed to release the resource lock for the resource allocation commands\n");
3227                 }
3228         }
3229
3230         rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
3231         if (rc != ECORE_SUCCESS)
3232                 goto unlock_and_exit;
3233
3234         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3235                 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3236                                            &resc_unlock_params);
3237                 if (rc != ECORE_SUCCESS)
3238                         DP_INFO(p_hwfn,
3239                                 "Failed to release the resource lock for the resource allocation commands\n");
3240         }
3241
3242 #ifndef ASIC_ONLY
3243         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3244                 /* Reduced build contains less PQs */
3245                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
3246                         resc_num[ECORE_PQ] = 32;
3247                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
3248                             p_hwfn->enabled_func_idx;
3249                 }
3250
3251                 /* For AH emulation, since we have a possible maximal number of
3252                  * 16 enabled PFs, in case there are not enough ILT lines -
3253                  * allocate only first PF as RoCE and have all the other ETH
3254                  * only with less ILT lines.
3255                  */
3256                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
3257                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
3258                                                          resc_num[ECORE_ILT],
3259                                                          roce_min_ilt_lines);
3260         }
3261
3262         /* Correct the common ILT calculation if PF0 has more */
3263         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
3264             p_hwfn->p_dev->b_is_emul_full &&
3265             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
3266                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
3267                     resc_num[ECORE_ILT];
3268 #endif
3269
3270         /* Sanity for ILT */
3271         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3272             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3273                 DP_NOTICE(p_hwfn, true,
3274                           "Can't assign ILT pages [%08x,...,%08x]\n",
3275                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
3276                                                                   ECORE_ILT) -
3277                           1);
3278                 return ECORE_INVAL;
3279         }
3280
3281         /* This will also learn the number of SBs from MFW */
3282         if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
3283                 return ECORE_INVAL;
3284
3285         ecore_hw_set_feat(p_hwfn);
3286
3287         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3288                    "The numbers for each resource are:\n");
3289         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
3290                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
3291                            ecore_hw_get_resc_name(res_id),
3292                            RESC_NUM(p_hwfn, res_id),
3293                            RESC_START(p_hwfn, res_id));
3294
3295         return ECORE_SUCCESS;
3296
3297 unlock_and_exit:
3298         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3299                 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3300                                       &resc_unlock_params);
3301         return rc;
3302 }
3303
3304 static enum _ecore_status_t
3305 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
3306                       struct ecore_ptt *p_ptt,
3307                       struct ecore_hw_prepare_params *p_params)
3308 {
3309         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
3310         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
3311         struct ecore_mcp_link_capabilities *p_caps;
3312         struct ecore_mcp_link_params *link;
3313         enum _ecore_status_t rc;
3314
3315         /* Read global nvm_cfg address */
3316         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
3317
3318         /* Verify MCP has initialized it */
3319         if (!nvm_cfg_addr) {
3320                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
3321                 if (p_params->b_relaxed_probe)
3322                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
3323                 return ECORE_INVAL;
3324         }
3325
3326 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
3327
3328         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
3329
3330         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3331             OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
3332                                                        core_cfg);
3333
3334         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
3335
3336         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
3337                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
3338         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
3339                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
3340                 break;
3341         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
3342                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
3343                 break;
3344         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
3345                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
3346                 break;
3347         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
3348                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
3349                 break;
3350         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
3351                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
3352                 break;
3353         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
3354                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
3355                 break;
3356         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
3357                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
3358                 break;
3359         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
3360                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
3361                 break;
3362         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
3363                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
3364                 break;
3365         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
3366                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
3367                 break;
3368         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3369                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
3370                 break;
3371         default:
3372                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
3373                           core_cfg);
3374                 break;
3375         }
3376
3377         /* Read DCBX configuration */
3378         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3379                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3380         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
3381                              port_cfg_addr +
3382                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
3383         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
3384                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
3385         switch (dcbx_mode) {
3386         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
3387                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
3388                 break;
3389         case NVM_CFG1_PORT_DCBX_MODE_CEE:
3390                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
3391                 break;
3392         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
3393                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
3394                 break;
3395         default:
3396                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
3397         }
3398
3399         /* Read default link configuration */
3400         link = &p_hwfn->mcp_info->link_input;
3401         p_caps = &p_hwfn->mcp_info->link_capabilities;
3402         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3403             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3404         link_temp = ecore_rd(p_hwfn, p_ptt,
3405                              port_cfg_addr +
3406                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
3407         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
3408         link->speed.advertised_speeds = link_temp;
3409         p_caps->speed_capabilities = link->speed.advertised_speeds;
3410
3411         link_temp = ecore_rd(p_hwfn, p_ptt,
3412                              port_cfg_addr +
3413                              OFFSETOF(struct nvm_cfg1_port, link_settings));
3414         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
3415                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
3416         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
3417                 link->speed.autoneg = true;
3418                 break;
3419         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
3420                 link->speed.forced_speed = 1000;
3421                 break;
3422         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
3423                 link->speed.forced_speed = 10000;
3424                 break;
3425         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3426                 link->speed.forced_speed = 25000;
3427                 break;
3428         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3429                 link->speed.forced_speed = 40000;
3430                 break;
3431         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3432                 link->speed.forced_speed = 50000;
3433                 break;
3434         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3435                 link->speed.forced_speed = 100000;
3436                 break;
3437         default:
3438                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
3439         }
3440
3441         p_caps->default_speed = link->speed.forced_speed;
3442         p_caps->default_speed_autoneg = link->speed.autoneg;
3443
3444         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3445         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3446         link->pause.autoneg = !!(link_temp &
3447                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3448         link->pause.forced_rx = !!(link_temp &
3449                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3450         link->pause.forced_tx = !!(link_temp &
3451                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3452         link->loopback_mode = 0;
3453
3454         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
3455                 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
3456                                      OFFSETOF(struct nvm_cfg1_port, ext_phy));
3457                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
3458                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
3459                 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
3460                 link->eee.enable = true;
3461                 switch (link_temp) {
3462                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
3463                         p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
3464                         link->eee.enable = false;
3465                         break;
3466                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
3467                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
3468                         break;
3469                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
3470                         p_caps->eee_lpi_timer =
3471                                 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
3472                         break;
3473                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
3474                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
3475                         break;
3476                 }
3477
3478                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
3479                 link->eee.tx_lpi_enable = link->eee.enable;
3480                 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
3481         } else {
3482                 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
3483         }
3484
3485         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3486                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
3487                    link->speed.forced_speed, link->speed.advertised_speeds,
3488                    link->speed.autoneg, link->pause.autoneg,
3489                    p_caps->default_eee, p_caps->eee_lpi_timer);
3490
3491         /* Read Multi-function information from shmem */
3492         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3493             OFFSETOF(struct nvm_cfg1, glob) +
3494             OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3495
3496         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3497
3498         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3499             NVM_CFG1_GLOB_MF_MODE_OFFSET;
3500
3501         switch (mf_mode) {
3502         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3503                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS;
3504                 break;
3505         case NVM_CFG1_GLOB_MF_MODE_UFP:
3506                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
3507                                          1 << ECORE_MF_UFP_SPECIFIC;
3508                 break;
3509
3510         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3511                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3512                                          1 << ECORE_MF_LLH_PROTO_CLSS |
3513                                          1 << ECORE_MF_LL2_NON_UNICAST |
3514                                          1 << ECORE_MF_INTER_PF_SWITCH;
3515                 break;
3516         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3517                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3518                                          1 << ECORE_MF_LLH_PROTO_CLSS |
3519                                          1 << ECORE_MF_LL2_NON_UNICAST;
3520                 if (ECORE_IS_BB(p_hwfn->p_dev))
3521                         p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
3522                 break;
3523         }
3524         DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
3525                 p_hwfn->p_dev->mf_bits);
3526
3527         /* It's funny since we have another switch, but it's easier
3528          * to throw this away in linux this way. Long term, it might be
3529          * better to have have getters for needed ECORE_MF_* fields,
3530          * convert client code and eliminate this.
3531          */
3532         switch (mf_mode) {
3533         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3534                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3535                 break;
3536         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3537                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3538                 break;
3539         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3540                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3541                 break;
3542         case NVM_CFG1_GLOB_MF_MODE_UFP:
3543                 p_hwfn->p_dev->mf_mode = ECORE_MF_UFP;
3544                 break;
3545         }
3546
3547         /* Read Multi-function information from shmem */
3548         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3549             OFFSETOF(struct nvm_cfg1, glob) +
3550             OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3551
3552         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3553         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3554                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3555                              &p_hwfn->hw_info.device_capabilities);
3556         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3557                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3558                              &p_hwfn->hw_info.device_capabilities);
3559         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3560                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3561                              &p_hwfn->hw_info.device_capabilities);
3562         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3563                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3564                              &p_hwfn->hw_info.device_capabilities);
3565         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3566                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3567                              &p_hwfn->hw_info.device_capabilities);
3568
3569         rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3570         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3571                 rc = ECORE_SUCCESS;
3572                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3573         }
3574
3575         return rc;
3576 }
3577
3578 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3579                                 struct ecore_ptt *p_ptt)
3580 {
3581         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3582         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3583         struct ecore_dev *p_dev = p_hwfn->p_dev;
3584
3585         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3586
3587         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3588          * in the other bits are selected.
3589          * Bits 1-15 are for functions 1-15, respectively, and their value is
3590          * '0' only for enabled functions (function 0 always exists and
3591          * enabled).
3592          * In case of CMT in BB, only the "even" functions are enabled, and thus
3593          * the number of functions for both hwfns is learnt from the same bits.
3594          */
3595         if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3596                 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3597                                              MISCS_REG_FUNCTION_HIDE_BB_K2);
3598         } else { /* E5 */
3599                 reg_function_hide = 0;
3600         }
3601
3602         if (reg_function_hide & 0x1) {
3603                 if (ECORE_IS_BB(p_dev)) {
3604                         if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) {
3605                                 num_funcs = 0;
3606                                 eng_mask = 0xaaaa;
3607                         } else {
3608                                 num_funcs = 1;
3609                                 eng_mask = 0x5554;
3610                         }
3611                 } else {
3612                         num_funcs = 1;
3613                         eng_mask = 0xfffe;
3614                 }
3615
3616                 /* Get the number of the enabled functions on the engine */
3617                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3618                 while (tmp) {
3619                         if (tmp & 0x1)
3620                                 num_funcs++;
3621                         tmp >>= 0x1;
3622                 }
3623
3624                 /* Get the PF index within the enabled functions */
3625                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3626                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3627                 while (tmp) {
3628                         if (tmp & 0x1)
3629                                 enabled_func_idx--;
3630                         tmp >>= 0x1;
3631                 }
3632         }
3633
3634         p_hwfn->num_funcs_on_engine = num_funcs;
3635         p_hwfn->enabled_func_idx = enabled_func_idx;
3636
3637 #ifndef ASIC_ONLY
3638         if (CHIP_REV_IS_FPGA(p_dev)) {
3639                 DP_NOTICE(p_hwfn, false,
3640                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3641                 p_hwfn->num_funcs_on_engine = 4;
3642         }
3643 #endif
3644
3645         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3646                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3647                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3648                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3649 }
3650
3651 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3652                                       struct ecore_ptt *p_ptt)
3653 {
3654         struct ecore_dev *p_dev = p_hwfn->p_dev;
3655         u32 port_mode;
3656
3657 #ifndef ASIC_ONLY
3658         /* Read the port mode */
3659         if (CHIP_REV_IS_FPGA(p_dev))
3660                 port_mode = 4;
3661         else if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_CMT(p_dev))
3662                 /* In CMT on emulation, assume 1 port */
3663                 port_mode = 1;
3664         else
3665 #endif
3666         port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3667
3668         if (port_mode < 3) {
3669                 p_dev->num_ports_in_engine = 1;
3670         } else if (port_mode <= 5) {
3671                 p_dev->num_ports_in_engine = 2;
3672         } else {
3673                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3674                           p_dev->num_ports_in_engine);
3675
3676                 /* Default num_ports_in_engine to something */
3677                 p_dev->num_ports_in_engine = 1;
3678         }
3679 }
3680
3681 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3682                                          struct ecore_ptt *p_ptt)
3683 {
3684         struct ecore_dev *p_dev = p_hwfn->p_dev;
3685         u32 port;
3686         int i;
3687
3688         p_dev->num_ports_in_engine = 0;
3689
3690 #ifndef ASIC_ONLY
3691         if (CHIP_REV_IS_EMUL(p_dev)) {
3692                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3693                 switch ((port & 0xf000) >> 12) {
3694                 case 1:
3695                         p_dev->num_ports_in_engine = 1;
3696                         break;
3697                 case 3:
3698                         p_dev->num_ports_in_engine = 2;
3699                         break;
3700                 case 0xf:
3701                         p_dev->num_ports_in_engine = 4;
3702                         break;
3703                 default:
3704                         DP_NOTICE(p_hwfn, false,
3705                                   "Unknown port mode in ECO_RESERVED %08x\n",
3706                                   port);
3707                 }
3708         } else
3709 #endif
3710                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3711                         port = ecore_rd(p_hwfn, p_ptt,
3712                                         CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3713                                         (i * 4));
3714                         if (port & 1)
3715                                 p_dev->num_ports_in_engine++;
3716                 }
3717
3718         if (!p_dev->num_ports_in_engine) {
3719                 DP_NOTICE(p_hwfn, true, "All NIG ports are inactive\n");
3720
3721                 /* Default num_ports_in_engine to something */
3722                 p_dev->num_ports_in_engine = 1;
3723         }
3724 }
3725
3726 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3727                                    struct ecore_ptt *p_ptt)
3728 {
3729         struct ecore_dev *p_dev = p_hwfn->p_dev;
3730
3731         /* Determine the number of ports per engine */
3732         if (ECORE_IS_BB(p_dev))
3733                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3734         else
3735                 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3736
3737         /* Get the total number of ports of the device */
3738         if (ECORE_IS_CMT(p_dev)) {
3739                 /* In CMT there is always only one port */
3740                 p_dev->num_ports = 1;
3741 #ifndef ASIC_ONLY
3742         } else if (CHIP_REV_IS_EMUL(p_dev) || CHIP_REV_IS_TEDIBEAR(p_dev)) {
3743                 p_dev->num_ports = p_dev->num_ports_in_engine *
3744                                    ecore_device_num_engines(p_dev);
3745 #endif
3746         } else {
3747                 u32 addr, global_offsize, global_addr;
3748
3749                 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
3750                                             PUBLIC_GLOBAL);
3751                 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
3752                 global_addr = SECTION_ADDR(global_offsize, 0);
3753                 addr = global_addr + OFFSETOF(struct public_global, max_ports);
3754                 p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
3755         }
3756 }
3757
3758 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
3759                                    struct ecore_ptt *p_ptt)
3760 {
3761         struct ecore_mcp_link_capabilities *p_caps;
3762         u32 eee_status;
3763
3764         p_caps = &p_hwfn->mcp_info->link_capabilities;
3765         if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
3766                 return;
3767
3768         p_caps->eee_speed_caps = 0;
3769         eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
3770                               OFFSETOF(struct public_port, eee_status));
3771         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
3772                         EEE_SUPPORTED_SPEED_OFFSET;
3773         if (eee_status & EEE_1G_SUPPORTED)
3774                 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
3775         if (eee_status & EEE_10G_ADV)
3776                 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
3777 }
3778
3779 static enum _ecore_status_t
3780 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3781                   enum ecore_pci_personality personality,
3782                   struct ecore_hw_prepare_params *p_params)
3783 {
3784         bool drv_resc_alloc = p_params->drv_resc_alloc;
3785         enum _ecore_status_t rc;
3786
3787         /* Since all information is common, only first hwfns should do this */
3788         if (IS_LEAD_HWFN(p_hwfn)) {
3789                 rc = ecore_iov_hw_info(p_hwfn);
3790                 if (rc != ECORE_SUCCESS) {
3791                         if (p_params->b_relaxed_probe)
3792                                 p_params->p_relaxed_res =
3793                                                 ECORE_HW_PREPARE_BAD_IOV;
3794                         else
3795                                 return rc;
3796                 }
3797         }
3798
3799         if (IS_LEAD_HWFN(p_hwfn))
3800                 ecore_hw_info_port_num(p_hwfn, p_ptt);
3801
3802         ecore_mcp_get_capabilities(p_hwfn, p_ptt);
3803
3804 #ifndef ASIC_ONLY
3805         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3806 #endif
3807         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3808         if (rc != ECORE_SUCCESS)
3809                 return rc;
3810 #ifndef ASIC_ONLY
3811         }
3812 #endif
3813
3814         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3815         if (rc != ECORE_SUCCESS) {
3816                 if (p_params->b_relaxed_probe)
3817                         p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3818                 else
3819                         return rc;
3820         }
3821
3822 #ifndef ASIC_ONLY
3823         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3824 #endif
3825                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3826                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3827 #ifndef ASIC_ONLY
3828         } else {
3829                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3830
3831                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3832                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3833         }
3834 #endif
3835
3836         if (ecore_mcp_is_init(p_hwfn)) {
3837                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3838                         p_hwfn->hw_info.ovlan =
3839                             p_hwfn->mcp_info->func_info.ovlan;
3840
3841                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3842
3843                 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
3844
3845                 ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
3846         }
3847
3848         if (personality != ECORE_PCI_DEFAULT) {
3849                 p_hwfn->hw_info.personality = personality;
3850         } else if (ecore_mcp_is_init(p_hwfn)) {
3851                 enum ecore_pci_personality protocol;
3852
3853                 protocol = p_hwfn->mcp_info->func_info.protocol;
3854                 p_hwfn->hw_info.personality = protocol;
3855         }
3856
3857 #ifndef ASIC_ONLY
3858         /* To overcome ILT lack for emulation, until at least until we'll have
3859          * a definite answer from system about it, allow only PF0 to be RoCE.
3860          */
3861         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3862                 if (!p_hwfn->rel_pf_id)
3863                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3864                 else
3865                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3866         }
3867 #endif
3868
3869         /* although in BB some constellations may support more than 4 tcs,
3870          * that can result in performance penalty in some cases. 4
3871          * represents a good tradeoff between performance and flexibility.
3872          */
3873         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3874
3875         /* start out with a single active tc. This can be increased either
3876          * by dcbx negotiation or by upper layer driver
3877          */
3878         p_hwfn->hw_info.num_active_tc = 1;
3879
3880         ecore_get_num_funcs(p_hwfn, p_ptt);
3881
3882         if (ecore_mcp_is_init(p_hwfn))
3883                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3884
3885         /* In case of forcing the driver's default resource allocation, calling
3886          * ecore_hw_get_resc() should come after initializing the personality
3887          * and after getting the number of functions, since the calculation of
3888          * the resources/features depends on them.
3889          * This order is not harmful if not forcing.
3890          */
3891         rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
3892         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3893                 rc = ECORE_SUCCESS;
3894                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3895         }
3896
3897         return rc;
3898 }
3899
3900 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
3901                                                struct ecore_ptt *p_ptt)
3902 {
3903         struct ecore_dev *p_dev = p_hwfn->p_dev;
3904         u16 device_id_mask;
3905         u32 tmp;
3906
3907         /* Read Vendor Id / Device Id */
3908         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3909                                   &p_dev->vendor_id);
3910         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3911                                   &p_dev->device_id);
3912
3913         /* Determine type */
3914         device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
3915         switch (device_id_mask) {
3916         case ECORE_DEV_ID_MASK_BB:
3917                 p_dev->type = ECORE_DEV_TYPE_BB;
3918                 break;
3919         case ECORE_DEV_ID_MASK_AH:
3920                 p_dev->type = ECORE_DEV_TYPE_AH;
3921                 break;
3922         default:
3923                 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
3924                           p_dev->device_id);
3925                 return ECORE_ABORTED;
3926         }
3927
3928         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
3929         p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM);
3930         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
3931         p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV);
3932
3933         /* Learn number of HW-functions */
3934         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
3935
3936         if (tmp & (1 << p_hwfn->rel_pf_id)) {
3937                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3938                 p_dev->num_hwfns = 2;
3939         } else {
3940                 p_dev->num_hwfns = 1;
3941         }
3942
3943 #ifndef ASIC_ONLY
3944         if (CHIP_REV_IS_EMUL(p_dev)) {
3945                 /* For some reason we have problems with this register
3946                  * in B0 emulation; Simply assume no CMT
3947                  */
3948                 DP_NOTICE(p_dev->hwfns, false,
3949                           "device on emul - assume no CMT\n");
3950                 p_dev->num_hwfns = 1;
3951         }
3952 #endif
3953
3954         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG);
3955         p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID);
3956         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
3957         p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL);
3958
3959         DP_INFO(p_dev->hwfns,
3960                 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n",
3961                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3962                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3963                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3964                 p_dev->chip_metal);
3965
3966         if (ECORE_IS_BB_A0(p_dev)) {
3967                 DP_NOTICE(p_dev->hwfns, false,
3968                           "The chip type/rev (BB A0) is not supported!\n");
3969                 return ECORE_ABORTED;
3970         }
3971 #ifndef ASIC_ONLY
3972         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3973                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3974
3975         if (CHIP_REV_IS_EMUL(p_dev)) {
3976                 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3977                 if (tmp & (1 << 29)) {
3978                         DP_NOTICE(p_hwfn, false,
3979                                   "Emulation: Running on a FULL build\n");
3980                         p_dev->b_is_emul_full = true;
3981                 } else {
3982                         DP_NOTICE(p_hwfn, false,
3983                                   "Emulation: Running on a REDUCED build\n");
3984                 }
3985         }
3986 #endif
3987
3988         return ECORE_SUCCESS;
3989 }
3990
3991 #ifndef LINUX_REMOVE
3992 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3993 {
3994         int j;
3995
3996         if (IS_VF(p_dev))
3997                 return;
3998
3999         for_each_hwfn(p_dev, j) {
4000                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
4001
4002                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
4003                            "Mark hw/fw uninitialized\n");
4004
4005                 p_hwfn->hw_init_done = false;
4006
4007                 ecore_ptt_invalidate(p_hwfn);
4008         }
4009 }
4010 #endif
4011
4012 static enum _ecore_status_t
4013 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
4014                         void OSAL_IOMEM * p_regview,
4015                         void OSAL_IOMEM * p_doorbells,
4016                         struct ecore_hw_prepare_params *p_params)
4017 {
4018         struct ecore_mdump_retain_data mdump_retain;
4019         struct ecore_dev *p_dev = p_hwfn->p_dev;
4020         struct ecore_mdump_info mdump_info;
4021         enum _ecore_status_t rc = ECORE_SUCCESS;
4022
4023         /* Split PCI bars evenly between hwfns */
4024         p_hwfn->regview = p_regview;
4025         p_hwfn->doorbells = p_doorbells;
4026
4027         if (IS_VF(p_dev))
4028                 return ecore_vf_hw_prepare(p_hwfn);
4029
4030         /* Validate that chip access is feasible */
4031         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
4032                 DP_ERR(p_hwfn,
4033                        "Reading the ME register returns all Fs; Preventing further chip access\n");
4034                 if (p_params->b_relaxed_probe)
4035                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
4036                 return ECORE_INVAL;
4037         }
4038
4039         get_function_id(p_hwfn);
4040
4041         /* Allocate PTT pool */
4042         rc = ecore_ptt_pool_alloc(p_hwfn);
4043         if (rc) {
4044                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
4045                 if (p_params->b_relaxed_probe)
4046                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4047                 goto err0;
4048         }
4049
4050         /* Allocate the main PTT */
4051         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4052
4053         /* First hwfn learns basic information, e.g., number of hwfns */
4054         if (!p_hwfn->my_id) {
4055                 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
4056                 if (rc != ECORE_SUCCESS) {
4057                         if (p_params->b_relaxed_probe)
4058                                 p_params->p_relaxed_res =
4059                                         ECORE_HW_PREPARE_FAILED_DEV;
4060                         goto err1;
4061                 }
4062         }
4063
4064         ecore_hw_hwfn_prepare(p_hwfn);
4065
4066         /* Initialize MCP structure */
4067         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4068         if (rc) {
4069                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
4070                 if (p_params->b_relaxed_probe)
4071                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4072                 goto err1;
4073         }
4074
4075         /* Read the device configuration information from the HW and SHMEM */
4076         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
4077                                p_params->personality, p_params);
4078         if (rc) {
4079                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
4080                 goto err2;
4081         }
4082
4083         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
4084          * called, since among others it sets the ports number in an engine.
4085          */
4086         if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
4087             !p_dev->recov_in_prog) {
4088                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4089                 if (rc != ECORE_SUCCESS)
4090                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
4091         }
4092
4093         /* Check if mdump logs/data are present and update the epoch value */
4094         if (IS_LEAD_HWFN(p_hwfn)) {
4095 #ifndef ASIC_ONLY
4096                 if (!CHIP_REV_IS_EMUL(p_dev)) {
4097 #endif
4098                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
4099                                               &mdump_info);
4100                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
4101                         DP_NOTICE(p_hwfn, false,
4102                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
4103
4104                 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
4105                                                 &mdump_retain);
4106                 if (rc == ECORE_SUCCESS && mdump_retain.valid)
4107                         DP_NOTICE(p_hwfn, false,
4108                                   "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
4109                                   mdump_retain.epoch, mdump_retain.pf,
4110                                   mdump_retain.status);
4111
4112                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
4113                                            p_params->epoch);
4114 #ifndef ASIC_ONLY
4115                 }
4116 #endif
4117         }
4118
4119         /* Allocate the init RT array and initialize the init-ops engine */
4120         rc = ecore_init_alloc(p_hwfn);
4121         if (rc) {
4122                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
4123                 if (p_params->b_relaxed_probe)
4124                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4125                 goto err2;
4126         }
4127 #ifndef ASIC_ONLY
4128         if (CHIP_REV_IS_FPGA(p_dev)) {
4129                 DP_NOTICE(p_hwfn, false,
4130                           "FPGA: workaround; Prevent DMAE parities\n");
4131                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
4132                          7);
4133
4134                 DP_NOTICE(p_hwfn, false,
4135                           "FPGA: workaround: Set VF bar0 size\n");
4136                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4137                          PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
4138         }
4139 #endif
4140
4141         return rc;
4142 err2:
4143         if (IS_LEAD_HWFN(p_hwfn))
4144                 ecore_iov_free_hw_info(p_dev);
4145         ecore_mcp_free(p_hwfn);
4146 err1:
4147         ecore_hw_hwfn_free(p_hwfn);
4148 err0:
4149         return rc;
4150 }
4151
4152 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
4153                                       struct ecore_hw_prepare_params *p_params)
4154 {
4155         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4156         enum _ecore_status_t rc;
4157
4158         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
4159         p_dev->allow_mdump = p_params->allow_mdump;
4160
4161         if (p_params->b_relaxed_probe)
4162                 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
4163
4164         /* Store the precompiled init data ptrs */
4165         if (IS_PF(p_dev))
4166                 ecore_init_iro_array(p_dev);
4167
4168         /* Initialize the first hwfn - will learn number of hwfns */
4169         rc = ecore_hw_prepare_single(p_hwfn,
4170                                      p_dev->regview,
4171                                      p_dev->doorbells, p_params);
4172         if (rc != ECORE_SUCCESS)
4173                 return rc;
4174
4175         p_params->personality = p_hwfn->hw_info.personality;
4176
4177         /* initilalize 2nd hwfn if necessary */
4178         if (ECORE_IS_CMT(p_dev)) {
4179                 void OSAL_IOMEM *p_regview, *p_doorbell;
4180                 u8 OSAL_IOMEM *addr;
4181
4182                 /* adjust bar offset for second engine */
4183                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
4184                                         ecore_hw_bar_size(p_hwfn,
4185                                                           p_hwfn->p_main_ptt,
4186                                                           BAR_ID_0) / 2;
4187                 p_regview = (void OSAL_IOMEM *)addr;
4188
4189                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
4190                                         ecore_hw_bar_size(p_hwfn,
4191                                                           p_hwfn->p_main_ptt,
4192                                                           BAR_ID_1) / 2;
4193                 p_doorbell = (void OSAL_IOMEM *)addr;
4194
4195                 /* prepare second hw function */
4196                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
4197                                              p_doorbell, p_params);
4198
4199                 /* in case of error, need to free the previously
4200                  * initiliazed hwfn 0.
4201                  */
4202                 if (rc != ECORE_SUCCESS) {
4203                         if (p_params->b_relaxed_probe)
4204                                 p_params->p_relaxed_res =
4205                                                 ECORE_HW_PREPARE_FAILED_ENG2;
4206
4207                         if (IS_PF(p_dev)) {
4208                                 ecore_init_free(p_hwfn);
4209                                 ecore_mcp_free(p_hwfn);
4210                                 ecore_hw_hwfn_free(p_hwfn);
4211                         } else {
4212                                 DP_NOTICE(p_dev, true,
4213                                           "What do we need to free when VF hwfn1 init fails\n");
4214                         }
4215                         return rc;
4216                 }
4217         }
4218
4219         return rc;
4220 }
4221
4222 void ecore_hw_remove(struct ecore_dev *p_dev)
4223 {
4224         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4225         int i;
4226
4227         if (IS_PF(p_dev))
4228                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4229                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
4230
4231         for_each_hwfn(p_dev, i) {
4232                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4233
4234                 if (IS_VF(p_dev)) {
4235                         ecore_vf_pf_release(p_hwfn);
4236                         continue;
4237                 }
4238
4239                 ecore_init_free(p_hwfn);
4240                 ecore_hw_hwfn_free(p_hwfn);
4241                 ecore_mcp_free(p_hwfn);
4242
4243 #ifdef CONFIG_ECORE_LOCK_ALLOC
4244                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
4245 #endif
4246         }
4247
4248         ecore_iov_free_hw_info(p_dev);
4249 }
4250
4251 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
4252                                       struct ecore_chain *p_chain)
4253 {
4254         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
4255         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
4256         struct ecore_chain_next *p_next;
4257         u32 size, i;
4258
4259         if (!p_virt)
4260                 return;
4261
4262         size = p_chain->elem_size * p_chain->usable_per_page;
4263
4264         for (i = 0; i < p_chain->page_cnt; i++) {
4265                 if (!p_virt)
4266                         break;
4267
4268                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
4269                 p_virt_next = p_next->next_virt;
4270                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
4271
4272                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
4273                                        ECORE_CHAIN_PAGE_SIZE);
4274
4275                 p_virt = p_virt_next;
4276                 p_phys = p_phys_next;
4277         }
4278 }
4279
4280 static void ecore_chain_free_single(struct ecore_dev *p_dev,
4281                                     struct ecore_chain *p_chain)
4282 {
4283         if (!p_chain->p_virt_addr)
4284                 return;
4285
4286         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
4287                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
4288 }
4289
4290 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
4291                                  struct ecore_chain *p_chain)
4292 {
4293         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
4294         u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
4295         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
4296
4297         if (!pp_virt_addr_tbl)
4298                 return;
4299
4300         if (!p_pbl_virt)
4301                 goto out;
4302
4303         for (i = 0; i < page_cnt; i++) {
4304                 if (!pp_virt_addr_tbl[i])
4305                         break;
4306
4307                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
4308                                        *(dma_addr_t *)p_pbl_virt,
4309                                        ECORE_CHAIN_PAGE_SIZE);
4310
4311                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4312         }
4313
4314         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4315
4316         if (!p_chain->b_external_pbl)
4317                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
4318                                        p_chain->pbl_sp.p_phys_table, pbl_size);
4319 out:
4320         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
4321 }
4322
4323 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4324 {
4325         switch (p_chain->mode) {
4326         case ECORE_CHAIN_MODE_NEXT_PTR:
4327                 ecore_chain_free_next_ptr(p_dev, p_chain);
4328                 break;
4329         case ECORE_CHAIN_MODE_SINGLE:
4330                 ecore_chain_free_single(p_dev, p_chain);
4331                 break;
4332         case ECORE_CHAIN_MODE_PBL:
4333                 ecore_chain_free_pbl(p_dev, p_chain);
4334                 break;
4335         }
4336 }
4337
4338 static enum _ecore_status_t
4339 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
4340                                enum ecore_chain_cnt_type cnt_type,
4341                                osal_size_t elem_size, u32 page_cnt)
4342 {
4343         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
4344
4345         /* The actual chain size can be larger than the maximal possible value
4346          * after rounding up the requested elements number to pages, and after
4347          * taking into acount the unusuable elements (next-ptr elements).
4348          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
4349          * size/capacity fields are of a u32 type.
4350          */
4351         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
4352              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
4353             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
4354              chain_size > ECORE_U32_MAX)) {
4355                 DP_NOTICE(p_dev, true,
4356                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
4357                           (unsigned long)chain_size);
4358                 return ECORE_INVAL;
4359         }
4360
4361         return ECORE_SUCCESS;
4362 }
4363
4364 static enum _ecore_status_t
4365 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4366 {
4367         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
4368         dma_addr_t p_phys = 0;
4369         u32 i;
4370
4371         for (i = 0; i < p_chain->page_cnt; i++) {
4372                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4373                                                  ECORE_CHAIN_PAGE_SIZE);
4374                 if (!p_virt) {
4375                         DP_NOTICE(p_dev, true,
4376                                   "Failed to allocate chain memory\n");
4377                         return ECORE_NOMEM;
4378                 }
4379
4380                 if (i == 0) {
4381                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4382                         ecore_chain_reset(p_chain);
4383                 } else {
4384                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4385                                                        p_virt, p_phys);
4386                 }
4387
4388                 p_virt_prev = p_virt;
4389         }
4390         /* Last page's next element should point to the beginning of the
4391          * chain.
4392          */
4393         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4394                                        p_chain->p_virt_addr,
4395                                        p_chain->p_phys_addr);
4396
4397         return ECORE_SUCCESS;
4398 }
4399
4400 static enum _ecore_status_t
4401 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4402 {
4403         dma_addr_t p_phys = 0;
4404         void *p_virt = OSAL_NULL;
4405
4406         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
4407         if (!p_virt) {
4408                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
4409                 return ECORE_NOMEM;
4410         }
4411
4412         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4413         ecore_chain_reset(p_chain);
4414
4415         return ECORE_SUCCESS;
4416 }
4417
4418 static enum _ecore_status_t
4419 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
4420                       struct ecore_chain *p_chain,
4421                       struct ecore_chain_ext_pbl *ext_pbl)
4422 {
4423         void *p_virt = OSAL_NULL;
4424         u8 *p_pbl_virt = OSAL_NULL;
4425         void **pp_virt_addr_tbl = OSAL_NULL;
4426         dma_addr_t p_phys = 0, p_pbl_phys = 0;
4427         u32 page_cnt = p_chain->page_cnt, size, i;
4428
4429         size = page_cnt * sizeof(*pp_virt_addr_tbl);
4430         pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
4431         if (!pp_virt_addr_tbl) {
4432                 DP_NOTICE(p_dev, true,
4433                           "Failed to allocate memory for the chain virtual addresses table\n");
4434                 return ECORE_NOMEM;
4435         }
4436
4437         /* The allocation of the PBL table is done with its full size, since it
4438          * is expected to be successive.
4439          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
4440          * failure, since pp_virt_addr_tbl was previously allocated, and it
4441          * should be saved to allow its freeing during the error flow.
4442          */
4443         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4444
4445         if (ext_pbl == OSAL_NULL) {
4446                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
4447         } else {
4448                 p_pbl_virt = ext_pbl->p_pbl_virt;
4449                 p_pbl_phys = ext_pbl->p_pbl_phys;
4450                 p_chain->b_external_pbl = true;
4451         }
4452
4453         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
4454                                  pp_virt_addr_tbl);
4455         if (!p_pbl_virt) {
4456                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
4457                 return ECORE_NOMEM;
4458         }
4459
4460         for (i = 0; i < page_cnt; i++) {
4461                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4462                                                  ECORE_CHAIN_PAGE_SIZE);
4463                 if (!p_virt) {
4464                         DP_NOTICE(p_dev, true,
4465                                   "Failed to allocate chain memory\n");
4466                         return ECORE_NOMEM;
4467                 }
4468
4469                 if (i == 0) {
4470                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4471                         ecore_chain_reset(p_chain);
4472                 }
4473
4474                 /* Fill the PBL table with the physical address of the page */
4475                 *(dma_addr_t *)p_pbl_virt = p_phys;
4476                 /* Keep the virtual address of the page */
4477                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
4478
4479                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4480         }
4481
4482         return ECORE_SUCCESS;
4483 }
4484
4485 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
4486                                        enum ecore_chain_use_mode intended_use,
4487                                        enum ecore_chain_mode mode,
4488                                        enum ecore_chain_cnt_type cnt_type,
4489                                        u32 num_elems, osal_size_t elem_size,
4490                                        struct ecore_chain *p_chain,
4491                                        struct ecore_chain_ext_pbl *ext_pbl)
4492 {
4493         u32 page_cnt;
4494         enum _ecore_status_t rc = ECORE_SUCCESS;
4495
4496         if (mode == ECORE_CHAIN_MODE_SINGLE)
4497                 page_cnt = 1;
4498         else
4499                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4500
4501         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
4502                                             page_cnt);
4503         if (rc) {
4504                 DP_NOTICE(p_dev, true,
4505                           "Cannot allocate a chain with the given arguments:\n"
4506                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4507                           intended_use, mode, cnt_type, num_elems, elem_size);
4508                 return rc;
4509         }
4510
4511         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
4512                                 mode, cnt_type, p_dev->dp_ctx);
4513
4514         switch (mode) {
4515         case ECORE_CHAIN_MODE_NEXT_PTR:
4516                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
4517                 break;
4518         case ECORE_CHAIN_MODE_SINGLE:
4519                 rc = ecore_chain_alloc_single(p_dev, p_chain);
4520                 break;
4521         case ECORE_CHAIN_MODE_PBL:
4522                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
4523                 break;
4524         }
4525         if (rc)
4526                 goto nomem;
4527
4528         return ECORE_SUCCESS;
4529
4530 nomem:
4531         ecore_chain_free(p_dev, p_chain);
4532         return rc;
4533 }
4534
4535 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
4536                                        u16 src_id, u16 *dst_id)
4537 {
4538         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
4539                 u16 min, max;
4540
4541                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
4542                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
4543                 DP_NOTICE(p_hwfn, true,
4544                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4545                           src_id, min, max);
4546
4547                 return ECORE_INVAL;
4548         }
4549
4550         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
4551
4552         return ECORE_SUCCESS;
4553 }
4554
4555 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
4556                                     u8 src_id, u8 *dst_id)
4557 {
4558         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
4559                 u8 min, max;
4560
4561                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
4562                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
4563                 DP_NOTICE(p_hwfn, true,
4564                           "vport id [%d] is not valid, available indices [%d - %d]\n",
4565                           src_id, min, max);
4566
4567                 return ECORE_INVAL;
4568         }
4569
4570         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
4571
4572         return ECORE_SUCCESS;
4573 }
4574
4575 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
4576                                       u8 src_id, u8 *dst_id)
4577 {
4578         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
4579                 u8 min, max;
4580
4581                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
4582                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
4583                 DP_NOTICE(p_hwfn, true,
4584                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4585                           src_id, min, max);
4586
4587                 return ECORE_INVAL;
4588         }
4589
4590         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
4591
4592         return ECORE_SUCCESS;
4593 }
4594
4595 static enum _ecore_status_t
4596 ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4597                                struct ecore_ptt *p_ptt, u32 high, u32 low,
4598                                u32 *p_entry_num)
4599 {
4600         u32 en;
4601         int i;
4602
4603         /* Find a free entry and utilize it */
4604         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4605                 en = ecore_rd(p_hwfn, p_ptt,
4606                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4607                               i * sizeof(u32));
4608                 if (en)
4609                         continue;
4610                 ecore_wr(p_hwfn, p_ptt,
4611                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4612                          2 * i * sizeof(u32), low);
4613                 ecore_wr(p_hwfn, p_ptt,
4614                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4615                          (2 * i + 1) * sizeof(u32), high);
4616                 ecore_wr(p_hwfn, p_ptt,
4617                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4618                          i * sizeof(u32), 0);
4619                 ecore_wr(p_hwfn, p_ptt,
4620                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4621                          i * sizeof(u32), 0);
4622                 ecore_wr(p_hwfn, p_ptt,
4623                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4624                          i * sizeof(u32), 1);
4625                 break;
4626         }
4627
4628         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4629                 return ECORE_NORESOURCES;
4630
4631         *p_entry_num = i;
4632
4633         return ECORE_SUCCESS;
4634 }
4635
4636 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4637                                           struct ecore_ptt *p_ptt, u8 *p_filter)
4638 {
4639         u32 high, low, entry_num;
4640         enum _ecore_status_t rc;
4641
4642         if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4643                            &p_hwfn->p_dev->mf_bits))
4644                 return ECORE_SUCCESS;
4645
4646         high = p_filter[1] | (p_filter[0] << 8);
4647         low = p_filter[5] | (p_filter[4] << 8) |
4648               (p_filter[3] << 16) | (p_filter[2] << 24);
4649
4650         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4651                 rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low,
4652                                                     &entry_num);
4653         if (rc != ECORE_SUCCESS) {
4654                 DP_NOTICE(p_hwfn, false,
4655                           "Failed to find an empty LLH filter to utilize\n");
4656                 return rc;
4657         }
4658
4659         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4660                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n",
4661                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4662                    p_filter[4], p_filter[5], entry_num);
4663
4664         return ECORE_SUCCESS;
4665 }
4666
4667 static enum _ecore_status_t
4668 ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4669                                   struct ecore_ptt *p_ptt, u32 high, u32 low,
4670                                   u32 *p_entry_num)
4671 {
4672         int i;
4673
4674         /* Find the entry and clean it */
4675         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4676                 if (ecore_rd(p_hwfn, p_ptt,
4677                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4678                              2 * i * sizeof(u32)) != low)
4679                         continue;
4680                 if (ecore_rd(p_hwfn, p_ptt,
4681                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4682                              (2 * i + 1) * sizeof(u32)) != high)
4683                         continue;
4684
4685                 ecore_wr(p_hwfn, p_ptt,
4686                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4687                 ecore_wr(p_hwfn, p_ptt,
4688                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4689                          2 * i * sizeof(u32), 0);
4690                 ecore_wr(p_hwfn, p_ptt,
4691                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4692                          (2 * i + 1) * sizeof(u32), 0);
4693                 break;
4694         }
4695
4696         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4697                 return ECORE_INVAL;
4698
4699         *p_entry_num = i;
4700
4701         return ECORE_SUCCESS;
4702 }
4703
4704 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4705                              struct ecore_ptt *p_ptt, u8 *p_filter)
4706 {
4707         u32 high, low, entry_num;
4708         enum _ecore_status_t rc;
4709
4710         if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4711                            &p_hwfn->p_dev->mf_bits))
4712                 return;
4713
4714         high = p_filter[1] | (p_filter[0] << 8);
4715         low = p_filter[5] | (p_filter[4] << 8) |
4716               (p_filter[3] << 16) | (p_filter[2] << 24);
4717
4718         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4719                 rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high,
4720                                                        low, &entry_num);
4721         if (rc != ECORE_SUCCESS) {
4722                 DP_NOTICE(p_hwfn, false,
4723                           "Tried to remove a non-configured filter\n");
4724                 return;
4725         }
4726
4727
4728         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4729                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n",
4730                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4731                    p_filter[4], p_filter[5], entry_num);
4732 }
4733
4734 static enum _ecore_status_t
4735 ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4736                                     struct ecore_ptt *p_ptt,
4737                                     enum ecore_llh_port_filter_type_t type,
4738                                     u32 high, u32 low, u32 *p_entry_num)
4739 {
4740         u32 en;
4741         int i;
4742
4743         /* Find a free entry and utilize it */
4744         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4745                 en = ecore_rd(p_hwfn, p_ptt,
4746                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4747                               i * sizeof(u32));
4748                 if (en)
4749                         continue;
4750                 ecore_wr(p_hwfn, p_ptt,
4751                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4752                          2 * i * sizeof(u32), low);
4753                 ecore_wr(p_hwfn, p_ptt,
4754                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4755                          (2 * i + 1) * sizeof(u32), high);
4756                 ecore_wr(p_hwfn, p_ptt,
4757                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4758                          i * sizeof(u32), 1);
4759                 ecore_wr(p_hwfn, p_ptt,
4760                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4761                          i * sizeof(u32), 1 << type);
4762                 ecore_wr(p_hwfn, p_ptt,
4763                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1);
4764                 break;
4765         }
4766
4767         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4768                 return ECORE_NORESOURCES;
4769
4770         *p_entry_num = i;
4771
4772         return ECORE_SUCCESS;
4773 }
4774
4775 enum _ecore_status_t
4776 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4777                               struct ecore_ptt *p_ptt,
4778                               u16 source_port_or_eth_type,
4779                               u16 dest_port,
4780                               enum ecore_llh_port_filter_type_t type)
4781 {
4782         u32 high, low, entry_num;
4783         enum _ecore_status_t rc;
4784
4785         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
4786                            &p_hwfn->p_dev->mf_bits))
4787                 return ECORE_SUCCESS;
4788
4789         high = 0;
4790         low = 0;
4791
4792         switch (type) {
4793         case ECORE_LLH_FILTER_ETHERTYPE:
4794                 high = source_port_or_eth_type;
4795                 break;
4796         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4797         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4798                 low = source_port_or_eth_type << 16;
4799                 break;
4800         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4801         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4802                 low = dest_port;
4803                 break;
4804         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4805         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4806                 low = (source_port_or_eth_type << 16) | dest_port;
4807                 break;
4808         default:
4809                 DP_NOTICE(p_hwfn, true,
4810                           "Non valid LLH protocol filter type %d\n", type);
4811                 return ECORE_INVAL;
4812         }
4813
4814         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4815                 rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4816                                                          high, low, &entry_num);
4817         if (rc != ECORE_SUCCESS) {
4818                 DP_NOTICE(p_hwfn, false,
4819                           "Failed to find an empty LLH filter to utilize\n");
4820                 return rc;
4821         }
4822         switch (type) {
4823         case ECORE_LLH_FILTER_ETHERTYPE:
4824                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4825                            "ETH type %x is added at %d\n",
4826                            source_port_or_eth_type, entry_num);
4827                 break;
4828         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4829                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4830                            "TCP src port %x is added at %d\n",
4831                            source_port_or_eth_type, entry_num);
4832                 break;
4833         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4834                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4835                            "UDP src port %x is added at %d\n",
4836                            source_port_or_eth_type, entry_num);
4837                 break;
4838         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4839                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4840                            "TCP dst port %x is added at %d\n", dest_port,
4841                            entry_num);
4842                 break;
4843         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4844                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4845                            "UDP dst port %x is added at %d\n", dest_port,
4846                            entry_num);
4847                 break;
4848         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4849                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4850                            "TCP src/dst ports %x/%x are added at %d\n",
4851                            source_port_or_eth_type, dest_port, entry_num);
4852                 break;
4853         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4854                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4855                            "UDP src/dst ports %x/%x are added at %d\n",
4856                            source_port_or_eth_type, dest_port, entry_num);
4857                 break;
4858         }
4859
4860         return ECORE_SUCCESS;
4861 }
4862
4863 static enum _ecore_status_t
4864 ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4865                                        struct ecore_ptt *p_ptt,
4866                                        enum ecore_llh_port_filter_type_t type,
4867                                        u32 high, u32 low, u32 *p_entry_num)
4868 {
4869         int i;
4870
4871         /* Find the entry and clean it */
4872         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4873                 if (!ecore_rd(p_hwfn, p_ptt,
4874                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4875                               i * sizeof(u32)))
4876                         continue;
4877                 if (!ecore_rd(p_hwfn, p_ptt,
4878                               NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4879                               i * sizeof(u32)))
4880                         continue;
4881                 if (!(ecore_rd(p_hwfn, p_ptt,
4882                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4883                                i * sizeof(u32)) & (1 << type)))
4884                         continue;
4885                 if (ecore_rd(p_hwfn, p_ptt,
4886                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4887                              2 * i * sizeof(u32)) != low)
4888                         continue;
4889                 if (ecore_rd(p_hwfn, p_ptt,
4890                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4891                              (2 * i + 1) * sizeof(u32)) != high)
4892                         continue;
4893
4894                 ecore_wr(p_hwfn, p_ptt,
4895                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4896                 ecore_wr(p_hwfn, p_ptt,
4897                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4898                          i * sizeof(u32), 0);
4899                 ecore_wr(p_hwfn, p_ptt,
4900                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4901                          i * sizeof(u32), 0);
4902                 ecore_wr(p_hwfn, p_ptt,
4903                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4904                          2 * i * sizeof(u32), 0);
4905                 ecore_wr(p_hwfn, p_ptt,
4906                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4907                          (2 * i + 1) * sizeof(u32), 0);
4908                 break;
4909         }
4910
4911         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4912                 return ECORE_INVAL;
4913
4914         *p_entry_num = i;
4915
4916         return ECORE_SUCCESS;
4917 }
4918
4919 void
4920 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4921                                  struct ecore_ptt *p_ptt,
4922                                  u16 source_port_or_eth_type,
4923                                  u16 dest_port,
4924                                  enum ecore_llh_port_filter_type_t type)
4925 {
4926         u32 high, low, entry_num;
4927         enum _ecore_status_t rc;
4928
4929         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
4930                            &p_hwfn->p_dev->mf_bits))
4931                 return;
4932
4933         high = 0;
4934         low = 0;
4935
4936         switch (type) {
4937         case ECORE_LLH_FILTER_ETHERTYPE:
4938                 high = source_port_or_eth_type;
4939                 break;
4940         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4941         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4942                 low = source_port_or_eth_type << 16;
4943                 break;
4944         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4945         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4946                 low = dest_port;
4947                 break;
4948         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4949         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4950                 low = (source_port_or_eth_type << 16) | dest_port;
4951                 break;
4952         default:
4953                 DP_NOTICE(p_hwfn, true,
4954                           "Non valid LLH protocol filter type %d\n", type);
4955                 return;
4956         }
4957
4958         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4959                 rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4960                                                             high, low,
4961                                                             &entry_num);
4962         if (rc != ECORE_SUCCESS) {
4963                 DP_NOTICE(p_hwfn, false,
4964                           "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n",
4965                           type, source_port_or_eth_type, dest_port);
4966                 return;
4967         }
4968
4969         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4970                    "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n",
4971                    type, source_port_or_eth_type, dest_port, entry_num);
4972 }
4973
4974 static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn,
4975                                               struct ecore_ptt *p_ptt)
4976 {
4977         int i;
4978
4979         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4980                 return;
4981
4982         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4983                 ecore_wr(p_hwfn, p_ptt,
4984                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2  +
4985                          i * sizeof(u32), 0);
4986                 ecore_wr(p_hwfn, p_ptt,
4987                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4988                          2 * i * sizeof(u32), 0);
4989                 ecore_wr(p_hwfn, p_ptt,
4990                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4991                          (2 * i + 1) * sizeof(u32), 0);
4992         }
4993 }
4994
4995 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4996                              struct ecore_ptt *p_ptt)
4997 {
4998         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
4999                            &p_hwfn->p_dev->mf_bits) &&
5000             !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
5001                            &p_hwfn->p_dev->mf_bits))
5002                 return;
5003
5004         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5005                 ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt);
5006 }
5007
5008 enum _ecore_status_t
5009 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
5010                                   struct ecore_ptt *p_ptt)
5011 {
5012         if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
5013                 ecore_wr(p_hwfn, p_ptt,
5014                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
5015                          1 << p_hwfn->abs_pf_id / 2);
5016                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
5017                 return ECORE_SUCCESS;
5018         }
5019
5020         DP_NOTICE(p_hwfn, false,
5021                   "This function can't be set as default\n");
5022         return ECORE_INVAL;
5023 }
5024
5025 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
5026                                                struct ecore_ptt *p_ptt,
5027                                                u32 hw_addr, void *p_eth_qzone,
5028                                                osal_size_t eth_qzone_size,
5029                                                u8 timeset)
5030 {
5031         struct coalescing_timeset *p_coal_timeset;
5032
5033         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
5034                 DP_NOTICE(p_hwfn, true,
5035                           "Coalescing configuration not enabled\n");
5036                 return ECORE_INVAL;
5037         }
5038
5039         p_coal_timeset = p_eth_qzone;
5040         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
5041         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
5042         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
5043         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
5044
5045         return ECORE_SUCCESS;
5046 }
5047
5048 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
5049                                               u16 rx_coal, u16 tx_coal,
5050                                               void *p_handle)
5051 {
5052         struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
5053         enum _ecore_status_t rc = ECORE_SUCCESS;
5054         struct ecore_ptt *p_ptt;
5055
5056         /* TODO - Configuring a single queue's coalescing but
5057          * claiming all queues are abiding same configuration
5058          * for PF and VF both.
5059          */
5060
5061         if (IS_VF(p_hwfn->p_dev))
5062                 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
5063                                                 tx_coal, p_cid);
5064
5065         p_ptt = ecore_ptt_acquire(p_hwfn);
5066         if (!p_ptt)
5067                 return ECORE_AGAIN;
5068
5069         if (rx_coal) {
5070                 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
5071                 if (rc)
5072                         goto out;
5073                 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
5074         }
5075
5076         if (tx_coal) {
5077                 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
5078                 if (rc)
5079                         goto out;
5080                 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
5081         }
5082 out:
5083         ecore_ptt_release(p_hwfn, p_ptt);
5084
5085         return rc;
5086 }
5087
5088 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
5089                                             struct ecore_ptt *p_ptt,
5090                                             u16 coalesce,
5091                                             struct ecore_queue_cid *p_cid)
5092 {
5093         struct ustorm_eth_queue_zone eth_qzone;
5094         u8 timeset, timer_res;
5095         u32 address;
5096         enum _ecore_status_t rc;
5097
5098         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5099         if (coalesce <= 0x7F) {
5100                 timer_res = 0;
5101         } else if (coalesce <= 0xFF) {
5102                 timer_res = 1;
5103         } else if (coalesce <= 0x1FF) {
5104                 timer_res = 2;
5105         } else {
5106                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5107                 return ECORE_INVAL;
5108         }
5109         timeset = (u8)(coalesce >> timer_res);
5110
5111         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5112                                      p_cid->sb_igu_id, false);
5113         if (rc != ECORE_SUCCESS)
5114                 goto out;
5115
5116         address = BAR0_MAP_REG_USDM_RAM +
5117                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5118
5119         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5120                                 sizeof(struct ustorm_eth_queue_zone), timeset);
5121         if (rc != ECORE_SUCCESS)
5122                 goto out;
5123
5124 out:
5125         return rc;
5126 }
5127
5128 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
5129                                             struct ecore_ptt *p_ptt,
5130                                             u16 coalesce,
5131                                             struct ecore_queue_cid *p_cid)
5132 {
5133         struct xstorm_eth_queue_zone eth_qzone;
5134         u8 timeset, timer_res;
5135         u32 address;
5136         enum _ecore_status_t rc;
5137
5138         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5139         if (coalesce <= 0x7F) {
5140                 timer_res = 0;
5141         } else if (coalesce <= 0xFF) {
5142                 timer_res = 1;
5143         } else if (coalesce <= 0x1FF) {
5144                 timer_res = 2;
5145         } else {
5146                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5147                 return ECORE_INVAL;
5148         }
5149
5150         timeset = (u8)(coalesce >> timer_res);
5151
5152         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5153                                      p_cid->sb_igu_id, true);
5154         if (rc != ECORE_SUCCESS)
5155                 goto out;
5156
5157         address = BAR0_MAP_REG_XSDM_RAM +
5158                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5159
5160         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5161                                 sizeof(struct xstorm_eth_queue_zone), timeset);
5162 out:
5163         return rc;
5164 }
5165
5166 /* Calculate final WFQ values for all vports and configure it.
5167  * After this configuration each vport must have
5168  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
5169  */
5170 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5171                                                struct ecore_ptt *p_ptt,
5172                                                u32 min_pf_rate)
5173 {
5174         struct init_qm_vport_params *vport_params;
5175         int i;
5176
5177         vport_params = p_hwfn->qm_info.qm_vport_params;
5178
5179         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5180                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5181
5182                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
5183                     min_pf_rate;
5184                 ecore_init_vport_wfq(p_hwfn, p_ptt,
5185                                      vport_params[i].first_tx_pq_id,
5186                                      vport_params[i].vport_wfq);
5187         }
5188 }
5189
5190 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn)
5191 {
5192         int i;
5193
5194         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5195                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
5196 }
5197
5198 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5199                                              struct ecore_ptt *p_ptt)
5200 {
5201         struct init_qm_vport_params *vport_params;
5202         int i;
5203
5204         vport_params = p_hwfn->qm_info.qm_vport_params;
5205
5206         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5207                 ecore_init_wfq_default_param(p_hwfn);
5208                 ecore_init_vport_wfq(p_hwfn, p_ptt,
5209                                      vport_params[i].first_tx_pq_id,
5210                                      vport_params[i].vport_wfq);
5211         }
5212 }
5213
5214 /* This function performs several validations for WFQ
5215  * configuration and required min rate for a given vport
5216  * 1. req_rate must be greater than one percent of min_pf_rate.
5217  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
5218  *    rates to get less than one percent of min_pf_rate.
5219  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
5220  */
5221 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
5222                                                  u16 vport_id, u32 req_rate,
5223                                                  u32 min_pf_rate)
5224 {
5225         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
5226         int non_requested_count = 0, req_count = 0, i, num_vports;
5227
5228         num_vports = p_hwfn->qm_info.num_vports;
5229
5230 /* Accounting for the vports which are configured for WFQ explicitly */
5231
5232         for (i = 0; i < num_vports; i++) {
5233                 u32 tmp_speed;
5234
5235                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
5236                         req_count++;
5237                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5238                         total_req_min_rate += tmp_speed;
5239                 }
5240         }
5241
5242         /* Include current vport data as well */
5243         req_count++;
5244         total_req_min_rate += req_rate;
5245         non_requested_count = num_vports - req_count;
5246
5247         /* validate possible error cases */
5248         if (req_rate > min_pf_rate) {
5249                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5250                            "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5251                            vport_id, req_rate, min_pf_rate);
5252                 return ECORE_INVAL;
5253         }
5254
5255         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
5256                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5257                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5258                            vport_id, req_rate, min_pf_rate);
5259                 return ECORE_INVAL;
5260         }
5261
5262         /* TBD - for number of vports greater than 100 */
5263         if (num_vports > ECORE_WFQ_UNIT) {
5264                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5265                            "Number of vports is greater than %d\n",
5266                            ECORE_WFQ_UNIT);
5267                 return ECORE_INVAL;
5268         }
5269
5270         if (total_req_min_rate > min_pf_rate) {
5271                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5272                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5273                            total_req_min_rate, min_pf_rate);
5274                 return ECORE_INVAL;
5275         }
5276
5277         /* Data left for non requested vports */
5278         total_left_rate = min_pf_rate - total_req_min_rate;
5279         left_rate_per_vp = total_left_rate / non_requested_count;
5280
5281         /* validate if non requested get < 1% of min bw */
5282         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
5283                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5284                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5285                            left_rate_per_vp, min_pf_rate);
5286                 return ECORE_INVAL;
5287         }
5288
5289         /* now req_rate for given vport passes all scenarios.
5290          * assign final wfq rates to all vports.
5291          */
5292         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5293         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5294
5295         for (i = 0; i < num_vports; i++) {
5296                 if (p_hwfn->qm_info.wfq_data[i].configured)
5297                         continue;
5298
5299                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5300         }
5301
5302         return ECORE_SUCCESS;
5303 }
5304
5305 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
5306                                        struct ecore_ptt *p_ptt,
5307                                        u16 vp_id, u32 rate)
5308 {
5309         struct ecore_mcp_link_state *p_link;
5310         int rc = ECORE_SUCCESS;
5311
5312         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
5313
5314         if (!p_link->min_pf_rate) {
5315                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5316                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5317                 return rc;
5318         }
5319
5320         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5321
5322         if (rc == ECORE_SUCCESS)
5323                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5324                                                    p_link->min_pf_rate);
5325         else
5326                 DP_NOTICE(p_hwfn, false,
5327                           "Validation failed while configuring min rate\n");
5328
5329         return rc;
5330 }
5331
5332 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
5333                                                    struct ecore_ptt *p_ptt,
5334                                                    u32 min_pf_rate)
5335 {
5336         bool use_wfq = false;
5337         int rc = ECORE_SUCCESS;
5338         u16 i;
5339
5340         /* Validate all pre configured vports for wfq */
5341         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5342                 u32 rate;
5343
5344                 if (!p_hwfn->qm_info.wfq_data[i].configured)
5345                         continue;
5346
5347                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5348                 use_wfq = true;
5349
5350                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5351                 if (rc != ECORE_SUCCESS) {
5352                         DP_NOTICE(p_hwfn, false,
5353                                   "WFQ validation failed while configuring min rate\n");
5354                         break;
5355                 }
5356         }
5357
5358         if (rc == ECORE_SUCCESS && use_wfq)
5359                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5360         else
5361                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5362
5363         return rc;
5364 }
5365
5366 /* Main API for ecore clients to configure vport min rate.
5367  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5368  * rate - Speed in Mbps needs to be assigned to a given vport.
5369  */
5370 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
5371 {
5372         int i, rc = ECORE_INVAL;
5373
5374         /* TBD - for multiple hardware functions - that is 100 gig */
5375         if (ECORE_IS_CMT(p_dev)) {
5376                 DP_NOTICE(p_dev, false,
5377                           "WFQ configuration is not supported for this device\n");
5378                 return rc;
5379         }
5380
5381         for_each_hwfn(p_dev, i) {
5382                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5383                 struct ecore_ptt *p_ptt;
5384
5385                 p_ptt = ecore_ptt_acquire(p_hwfn);
5386                 if (!p_ptt)
5387                         return ECORE_TIMEOUT;
5388
5389                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5390
5391                 if (rc != ECORE_SUCCESS) {
5392                         ecore_ptt_release(p_hwfn, p_ptt);
5393                         return rc;
5394                 }
5395
5396                 ecore_ptt_release(p_hwfn, p_ptt);
5397         }
5398
5399         return rc;
5400 }
5401
5402 /* API to configure WFQ from mcp link change */
5403 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
5404                                            struct ecore_ptt *p_ptt,
5405                                            u32 min_pf_rate)
5406 {
5407         int i;
5408
5409         /* TBD - for multiple hardware functions - that is 100 gig */
5410         if (ECORE_IS_CMT(p_dev)) {
5411                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
5412                            "WFQ configuration is not supported for this device\n");
5413                 return;
5414         }
5415
5416         for_each_hwfn(p_dev, i) {
5417                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5418
5419                 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5420                                                         min_pf_rate);
5421         }
5422 }
5423
5424 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
5425                                        struct ecore_ptt *p_ptt,
5426                                        struct ecore_mcp_link_state *p_link,
5427                                        u8 max_bw)
5428 {
5429         int rc = ECORE_SUCCESS;
5430
5431         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5432
5433         if (!p_link->line_speed && (max_bw != 100))
5434                 return rc;
5435
5436         p_link->speed = (p_link->line_speed * max_bw) / 100;
5437         p_hwfn->qm_info.pf_rl = p_link->speed;
5438
5439         /* Since the limiter also affects Tx-switched traffic, we don't want it
5440          * to limit such traffic in case there's no actual limit.
5441          * In that case, set limit to imaginary high boundary.
5442          */
5443         if (max_bw == 100)
5444                 p_hwfn->qm_info.pf_rl = 100000;
5445
5446         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5447                               p_hwfn->qm_info.pf_rl);
5448
5449         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5450                    "Configured MAX bandwidth to be %08x Mb/sec\n",
5451                    p_link->speed);
5452
5453         return rc;
5454 }
5455
5456 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5457 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
5458 {
5459         int i, rc = ECORE_INVAL;
5460
5461         if (max_bw < 1 || max_bw > 100) {
5462                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
5463                 return rc;
5464         }
5465
5466         for_each_hwfn(p_dev, i) {
5467                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5468                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5469                 struct ecore_mcp_link_state *p_link;
5470                 struct ecore_ptt *p_ptt;
5471
5472                 p_link = &p_lead->mcp_info->link_output;
5473
5474                 p_ptt = ecore_ptt_acquire(p_hwfn);
5475                 if (!p_ptt)
5476                         return ECORE_TIMEOUT;
5477
5478                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5479                                                         p_link, max_bw);
5480
5481                 ecore_ptt_release(p_hwfn, p_ptt);
5482
5483                 if (rc != ECORE_SUCCESS)
5484                         break;
5485         }
5486
5487         return rc;
5488 }
5489
5490 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
5491                                        struct ecore_ptt *p_ptt,
5492                                        struct ecore_mcp_link_state *p_link,
5493                                        u8 min_bw)
5494 {
5495         int rc = ECORE_SUCCESS;
5496
5497         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5498         p_hwfn->qm_info.pf_wfq = min_bw;
5499
5500         if (!p_link->line_speed)
5501                 return rc;
5502
5503         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5504
5505         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5506
5507         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5508                    "Configured MIN bandwidth to be %d Mb/sec\n",
5509                    p_link->min_pf_rate);
5510
5511         return rc;
5512 }
5513
5514 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5515 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
5516 {
5517         int i, rc = ECORE_INVAL;
5518
5519         if (min_bw < 1 || min_bw > 100) {
5520                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
5521                 return rc;
5522         }
5523
5524         for_each_hwfn(p_dev, i) {
5525                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5526                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5527                 struct ecore_mcp_link_state *p_link;
5528                 struct ecore_ptt *p_ptt;
5529
5530                 p_link = &p_lead->mcp_info->link_output;
5531
5532                 p_ptt = ecore_ptt_acquire(p_hwfn);
5533                 if (!p_ptt)
5534                         return ECORE_TIMEOUT;
5535
5536                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5537                                                         p_link, min_bw);
5538                 if (rc != ECORE_SUCCESS) {
5539                         ecore_ptt_release(p_hwfn, p_ptt);
5540                         return rc;
5541                 }
5542
5543                 if (p_link->min_pf_rate) {
5544                         u32 min_rate = p_link->min_pf_rate;
5545
5546                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
5547                                                                      p_ptt,
5548                                                                      min_rate);
5549                 }
5550
5551                 ecore_ptt_release(p_hwfn, p_ptt);
5552         }
5553
5554         return rc;
5555 }
5556
5557 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
5558 {
5559         struct ecore_mcp_link_state *p_link;
5560
5561         p_link = &p_hwfn->mcp_info->link_output;
5562
5563         if (p_link->min_pf_rate)
5564                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5565
5566         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
5567                     sizeof(*p_hwfn->qm_info.wfq_data) *
5568                     p_hwfn->qm_info.num_vports);
5569 }
5570
5571 int ecore_device_num_engines(struct ecore_dev *p_dev)
5572 {
5573         return ECORE_IS_BB(p_dev) ? 2 : 1;
5574 }
5575
5576 int ecore_device_num_ports(struct ecore_dev *p_dev)
5577 {
5578         return p_dev->num_ports;
5579 }
5580
5581 void ecore_set_fw_mac_addr(__le16 *fw_msb,
5582                           __le16 *fw_mid,
5583                           __le16 *fw_lsb,
5584                           u8 *mac)
5585 {
5586         ((u8 *)fw_msb)[0] = mac[1];
5587         ((u8 *)fw_msb)[1] = mac[0];
5588         ((u8 *)fw_mid)[0] = mac[3];
5589         ((u8 *)fw_mid)[1] = mac[2];
5590         ((u8 *)fw_lsb)[0] = mac[5];
5591         ((u8 *)fw_lsb)[1] = mac[4];
5592 }