2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_gtt_reg_addr.h"
13 #include "ecore_chain.h"
14 #include "ecore_status.h"
16 #include "ecore_rt_defs.h"
17 #include "ecore_init_ops.h"
18 #include "ecore_int.h"
19 #include "ecore_cxt.h"
20 #include "ecore_spq.h"
21 #include "ecore_init_fw_funcs.h"
22 #include "ecore_sp_commands.h"
23 #include "ecore_dev_api.h"
24 #include "ecore_sriov.h"
26 #include "ecore_mcp.h"
27 #include "ecore_hw_defs.h"
28 #include "mcp_public.h"
29 #include "ecore_iro.h"
31 #include "ecore_dcbx.h"
34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
35 * registers involved are not split and thus configuration is a race where
36 * some of the PFs configuration might be lost.
37 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
38 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
39 * there's more than a single compiled ecore component in system].
41 static osal_spinlock_t qm_lock;
42 static u32 qm_lock_ref_cnt;
44 /******************** Doorbell Recovery *******************/
45 /* The doorbell recovery mechanism consists of a list of entries which represent
46 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
47 * entity needs to register with the mechanism and provide the parameters
48 * describing it's doorbell, including a location where last used doorbell data
49 * can be found. The doorbell execute function will traverse the list and
50 * doorbell all of the registered entries.
52 struct ecore_db_recovery_entry {
53 osal_list_entry_t list_entry;
54 void OSAL_IOMEM *db_addr;
56 enum ecore_db_rec_width db_width;
57 enum ecore_db_rec_space db_space;
61 /* display a single doorbell recovery entry */
62 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
63 struct ecore_db_recovery_entry *db_entry,
66 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
67 action, db_entry, db_entry->db_addr, db_entry->db_data,
68 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
69 db_entry->db_space == DB_REC_USER ? "user" : "kernel",
73 /* doorbell address sanity (address within doorbell bar range) */
74 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
77 /* make sure doorbell address is within the doorbell bar */
78 if (db_addr < p_dev->doorbells || (u8 *)db_addr >
79 (u8 *)p_dev->doorbells + p_dev->db_size) {
81 "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
82 db_addr, p_dev->doorbells,
83 (u8 *)p_dev->doorbells + p_dev->db_size);
87 /* make sure doorbell data pointer is not null */
89 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
96 /* find hwfn according to the doorbell address */
97 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
98 void OSAL_IOMEM *db_addr)
100 struct ecore_hwfn *p_hwfn;
102 /* In CMT doorbell bar is split down the middle between engine 0 and
105 if (ECORE_IS_CMT(p_dev))
106 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
107 &p_dev->hwfns[0] : &p_dev->hwfns[1];
109 p_hwfn = ECORE_LEADING_HWFN(p_dev);
114 /* add a new entry to the doorbell recovery mechanism */
115 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
116 void OSAL_IOMEM *db_addr,
118 enum ecore_db_rec_width db_width,
119 enum ecore_db_rec_space db_space)
121 struct ecore_db_recovery_entry *db_entry;
122 struct ecore_hwfn *p_hwfn;
124 /* shortcircuit VFs, for now */
126 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
127 return ECORE_SUCCESS;
130 /* sanitize doorbell address */
131 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
134 /* obtain hwfn from doorbell address */
135 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
138 db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
140 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
145 db_entry->db_addr = db_addr;
146 db_entry->db_data = db_data;
147 db_entry->db_width = db_width;
148 db_entry->db_space = db_space;
149 db_entry->hwfn_idx = p_hwfn->my_id;
152 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
154 /* protect the list */
155 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
156 OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
157 &p_hwfn->db_recovery_info.list);
158 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
160 return ECORE_SUCCESS;
163 /* remove an entry from the doorbell recovery mechanism */
164 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
165 void OSAL_IOMEM *db_addr,
168 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
169 enum _ecore_status_t rc = ECORE_INVAL;
170 struct ecore_hwfn *p_hwfn;
172 /* shortcircuit VFs, for now */
174 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
175 return ECORE_SUCCESS;
178 /* sanitize doorbell address */
179 if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
182 /* obtain hwfn from doorbell address */
183 p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
185 /* protect the list */
186 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
187 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
188 &p_hwfn->db_recovery_info.list,
190 struct ecore_db_recovery_entry) {
191 /* search according to db_data addr since db_addr is not unique
194 if (db_entry->db_data == db_data) {
195 ecore_db_recovery_dp_entry(p_hwfn, db_entry,
197 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
198 &p_hwfn->db_recovery_info.list);
204 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
206 if (rc == ECORE_INVAL)
208 DP_NOTICE(p_hwfn, false,
209 "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
212 OSAL_FREE(p_dev, db_entry);
217 /* initialize the doorbell recovery mechanism */
218 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
220 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
222 /* make sure db_size was set in p_dev */
223 if (!p_hwfn->p_dev->db_size) {
224 DP_ERR(p_hwfn->p_dev, "db_size not set\n");
228 OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
229 #ifdef CONFIG_ECORE_LOCK_ALLOC
230 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock))
233 OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
234 p_hwfn->db_recovery_info.db_recovery_counter = 0;
236 return ECORE_SUCCESS;
239 /* destroy the doorbell recovery mechanism */
240 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
242 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
244 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
245 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
246 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
247 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
248 db_entry = OSAL_LIST_FIRST_ENTRY(
249 &p_hwfn->db_recovery_info.list,
250 struct ecore_db_recovery_entry,
252 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
253 OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
254 &p_hwfn->db_recovery_info.list);
255 OSAL_FREE(p_hwfn->p_dev, db_entry);
258 #ifdef CONFIG_ECORE_LOCK_ALLOC
259 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
261 p_hwfn->db_recovery_info.db_recovery_counter = 0;
264 /* print the content of the doorbell recovery mechanism */
265 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
267 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
269 DP_NOTICE(p_hwfn, false,
270 "Dispalying doorbell recovery database. Counter was %d\n",
271 p_hwfn->db_recovery_info.db_recovery_counter);
273 /* protect the list */
274 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
275 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
276 &p_hwfn->db_recovery_info.list,
278 struct ecore_db_recovery_entry) {
279 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
282 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
285 /* ring the doorbell of a single doorbell recovery entry */
286 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
287 struct ecore_db_recovery_entry *db_entry,
288 enum ecore_db_rec_exec db_exec)
290 /* Print according to width */
291 if (db_entry->db_width == DB_REC_WIDTH_32B)
292 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
293 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
294 db_entry->db_addr, *(u32 *)db_entry->db_data);
296 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n",
297 db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
299 *(unsigned long *)(db_entry->db_data));
302 if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
306 /* Flush the write combined buffer. Since there are multiple doorbelling
307 * entities using the same address, if we don't flush, a transaction
310 OSAL_WMB(p_hwfn->p_dev);
312 /* Ring the doorbell */
313 if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
314 if (db_entry->db_width == DB_REC_WIDTH_32B)
315 DIRECT_REG_WR(p_hwfn, db_entry->db_addr,
316 *(u32 *)(db_entry->db_data));
318 DIRECT_REG_WR64(p_hwfn, db_entry->db_addr,
319 *(u64 *)(db_entry->db_data));
322 /* Flush the write combined buffer. Next doorbell may come from a
323 * different entity to the same address...
325 OSAL_WMB(p_hwfn->p_dev);
328 /* traverse the doorbell recovery entry list and ring all the doorbells */
329 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
330 enum ecore_db_rec_exec db_exec)
332 struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
334 if (db_exec != DB_REC_ONCE) {
335 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
336 p_hwfn->db_recovery_info.db_recovery_counter);
338 /* track amount of times recovery was executed */
339 p_hwfn->db_recovery_info.db_recovery_counter++;
342 /* protect the list */
343 OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
344 OSAL_LIST_FOR_EACH_ENTRY(db_entry,
345 &p_hwfn->db_recovery_info.list,
347 struct ecore_db_recovery_entry) {
348 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
349 if (db_exec == DB_REC_ONCE)
353 OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
355 /******************** Doorbell Recovery end ****************/
358 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to
359 * load the driver. The number was
364 #define ECORE_MIN_PWM_REGION (ECORE_WID_SIZE * ECORE_MIN_DPIS)
366 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
367 struct ecore_ptt *p_ptt,
370 u32 bar_reg = (bar_id == BAR_ID_0 ?
371 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
374 if (IS_VF(p_hwfn->p_dev))
375 return ecore_vf_hw_bar_size(p_hwfn, bar_id);
377 val = ecore_rd(p_hwfn, p_ptt, bar_reg);
379 return 1 << (val + 15);
381 /* The above registers were updated in the past only in CMT mode. Since
382 * they were found to be useful MFW started updating them from 8.7.7.0.
383 * In older MFW versions they are set to 0 which means disabled.
385 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
387 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
388 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
391 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
398 void ecore_init_dp(struct ecore_dev *p_dev,
399 u32 dp_module, u8 dp_level, void *dp_ctx)
403 p_dev->dp_level = dp_level;
404 p_dev->dp_module = dp_module;
405 p_dev->dp_ctx = dp_ctx;
406 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
407 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
409 p_hwfn->dp_level = dp_level;
410 p_hwfn->dp_module = dp_module;
411 p_hwfn->dp_ctx = dp_ctx;
415 enum _ecore_status_t ecore_init_struct(struct ecore_dev *p_dev)
419 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
420 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
422 p_hwfn->p_dev = p_dev;
424 p_hwfn->b_active = false;
426 #ifdef CONFIG_ECORE_LOCK_ALLOC
427 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->dmae_info.lock))
430 OSAL_SPIN_LOCK_INIT(&p_hwfn->dmae_info.lock);
433 /* hwfn 0 is always active */
434 p_dev->hwfns[0].b_active = true;
436 /* set the default cache alignment to 128 (may be overridden later) */
437 p_dev->cache_shift = 7;
438 return ECORE_SUCCESS;
439 #ifdef CONFIG_ECORE_LOCK_ALLOC
442 struct ecore_hwfn *p_hwfn = OSAL_NULL;
444 p_hwfn = &p_dev->hwfns[i];
445 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
451 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
453 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
455 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
456 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
457 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
458 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
461 void ecore_resc_free(struct ecore_dev *p_dev)
466 for_each_hwfn(p_dev, i)
467 ecore_l2_free(&p_dev->hwfns[i]);
471 OSAL_FREE(p_dev, p_dev->fw_data);
473 OSAL_FREE(p_dev, p_dev->reset_stats);
475 for_each_hwfn(p_dev, i) {
476 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
478 ecore_cxt_mngr_free(p_hwfn);
479 ecore_qm_info_free(p_hwfn);
480 ecore_spq_free(p_hwfn);
481 ecore_eq_free(p_hwfn);
482 ecore_consq_free(p_hwfn);
483 ecore_int_free(p_hwfn);
484 ecore_iov_free(p_hwfn);
485 ecore_l2_free(p_hwfn);
486 ecore_dmae_info_free(p_hwfn);
487 ecore_dcbx_info_free(p_hwfn);
488 /* @@@TBD Flush work-queue ? */
490 /* destroy doorbell recovery mechanism */
491 ecore_db_recovery_teardown(p_hwfn);
495 /******************** QM initialization *******************/
497 /* bitmaps for indicating active traffic classes.
498 * Special case for Arrowhead 4 port
500 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
501 #define ACTIVE_TCS_BMAP 0x9f
502 /* 0..3 actually used, OOO and high priority stuff all use 3 */
503 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
505 /* determines the physical queue flags for a given PF. */
506 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
514 if (IS_ECORE_SRIOV(p_hwfn->p_dev))
515 flags |= PQ_FLAGS_VFS;
516 if (IS_ECORE_PACING(p_hwfn))
517 flags |= PQ_FLAGS_RLS;
520 switch (p_hwfn->hw_info.personality) {
522 if (!IS_ECORE_PACING(p_hwfn))
523 flags |= PQ_FLAGS_MCOS;
526 flags |= PQ_FLAGS_OFLD;
528 case ECORE_PCI_ISCSI:
529 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
531 case ECORE_PCI_ETH_ROCE:
532 flags |= PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
533 if (!IS_ECORE_PACING(p_hwfn))
534 flags |= PQ_FLAGS_MCOS;
536 case ECORE_PCI_ETH_IWARP:
537 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
538 if (!IS_ECORE_PACING(p_hwfn))
539 flags |= PQ_FLAGS_MCOS;
542 DP_ERR(p_hwfn, "unknown personality %d\n",
543 p_hwfn->hw_info.personality);
549 /* Getters for resource amounts necessary for qm initialization */
550 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
552 return p_hwfn->hw_info.num_hw_tc;
555 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
557 return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
558 p_hwfn->p_dev->p_iov_info->total_vfs : 0;
561 #define NUM_DEFAULT_RLS 1
563 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
565 u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
568 /* num RLs can't exceed resource amount of rls or vports or the
571 num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
572 (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
574 /* make sure after we reserve the default and VF rls we'll have
577 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
578 DP_NOTICE(p_hwfn, false,
579 "no rate limiters left for PF rate limiting"
580 " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
584 /* subtract rls necessary for VFs and one default one for the PF */
585 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
590 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
592 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
594 /* all pqs share the same vport (hence the 1 below), except for vfs
597 return (!!(PQ_FLAGS_RLS & pq_flags)) *
598 ecore_init_qm_get_num_pf_rls(p_hwfn) +
599 (!!(PQ_FLAGS_VFS & pq_flags)) *
600 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
603 /* calc amount of PQs according to the requested flags */
604 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
606 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
608 return (!!(PQ_FLAGS_RLS & pq_flags)) *
609 ecore_init_qm_get_num_pf_rls(p_hwfn) +
610 (!!(PQ_FLAGS_MCOS & pq_flags)) *
611 ecore_init_qm_get_num_tcs(p_hwfn) +
612 (!!(PQ_FLAGS_LB & pq_flags)) +
613 (!!(PQ_FLAGS_OOO & pq_flags)) +
614 (!!(PQ_FLAGS_ACK & pq_flags)) +
615 (!!(PQ_FLAGS_OFLD & pq_flags)) +
616 (!!(PQ_FLAGS_VFS & pq_flags)) *
617 ecore_init_qm_get_num_vfs(p_hwfn);
620 /* initialize the top level QM params */
621 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
623 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
626 /* pq and vport bases for this PF */
627 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
628 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
630 /* rate limiting and weighted fair queueing are always enabled */
631 qm_info->vport_rl_en = 1;
632 qm_info->vport_wfq_en = 1;
634 /* TC config is different for AH 4 port */
635 four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;
637 /* in AH 4 port we have fewer TCs per port */
638 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
641 /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
644 if (!qm_info->ooo_tc)
645 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
649 /* initialize qm vport params */
650 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
652 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
655 /* all vports participate in weighted fair queueing */
656 for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
657 qm_info->qm_vport_params[i].vport_wfq = 1;
660 /* initialize qm port params */
661 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
663 /* Initialize qm port parameters */
664 u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
666 /* indicate how ooo and high pri traffic is dealt with */
667 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
668 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
670 for (i = 0; i < num_ports; i++) {
671 struct init_qm_port_params *p_qm_port =
672 &p_hwfn->qm_info.qm_port_params[i];
674 p_qm_port->active = 1;
675 p_qm_port->active_phys_tcs = active_phys_tcs;
676 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES_E4 / num_ports;
677 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
681 /* Reset the params which must be reset for qm init. QM init may be called as
682 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
683 * params may be affected by the init but would simply recalculate to the same
684 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
685 * affected as these amounts stay the same.
687 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
689 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
691 qm_info->num_pqs = 0;
692 qm_info->num_vports = 0;
693 qm_info->num_pf_rls = 0;
694 qm_info->num_vf_pqs = 0;
695 qm_info->first_vf_pq = 0;
696 qm_info->first_mcos_pq = 0;
697 qm_info->first_rl_pq = 0;
700 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
702 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
704 qm_info->num_vports++;
706 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
708 "vport overflow! qm_info->num_vports %d,"
709 " qm_init_get_num_vports() %d\n",
711 ecore_init_qm_get_num_vports(p_hwfn));
714 /* initialize a single pq and manage qm_info resources accounting.
715 * The pq_init_flags param determines whether the PQ is rate limited
717 * and whether a new vport is allocated to the pq or not (i.e. vport will be
721 /* flags for pq init */
722 #define PQ_INIT_SHARE_VPORT (1 << 0)
723 #define PQ_INIT_PF_RL (1 << 1)
724 #define PQ_INIT_VF_RL (1 << 2)
726 /* defines for pq init */
727 #define PQ_INIT_DEFAULT_WRR_GROUP 1
728 #define PQ_INIT_DEFAULT_TC 0
729 #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc)
731 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
732 struct ecore_qm_info *qm_info,
733 u8 tc, u32 pq_init_flags)
735 u16 pq_idx = qm_info->num_pqs, max_pq =
736 ecore_init_qm_get_num_pqs(p_hwfn);
740 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
743 qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
744 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
746 qm_info->qm_pq_params[pq_idx].tc_id = tc;
747 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
748 qm_info->qm_pq_params[pq_idx].rl_valid =
749 (pq_init_flags & PQ_INIT_PF_RL ||
750 pq_init_flags & PQ_INIT_VF_RL);
752 /* qm params accounting */
754 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
755 qm_info->num_vports++;
757 if (pq_init_flags & PQ_INIT_PF_RL)
758 qm_info->num_pf_rls++;
760 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
762 "vport overflow! qm_info->num_vports %d,"
763 " qm_init_get_num_vports() %d\n",
765 ecore_init_qm_get_num_vports(p_hwfn));
767 if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
768 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
769 " qm_init_get_num_pf_rls() %d\n",
771 ecore_init_qm_get_num_pf_rls(p_hwfn));
774 /* get pq index according to PQ_FLAGS */
775 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
778 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
780 /* Can't have multiple flags set here */
781 if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
782 sizeof(pq_flags)) > 1)
787 return &qm_info->first_rl_pq;
789 return &qm_info->first_mcos_pq;
791 return &qm_info->pure_lb_pq;
793 return &qm_info->ooo_pq;
795 return &qm_info->pure_ack_pq;
797 return &qm_info->offload_pq;
799 return &qm_info->first_vf_pq;
805 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
809 /* save pq index in qm info */
810 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
811 u32 pq_flags, u16 pq_val)
813 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
815 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
818 /* get tx pq index, with the PQ TX base already set (ready for context init) */
819 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
821 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
823 return *base_pq_idx + CM_TX_PQ_BASE;
826 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
828 u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
831 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
833 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
836 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
838 u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
841 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
843 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
846 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
848 u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
851 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
853 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
856 u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
858 u16 start_pq, pq, qm_pq_idx;
860 pq = ecore_get_cm_pq_idx_rl(p_hwfn, rl);
861 start_pq = p_hwfn->qm_info.start_pq;
862 qm_pq_idx = pq - start_pq - CM_TX_PQ_BASE;
864 if (qm_pq_idx > p_hwfn->qm_info.num_pqs) {
866 "qm_pq_idx %d must be smaller than %d\n",
867 qm_pq_idx, p_hwfn->qm_info.num_pqs);
870 return p_hwfn->qm_info.qm_pq_params[qm_pq_idx].vport_id;
873 /* Functions for creating specific types of pqs */
874 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
876 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
878 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
881 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
882 ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
885 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
887 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
889 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
892 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
893 ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
896 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
898 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
900 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
903 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
904 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
907 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
909 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
911 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
914 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
915 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
918 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
920 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
923 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
926 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
927 for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
928 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
931 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
933 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
934 u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
936 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
939 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
941 qm_info->num_vf_pqs = num_vfs;
942 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
943 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
947 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
949 u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
950 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
952 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
955 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
956 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
957 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
961 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
963 /* rate limited pqs, must come first (FW assumption) */
964 ecore_init_qm_rl_pqs(p_hwfn);
966 /* pqs for multi cos */
967 ecore_init_qm_mcos_pqs(p_hwfn);
969 /* pure loopback pq */
970 ecore_init_qm_lb_pq(p_hwfn);
972 /* out of order pq */
973 ecore_init_qm_ooo_pq(p_hwfn);
976 ecore_init_qm_pure_ack_pq(p_hwfn);
978 /* pq for offloaded protocol */
979 ecore_init_qm_offload_pq(p_hwfn);
981 /* done sharing vports */
982 ecore_init_qm_advance_vport(p_hwfn);
985 ecore_init_qm_vf_pqs(p_hwfn);
988 /* compare values of getters against resources amounts */
989 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
991 if (ecore_init_qm_get_num_vports(p_hwfn) >
992 RESC_NUM(p_hwfn, ECORE_VPORT)) {
993 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
997 if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
998 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
1002 return ECORE_SUCCESS;
1006 * Function for verbose printing of the qm initialization results
1008 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
1010 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1011 struct init_qm_vport_params *vport;
1012 struct init_qm_port_params *port;
1013 struct init_qm_pq_params *pq;
1016 /* top level params */
1017 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1018 "qm init top level params: start_pq %d, start_vport %d,"
1019 " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
1020 qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
1021 qm_info->offload_pq, qm_info->pure_ack_pq);
1022 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1023 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
1024 " num_vports %d, max_phys_tcs_per_port %d\n",
1025 qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
1026 qm_info->num_vf_pqs, qm_info->num_vports,
1027 qm_info->max_phys_tcs_per_port);
1028 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1029 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
1030 " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
1031 qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
1032 qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
1033 qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
1036 for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
1037 port = &qm_info->qm_port_params[i];
1038 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1039 "port idx %d, active %d, active_phys_tcs %d,"
1040 " num_pbf_cmd_lines %d, num_btb_blocks %d,"
1042 i, port->active, port->active_phys_tcs,
1043 port->num_pbf_cmd_lines, port->num_btb_blocks,
1048 for (i = 0; i < qm_info->num_vports; i++) {
1049 vport = &qm_info->qm_vport_params[i];
1050 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1051 "vport idx %d, vport_rl %d, wfq %d,"
1052 " first_tx_pq_id [ ",
1053 qm_info->start_vport + i, vport->vport_rl,
1055 for (tc = 0; tc < NUM_OF_TCS; tc++)
1056 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
1057 vport->first_tx_pq_id[tc]);
1058 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
1062 for (i = 0; i < qm_info->num_pqs; i++) {
1063 pq = &qm_info->qm_pq_params[i];
1064 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1065 "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
1066 qm_info->start_pq + i, pq->port_id, pq->vport_id,
1067 pq->tc_id, pq->wrr_group, pq->rl_valid);
1071 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
1073 /* reset params required for init run */
1074 ecore_init_qm_reset_params(p_hwfn);
1076 /* init QM top level params */
1077 ecore_init_qm_params(p_hwfn);
1079 /* init QM port params */
1080 ecore_init_qm_port_params(p_hwfn);
1082 /* init QM vport params */
1083 ecore_init_qm_vport_params(p_hwfn);
1085 /* init QM physical queue params */
1086 ecore_init_qm_pq_params(p_hwfn);
1088 /* display all that init */
1089 ecore_dp_init_qm_params(p_hwfn);
1092 /* This function reconfigures the QM pf on the fly.
1093 * For this purpose we:
1094 * 1. reconfigure the QM database
1095 * 2. set new values to runtime array
1096 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
1097 * 4. activate init tool in QM_PF stage
1098 * 5. send an sdm_qm_cmd through rbc interface to release the QM
1100 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
1101 struct ecore_ptt *p_ptt)
1103 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1105 enum _ecore_status_t rc;
1107 /* initialize ecore's qm data structure */
1108 ecore_init_qm_info(p_hwfn);
1110 /* stop PF's qm queues */
1111 OSAL_SPIN_LOCK(&qm_lock);
1112 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
1113 qm_info->start_pq, qm_info->num_pqs);
1114 OSAL_SPIN_UNLOCK(&qm_lock);
1118 /* clear the QM_PF runtime phase leftovers from previous init */
1119 ecore_init_clear_rt_data(p_hwfn);
1121 /* prepare QM portion of runtime array */
1122 ecore_qm_init_pf(p_hwfn, p_ptt, false);
1124 /* activate init tool on runtime array */
1125 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
1126 p_hwfn->hw_info.hw_mode);
1127 if (rc != ECORE_SUCCESS)
1130 /* start PF's qm queues */
1131 OSAL_SPIN_LOCK(&qm_lock);
1132 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
1133 qm_info->start_pq, qm_info->num_pqs);
1134 OSAL_SPIN_UNLOCK(&qm_lock);
1138 return ECORE_SUCCESS;
1141 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
1143 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1144 enum _ecore_status_t rc;
1146 rc = ecore_init_qm_sanity(p_hwfn);
1147 if (rc != ECORE_SUCCESS)
1150 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1151 sizeof(struct init_qm_pq_params) *
1152 ecore_init_qm_get_num_pqs(p_hwfn));
1153 if (!qm_info->qm_pq_params)
1156 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1157 sizeof(struct init_qm_vport_params) *
1158 ecore_init_qm_get_num_vports(p_hwfn));
1159 if (!qm_info->qm_vport_params)
1162 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1163 sizeof(struct init_qm_port_params) *
1164 p_hwfn->p_dev->num_ports_in_engine);
1165 if (!qm_info->qm_port_params)
1168 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1169 sizeof(struct ecore_wfq_data) *
1170 ecore_init_qm_get_num_vports(p_hwfn));
1171 if (!qm_info->wfq_data)
1174 return ECORE_SUCCESS;
1177 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
1178 ecore_qm_info_free(p_hwfn);
1181 /******************** End QM initialization ***************/
1183 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
1185 enum _ecore_status_t rc = ECORE_SUCCESS;
1189 for_each_hwfn(p_dev, i) {
1190 rc = ecore_l2_alloc(&p_dev->hwfns[i]);
1191 if (rc != ECORE_SUCCESS)
1197 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1198 sizeof(*p_dev->fw_data));
1199 if (!p_dev->fw_data)
1202 for_each_hwfn(p_dev, i) {
1203 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1204 u32 n_eqes, num_cons;
1206 /* initialize the doorbell recovery mechanism */
1207 rc = ecore_db_recovery_setup(p_hwfn);
1211 /* First allocate the context manager structure */
1212 rc = ecore_cxt_mngr_alloc(p_hwfn);
1216 /* Set the HW cid/tid numbers (in the context manager)
1217 * Must be done prior to any further computations.
1219 rc = ecore_cxt_set_pf_params(p_hwfn);
1223 rc = ecore_alloc_qm_data(p_hwfn);
1228 ecore_init_qm_info(p_hwfn);
1230 /* Compute the ILT client partition */
1231 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
1235 /* CID map / ILT shadow table / T2
1236 * The talbes sizes are determined by the computations above
1238 rc = ecore_cxt_tables_alloc(p_hwfn);
1242 /* SPQ, must follow ILT because initializes SPQ context */
1243 rc = ecore_spq_alloc(p_hwfn);
1247 /* SP status block allocation */
1248 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
1251 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1255 rc = ecore_iov_alloc(p_hwfn);
1260 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
1261 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
1262 /* Calculate the EQ size
1263 * ---------------------
1264 * Each ICID may generate up to one event at a time i.e.
1265 * the event must be handled/cleared before a new one
1266 * can be generated. We calculate the sum of events per
1267 * protocol and create an EQ deep enough to handle the
1269 * - Core - according to SPQ.
1270 * - RoCE - per QP there are a couple of ICIDs, one
1271 * responder and one requester, each can
1272 * generate an EQE => n_eqes_qp = 2 * n_qp.
1273 * Each CQ can generate an EQE. There are 2 CQs
1274 * per QP => n_eqes_cq = 2 * n_qp.
1275 * Hence the RoCE total is 4 * n_qp or
1277 * - ENet - There can be up to two events per VF. One
1278 * for VF-PF channel and another for VF FLR
1279 * initial cleanup. The number of VFs is
1280 * bounded by MAX_NUM_VFS_BB, and is much
1281 * smaller than RoCE's so we avoid exact
1284 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
1286 ecore_cxt_get_proto_cid_count(
1292 num_cons = ecore_cxt_get_proto_cid_count(
1297 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1298 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
1300 ecore_cxt_get_proto_cid_count(p_hwfn,
1303 n_eqes += 2 * num_cons;
1306 if (n_eqes > 0xFFFF) {
1307 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
1308 "The maximum of a u16 chain is 0x%x\n",
1313 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
1317 rc = ecore_consq_alloc(p_hwfn);
1321 rc = ecore_l2_alloc(p_hwfn);
1322 if (rc != ECORE_SUCCESS)
1325 /* DMA info initialization */
1326 rc = ecore_dmae_info_alloc(p_hwfn);
1328 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for dmae_info structure\n");
1332 /* DCBX initialization */
1333 rc = ecore_dcbx_info_alloc(p_hwfn);
1335 DP_NOTICE(p_hwfn, false,
1336 "Failed to allocate memory for dcbx structure\n");
1341 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1342 sizeof(*p_dev->reset_stats));
1343 if (!p_dev->reset_stats) {
1344 DP_NOTICE(p_dev, false, "Failed to allocate reset statistics\n");
1348 return ECORE_SUCCESS;
1353 ecore_resc_free(p_dev);
1357 void ecore_resc_setup(struct ecore_dev *p_dev)
1362 for_each_hwfn(p_dev, i)
1363 ecore_l2_setup(&p_dev->hwfns[i]);
1367 for_each_hwfn(p_dev, i) {
1368 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1370 ecore_cxt_mngr_setup(p_hwfn);
1371 ecore_spq_setup(p_hwfn);
1372 ecore_eq_setup(p_hwfn);
1373 ecore_consq_setup(p_hwfn);
1375 /* Read shadow of current MFW mailbox */
1376 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1377 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1378 p_hwfn->mcp_info->mfw_mb_cur,
1379 p_hwfn->mcp_info->mfw_mb_length);
1381 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1383 ecore_l2_setup(p_hwfn);
1384 ecore_iov_setup(p_hwfn);
1388 #define FINAL_CLEANUP_POLL_CNT (100)
1389 #define FINAL_CLEANUP_POLL_TIME (10)
1390 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1391 struct ecore_ptt *p_ptt,
1394 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1395 enum _ecore_status_t rc = ECORE_TIMEOUT;
1398 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1399 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1400 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1401 return ECORE_SUCCESS;
1405 addr = GTT_BAR0_MAP_REG_USDM_RAM +
1406 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1411 command |= X_FINAL_CLEANUP_AGG_INT <<
1412 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1413 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1414 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1415 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1417 /* Make sure notification is not set before initiating final cleanup */
1419 if (REG_RD(p_hwfn, addr)) {
1420 DP_NOTICE(p_hwfn, false,
1421 "Unexpected; Found final cleanup notification");
1422 DP_NOTICE(p_hwfn, false,
1423 " before initiating final cleanup\n");
1424 REG_WR(p_hwfn, addr, 0);
1427 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1428 "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1431 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1433 /* Poll until completion */
1434 while (!REG_RD(p_hwfn, addr) && count--)
1435 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1437 if (REG_RD(p_hwfn, addr))
1440 DP_NOTICE(p_hwfn, true,
1441 "Failed to receive FW final cleanup notification\n");
1443 /* Cleanup afterwards */
1444 REG_WR(p_hwfn, addr, 0);
1449 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1453 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1454 hw_mode |= 1 << MODE_BB;
1455 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1456 hw_mode |= 1 << MODE_K2;
1458 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1459 p_hwfn->p_dev->type);
1463 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1464 switch (p_hwfn->p_dev->num_ports_in_engine) {
1466 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1469 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1472 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1475 DP_NOTICE(p_hwfn, true,
1476 "num_ports_in_engine = %d not supported\n",
1477 p_hwfn->p_dev->num_ports_in_engine);
1481 if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS,
1482 &p_hwfn->p_dev->mf_bits))
1483 hw_mode |= 1 << MODE_MF_SD;
1485 hw_mode |= 1 << MODE_MF_SI;
1488 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1489 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1490 hw_mode |= 1 << MODE_FPGA;
1492 if (p_hwfn->p_dev->b_is_emul_full)
1493 hw_mode |= 1 << MODE_EMUL_FULL;
1495 hw_mode |= 1 << MODE_EMUL_REDUCED;
1499 hw_mode |= 1 << MODE_ASIC;
1501 if (ECORE_IS_CMT(p_hwfn->p_dev))
1502 hw_mode |= 1 << MODE_100G;
1504 p_hwfn->hw_info.hw_mode = hw_mode;
1506 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1507 "Configuring function for hw_mode: 0x%08x\n",
1508 p_hwfn->hw_info.hw_mode);
1510 return ECORE_SUCCESS;
1514 /* MFW-replacement initializations for non-ASIC */
1515 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1516 struct ecore_ptt *p_ptt)
1518 struct ecore_dev *p_dev = p_hwfn->p_dev;
1522 if (CHIP_REV_IS_EMUL(p_dev)) {
1523 if (ECORE_IS_AH(p_dev))
1527 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1529 if (CHIP_REV_IS_EMUL(p_dev) &&
1530 (ECORE_IS_AH(p_dev)))
1531 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1534 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1535 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1536 if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1537 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1539 if (CHIP_REV_IS_EMUL(p_dev)) {
1540 if (ECORE_IS_AH(p_dev)) {
1541 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1542 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1543 (p_dev->num_ports_in_engine >> 1));
1545 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1546 p_dev->num_ports_in_engine == 4 ? 0 : 3);
1551 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1552 for (i = 0; i < 100; i++) {
1554 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1558 DP_NOTICE(p_hwfn, true,
1559 "RBC done failed to complete in PSWRQ2\n");
1561 return ECORE_SUCCESS;
1565 /* Init run time data for all PFs and their VFs on an engine.
1566 * TBD - for VFs - Once we have parent PF info for each VF in
1567 * shmem available as CAU requires knowledge of parent PF for each VF.
1569 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1571 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1574 for_each_hwfn(p_dev, i) {
1575 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1576 struct ecore_igu_info *p_igu_info;
1577 struct ecore_igu_block *p_block;
1578 struct cau_sb_entry sb_entry;
1580 p_igu_info = p_hwfn->hw_info.p_igu_info;
1583 igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1585 p_block = &p_igu_info->entry[igu_sb_id];
1587 if (!p_block->is_pf)
1590 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1591 p_block->function_id, 0, 0);
1592 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1598 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
1599 struct ecore_ptt *p_ptt)
1601 u32 val, wr_mbs, cache_line_size;
1603 val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1616 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1621 cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
1622 switch (cache_line_size) {
1637 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1641 if (wr_mbs < OSAL_CACHE_LINE_SIZE)
1643 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1644 OSAL_CACHE_LINE_SIZE, wr_mbs);
1646 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1648 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1649 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1653 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1654 struct ecore_ptt *p_ptt,
1657 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1658 struct ecore_dev *p_dev = p_hwfn->p_dev;
1659 u8 vf_id, max_num_vfs;
1662 enum _ecore_status_t rc = ECORE_SUCCESS;
1664 ecore_init_cau_rt_data(p_dev);
1666 /* Program GTT windows */
1667 ecore_gtt_init(p_hwfn, p_ptt);
1670 if (CHIP_REV_IS_EMUL(p_dev)) {
1671 rc = ecore_hw_init_chip(p_hwfn, p_ptt);
1672 if (rc != ECORE_SUCCESS)
1677 if (p_hwfn->mcp_info) {
1678 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1679 qm_info->pf_rl_en = 1;
1680 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1681 qm_info->pf_wfq_en = 1;
1684 ecore_qm_common_rt_init(p_hwfn,
1685 p_dev->num_ports_in_engine,
1686 qm_info->max_phys_tcs_per_port,
1687 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1688 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1689 qm_info->qm_port_params);
1691 ecore_cxt_hw_init_common(p_hwfn);
1693 ecore_init_cache_line_size(p_hwfn, p_ptt);
1695 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ECORE_PATH_ID(p_hwfn),
1697 if (rc != ECORE_SUCCESS)
1700 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1701 * need to decide with which value, maybe runtime
1703 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1704 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1706 if (ECORE_IS_BB(p_dev)) {
1707 /* Workaround clears ROCE search for all functions to prevent
1708 * involving non initialized function in processing ROCE packet.
1710 num_pfs = NUM_OF_ENG_PFS(p_dev);
1711 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1712 ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1713 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1714 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1716 /* pretend to original PF */
1717 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1720 /* Workaround for avoiding CCFC execution error when getting packets
1721 * with CRC errors, and allowing instead the invoking of the FW error
1723 * This is not done inside the init tool since it currently can't
1724 * perform a pretending to VFs.
1726 max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1727 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1728 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1729 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1730 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1731 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1732 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1733 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1735 /* pretend to original PF */
1736 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1742 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1743 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1745 #define PMEG_IF_BYTE_COUNT 8
1747 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1748 struct ecore_ptt *p_ptt,
1749 u32 addr, u64 data, u8 reg_type, u8 port)
1751 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1752 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1753 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1754 (8 << PMEG_IF_BYTE_COUNT),
1755 (reg_type << 25) | (addr << 8) | port,
1756 (u32)((data >> 32) & 0xffffffff),
1757 (u32)(data & 0xffffffff));
1759 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1760 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1761 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1762 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1763 (reg_type << 25) | (addr << 8) | port);
1764 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1765 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1766 (data >> 32) & 0xffffffff);
1769 #define XLPORT_MODE_REG (0x20a)
1770 #define XLPORT_MAC_CONTROL (0x210)
1771 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1772 #define XLPORT_ENABLE_REG (0x20b)
1774 #define XLMAC_CTRL (0x600)
1775 #define XLMAC_MODE (0x601)
1776 #define XLMAC_RX_MAX_SIZE (0x608)
1777 #define XLMAC_TX_CTRL (0x604)
1778 #define XLMAC_PAUSE_CTRL (0x60d)
1779 #define XLMAC_PFC_CTRL (0x60e)
1781 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1782 struct ecore_ptt *p_ptt)
1784 u8 loopback = 0, port = p_hwfn->port_id * 2;
1786 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1788 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1789 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1791 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1792 /* XLMAC: SOFT RESET */
1793 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1794 /* XLMAC: Port Speed >= 10Gbps */
1795 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1796 /* XLMAC: Max Size */
1797 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1798 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1799 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1801 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1802 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1803 0x30ffffc000ULL, 0, port);
1804 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1805 port); /* XLMAC: TX_EN, RX_EN */
1806 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1807 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1808 0x1003 | (loopback << 2), 0, port);
1809 /* Enabled Parallel PFC interface */
1810 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1812 /* XLPORT port enable */
1813 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1816 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1817 struct ecore_ptt *p_ptt)
1819 u8 port = p_hwfn->port_id;
1820 u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1822 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1824 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1825 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1827 CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1828 (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1830 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1831 1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1833 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1834 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1836 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1837 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1839 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1840 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1842 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1844 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1846 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1848 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1852 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1853 struct ecore_ptt *p_ptt)
1855 if (ECORE_IS_AH(p_hwfn->p_dev))
1856 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1858 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1861 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1862 struct ecore_ptt *p_ptt, u8 port)
1864 int port_offset = port ? 0x800 : 0;
1865 u32 xmac_rxctrl = 0;
1868 /* FIXME: move to common start */
1869 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1870 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
1872 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1873 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
1875 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1877 /* Set the number of ports on the Warp Core to 10G */
1878 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1880 /* Soft reset of XMAC */
1881 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1882 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1884 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1885 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1887 /* FIXME: move to common end */
1888 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1889 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1891 /* Set Max packet size: initialize XMAC block register for port 0 */
1892 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1894 /* CRC append for Tx packets: init XMAC block register for port 1 */
1895 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1897 /* Enable TX and RX: initialize XMAC block register for port 1 */
1898 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1899 XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1900 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1901 XMAC_REG_RX_CTRL_BB + port_offset);
1902 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1903 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1907 static enum _ecore_status_t
1908 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1909 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1911 u32 dpi_bit_shift, dpi_count, dpi_page_size;
1915 /* Calculate DPI size
1916 * ------------------
1917 * The PWM region contains Doorbell Pages. The first is reserverd for
1918 * the kernel for, e.g, L2. The others are free to be used by non-
1919 * trusted applications, typically from user space. Each page, called a
1920 * doorbell page is sectioned into windows that allow doorbells to be
1921 * issued in parallel by the kernel/application. The size of such a
1922 * window (a.k.a. WID) is 1kB.
1924 * 1kB WID x N WIDS = DPI page size
1925 * DPI page size x N DPIs = PWM region size
1927 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1928 * in order to ensure that two applications won't share the same page.
1929 * It also must contain at least one WID per CPU to allow parallelism.
1930 * It also must be a power of 2, since it is stored as a bit shift.
1932 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1933 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1934 * containing 4 WIDs.
1936 n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus);
1937 dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids);
1938 dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) &
1939 ~(OSAL_PAGE_SIZE - 1);
1940 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1941 dpi_count = pwm_region_size / dpi_page_size;
1943 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1944 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1947 p_hwfn->dpi_size = dpi_page_size;
1948 p_hwfn->dpi_count = dpi_count;
1950 /* Update registers */
1951 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1953 if (dpi_count < min_dpis)
1954 return ECORE_NORESOURCES;
1956 return ECORE_SUCCESS;
1959 enum ECORE_ROCE_EDPM_MODE {
1960 ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1961 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1962 ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1965 static enum _ecore_status_t
1966 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1967 struct ecore_ptt *p_ptt)
1969 u32 pwm_regsize, norm_regsize;
1970 u32 non_pwm_conn, min_addr_reg1;
1971 u32 db_bar_size, n_cpus;
1974 enum _ecore_status_t rc = ECORE_SUCCESS;
1977 db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1978 if (ECORE_IS_CMT(p_hwfn->p_dev))
1981 /* Calculate doorbell regions
1982 * -----------------------------------
1983 * The doorbell BAR is made of two regions. The first is called normal
1984 * region and the second is called PWM region. In the normal region
1985 * each ICID has its own set of addresses so that writing to that
1986 * specific address identifies the ICID. In the Process Window Mode
1987 * region the ICID is given in the data written to the doorbell. The
1988 * above per PF register denotes the offset in the doorbell BAR in which
1989 * the PWM region begins.
1990 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1991 * non-PWM connection. The calculation below computes the total non-PWM
1992 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1993 * in units of 4,096 bytes.
1995 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1996 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1998 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1999 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn,
2001 min_addr_reg1 = norm_regsize / 4096;
2002 pwm_regsize = db_bar_size - norm_regsize;
2004 /* Check that the normal and PWM sizes are valid */
2005 if (db_bar_size < norm_regsize) {
2006 DP_ERR(p_hwfn->p_dev,
2007 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
2008 db_bar_size, norm_regsize);
2009 return ECORE_NORESOURCES;
2011 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
2012 DP_ERR(p_hwfn->p_dev,
2013 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
2014 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
2016 return ECORE_NORESOURCES;
2019 /* Calculate number of DPIs */
2020 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
2021 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
2022 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
2023 /* Either EDPM is mandatory, or we are attempting to allocate a
2026 n_cpus = OSAL_NUM_CPUS();
2027 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2030 cond = ((rc != ECORE_SUCCESS) &&
2031 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
2032 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
2033 if (cond || p_hwfn->dcbx_no_edpm) {
2034 /* Either EDPM is disabled from user configuration, or it is
2035 * disabled via DCBx, or it is not mandatory and we failed to
2036 * allocated a WID per CPU.
2039 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2041 /* If we entered this flow due to DCBX then the DPM register is
2042 * already configured.
2047 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
2048 norm_regsize, pwm_regsize);
2050 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
2051 p_hwfn->dpi_size, p_hwfn->dpi_count,
2052 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
2053 "disabled" : "enabled");
2055 /* Check return codes from above calls */
2056 if (rc != ECORE_SUCCESS) {
2058 "Failed to allocate enough DPIs\n");
2059 return ECORE_NORESOURCES;
2063 p_hwfn->dpi_start_offset = norm_regsize;
2065 /* Update registers */
2066 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2067 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
2068 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2069 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2071 return ECORE_SUCCESS;
2074 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
2075 struct ecore_ptt *p_ptt,
2078 u32 ppf_to_eng_sel[NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE];
2080 enum _ecore_status_t rc = ECORE_SUCCESS;
2083 /* In CMT for non-RoCE packets - use connection based classification */
2084 val = ECORE_IS_CMT(p_hwfn->p_dev) ? 0x8 : 0x0;
2085 for (i = 0; i < NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE; i++)
2086 ppf_to_eng_sel[i] = val;
2087 STORE_RT_REG_AGG(p_hwfn, NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET,
2090 /* In CMT the gate should be cleared by the 2nd hwfn */
2091 if (!ECORE_IS_CMT(p_hwfn->p_dev) || !IS_LEAD_HWFN(p_hwfn))
2092 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
2094 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
2096 if (rc != ECORE_SUCCESS)
2099 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2102 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2103 return ECORE_SUCCESS;
2105 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2106 if (ECORE_IS_AH(p_hwfn->p_dev))
2107 return ECORE_SUCCESS;
2108 else if (ECORE_IS_BB(p_hwfn->p_dev))
2109 ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
2110 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2111 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
2112 /* Activate OPTE in CMT */
2115 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
2117 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
2118 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
2119 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
2120 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
2121 ecore_wr(p_hwfn, p_ptt,
2122 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
2123 ecore_wr(p_hwfn, p_ptt,
2124 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
2125 ecore_wr(p_hwfn, p_ptt,
2126 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
2130 ecore_emul_link_init(p_hwfn, p_ptt);
2132 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
2139 static enum _ecore_status_t
2140 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
2141 struct ecore_ptt *p_ptt,
2142 struct ecore_tunnel_info *p_tunn,
2145 enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
2147 u8 rel_pf_id = p_hwfn->rel_pf_id;
2149 enum _ecore_status_t rc = ECORE_SUCCESS;
2153 if (p_hwfn->mcp_info) {
2154 struct ecore_mcp_function_info *p_info;
2156 p_info = &p_hwfn->mcp_info->func_info;
2157 if (p_info->bandwidth_min)
2158 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2160 /* Update rate limit once we'll actually have a link */
2161 p_hwfn->qm_info.pf_rl = 100000;
2163 ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
2165 ecore_int_igu_init_rt(p_hwfn);
2167 /* Set VLAN in NIG if needed */
2168 if (hw_mode & (1 << MODE_MF_SD)) {
2169 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2170 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2171 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2172 p_hwfn->hw_info.ovlan);
2174 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2175 "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
2176 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
2180 /* Enable classification by MAC if needed */
2181 if (hw_mode & (1 << MODE_MF_SI)) {
2182 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2183 "Configuring TAGMAC_CLS_TYPE\n");
2184 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
2188 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
2189 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2190 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
2191 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2192 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
2193 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2195 /* perform debug configuration when chip is out of reset */
2196 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
2198 /* Sanity check before the PF init sequence that uses DMAE */
2199 rc = ecore_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
2203 /* PF Init sequence */
2204 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2208 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2209 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2213 /* Pure runtime initializations - directly to the HW */
2214 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2216 /* PCI relaxed ordering causes a decrease in the performance on some
2217 * systems. Till a root cause is found, disable this attribute in the
2221 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
2223 * DP_NOTICE(p_hwfn, true,
2224 * "Failed to find the PCIe Cap\n");
2227 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
2228 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
2229 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
2232 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2236 /* enable interrupts */
2237 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
2238 if (rc != ECORE_SUCCESS)
2241 /* send function start command */
2242 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2243 allow_npar_tx_switch);
2245 DP_NOTICE(p_hwfn, true,
2246 "Function start ramrod failed\n");
2250 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2251 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2252 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2254 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
2255 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
2257 ecore_wr(p_hwfn, p_ptt,
2258 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2261 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2262 "PRS_REG_SEARCH registers after start PFn\n");
2263 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
2264 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2265 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
2266 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
2267 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2268 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
2269 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
2270 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2271 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
2272 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
2273 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2274 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
2275 prs_reg = ecore_rd(p_hwfn, p_ptt,
2276 PRS_REG_SEARCH_TCP_FIRST_FRAG);
2277 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2278 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
2280 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2281 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2282 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2284 return ECORE_SUCCESS;
2287 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
2288 struct ecore_ptt *p_ptt,
2291 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2293 /* Configure the PF's internal FID_enable for master transactions */
2294 ecore_wr(p_hwfn, p_ptt,
2295 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2297 /* Wait until value is set - try for 1 second every 50us */
2298 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2299 val = ecore_rd(p_hwfn, p_ptt,
2300 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2307 if (val != set_val) {
2308 DP_NOTICE(p_hwfn, true,
2309 "PFID_ENABLE_MASTER wasn't changed after a second\n");
2310 return ECORE_UNKNOWN_ERROR;
2313 return ECORE_SUCCESS;
2316 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
2317 struct ecore_ptt *p_main_ptt)
2319 /* Read shadow of current MFW mailbox */
2320 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
2321 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
2322 p_hwfn->mcp_info->mfw_mb_cur,
2323 p_hwfn->mcp_info->mfw_mb_length);
2326 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
2327 struct ecore_ptt *p_ptt)
2329 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
2330 1 << p_hwfn->abs_pf_id);
2333 static enum _ecore_status_t
2334 ecore_fill_load_req_params(struct ecore_hwfn *p_hwfn,
2335 struct ecore_load_req_params *p_load_req,
2336 struct ecore_drv_load_params *p_drv_load)
2338 /* Make sure that if ecore-client didn't provide inputs, all the
2339 * expected defaults are indeed zero.
2341 OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
2342 OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
2343 OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
2345 OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
2347 if (p_drv_load == OSAL_NULL)
2350 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2351 ECORE_DRV_ROLE_KDUMP :
2353 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2354 p_load_req->override_force_load = p_drv_load->override_force_load;
2356 /* Old MFW versions don't support timeout values other than default and
2357 * none, so these values are replaced according to the fall-back action.
2360 if (p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT ||
2361 p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_NONE ||
2362 (p_hwfn->mcp_info->capabilities &
2363 FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO)) {
2364 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2368 switch (p_drv_load->mfw_timeout_fallback) {
2369 case ECORE_TO_FALLBACK_TO_NONE:
2370 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_NONE;
2372 case ECORE_TO_FALLBACK_TO_DEFAULT:
2373 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_DEFAULT;
2375 case ECORE_TO_FALLBACK_FAIL_LOAD:
2376 DP_NOTICE(p_hwfn, false,
2377 "Received %d as a value for MFW timeout while the MFW supports only default [%d] or none [%d]. Abort.\n",
2378 p_drv_load->mfw_timeout_val,
2379 ECORE_LOAD_REQ_LOCK_TO_DEFAULT,
2380 ECORE_LOAD_REQ_LOCK_TO_NONE);
2381 return ECORE_ABORTED;
2385 "Modified the MFW timeout value from %d to %s [%d] due to lack of MFW support\n",
2386 p_drv_load->mfw_timeout_val,
2387 (p_load_req->timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT) ?
2389 p_load_req->timeout_val);
2391 return ECORE_SUCCESS;
2394 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
2395 struct ecore_hw_init_params *p_params)
2397 if (p_params->p_tunn) {
2398 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2399 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2402 p_hwfn->b_int_enabled = 1;
2404 return ECORE_SUCCESS;
2407 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
2408 struct ecore_hw_init_params *p_params)
2410 struct ecore_load_req_params load_req_params;
2411 u32 load_code, resp, param, drv_mb_param;
2412 bool b_default_mtu = true;
2413 struct ecore_hwfn *p_hwfn;
2414 enum _ecore_status_t rc = ECORE_SUCCESS;
2417 if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) {
2418 DP_NOTICE(p_dev, false,
2419 "MSI mode is not supported for CMT devices\n");
2424 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
2425 if (rc != ECORE_SUCCESS)
2429 for_each_hwfn(p_dev, i) {
2430 p_hwfn = &p_dev->hwfns[i];
2432 /* If management didn't provide a default, set one of our own */
2433 if (!p_hwfn->hw_info.mtu) {
2434 p_hwfn->hw_info.mtu = 1500;
2435 b_default_mtu = false;
2439 ecore_vf_start(p_hwfn, p_params);
2443 rc = ecore_calc_hw_mode(p_hwfn);
2444 if (rc != ECORE_SUCCESS)
2447 ecore_set_spq_block_timeout(p_hwfn, p_params->spq_timeout_ms);
2449 rc = ecore_fill_load_req_params(p_hwfn, &load_req_params,
2450 p_params->p_drv_load_params);
2451 if (rc != ECORE_SUCCESS)
2454 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
2456 if (rc != ECORE_SUCCESS) {
2457 DP_NOTICE(p_hwfn, false,
2458 "Failed sending a LOAD_REQ command\n");
2462 load_code = load_req_params.load_code;
2463 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2464 "Load request was sent. Load code: 0x%x\n",
2467 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
2470 * When coming back from hiberbate state, the registers from
2471 * which shadow is read initially are not initialized. It turns
2472 * out that these registers get initialized during the call to
2473 * ecore_mcp_load_req request. So we need to reread them here
2474 * to get the proper shadow register value.
2475 * Note: This is a workaround for the missing MFW
2476 * initialization. It may be removed once the implementation
2479 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2481 /* Only relevant for recovery:
2482 * Clear the indication after the LOAD_REQ command is responded
2485 p_dev->recov_in_prog = false;
2487 p_hwfn->first_on_engine = (load_code ==
2488 FW_MSG_CODE_DRV_LOAD_ENGINE);
2490 if (!qm_lock_ref_cnt) {
2491 #ifdef CONFIG_ECORE_LOCK_ALLOC
2492 rc = OSAL_SPIN_LOCK_ALLOC(p_hwfn, &qm_lock);
2494 DP_ERR(p_hwfn, "qm_lock allocation failed\n");
2498 OSAL_SPIN_LOCK_INIT(&qm_lock);
2502 /* Clean up chip from previous driver if such remains exist.
2503 * This is not needed when the PF is the first one on the
2504 * engine, since afterwards we are going to init the FW.
2506 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2507 rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2508 p_hwfn->rel_pf_id, false);
2509 if (rc != ECORE_SUCCESS) {
2510 ecore_hw_err_notify(p_hwfn,
2511 ECORE_HW_ERR_RAMROD_FAIL);
2516 /* Log and clean previous pglue_b errors if such exist */
2517 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt, true);
2518 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2520 /* Enable the PF's internal FID_enable in the PXP */
2521 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2523 if (rc != ECORE_SUCCESS)
2526 switch (load_code) {
2527 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2528 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2529 p_hwfn->hw_info.hw_mode);
2530 if (rc != ECORE_SUCCESS)
2533 case FW_MSG_CODE_DRV_LOAD_PORT:
2534 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2535 p_hwfn->hw_info.hw_mode);
2536 if (rc != ECORE_SUCCESS)
2539 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2540 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2542 p_hwfn->hw_info.hw_mode,
2543 p_params->b_hw_start,
2545 p_params->allow_npar_tx_switch);
2548 DP_NOTICE(p_hwfn, false,
2549 "Unexpected load code [0x%08x]", load_code);
2554 if (rc != ECORE_SUCCESS) {
2555 DP_NOTICE(p_hwfn, false,
2556 "init phase failed for loadcode 0x%x (rc %d)\n",
2561 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2562 if (rc != ECORE_SUCCESS) {
2563 DP_NOTICE(p_hwfn, false,
2564 "Sending load done failed, rc = %d\n", rc);
2565 if (rc == ECORE_NOMEM) {
2566 DP_NOTICE(p_hwfn, false,
2567 "Sending load done was failed due to memory allocation failure\n");
2573 /* send DCBX attention request command */
2574 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2575 "sending phony dcbx set command to trigger DCBx attention handling\n");
2576 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2577 DRV_MSG_CODE_SET_DCBX,
2578 1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
2580 if (rc != ECORE_SUCCESS) {
2581 DP_NOTICE(p_hwfn, false,
2582 "Failed to send DCBX attention request\n");
2586 p_hwfn->hw_init_done = true;
2590 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2591 drv_mb_param = STORM_FW_VERSION;
2592 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2593 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2594 drv_mb_param, &resp, ¶m);
2595 if (rc != ECORE_SUCCESS)
2596 DP_INFO(p_hwfn, "Failed to update firmware version\n");
2599 rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2600 p_hwfn->hw_info.mtu);
2601 if (rc != ECORE_SUCCESS)
2602 DP_INFO(p_hwfn, "Failed to update default mtu\n");
2604 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2606 ECORE_OV_DRIVER_STATE_DISABLED);
2607 if (rc != ECORE_SUCCESS)
2608 DP_INFO(p_hwfn, "Failed to update driver state\n");
2615 #ifdef CONFIG_ECORE_LOCK_ALLOC
2616 if (!qm_lock_ref_cnt)
2617 OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
2620 /* The MFW load lock should be released regardless of success or failure
2621 * of initialization.
2622 * TODO: replace this with an attempt to send cancel_load.
2624 ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2628 #define ECORE_HW_STOP_RETRY_LIMIT (10)
2629 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2630 struct ecore_hwfn *p_hwfn,
2631 struct ecore_ptt *p_ptt)
2636 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2637 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2638 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2640 if ((!ecore_rd(p_hwfn, p_ptt,
2641 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2642 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2645 /* Dependent on number of connection/tasks, possibly
2646 * 1ms sleep is required between polls
2651 if (i < ECORE_HW_STOP_RETRY_LIMIT)
2654 DP_NOTICE(p_hwfn, false,
2655 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
2656 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2657 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2660 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2664 for_each_hwfn(p_dev, j) {
2665 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2666 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2668 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2672 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
2673 struct ecore_ptt *p_ptt,
2674 u32 addr, u32 expected_val)
2676 u32 val = ecore_rd(p_hwfn, p_ptt, addr);
2678 if (val != expected_val) {
2679 DP_NOTICE(p_hwfn, true,
2680 "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
2681 addr, val, expected_val);
2682 return ECORE_UNKNOWN_ERROR;
2685 return ECORE_SUCCESS;
2688 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2690 struct ecore_hwfn *p_hwfn;
2691 struct ecore_ptt *p_ptt;
2692 enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
2695 for_each_hwfn(p_dev, j) {
2696 p_hwfn = &p_dev->hwfns[j];
2697 p_ptt = p_hwfn->p_main_ptt;
2699 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2702 ecore_vf_pf_int_cleanup(p_hwfn);
2703 rc = ecore_vf_pf_reset(p_hwfn);
2704 if (rc != ECORE_SUCCESS) {
2705 DP_NOTICE(p_hwfn, true,
2706 "ecore_vf_pf_reset failed. rc = %d.\n",
2708 rc2 = ECORE_UNKNOWN_ERROR;
2713 /* mark the hw as uninitialized... */
2714 p_hwfn->hw_init_done = false;
2716 /* Send unload command to MCP */
2717 if (!p_dev->recov_in_prog) {
2718 rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
2719 if (rc != ECORE_SUCCESS) {
2720 DP_NOTICE(p_hwfn, false,
2721 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2723 rc2 = ECORE_UNKNOWN_ERROR;
2727 OSAL_DPC_SYNC(p_hwfn);
2729 /* After this point no MFW attentions are expected, e.g. prevent
2730 * race between pf stop and dcbx pf update.
2733 rc = ecore_sp_pf_stop(p_hwfn);
2734 if (rc != ECORE_SUCCESS) {
2735 DP_NOTICE(p_hwfn, false,
2736 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2738 rc2 = ECORE_UNKNOWN_ERROR;
2741 /* perform debug action after PF stop was sent */
2742 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
2744 /* close NIG to BRB gate */
2745 ecore_wr(p_hwfn, p_ptt,
2746 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2749 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2750 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2751 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2752 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2753 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2755 /* @@@TBD - clean transmission queues (5.b) */
2756 /* @@@TBD - clean BTB (5.c) */
2758 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2760 /* @@@TBD - verify DMAE requests are done (8) */
2762 /* Disable Attention Generation */
2763 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2764 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2765 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2766 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2767 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
2768 if (rc != ECORE_SUCCESS) {
2769 DP_NOTICE(p_hwfn, true,
2770 "Failed to return IGU CAM to default\n");
2771 rc2 = ECORE_UNKNOWN_ERROR;
2774 /* Need to wait 1ms to guarantee SBs are cleared */
2777 if (!p_dev->recov_in_prog) {
2778 ecore_verify_reg_val(p_hwfn, p_ptt,
2779 QM_REG_USG_CNT_PF_TX, 0);
2780 ecore_verify_reg_val(p_hwfn, p_ptt,
2781 QM_REG_USG_CNT_PF_OTHER, 0);
2782 /* @@@TBD - assert on incorrect xCFC values (10.b) */
2785 /* Disable PF in HW blocks */
2786 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2787 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2790 #ifdef CONFIG_ECORE_LOCK_ALLOC
2791 if (!qm_lock_ref_cnt)
2792 OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
2795 if (!p_dev->recov_in_prog) {
2796 rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
2797 if (rc == ECORE_NOMEM) {
2798 DP_NOTICE(p_hwfn, false,
2799 "Failed sending an UNLOAD_DONE command due to a memory allocation failure. Resending.\n");
2800 rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
2802 if (rc != ECORE_SUCCESS) {
2803 DP_NOTICE(p_hwfn, false,
2804 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2806 rc2 = ECORE_UNKNOWN_ERROR;
2811 if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
2812 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2813 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2815 /* Clear the PF's internal FID_enable in the PXP.
2816 * In CMT this should only be done for first hw-function, and
2817 * only after all transactions have stopped for all active
2820 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2822 if (rc != ECORE_SUCCESS) {
2823 DP_NOTICE(p_hwfn, true,
2824 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2826 rc2 = ECORE_UNKNOWN_ERROR;
2833 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2837 for_each_hwfn(p_dev, j) {
2838 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2839 struct ecore_ptt *p_ptt;
2842 ecore_vf_pf_int_cleanup(p_hwfn);
2845 p_ptt = ecore_ptt_acquire(p_hwfn);
2849 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2850 "Shutting down the fastpath\n");
2852 ecore_wr(p_hwfn, p_ptt,
2853 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2855 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2856 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2857 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2858 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2859 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2861 /* @@@TBD - clean transmission queues (5.b) */
2862 /* @@@TBD - clean BTB (5.c) */
2864 /* @@@TBD - verify DMAE requests are done (8) */
2866 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2867 /* Need to wait 1ms to guarantee SBs are cleared */
2869 ecore_ptt_release(p_hwfn, p_ptt);
2872 return ECORE_SUCCESS;
2875 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2877 struct ecore_ptt *p_ptt;
2879 if (IS_VF(p_hwfn->p_dev))
2880 return ECORE_SUCCESS;
2882 p_ptt = ecore_ptt_acquire(p_hwfn);
2886 /* If roce info is allocated it means roce is initialized and should
2887 * be enabled in searcher.
2889 if (p_hwfn->p_rdma_info) {
2890 if (p_hwfn->b_rdma_enabled_in_prs)
2891 ecore_wr(p_hwfn, p_ptt,
2892 p_hwfn->rdma_prs_search_reg, 0x1);
2893 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2896 /* Re-open incoming traffic */
2897 ecore_wr(p_hwfn, p_ptt,
2898 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2899 ecore_ptt_release(p_hwfn, p_ptt);
2901 return ECORE_SUCCESS;
2904 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2905 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2907 ecore_ptt_pool_free(p_hwfn);
2908 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2911 /* Setup bar access */
2912 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2914 /* clear indirect access */
2915 if (ECORE_IS_AH(p_hwfn->p_dev)) {
2916 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2917 PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2918 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2919 PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2920 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2921 PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2922 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2923 PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2925 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2926 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2927 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2928 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2929 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2930 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2931 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2932 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2935 /* Clean previous pglue_b errors if such exist */
2936 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2938 /* enable internal target-read */
2939 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2940 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2943 static void get_function_id(struct ecore_hwfn *p_hwfn)
2946 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2947 PXP_PF_ME_OPAQUE_ADDR);
2949 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2951 /* Bits 16-19 from the ME registers are the pf_num */
2952 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2953 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2954 PXP_CONCRETE_FID_PFID);
2955 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2956 PXP_CONCRETE_FID_PORT);
2958 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2959 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2960 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2963 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2965 u32 *feat_num = p_hwfn->hw_info.feat_num;
2966 struct ecore_sb_cnt_info sb_cnt;
2969 OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
2970 ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
2972 /* L2 Queues require each: 1 status block. 1 L2 queue */
2973 if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
2974 /* Start by allocating VF queues, then PF's */
2975 feat_num[ECORE_VF_L2_QUE] =
2977 RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
2979 feat_num[ECORE_PF_L2_QUE] =
2981 sb_cnt.cnt - non_l2_sbs,
2982 RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2983 FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
2986 if (ECORE_IS_FCOE_PERSONALITY(p_hwfn))
2987 feat_num[ECORE_FCOE_CQ] =
2988 OSAL_MIN_T(u32, sb_cnt.cnt, RESC_NUM(p_hwfn,
2991 if (ECORE_IS_ISCSI_PERSONALITY(p_hwfn))
2992 feat_num[ECORE_ISCSI_CQ] =
2993 OSAL_MIN_T(u32, sb_cnt.cnt, RESC_NUM(p_hwfn,
2996 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2997 "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2998 (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2999 (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
3000 (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
3001 (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
3002 (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
3006 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
3009 case ECORE_L2_QUEUE:
3023 case ECORE_RDMA_CNQ_RAM:
3024 return "RDMA_CNQ_RAM";
3027 case ECORE_LL2_QUEUE:
3029 case ECORE_CMDQS_CQS:
3031 case ECORE_RDMA_STATS_QUEUE:
3032 return "RDMA_STATS_QUEUE";
3038 return "UNKNOWN_RESOURCE";
3042 static enum _ecore_status_t
3043 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
3044 struct ecore_ptt *p_ptt,
3045 enum ecore_resources res_id,
3049 enum _ecore_status_t rc;
3051 rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
3052 resc_max_val, p_mcp_resp);
3053 if (rc != ECORE_SUCCESS) {
3054 DP_NOTICE(p_hwfn, false,
3055 "MFW response failure for a max value setting of resource %d [%s]\n",
3056 res_id, ecore_hw_get_resc_name(res_id));
3060 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
3062 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
3063 res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
3065 return ECORE_SUCCESS;
3068 static enum _ecore_status_t
3069 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
3070 struct ecore_ptt *p_ptt)
3072 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3073 u32 resc_max_val, mcp_resp;
3075 enum _ecore_status_t rc;
3077 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3080 case ECORE_LL2_QUEUE:
3081 case ECORE_RDMA_CNQ_RAM:
3082 case ECORE_RDMA_STATS_QUEUE:
3090 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
3091 resc_max_val, &mcp_resp);
3092 if (rc != ECORE_SUCCESS)
3095 /* There's no point to continue to the next resource if the
3096 * command is not supported by the MFW.
3097 * We do continue if the command is supported but the resource
3098 * is unknown to the MFW. Such a resource will be later
3099 * configured with the default allocation values.
3101 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
3102 return ECORE_NOTIMPL;
3105 return ECORE_SUCCESS;
3109 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
3110 enum ecore_resources res_id,
3111 u32 *p_resc_num, u32 *p_resc_start)
3113 u8 num_funcs = p_hwfn->num_funcs_on_engine;
3114 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3117 case ECORE_L2_QUEUE:
3118 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
3119 MAX_NUM_L2_QUEUES_BB) / num_funcs;
3122 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3123 MAX_NUM_VPORTS_BB) / num_funcs;
3126 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
3127 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
3130 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
3131 MAX_QM_TX_QUEUES_BB) / num_funcs;
3134 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
3138 /* Each VFC resource can accommodate both a MAC and a VLAN */
3139 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3142 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
3143 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
3145 case ECORE_LL2_QUEUE:
3146 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
3148 case ECORE_RDMA_CNQ_RAM:
3149 case ECORE_CMDQS_CQS:
3150 /* CNQ/CMDQS are the same resource */
3152 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
3154 case ECORE_RDMA_STATS_QUEUE:
3156 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3157 MAX_NUM_VPORTS_BB) / num_funcs;
3174 /* Since we want its value to reflect whether MFW supports
3175 * the new scheme, have a default of 0.
3180 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3184 return ECORE_SUCCESS;
3187 static enum _ecore_status_t
3188 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
3189 bool drv_resc_alloc)
3191 u32 dflt_resc_num = 0, dflt_resc_start = 0;
3192 u32 mcp_resp, *p_resc_num, *p_resc_start;
3193 enum _ecore_status_t rc;
3195 p_resc_num = &RESC_NUM(p_hwfn, res_id);
3196 p_resc_start = &RESC_START(p_hwfn, res_id);
3198 rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3200 if (rc != ECORE_SUCCESS) {
3202 "Failed to get default amount for resource %d [%s]\n",
3203 res_id, ecore_hw_get_resc_name(res_id));
3208 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3209 *p_resc_num = dflt_resc_num;
3210 *p_resc_start = dflt_resc_start;
3215 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3216 &mcp_resp, p_resc_num, p_resc_start);
3217 if (rc != ECORE_SUCCESS) {
3218 DP_NOTICE(p_hwfn, true,
3219 "MFW response failure for an allocation request for"
3220 " resource %d [%s]\n",
3221 res_id, ecore_hw_get_resc_name(res_id));
3225 /* Default driver values are applied in the following cases:
3226 * - The resource allocation MB command is not supported by the MFW
3227 * - There is an internal error in the MFW while processing the request
3228 * - The resource ID is unknown to the MFW
3230 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3232 "Failed to receive allocation info for resource %d [%s]."
3233 " mcp_resp = 0x%x. Applying default values"
3235 res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
3236 dflt_resc_num, dflt_resc_start);
3238 *p_resc_num = dflt_resc_num;
3239 *p_resc_start = dflt_resc_start;
3243 if ((*p_resc_num != dflt_resc_num ||
3244 *p_resc_start != dflt_resc_start) &&
3245 res_id != ECORE_SB) {
3247 "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
3248 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
3249 *p_resc_start, dflt_resc_num, dflt_resc_start,
3250 drv_resc_alloc ? " - Applying default values" : "");
3251 if (drv_resc_alloc) {
3252 *p_resc_num = dflt_resc_num;
3253 *p_resc_start = dflt_resc_start;
3257 return ECORE_SUCCESS;
3260 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
3261 bool drv_resc_alloc)
3263 enum _ecore_status_t rc;
3266 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3267 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
3268 if (rc != ECORE_SUCCESS)
3272 return ECORE_SUCCESS;
3275 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
3276 struct ecore_ptt *p_ptt,
3277 bool drv_resc_alloc)
3279 struct ecore_resc_unlock_params resc_unlock_params;
3280 struct ecore_resc_lock_params resc_lock_params;
3281 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3283 enum _ecore_status_t rc;
3285 u32 *resc_start = p_hwfn->hw_info.resc_start;
3286 u32 *resc_num = p_hwfn->hw_info.resc_num;
3287 /* For AH, an equal share of the ILT lines between the maximal number of
3288 * PFs is not enough for RoCE. This would be solved by the future
3289 * resource allocation scheme, but isn't currently present for
3290 * FPGA/emulation. For now we keep a number that is sufficient for RoCE
3291 * to work - the BB number of ILT lines divided by its max PFs number.
3293 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
3296 /* Setting the max values of the soft resources and the following
3297 * resources allocation queries should be atomic. Since several PFs can
3298 * run in parallel - a resource lock is needed.
3299 * If either the resource lock or resource set value commands are not
3300 * supported - skip the max values setting, release the lock if
3301 * needed, and proceed to the queries. Other failures, including a
3302 * failure to acquire the lock, will cause this function to fail.
3303 * Old drivers that don't acquire the lock can run in parallel, and
3304 * their allocation values won't be affected by the updated max values.
3306 ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3307 ECORE_RESC_LOCK_RESC_ALLOC, false);
3309 rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3310 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3312 } else if (rc == ECORE_NOTIMPL) {
3314 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3315 } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
3316 DP_NOTICE(p_hwfn, false,
3317 "Failed to acquire the resource lock for the resource allocation commands\n");
3319 goto unlock_and_exit;
3321 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
3322 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3323 DP_NOTICE(p_hwfn, false,
3324 "Failed to set the max values of the soft resources\n");
3325 goto unlock_and_exit;
3326 } else if (rc == ECORE_NOTIMPL) {
3328 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3329 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3330 &resc_unlock_params);
3331 if (rc != ECORE_SUCCESS)
3333 "Failed to release the resource lock for the resource allocation commands\n");
3337 rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
3338 if (rc != ECORE_SUCCESS)
3339 goto unlock_and_exit;
3341 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3342 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3343 &resc_unlock_params);
3344 if (rc != ECORE_SUCCESS)
3346 "Failed to release the resource lock for the resource allocation commands\n");
3350 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3351 /* Reduced build contains less PQs */
3352 if (!(p_hwfn->p_dev->b_is_emul_full)) {
3353 resc_num[ECORE_PQ] = 32;
3354 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
3355 p_hwfn->enabled_func_idx;
3358 /* For AH emulation, since we have a possible maximal number of
3359 * 16 enabled PFs, in case there are not enough ILT lines -
3360 * allocate only first PF as RoCE and have all the other ETH
3361 * only with less ILT lines.
3363 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
3364 resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
3365 resc_num[ECORE_ILT],
3366 roce_min_ilt_lines);
3369 /* Correct the common ILT calculation if PF0 has more */
3370 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
3371 p_hwfn->p_dev->b_is_emul_full &&
3372 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
3373 resc_start[ECORE_ILT] += roce_min_ilt_lines -
3374 resc_num[ECORE_ILT];
3377 /* Sanity for ILT */
3378 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3379 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3380 DP_NOTICE(p_hwfn, true,
3381 "Can't assign ILT pages [%08x,...,%08x]\n",
3382 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
3388 /* This will also learn the number of SBs from MFW */
3389 if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
3392 ecore_hw_set_feat(p_hwfn);
3394 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3395 "The numbers for each resource are:\n");
3396 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
3397 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
3398 ecore_hw_get_resc_name(res_id),
3399 RESC_NUM(p_hwfn, res_id),
3400 RESC_START(p_hwfn, res_id));
3402 return ECORE_SUCCESS;
3405 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3406 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3407 &resc_unlock_params);
3411 static enum _ecore_status_t
3412 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
3413 struct ecore_ptt *p_ptt,
3414 struct ecore_hw_prepare_params *p_params)
3416 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
3417 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
3418 struct ecore_mcp_link_capabilities *p_caps;
3419 struct ecore_mcp_link_params *link;
3420 enum _ecore_status_t rc;
3422 /* Read global nvm_cfg address */
3423 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
3425 /* Verify MCP has initialized it */
3426 if (!nvm_cfg_addr) {
3427 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
3428 if (p_params->b_relaxed_probe)
3429 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
3433 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
3435 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
3437 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3438 OFFSETOF(struct nvm_cfg1, glob) +
3439 OFFSETOF(struct nvm_cfg1_glob, core_cfg);
3441 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
3443 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
3444 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
3445 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
3446 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
3448 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
3449 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
3451 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
3452 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
3454 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
3455 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
3457 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
3458 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
3460 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
3461 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
3463 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
3464 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
3466 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
3467 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
3469 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
3470 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
3472 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
3473 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
3475 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3476 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
3479 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
3484 /* Read DCBX configuration */
3485 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3486 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3487 dcbx_mode = ecore_rd(p_hwfn, p_ptt,
3489 OFFSETOF(struct nvm_cfg1_port, generic_cont0));
3490 dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
3491 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
3492 switch (dcbx_mode) {
3493 case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
3494 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
3496 case NVM_CFG1_PORT_DCBX_MODE_CEE:
3497 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
3499 case NVM_CFG1_PORT_DCBX_MODE_IEEE:
3500 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
3503 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
3506 /* Read default link configuration */
3507 link = &p_hwfn->mcp_info->link_input;
3508 p_caps = &p_hwfn->mcp_info->link_capabilities;
3509 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3510 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3511 link_temp = ecore_rd(p_hwfn, p_ptt,
3513 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
3514 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
3515 link->speed.advertised_speeds = link_temp;
3516 p_caps->speed_capabilities = link->speed.advertised_speeds;
3518 link_temp = ecore_rd(p_hwfn, p_ptt,
3520 OFFSETOF(struct nvm_cfg1_port, link_settings));
3521 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
3522 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
3523 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
3524 link->speed.autoneg = true;
3526 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
3527 link->speed.forced_speed = 1000;
3529 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
3530 link->speed.forced_speed = 10000;
3532 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3533 link->speed.forced_speed = 25000;
3535 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3536 link->speed.forced_speed = 40000;
3538 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3539 link->speed.forced_speed = 50000;
3541 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3542 link->speed.forced_speed = 100000;
3545 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
3548 p_caps->default_speed = link->speed.forced_speed;
3549 p_caps->default_speed_autoneg = link->speed.autoneg;
3551 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3552 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3553 link->pause.autoneg = !!(link_temp &
3554 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3555 link->pause.forced_rx = !!(link_temp &
3556 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3557 link->pause.forced_tx = !!(link_temp &
3558 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3559 link->loopback_mode = 0;
3561 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
3562 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
3563 OFFSETOF(struct nvm_cfg1_port, ext_phy));
3564 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
3565 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
3566 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
3567 link->eee.enable = true;
3568 switch (link_temp) {
3569 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
3570 p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
3571 link->eee.enable = false;
3573 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
3574 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
3576 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
3577 p_caps->eee_lpi_timer =
3578 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
3580 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
3581 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
3585 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
3586 link->eee.tx_lpi_enable = link->eee.enable;
3587 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
3589 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
3592 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3593 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
3594 link->speed.forced_speed, link->speed.advertised_speeds,
3595 link->speed.autoneg, link->pause.autoneg,
3596 p_caps->default_eee, p_caps->eee_lpi_timer);
3598 /* Read Multi-function information from shmem */
3599 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3600 OFFSETOF(struct nvm_cfg1, glob) +
3601 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3603 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3605 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3606 NVM_CFG1_GLOB_MF_MODE_OFFSET;
3609 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3610 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS;
3612 case NVM_CFG1_GLOB_MF_MODE_UFP:
3613 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
3614 1 << ECORE_MF_UFP_SPECIFIC |
3615 1 << ECORE_MF_8021Q_TAGGING;
3617 case NVM_CFG1_GLOB_MF_MODE_BD:
3618 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
3619 1 << ECORE_MF_LLH_PROTO_CLSS |
3620 1 << ECORE_MF_8021AD_TAGGING;
3622 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3623 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3624 1 << ECORE_MF_LLH_PROTO_CLSS |
3625 1 << ECORE_MF_LL2_NON_UNICAST |
3626 1 << ECORE_MF_INTER_PF_SWITCH |
3627 1 << ECORE_MF_DISABLE_ARFS;
3629 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3630 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3631 1 << ECORE_MF_LLH_PROTO_CLSS |
3632 1 << ECORE_MF_LL2_NON_UNICAST;
3633 if (ECORE_IS_BB(p_hwfn->p_dev))
3634 p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
3637 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
3638 p_hwfn->p_dev->mf_bits);
3640 if (ECORE_IS_CMT(p_hwfn->p_dev))
3641 p_hwfn->p_dev->mf_bits |= (1 << ECORE_MF_DISABLE_ARFS);
3643 /* It's funny since we have another switch, but it's easier
3644 * to throw this away in linux this way. Long term, it might be
3645 * better to have have getters for needed ECORE_MF_* fields,
3646 * convert client code and eliminate this.
3649 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3650 case NVM_CFG1_GLOB_MF_MODE_BD:
3651 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3653 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3654 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3656 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3657 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3659 case NVM_CFG1_GLOB_MF_MODE_UFP:
3660 p_hwfn->p_dev->mf_mode = ECORE_MF_UFP;
3664 /* Read Multi-function information from shmem */
3665 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3666 OFFSETOF(struct nvm_cfg1, glob) +
3667 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3669 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3670 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3671 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3672 &p_hwfn->hw_info.device_capabilities);
3673 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3674 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3675 &p_hwfn->hw_info.device_capabilities);
3676 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3677 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3678 &p_hwfn->hw_info.device_capabilities);
3679 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3680 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3681 &p_hwfn->hw_info.device_capabilities);
3682 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3683 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3684 &p_hwfn->hw_info.device_capabilities);
3686 rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3687 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3689 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3695 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3696 struct ecore_ptt *p_ptt)
3698 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3699 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3700 struct ecore_dev *p_dev = p_hwfn->p_dev;
3702 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3704 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3705 * in the other bits are selected.
3706 * Bits 1-15 are for functions 1-15, respectively, and their value is
3707 * '0' only for enabled functions (function 0 always exists and
3709 * In case of CMT in BB, only the "even" functions are enabled, and thus
3710 * the number of functions for both hwfns is learnt from the same bits.
3712 if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3713 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3714 MISCS_REG_FUNCTION_HIDE_BB_K2);
3716 reg_function_hide = 0;
3719 if (reg_function_hide & 0x1) {
3720 if (ECORE_IS_BB(p_dev)) {
3721 if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) {
3733 /* Get the number of the enabled functions on the engine */
3734 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3741 /* Get the PF index within the enabled functions */
3742 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3743 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3751 p_hwfn->num_funcs_on_engine = num_funcs;
3752 p_hwfn->enabled_func_idx = enabled_func_idx;
3755 if (CHIP_REV_IS_FPGA(p_dev)) {
3756 DP_NOTICE(p_hwfn, false,
3757 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3758 p_hwfn->num_funcs_on_engine = 4;
3762 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3763 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3764 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3765 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3768 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3769 struct ecore_ptt *p_ptt)
3771 struct ecore_dev *p_dev = p_hwfn->p_dev;
3775 /* Read the port mode */
3776 if (CHIP_REV_IS_FPGA(p_dev))
3778 else if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_CMT(p_dev))
3779 /* In CMT on emulation, assume 1 port */
3783 port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3785 if (port_mode < 3) {
3786 p_dev->num_ports_in_engine = 1;
3787 } else if (port_mode <= 5) {
3788 p_dev->num_ports_in_engine = 2;
3790 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3791 p_dev->num_ports_in_engine);
3793 /* Default num_ports_in_engine to something */
3794 p_dev->num_ports_in_engine = 1;
3798 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3799 struct ecore_ptt *p_ptt)
3801 struct ecore_dev *p_dev = p_hwfn->p_dev;
3805 p_dev->num_ports_in_engine = 0;
3808 if (CHIP_REV_IS_EMUL(p_dev)) {
3809 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3810 switch ((port & 0xf000) >> 12) {
3812 p_dev->num_ports_in_engine = 1;
3815 p_dev->num_ports_in_engine = 2;
3818 p_dev->num_ports_in_engine = 4;
3821 DP_NOTICE(p_hwfn, false,
3822 "Unknown port mode in ECO_RESERVED %08x\n",
3827 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3828 port = ecore_rd(p_hwfn, p_ptt,
3829 CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3832 p_dev->num_ports_in_engine++;
3835 if (!p_dev->num_ports_in_engine) {
3836 DP_NOTICE(p_hwfn, true, "All NIG ports are inactive\n");
3838 /* Default num_ports_in_engine to something */
3839 p_dev->num_ports_in_engine = 1;
3843 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3844 struct ecore_ptt *p_ptt)
3846 struct ecore_dev *p_dev = p_hwfn->p_dev;
3848 /* Determine the number of ports per engine */
3849 if (ECORE_IS_BB(p_dev))
3850 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3852 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3854 /* Get the total number of ports of the device */
3855 if (ECORE_IS_CMT(p_dev)) {
3856 /* In CMT there is always only one port */
3857 p_dev->num_ports = 1;
3859 } else if (CHIP_REV_IS_EMUL(p_dev) || CHIP_REV_IS_TEDIBEAR(p_dev)) {
3860 p_dev->num_ports = p_dev->num_ports_in_engine *
3861 ecore_device_num_engines(p_dev);
3864 u32 addr, global_offsize, global_addr;
3866 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
3868 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
3869 global_addr = SECTION_ADDR(global_offsize, 0);
3870 addr = global_addr + OFFSETOF(struct public_global, max_ports);
3871 p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
3875 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
3876 struct ecore_ptt *p_ptt)
3878 struct ecore_mcp_link_capabilities *p_caps;
3881 p_caps = &p_hwfn->mcp_info->link_capabilities;
3882 if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
3885 p_caps->eee_speed_caps = 0;
3886 eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
3887 OFFSETOF(struct public_port, eee_status));
3888 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
3889 EEE_SUPPORTED_SPEED_OFFSET;
3890 if (eee_status & EEE_1G_SUPPORTED)
3891 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
3892 if (eee_status & EEE_10G_ADV)
3893 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
3896 static enum _ecore_status_t
3897 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3898 enum ecore_pci_personality personality,
3899 struct ecore_hw_prepare_params *p_params)
3901 bool drv_resc_alloc = p_params->drv_resc_alloc;
3902 enum _ecore_status_t rc;
3904 if (IS_ECORE_PACING(p_hwfn)) {
3905 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_IOV,
3906 "Skipping IOV as packet pacing is requested\n");
3909 /* Since all information is common, only first hwfns should do this */
3910 if (IS_LEAD_HWFN(p_hwfn) && !IS_ECORE_PACING(p_hwfn)) {
3911 rc = ecore_iov_hw_info(p_hwfn);
3912 if (rc != ECORE_SUCCESS) {
3913 if (p_params->b_relaxed_probe)
3914 p_params->p_relaxed_res =
3915 ECORE_HW_PREPARE_BAD_IOV;
3921 if (IS_LEAD_HWFN(p_hwfn))
3922 ecore_hw_info_port_num(p_hwfn, p_ptt);
3924 ecore_mcp_get_capabilities(p_hwfn, p_ptt);
3927 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3929 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3930 if (rc != ECORE_SUCCESS)
3936 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3937 if (rc != ECORE_SUCCESS) {
3938 if (p_params->b_relaxed_probe)
3939 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3945 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3947 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3948 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3951 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3953 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3954 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3958 if (ecore_mcp_is_init(p_hwfn)) {
3959 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3960 p_hwfn->hw_info.ovlan =
3961 p_hwfn->mcp_info->func_info.ovlan;
3963 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3965 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
3967 ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
3970 if (personality != ECORE_PCI_DEFAULT) {
3971 p_hwfn->hw_info.personality = personality;
3972 } else if (ecore_mcp_is_init(p_hwfn)) {
3973 enum ecore_pci_personality protocol;
3975 protocol = p_hwfn->mcp_info->func_info.protocol;
3976 p_hwfn->hw_info.personality = protocol;
3980 /* To overcome ILT lack for emulation, until at least until we'll have
3981 * a definite answer from system about it, allow only PF0 to be RoCE.
3983 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3984 if (!p_hwfn->rel_pf_id)
3985 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3987 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3991 /* although in BB some constellations may support more than 4 tcs,
3992 * that can result in performance penalty in some cases. 4
3993 * represents a good tradeoff between performance and flexibility.
3995 if (IS_ECORE_PACING(p_hwfn))
3996 p_hwfn->hw_info.num_hw_tc = 1;
3998 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
4000 /* start out with a single active tc. This can be increased either
4001 * by dcbx negotiation or by upper layer driver
4003 p_hwfn->hw_info.num_active_tc = 1;
4005 ecore_get_num_funcs(p_hwfn, p_ptt);
4007 if (ecore_mcp_is_init(p_hwfn))
4008 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
4010 /* In case of forcing the driver's default resource allocation, calling
4011 * ecore_hw_get_resc() should come after initializing the personality
4012 * and after getting the number of functions, since the calculation of
4013 * the resources/features depends on them.
4014 * This order is not harmful if not forcing.
4016 rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
4017 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
4019 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
4025 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
4026 struct ecore_ptt *p_ptt)
4028 struct ecore_dev *p_dev = p_hwfn->p_dev;
4032 /* Read Vendor Id / Device Id */
4033 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
4035 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
4038 /* Determine type */
4039 device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
4040 switch (device_id_mask) {
4041 case ECORE_DEV_ID_MASK_BB:
4042 p_dev->type = ECORE_DEV_TYPE_BB;
4044 case ECORE_DEV_ID_MASK_AH:
4045 p_dev->type = ECORE_DEV_TYPE_AH;
4048 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
4050 return ECORE_ABORTED;
4053 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
4054 p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM);
4055 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
4056 p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV);
4058 /* Learn number of HW-functions */
4059 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
4061 if (tmp & (1 << p_hwfn->rel_pf_id)) {
4062 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
4063 p_dev->num_hwfns = 2;
4065 p_dev->num_hwfns = 1;
4069 if (CHIP_REV_IS_EMUL(p_dev)) {
4070 /* For some reason we have problems with this register
4071 * in B0 emulation; Simply assume no CMT
4073 DP_NOTICE(p_dev->hwfns, false,
4074 "device on emul - assume no CMT\n");
4075 p_dev->num_hwfns = 1;
4079 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG);
4080 p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID);
4081 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
4082 p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL);
4084 DP_INFO(p_dev->hwfns,
4085 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n",
4086 ECORE_IS_BB(p_dev) ? "BB" : "AH",
4087 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
4088 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
4091 if (ECORE_IS_BB_A0(p_dev)) {
4092 DP_NOTICE(p_dev->hwfns, false,
4093 "The chip type/rev (BB A0) is not supported!\n");
4094 return ECORE_ABORTED;
4097 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
4098 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
4100 if (CHIP_REV_IS_EMUL(p_dev)) {
4101 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
4102 if (tmp & (1 << 29)) {
4103 DP_NOTICE(p_hwfn, false,
4104 "Emulation: Running on a FULL build\n");
4105 p_dev->b_is_emul_full = true;
4107 DP_NOTICE(p_hwfn, false,
4108 "Emulation: Running on a REDUCED build\n");
4113 return ECORE_SUCCESS;
4116 #ifndef LINUX_REMOVE
4117 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
4124 for_each_hwfn(p_dev, j) {
4125 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
4127 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
4128 "Mark hw/fw uninitialized\n");
4130 p_hwfn->hw_init_done = false;
4132 ecore_ptt_invalidate(p_hwfn);
4137 static enum _ecore_status_t
4138 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
4139 void OSAL_IOMEM * p_regview,
4140 void OSAL_IOMEM * p_doorbells,
4141 struct ecore_hw_prepare_params *p_params)
4143 struct ecore_mdump_retain_data mdump_retain;
4144 struct ecore_dev *p_dev = p_hwfn->p_dev;
4145 struct ecore_mdump_info mdump_info;
4146 enum _ecore_status_t rc = ECORE_SUCCESS;
4148 /* Split PCI bars evenly between hwfns */
4149 p_hwfn->regview = p_regview;
4150 p_hwfn->doorbells = p_doorbells;
4153 return ecore_vf_hw_prepare(p_hwfn);
4155 /* Validate that chip access is feasible */
4156 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
4158 "Reading the ME register returns all Fs; Preventing further chip access\n");
4159 if (p_params->b_relaxed_probe)
4160 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
4164 get_function_id(p_hwfn);
4166 /* Allocate PTT pool */
4167 rc = ecore_ptt_pool_alloc(p_hwfn);
4169 DP_NOTICE(p_hwfn, false, "Failed to prepare hwfn's hw\n");
4170 if (p_params->b_relaxed_probe)
4171 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4175 /* Allocate the main PTT */
4176 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4178 /* First hwfn learns basic information, e.g., number of hwfns */
4179 if (!p_hwfn->my_id) {
4180 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
4181 if (rc != ECORE_SUCCESS) {
4182 if (p_params->b_relaxed_probe)
4183 p_params->p_relaxed_res =
4184 ECORE_HW_PREPARE_FAILED_DEV;
4189 ecore_hw_hwfn_prepare(p_hwfn);
4191 /* Initialize MCP structure */
4192 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4194 DP_NOTICE(p_hwfn, false, "Failed initializing mcp command\n");
4195 if (p_params->b_relaxed_probe)
4196 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4200 /* Read the device configuration information from the HW and SHMEM */
4201 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
4202 p_params->personality, p_params);
4204 DP_NOTICE(p_hwfn, false, "Failed to get HW information\n");
4208 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
4209 * called, since among others it sets the ports number in an engine.
4211 if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
4212 !p_dev->recov_in_prog) {
4213 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4214 if (rc != ECORE_SUCCESS)
4215 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
4218 /* Check if mdump logs/data are present and update the epoch value */
4219 if (IS_LEAD_HWFN(p_hwfn)) {
4221 if (!CHIP_REV_IS_EMUL(p_dev)) {
4223 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
4225 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
4226 DP_NOTICE(p_hwfn, false,
4227 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
4229 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
4231 if (rc == ECORE_SUCCESS && mdump_retain.valid)
4232 DP_NOTICE(p_hwfn, false,
4233 "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
4234 mdump_retain.epoch, mdump_retain.pf,
4235 mdump_retain.status);
4237 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
4244 /* Allocate the init RT array and initialize the init-ops engine */
4245 rc = ecore_init_alloc(p_hwfn);
4247 DP_NOTICE(p_hwfn, false, "Failed to allocate the init array\n");
4248 if (p_params->b_relaxed_probe)
4249 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4253 if (CHIP_REV_IS_FPGA(p_dev)) {
4254 DP_NOTICE(p_hwfn, false,
4255 "FPGA: workaround; Prevent DMAE parities\n");
4256 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
4259 DP_NOTICE(p_hwfn, false,
4260 "FPGA: workaround: Set VF bar0 size\n");
4261 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4262 PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
4268 if (IS_LEAD_HWFN(p_hwfn))
4269 ecore_iov_free_hw_info(p_dev);
4270 ecore_mcp_free(p_hwfn);
4272 ecore_hw_hwfn_free(p_hwfn);
4277 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
4278 struct ecore_hw_prepare_params *p_params)
4280 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4281 enum _ecore_status_t rc;
4283 p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
4284 p_dev->allow_mdump = p_params->allow_mdump;
4285 p_hwfn->b_en_pacing = p_params->b_en_pacing;
4287 if (p_params->b_relaxed_probe)
4288 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
4290 /* Store the precompiled init data ptrs */
4292 ecore_init_iro_array(p_dev);
4294 /* Initialize the first hwfn - will learn number of hwfns */
4295 rc = ecore_hw_prepare_single(p_hwfn,
4297 p_dev->doorbells, p_params);
4298 if (rc != ECORE_SUCCESS)
4301 p_params->personality = p_hwfn->hw_info.personality;
4303 /* initilalize 2nd hwfn if necessary */
4304 if (ECORE_IS_CMT(p_dev)) {
4305 void OSAL_IOMEM *p_regview, *p_doorbell;
4306 u8 OSAL_IOMEM *addr;
4308 /* adjust bar offset for second engine */
4309 addr = (u8 OSAL_IOMEM *)p_dev->regview +
4310 ecore_hw_bar_size(p_hwfn,
4313 p_regview = (void OSAL_IOMEM *)addr;
4315 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
4316 ecore_hw_bar_size(p_hwfn,
4319 p_doorbell = (void OSAL_IOMEM *)addr;
4321 p_dev->hwfns[1].b_en_pacing = p_params->b_en_pacing;
4322 /* prepare second hw function */
4323 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
4324 p_doorbell, p_params);
4326 /* in case of error, need to free the previously
4327 * initiliazed hwfn 0.
4329 if (rc != ECORE_SUCCESS) {
4330 if (p_params->b_relaxed_probe)
4331 p_params->p_relaxed_res =
4332 ECORE_HW_PREPARE_FAILED_ENG2;
4335 ecore_init_free(p_hwfn);
4336 ecore_mcp_free(p_hwfn);
4337 ecore_hw_hwfn_free(p_hwfn);
4339 DP_NOTICE(p_dev, false, "What do we need to free when VF hwfn1 init fails\n");
4348 void ecore_hw_remove(struct ecore_dev *p_dev)
4350 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4354 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4355 ECORE_OV_DRIVER_STATE_NOT_LOADED);
4357 for_each_hwfn(p_dev, i) {
4358 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4361 ecore_vf_pf_release(p_hwfn);
4365 ecore_init_free(p_hwfn);
4366 ecore_hw_hwfn_free(p_hwfn);
4367 ecore_mcp_free(p_hwfn);
4369 #ifdef CONFIG_ECORE_LOCK_ALLOC
4370 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
4374 ecore_iov_free_hw_info(p_dev);
4377 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
4378 struct ecore_chain *p_chain)
4380 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
4381 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
4382 struct ecore_chain_next *p_next;
4388 size = p_chain->elem_size * p_chain->usable_per_page;
4390 for (i = 0; i < p_chain->page_cnt; i++) {
4394 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
4395 p_virt_next = p_next->next_virt;
4396 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
4398 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
4399 ECORE_CHAIN_PAGE_SIZE);
4401 p_virt = p_virt_next;
4402 p_phys = p_phys_next;
4406 static void ecore_chain_free_single(struct ecore_dev *p_dev,
4407 struct ecore_chain *p_chain)
4409 if (!p_chain->p_virt_addr)
4412 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
4413 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
4416 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
4417 struct ecore_chain *p_chain)
4419 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
4420 u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
4421 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
4423 if (!pp_virt_addr_tbl)
4429 for (i = 0; i < page_cnt; i++) {
4430 if (!pp_virt_addr_tbl[i])
4433 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
4434 *(dma_addr_t *)p_pbl_virt,
4435 ECORE_CHAIN_PAGE_SIZE);
4437 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4440 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4442 if (!p_chain->b_external_pbl)
4443 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
4444 p_chain->pbl_sp.p_phys_table, pbl_size);
4446 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
4449 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4451 switch (p_chain->mode) {
4452 case ECORE_CHAIN_MODE_NEXT_PTR:
4453 ecore_chain_free_next_ptr(p_dev, p_chain);
4455 case ECORE_CHAIN_MODE_SINGLE:
4456 ecore_chain_free_single(p_dev, p_chain);
4458 case ECORE_CHAIN_MODE_PBL:
4459 ecore_chain_free_pbl(p_dev, p_chain);
4464 static enum _ecore_status_t
4465 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
4466 enum ecore_chain_cnt_type cnt_type,
4467 osal_size_t elem_size, u32 page_cnt)
4469 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
4471 /* The actual chain size can be larger than the maximal possible value
4472 * after rounding up the requested elements number to pages, and after
4473 * taking into acount the unusuable elements (next-ptr elements).
4474 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
4475 * size/capacity fields are of a u32 type.
4477 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
4478 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
4479 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
4480 chain_size > ECORE_U32_MAX)) {
4481 DP_NOTICE(p_dev, true,
4482 "The actual chain size (0x%lx) is larger than the maximal possible value\n",
4483 (unsigned long)chain_size);
4487 return ECORE_SUCCESS;
4490 static enum _ecore_status_t
4491 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4493 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
4494 dma_addr_t p_phys = 0;
4497 for (i = 0; i < p_chain->page_cnt; i++) {
4498 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4499 ECORE_CHAIN_PAGE_SIZE);
4501 DP_NOTICE(p_dev, false,
4502 "Failed to allocate chain memory\n");
4507 ecore_chain_init_mem(p_chain, p_virt, p_phys);
4508 ecore_chain_reset(p_chain);
4510 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4514 p_virt_prev = p_virt;
4516 /* Last page's next element should point to the beginning of the
4519 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4520 p_chain->p_virt_addr,
4521 p_chain->p_phys_addr);
4523 return ECORE_SUCCESS;
4526 static enum _ecore_status_t
4527 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4529 dma_addr_t p_phys = 0;
4530 void *p_virt = OSAL_NULL;
4532 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
4534 DP_NOTICE(p_dev, false, "Failed to allocate chain memory\n");
4538 ecore_chain_init_mem(p_chain, p_virt, p_phys);
4539 ecore_chain_reset(p_chain);
4541 return ECORE_SUCCESS;
4544 static enum _ecore_status_t
4545 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
4546 struct ecore_chain *p_chain,
4547 struct ecore_chain_ext_pbl *ext_pbl)
4549 u32 page_cnt = p_chain->page_cnt, size, i;
4550 dma_addr_t p_phys = 0, p_pbl_phys = 0;
4551 void **pp_virt_addr_tbl = OSAL_NULL;
4552 u8 *p_pbl_virt = OSAL_NULL;
4553 void *p_virt = OSAL_NULL;
4555 size = page_cnt * sizeof(*pp_virt_addr_tbl);
4556 pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
4557 if (!pp_virt_addr_tbl) {
4558 DP_NOTICE(p_dev, false,
4559 "Failed to allocate memory for the chain virtual addresses table\n");
4563 /* The allocation of the PBL table is done with its full size, since it
4564 * is expected to be successive.
4565 * ecore_chain_init_pbl_mem() is called even in a case of an allocation
4566 * failure, since pp_virt_addr_tbl was previously allocated, and it
4567 * should be saved to allow its freeing during the error flow.
4569 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4571 if (ext_pbl == OSAL_NULL) {
4572 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
4574 p_pbl_virt = ext_pbl->p_pbl_virt;
4575 p_pbl_phys = ext_pbl->p_pbl_phys;
4576 p_chain->b_external_pbl = true;
4579 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
4582 DP_NOTICE(p_dev, false, "Failed to allocate chain pbl memory\n");
4586 for (i = 0; i < page_cnt; i++) {
4587 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4588 ECORE_CHAIN_PAGE_SIZE);
4590 DP_NOTICE(p_dev, false,
4591 "Failed to allocate chain memory\n");
4596 ecore_chain_init_mem(p_chain, p_virt, p_phys);
4597 ecore_chain_reset(p_chain);
4600 /* Fill the PBL table with the physical address of the page */
4601 *(dma_addr_t *)p_pbl_virt = p_phys;
4602 /* Keep the virtual address of the page */
4603 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
4605 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4608 return ECORE_SUCCESS;
4611 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
4612 enum ecore_chain_use_mode intended_use,
4613 enum ecore_chain_mode mode,
4614 enum ecore_chain_cnt_type cnt_type,
4615 u32 num_elems, osal_size_t elem_size,
4616 struct ecore_chain *p_chain,
4617 struct ecore_chain_ext_pbl *ext_pbl)
4620 enum _ecore_status_t rc = ECORE_SUCCESS;
4622 if (mode == ECORE_CHAIN_MODE_SINGLE)
4625 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4627 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
4630 DP_NOTICE(p_dev, false,
4631 "Cannot allocate a chain with the given arguments:\n"
4632 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4633 intended_use, mode, cnt_type, num_elems, elem_size);
4637 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
4638 mode, cnt_type, p_dev->dp_ctx);
4641 case ECORE_CHAIN_MODE_NEXT_PTR:
4642 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
4644 case ECORE_CHAIN_MODE_SINGLE:
4645 rc = ecore_chain_alloc_single(p_dev, p_chain);
4647 case ECORE_CHAIN_MODE_PBL:
4648 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
4654 return ECORE_SUCCESS;
4657 ecore_chain_free(p_dev, p_chain);
4661 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
4662 u16 src_id, u16 *dst_id)
4664 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
4667 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
4668 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
4669 DP_NOTICE(p_hwfn, true,
4670 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4676 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
4678 return ECORE_SUCCESS;
4681 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
4682 u8 src_id, u8 *dst_id)
4684 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
4687 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
4688 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
4689 DP_NOTICE(p_hwfn, true,
4690 "vport id [%d] is not valid, available indices [%d - %d]\n",
4696 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
4698 return ECORE_SUCCESS;
4701 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
4702 u8 src_id, u8 *dst_id)
4704 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
4707 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
4708 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
4709 DP_NOTICE(p_hwfn, true,
4710 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4716 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
4718 return ECORE_SUCCESS;
4721 static enum _ecore_status_t
4722 ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4723 struct ecore_ptt *p_ptt, u32 high, u32 low,
4729 /* Find a free entry and utilize it */
4730 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4731 en = ecore_rd(p_hwfn, p_ptt,
4732 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4736 ecore_wr(p_hwfn, p_ptt,
4737 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4738 2 * i * sizeof(u32), low);
4739 ecore_wr(p_hwfn, p_ptt,
4740 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4741 (2 * i + 1) * sizeof(u32), high);
4742 ecore_wr(p_hwfn, p_ptt,
4743 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4744 i * sizeof(u32), 0);
4745 ecore_wr(p_hwfn, p_ptt,
4746 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4747 i * sizeof(u32), 0);
4748 ecore_wr(p_hwfn, p_ptt,
4749 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4750 i * sizeof(u32), 1);
4754 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4755 return ECORE_NORESOURCES;
4759 return ECORE_SUCCESS;
4762 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4763 struct ecore_ptt *p_ptt, u8 *p_filter)
4765 u32 high, low, entry_num;
4766 enum _ecore_status_t rc = ECORE_SUCCESS;
4768 if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4769 &p_hwfn->p_dev->mf_bits))
4770 return ECORE_SUCCESS;
4772 high = p_filter[1] | (p_filter[0] << 8);
4773 low = p_filter[5] | (p_filter[4] << 8) |
4774 (p_filter[3] << 16) | (p_filter[2] << 24);
4776 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4777 rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low,
4779 if (rc != ECORE_SUCCESS) {
4780 DP_NOTICE(p_hwfn, false,
4781 "Failed to find an empty LLH filter to utilize\n");
4785 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4786 "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n",
4787 p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4788 p_filter[4], p_filter[5], entry_num);
4793 static enum _ecore_status_t
4794 ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4795 struct ecore_ptt *p_ptt, u32 high, u32 low,
4800 /* Find the entry and clean it */
4801 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4802 if (ecore_rd(p_hwfn, p_ptt,
4803 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4804 2 * i * sizeof(u32)) != low)
4806 if (ecore_rd(p_hwfn, p_ptt,
4807 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4808 (2 * i + 1) * sizeof(u32)) != high)
4811 ecore_wr(p_hwfn, p_ptt,
4812 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4813 ecore_wr(p_hwfn, p_ptt,
4814 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4815 2 * i * sizeof(u32), 0);
4816 ecore_wr(p_hwfn, p_ptt,
4817 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4818 (2 * i + 1) * sizeof(u32), 0);
4822 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4827 return ECORE_SUCCESS;
4830 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4831 struct ecore_ptt *p_ptt, u8 *p_filter)
4833 u32 high, low, entry_num;
4834 enum _ecore_status_t rc = ECORE_SUCCESS;
4836 if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4837 &p_hwfn->p_dev->mf_bits))
4840 high = p_filter[1] | (p_filter[0] << 8);
4841 low = p_filter[5] | (p_filter[4] << 8) |
4842 (p_filter[3] << 16) | (p_filter[2] << 24);
4844 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4845 rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high,
4847 if (rc != ECORE_SUCCESS) {
4848 DP_NOTICE(p_hwfn, false,
4849 "Tried to remove a non-configured filter\n");
4854 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4855 "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n",
4856 p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4857 p_filter[4], p_filter[5], entry_num);
4860 static enum _ecore_status_t
4861 ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4862 struct ecore_ptt *p_ptt,
4863 enum ecore_llh_port_filter_type_t type,
4864 u32 high, u32 low, u32 *p_entry_num)
4869 /* Find a free entry and utilize it */
4870 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4871 en = ecore_rd(p_hwfn, p_ptt,
4872 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4876 ecore_wr(p_hwfn, p_ptt,
4877 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4878 2 * i * sizeof(u32), low);
4879 ecore_wr(p_hwfn, p_ptt,
4880 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4881 (2 * i + 1) * sizeof(u32), high);
4882 ecore_wr(p_hwfn, p_ptt,
4883 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4884 i * sizeof(u32), 1);
4885 ecore_wr(p_hwfn, p_ptt,
4886 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4887 i * sizeof(u32), 1 << type);
4888 ecore_wr(p_hwfn, p_ptt,
4889 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1);
4893 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4894 return ECORE_NORESOURCES;
4898 return ECORE_SUCCESS;
4901 enum _ecore_status_t
4902 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4903 struct ecore_ptt *p_ptt,
4904 u16 source_port_or_eth_type,
4906 enum ecore_llh_port_filter_type_t type)
4908 u32 high, low, entry_num;
4909 enum _ecore_status_t rc = ECORE_SUCCESS;
4911 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
4912 &p_hwfn->p_dev->mf_bits))
4919 case ECORE_LLH_FILTER_ETHERTYPE:
4920 high = source_port_or_eth_type;
4922 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4923 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4924 low = source_port_or_eth_type << 16;
4926 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4927 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4930 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4931 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4932 low = (source_port_or_eth_type << 16) | dest_port;
4935 DP_NOTICE(p_hwfn, true,
4936 "Non valid LLH protocol filter type %d\n", type);
4940 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4941 rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4942 high, low, &entry_num);
4943 if (rc != ECORE_SUCCESS) {
4944 DP_NOTICE(p_hwfn, false,
4945 "Failed to find an empty LLH filter to utilize\n");
4949 case ECORE_LLH_FILTER_ETHERTYPE:
4950 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4951 "ETH type %x is added at %d\n",
4952 source_port_or_eth_type, entry_num);
4954 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4955 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4956 "TCP src port %x is added at %d\n",
4957 source_port_or_eth_type, entry_num);
4959 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4960 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4961 "UDP src port %x is added at %d\n",
4962 source_port_or_eth_type, entry_num);
4964 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4965 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4966 "TCP dst port %x is added at %d\n", dest_port,
4969 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4970 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4971 "UDP dst port %x is added at %d\n", dest_port,
4974 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4975 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4976 "TCP src/dst ports %x/%x are added at %d\n",
4977 source_port_or_eth_type, dest_port, entry_num);
4979 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4980 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4981 "UDP src/dst ports %x/%x are added at %d\n",
4982 source_port_or_eth_type, dest_port, entry_num);
4989 static enum _ecore_status_t
4990 ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4991 struct ecore_ptt *p_ptt,
4992 enum ecore_llh_port_filter_type_t type,
4993 u32 high, u32 low, u32 *p_entry_num)
4997 /* Find the entry and clean it */
4998 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4999 if (!ecore_rd(p_hwfn, p_ptt,
5000 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
5003 if (!ecore_rd(p_hwfn, p_ptt,
5004 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
5007 if (!(ecore_rd(p_hwfn, p_ptt,
5008 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
5009 i * sizeof(u32)) & (1 << type)))
5011 if (ecore_rd(p_hwfn, p_ptt,
5012 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5013 2 * i * sizeof(u32)) != low)
5015 if (ecore_rd(p_hwfn, p_ptt,
5016 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5017 (2 * i + 1) * sizeof(u32)) != high)
5020 ecore_wr(p_hwfn, p_ptt,
5021 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
5022 ecore_wr(p_hwfn, p_ptt,
5023 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
5024 i * sizeof(u32), 0);
5025 ecore_wr(p_hwfn, p_ptt,
5026 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
5027 i * sizeof(u32), 0);
5028 ecore_wr(p_hwfn, p_ptt,
5029 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5030 2 * i * sizeof(u32), 0);
5031 ecore_wr(p_hwfn, p_ptt,
5032 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5033 (2 * i + 1) * sizeof(u32), 0);
5037 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
5042 return ECORE_SUCCESS;
5046 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
5047 struct ecore_ptt *p_ptt,
5048 u16 source_port_or_eth_type,
5050 enum ecore_llh_port_filter_type_t type)
5052 u32 high, low, entry_num;
5053 enum _ecore_status_t rc = ECORE_SUCCESS;
5055 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
5056 &p_hwfn->p_dev->mf_bits))
5063 case ECORE_LLH_FILTER_ETHERTYPE:
5064 high = source_port_or_eth_type;
5066 case ECORE_LLH_FILTER_TCP_SRC_PORT:
5067 case ECORE_LLH_FILTER_UDP_SRC_PORT:
5068 low = source_port_or_eth_type << 16;
5070 case ECORE_LLH_FILTER_TCP_DEST_PORT:
5071 case ECORE_LLH_FILTER_UDP_DEST_PORT:
5074 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
5075 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
5076 low = (source_port_or_eth_type << 16) | dest_port;
5079 DP_NOTICE(p_hwfn, true,
5080 "Non valid LLH protocol filter type %d\n", type);
5084 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5085 rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
5088 if (rc != ECORE_SUCCESS) {
5089 DP_NOTICE(p_hwfn, false,
5090 "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n",
5091 type, source_port_or_eth_type, dest_port);
5095 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5096 "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n",
5097 type, source_port_or_eth_type, dest_port, entry_num);
5100 static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn,
5101 struct ecore_ptt *p_ptt)
5105 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
5108 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
5109 ecore_wr(p_hwfn, p_ptt,
5110 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
5111 i * sizeof(u32), 0);
5112 ecore_wr(p_hwfn, p_ptt,
5113 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5114 2 * i * sizeof(u32), 0);
5115 ecore_wr(p_hwfn, p_ptt,
5116 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5117 (2 * i + 1) * sizeof(u32), 0);
5121 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
5122 struct ecore_ptt *p_ptt)
5124 if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
5125 &p_hwfn->p_dev->mf_bits) &&
5126 !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
5127 &p_hwfn->p_dev->mf_bits))
5130 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5131 ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt);
5134 enum _ecore_status_t
5135 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
5136 struct ecore_ptt *p_ptt)
5138 if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
5139 ecore_wr(p_hwfn, p_ptt,
5140 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
5141 1 << p_hwfn->abs_pf_id / 2);
5142 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
5143 return ECORE_SUCCESS;
5146 DP_NOTICE(p_hwfn, false,
5147 "This function can't be set as default\n");
5151 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
5152 struct ecore_ptt *p_ptt,
5153 u32 hw_addr, void *p_eth_qzone,
5154 osal_size_t eth_qzone_size,
5157 struct coalescing_timeset *p_coal_timeset;
5159 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
5160 DP_NOTICE(p_hwfn, true,
5161 "Coalescing configuration not enabled\n");
5165 p_coal_timeset = p_eth_qzone;
5166 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
5167 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
5168 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
5169 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
5171 return ECORE_SUCCESS;
5174 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
5175 u16 rx_coal, u16 tx_coal,
5178 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
5179 enum _ecore_status_t rc = ECORE_SUCCESS;
5180 struct ecore_ptt *p_ptt;
5182 /* TODO - Configuring a single queue's coalescing but
5183 * claiming all queues are abiding same configuration
5184 * for PF and VF both.
5187 if (IS_VF(p_hwfn->p_dev))
5188 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
5191 p_ptt = ecore_ptt_acquire(p_hwfn);
5196 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
5199 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
5203 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
5206 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
5209 ecore_ptt_release(p_hwfn, p_ptt);
5214 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
5215 struct ecore_ptt *p_ptt,
5217 struct ecore_queue_cid *p_cid)
5219 struct ustorm_eth_queue_zone eth_qzone;
5220 u8 timeset, timer_res;
5222 enum _ecore_status_t rc;
5224 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5225 if (coalesce <= 0x7F) {
5227 } else if (coalesce <= 0xFF) {
5229 } else if (coalesce <= 0x1FF) {
5232 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5235 timeset = (u8)(coalesce >> timer_res);
5237 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5238 p_cid->sb_igu_id, false);
5239 if (rc != ECORE_SUCCESS)
5242 address = BAR0_MAP_REG_USDM_RAM +
5243 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5245 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
5246 sizeof(struct ustorm_eth_queue_zone), timeset);
5247 if (rc != ECORE_SUCCESS)
5254 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
5255 struct ecore_ptt *p_ptt,
5257 struct ecore_queue_cid *p_cid)
5259 struct xstorm_eth_queue_zone eth_qzone;
5260 u8 timeset, timer_res;
5262 enum _ecore_status_t rc;
5264 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5265 if (coalesce <= 0x7F) {
5267 } else if (coalesce <= 0xFF) {
5269 } else if (coalesce <= 0x1FF) {
5272 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5276 timeset = (u8)(coalesce >> timer_res);
5278 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5279 p_cid->sb_igu_id, true);
5280 if (rc != ECORE_SUCCESS)
5283 address = BAR0_MAP_REG_XSDM_RAM +
5284 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5286 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
5287 sizeof(struct xstorm_eth_queue_zone), timeset);
5292 /* Calculate final WFQ values for all vports and configure it.
5293 * After this configuration each vport must have
5294 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
5296 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5297 struct ecore_ptt *p_ptt,
5300 struct init_qm_vport_params *vport_params;
5303 vport_params = p_hwfn->qm_info.qm_vport_params;
5305 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5306 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5308 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
5310 ecore_init_vport_wfq(p_hwfn, p_ptt,
5311 vport_params[i].first_tx_pq_id,
5312 vport_params[i].vport_wfq);
5316 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn)
5320 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5321 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
5324 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5325 struct ecore_ptt *p_ptt)
5327 struct init_qm_vport_params *vport_params;
5330 vport_params = p_hwfn->qm_info.qm_vport_params;
5332 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5333 ecore_init_wfq_default_param(p_hwfn);
5334 ecore_init_vport_wfq(p_hwfn, p_ptt,
5335 vport_params[i].first_tx_pq_id,
5336 vport_params[i].vport_wfq);
5340 /* This function performs several validations for WFQ
5341 * configuration and required min rate for a given vport
5342 * 1. req_rate must be greater than one percent of min_pf_rate.
5343 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
5344 * rates to get less than one percent of min_pf_rate.
5345 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
5347 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
5348 u16 vport_id, u32 req_rate,
5351 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
5352 int non_requested_count = 0, req_count = 0, i, num_vports;
5354 num_vports = p_hwfn->qm_info.num_vports;
5356 /* Accounting for the vports which are configured for WFQ explicitly */
5358 for (i = 0; i < num_vports; i++) {
5361 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
5363 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5364 total_req_min_rate += tmp_speed;
5368 /* Include current vport data as well */
5370 total_req_min_rate += req_rate;
5371 non_requested_count = num_vports - req_count;
5373 /* validate possible error cases */
5374 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
5375 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5376 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5377 vport_id, req_rate, min_pf_rate);
5381 /* TBD - for number of vports greater than 100 */
5382 if (num_vports > ECORE_WFQ_UNIT) {
5383 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5384 "Number of vports is greater than %d\n",
5389 if (total_req_min_rate > min_pf_rate) {
5390 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5391 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5392 total_req_min_rate, min_pf_rate);
5396 /* Data left for non requested vports */
5397 total_left_rate = min_pf_rate - total_req_min_rate;
5398 left_rate_per_vp = total_left_rate / non_requested_count;
5400 /* validate if non requested get < 1% of min bw */
5401 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
5402 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5403 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5404 left_rate_per_vp, min_pf_rate);
5408 /* now req_rate for given vport passes all scenarios.
5409 * assign final wfq rates to all vports.
5411 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5412 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5414 for (i = 0; i < num_vports; i++) {
5415 if (p_hwfn->qm_info.wfq_data[i].configured)
5418 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5421 return ECORE_SUCCESS;
5424 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
5425 struct ecore_ptt *p_ptt,
5426 u16 vp_id, u32 rate)
5428 struct ecore_mcp_link_state *p_link;
5429 int rc = ECORE_SUCCESS;
5431 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
5433 if (!p_link->min_pf_rate) {
5434 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5435 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5439 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5441 if (rc == ECORE_SUCCESS)
5442 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5443 p_link->min_pf_rate);
5445 DP_NOTICE(p_hwfn, false,
5446 "Validation failed while configuring min rate\n");
5451 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
5452 struct ecore_ptt *p_ptt,
5455 bool use_wfq = false;
5456 int rc = ECORE_SUCCESS;
5459 /* Validate all pre configured vports for wfq */
5460 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5463 if (!p_hwfn->qm_info.wfq_data[i].configured)
5466 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5469 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5470 if (rc != ECORE_SUCCESS) {
5471 DP_NOTICE(p_hwfn, false,
5472 "WFQ validation failed while configuring min rate\n");
5477 if (rc == ECORE_SUCCESS && use_wfq)
5478 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5480 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5485 /* Main API for ecore clients to configure vport min rate.
5486 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5487 * rate - Speed in Mbps needs to be assigned to a given vport.
5489 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
5491 int i, rc = ECORE_INVAL;
5493 /* TBD - for multiple hardware functions - that is 100 gig */
5494 if (ECORE_IS_CMT(p_dev)) {
5495 DP_NOTICE(p_dev, false,
5496 "WFQ configuration is not supported for this device\n");
5500 for_each_hwfn(p_dev, i) {
5501 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5502 struct ecore_ptt *p_ptt;
5504 p_ptt = ecore_ptt_acquire(p_hwfn);
5506 return ECORE_TIMEOUT;
5508 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5510 if (rc != ECORE_SUCCESS) {
5511 ecore_ptt_release(p_hwfn, p_ptt);
5515 ecore_ptt_release(p_hwfn, p_ptt);
5521 /* API to configure WFQ from mcp link change */
5522 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
5523 struct ecore_ptt *p_ptt,
5528 /* TBD - for multiple hardware functions - that is 100 gig */
5529 if (ECORE_IS_CMT(p_dev)) {
5530 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
5531 "WFQ configuration is not supported for this device\n");
5535 for_each_hwfn(p_dev, i) {
5536 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5538 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5543 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
5544 struct ecore_ptt *p_ptt,
5545 struct ecore_mcp_link_state *p_link,
5548 int rc = ECORE_SUCCESS;
5550 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5552 if (!p_link->line_speed && (max_bw != 100))
5555 p_link->speed = (p_link->line_speed * max_bw) / 100;
5556 p_hwfn->qm_info.pf_rl = p_link->speed;
5558 /* Since the limiter also affects Tx-switched traffic, we don't want it
5559 * to limit such traffic in case there's no actual limit.
5560 * In that case, set limit to imaginary high boundary.
5563 p_hwfn->qm_info.pf_rl = 100000;
5565 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5566 p_hwfn->qm_info.pf_rl);
5568 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5569 "Configured MAX bandwidth to be %08x Mb/sec\n",
5575 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5576 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
5578 int i, rc = ECORE_INVAL;
5580 if (max_bw < 1 || max_bw > 100) {
5581 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
5585 for_each_hwfn(p_dev, i) {
5586 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5587 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5588 struct ecore_mcp_link_state *p_link;
5589 struct ecore_ptt *p_ptt;
5591 p_link = &p_lead->mcp_info->link_output;
5593 p_ptt = ecore_ptt_acquire(p_hwfn);
5595 return ECORE_TIMEOUT;
5597 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5600 ecore_ptt_release(p_hwfn, p_ptt);
5602 if (rc != ECORE_SUCCESS)
5609 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
5610 struct ecore_ptt *p_ptt,
5611 struct ecore_mcp_link_state *p_link,
5614 int rc = ECORE_SUCCESS;
5616 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5617 p_hwfn->qm_info.pf_wfq = min_bw;
5619 if (!p_link->line_speed)
5622 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5624 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5626 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5627 "Configured MIN bandwidth to be %d Mb/sec\n",
5628 p_link->min_pf_rate);
5633 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5634 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
5636 int i, rc = ECORE_INVAL;
5638 if (min_bw < 1 || min_bw > 100) {
5639 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
5643 for_each_hwfn(p_dev, i) {
5644 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5645 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5646 struct ecore_mcp_link_state *p_link;
5647 struct ecore_ptt *p_ptt;
5649 p_link = &p_lead->mcp_info->link_output;
5651 p_ptt = ecore_ptt_acquire(p_hwfn);
5653 return ECORE_TIMEOUT;
5655 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5657 if (rc != ECORE_SUCCESS) {
5658 ecore_ptt_release(p_hwfn, p_ptt);
5662 if (p_link->min_pf_rate) {
5663 u32 min_rate = p_link->min_pf_rate;
5665 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
5670 ecore_ptt_release(p_hwfn, p_ptt);
5676 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
5678 struct ecore_mcp_link_state *p_link;
5680 p_link = &p_hwfn->mcp_info->link_output;
5682 if (p_link->min_pf_rate)
5683 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5685 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
5686 sizeof(*p_hwfn->qm_info.wfq_data) *
5687 p_hwfn->qm_info.num_vports);
5690 int ecore_device_num_engines(struct ecore_dev *p_dev)
5692 return ECORE_IS_BB(p_dev) ? 2 : 1;
5695 int ecore_device_num_ports(struct ecore_dev *p_dev)
5697 return p_dev->num_ports;
5700 void ecore_set_fw_mac_addr(__le16 *fw_msb,
5705 ((u8 *)fw_msb)[0] = mac[1];
5706 ((u8 *)fw_msb)[1] = mac[0];
5707 ((u8 *)fw_mid)[0] = mac[3];
5708 ((u8 *)fw_mid)[1] = mac[2];
5709 ((u8 *)fw_lsb)[0] = mac[5];
5710 ((u8 *)fw_lsb)[1] = mac[4];