2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_gtt_reg_addr.h"
13 #include "ecore_chain.h"
14 #include "ecore_status.h"
16 #include "ecore_rt_defs.h"
17 #include "ecore_init_ops.h"
18 #include "ecore_int.h"
19 #include "ecore_cxt.h"
20 #include "ecore_spq.h"
21 #include "ecore_init_fw_funcs.h"
22 #include "ecore_sp_commands.h"
23 #include "ecore_dev_api.h"
24 #include "ecore_sriov.h"
26 #include "ecore_mcp.h"
27 #include "ecore_hw_defs.h"
28 #include "mcp_public.h"
29 #include "ecore_iro.h"
31 #include "ecore_dev_api.h"
32 #include "ecore_dcbx.h"
34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
35 * registers involved are not split and thus configuration is a race where
36 * some of the PFs configuration might be lost.
37 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
38 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
39 * there's more than a single compiled ecore component in system].
41 static osal_spinlock_t qm_lock;
42 static bool qm_lock_init;
45 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to
46 * load the driver. The number was
51 #define ECORE_MIN_PWM_REGION ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
54 BAR_ID_0, /* used for GRC */
55 BAR_ID_1 /* Used for doorbells */
58 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
60 u32 bar_reg = (bar_id == BAR_ID_0 ?
61 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
64 if (IS_VF(p_hwfn->p_dev)) {
65 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
66 * read from actual register, but we're currently not using
67 * it for actual doorbelling.
72 val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
74 /* The above registers were updated in the past only in CMT mode. Since
75 * they were found to be useful MFW started updating them from 8.7.7.0.
76 * In older MFW versions they are set to 0 which means disabled.
79 if (p_hwfn->p_dev->num_hwfns > 1) {
80 DP_NOTICE(p_hwfn, false,
81 "BAR size not configured. Assuming BAR size");
82 DP_NOTICE(p_hwfn, false,
83 "of 256kB for GRC and 512kB for DB\n");
84 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
86 DP_NOTICE(p_hwfn, false,
87 "BAR size not configured. Assuming BAR size");
88 DP_NOTICE(p_hwfn, false,
89 "of 512kB for GRC and 512kB for DB\n");
94 return 1 << (val + 15);
97 void ecore_init_dp(struct ecore_dev *p_dev,
98 u32 dp_module, u8 dp_level, void *dp_ctx)
102 p_dev->dp_level = dp_level;
103 p_dev->dp_module = dp_module;
104 p_dev->dp_ctx = dp_ctx;
105 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
106 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
108 p_hwfn->dp_level = dp_level;
109 p_hwfn->dp_module = dp_module;
110 p_hwfn->dp_ctx = dp_ctx;
114 void ecore_init_struct(struct ecore_dev *p_dev)
118 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
119 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
121 p_hwfn->p_dev = p_dev;
123 p_hwfn->b_active = false;
125 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
126 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
129 /* hwfn 0 is always active */
130 p_dev->hwfns[0].b_active = true;
132 /* set the default cache alignment to 128 (may be overridden later) */
133 p_dev->cache_shift = 7;
136 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
138 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
140 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
141 qm_info->qm_pq_params = OSAL_NULL;
142 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
143 qm_info->qm_vport_params = OSAL_NULL;
144 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
145 qm_info->qm_port_params = OSAL_NULL;
146 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
147 qm_info->wfq_data = OSAL_NULL;
150 void ecore_resc_free(struct ecore_dev *p_dev)
157 OSAL_FREE(p_dev, p_dev->fw_data);
158 p_dev->fw_data = OSAL_NULL;
160 OSAL_FREE(p_dev, p_dev->reset_stats);
162 for_each_hwfn(p_dev, i) {
163 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
165 OSAL_FREE(p_dev, p_hwfn->p_tx_cids);
166 p_hwfn->p_tx_cids = OSAL_NULL;
167 OSAL_FREE(p_dev, p_hwfn->p_rx_cids);
168 p_hwfn->p_rx_cids = OSAL_NULL;
171 for_each_hwfn(p_dev, i) {
172 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
174 ecore_cxt_mngr_free(p_hwfn);
175 ecore_qm_info_free(p_hwfn);
176 ecore_spq_free(p_hwfn);
177 ecore_eq_free(p_hwfn, p_hwfn->p_eq);
178 ecore_consq_free(p_hwfn, p_hwfn->p_consq);
179 ecore_int_free(p_hwfn);
180 #ifdef CONFIG_ECORE_LL2
181 ecore_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
183 ecore_iov_free(p_hwfn);
184 ecore_dmae_info_free(p_hwfn);
185 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
186 /* @@@TBD Flush work-queue ? */
190 static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn,
193 u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue;
194 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
195 struct init_qm_port_params *p_qm_port;
196 bool init_rdma_offload_pq = false;
197 bool init_pure_ack_pq = false;
198 bool init_ooo_pq = false;
199 u16 num_pqs, protocol_pqs;
205 /* @TMP - saving the existing min/max bw config before resetting the
206 * qm_info to restore them.
208 pf_rl = qm_info->pf_rl;
209 pf_wfq = qm_info->pf_wfq;
211 #ifdef CONFIG_ECORE_SRIOV
212 if (p_hwfn->p_dev->p_iov_info)
213 num_vfs = p_hwfn->p_dev->p_iov_info->total_vfs;
215 OSAL_MEM_ZERO(qm_info, sizeof(*qm_info));
218 /* @TMP - Don't allocate QM queues for VFs on emulation */
219 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
220 DP_NOTICE(p_hwfn, false,
221 "Emulation - skip configuring QM queues for VFs\n");
226 /* ethernet PFs require a pq per tc. Even if only a subset of the TCs
227 * active, we want physical queues allocated for all of them, since we
228 * don't have a good recycle flow. Non ethernet PFs require only a
229 * single physical queue.
231 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE ||
232 p_hwfn->hw_info.personality == ECORE_PCI_IWARP ||
233 p_hwfn->hw_info.personality == ECORE_PCI_ETH)
234 protocol_pqs = p_hwfn->hw_info.num_hw_tc;
238 num_pqs = protocol_pqs + num_vfs + 1; /* The '1' is for pure-LB */
239 num_vports = (u8)RESC_NUM(p_hwfn, ECORE_VPORT);
241 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
242 num_pqs++; /* for RoCE queue */
243 init_rdma_offload_pq = true;
244 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn) {
245 /* Due to FW assumption that rl==vport, we limit the
246 * number of rate limiters by the minimum between its
247 * allocated number and the allocated number of vports.
248 * Another limitation is the number of supported qps
249 * with rate limiters in FW.
252 (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
253 RESC_NUM(p_hwfn, ECORE_VPORT));
255 /* we subtract num_vfs because each one requires a rate
256 * limiter, and one default rate limiter.
258 if (num_pf_rls < num_vfs + 1) {
259 DP_ERR(p_hwfn, "No RL for DCQCN");
260 DP_ERR(p_hwfn, "[num_pf_rls %d num_vfs %d]\n",
261 num_pf_rls, num_vfs);
264 num_pf_rls -= num_vfs + 1;
267 num_pqs += num_pf_rls;
268 qm_info->num_pf_rls = (u8)num_pf_rls;
271 if (p_hwfn->hw_info.personality == ECORE_PCI_IWARP) {
272 num_pqs += 3; /* for iwarp queue / pure-ack / ooo */
273 init_rdma_offload_pq = true;
274 init_pure_ack_pq = true;
278 if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
279 num_pqs += 2; /* for iSCSI pure-ACK / OOO queue */
280 init_pure_ack_pq = true;
284 /* Sanity checking that setup requires legal number of resources */
285 if (num_pqs > RESC_NUM(p_hwfn, ECORE_PQ)) {
287 "Need too many Physical queues - 0x%04x avail %04x",
288 num_pqs, RESC_NUM(p_hwfn, ECORE_PQ));
292 /* PQs will be arranged as follows: First per-TC PQ, then pure-LB queue,
293 * then special queues (iSCSI pure-ACK / RoCE), then per-VF PQ.
295 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev,
296 b_sleepable ? GFP_KERNEL :
298 sizeof(struct init_qm_pq_params) *
300 if (!qm_info->qm_pq_params)
303 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev,
304 b_sleepable ? GFP_KERNEL :
307 init_qm_vport_params) *
309 if (!qm_info->qm_vport_params)
312 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev,
313 b_sleepable ? GFP_KERNEL :
315 sizeof(struct init_qm_port_params)
317 if (!qm_info->qm_port_params)
320 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev,
321 b_sleepable ? GFP_KERNEL :
323 sizeof(struct ecore_wfq_data) *
326 if (!qm_info->wfq_data)
329 vport_id = (u8)RESC_START(p_hwfn, ECORE_VPORT);
331 /* First init rate limited queues ( Due to RoCE assumption of
334 for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
335 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
336 qm_info->qm_pq_params[curr_queue].tc_id =
337 p_hwfn->hw_info.offload_tc;
338 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
339 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
343 for (i = 0; i < protocol_pqs; i++) {
344 struct init_qm_pq_params *params =
345 &qm_info->qm_pq_params[curr_queue++];
347 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE ||
348 p_hwfn->hw_info.personality == ECORE_PCI_IWARP ||
349 p_hwfn->hw_info.personality == ECORE_PCI_ETH) {
350 params->vport_id = vport_id;
352 /* Note: this assumes that if we had a configuration
353 * with N tcs and subsequently another configuration
354 * With Fewer TCs, the in flight traffic (in QM queues,
355 * in FW, from driver to FW) will still trickle out and
356 * not get "stuck" in the QM. This is determined by the
357 * NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ. Unused TCs are
358 * supposed to be cleared in this map, allowing traffic
359 * to flush out. If this is not the case, we would need
360 * to set the TC of unused queues to 0, and reconfigure
361 * QM every time num of TCs changes. Unused queues in
362 * this context would mean those intended for TCs where
363 * tc_id > hw_info.num_active_tcs.
365 params->wrr_group = 1; /* @@@TBD ECORE_WRR_MEDIUM */
367 params->vport_id = vport_id;
368 params->tc_id = p_hwfn->hw_info.offload_tc;
369 params->wrr_group = 1; /* @@@TBD ECORE_WRR_MEDIUM */
373 /* Then init pure-LB PQ */
374 qm_info->pure_lb_pq = curr_queue;
375 qm_info->qm_pq_params[curr_queue].vport_id =
376 (u8)RESC_START(p_hwfn, ECORE_VPORT);
377 qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
378 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
381 qm_info->offload_pq = 0; /* Already initialized for iSCSI/FCoE */
382 if (init_rdma_offload_pq) {
383 qm_info->offload_pq = curr_queue;
384 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
385 qm_info->qm_pq_params[curr_queue].tc_id =
386 p_hwfn->hw_info.offload_tc;
387 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
391 if (init_pure_ack_pq) {
392 qm_info->pure_ack_pq = curr_queue;
393 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
394 qm_info->qm_pq_params[curr_queue].tc_id =
395 p_hwfn->hw_info.offload_tc;
396 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
401 qm_info->ooo_pq = curr_queue;
402 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
403 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
404 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
408 /* Then init per-VF PQs */
409 vf_offset = curr_queue;
410 for (i = 0; i < num_vfs; i++) {
411 /* First vport is used by the PF */
412 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
413 /* @@@TBD VF Multi-cos */
414 qm_info->qm_pq_params[curr_queue].tc_id = 0;
415 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
416 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
420 qm_info->vf_queues_offset = vf_offset;
421 qm_info->num_pqs = num_pqs;
422 qm_info->num_vports = num_vports;
424 /* Initialize qm port parameters */
425 num_ports = p_hwfn->p_dev->num_ports_in_engines;
426 for (i = 0; i < num_ports; i++) {
427 p_qm_port = &qm_info->qm_port_params[i];
428 p_qm_port->active = 1;
429 /* @@@TMP - was NUM_OF_PHYS_TCS; Changed until dcbx will
433 p_qm_port->active_phys_tcs = 0xf;
435 p_qm_port->active_phys_tcs = 0x9f;
436 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
437 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
440 if (ECORE_IS_AH(p_hwfn->p_dev) && (num_ports == 4))
441 qm_info->max_phys_tcs_per_port = NUM_PHYS_TCS_4PORT_K2;
443 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
445 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
447 qm_info->num_vf_pqs = num_vfs;
448 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
450 for (i = 0; i < qm_info->num_vports; i++)
451 qm_info->qm_vport_params[i].vport_wfq = 1;
453 qm_info->vport_rl_en = 1;
454 qm_info->vport_wfq_en = 1;
455 qm_info->pf_rl = pf_rl;
456 qm_info->pf_wfq = pf_wfq;
458 return ECORE_SUCCESS;
461 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
462 ecore_qm_info_free(p_hwfn);
466 /* This function reconfigures the QM pf on the fly.
467 * For this purpose we:
468 * 1. reconfigure the QM database
469 * 2. set new values to runtime arrat
470 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
471 * 4. activate init tool in QM_PF stage
472 * 5. send an sdm_qm_cmd through rbc interface to release the QM
474 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
475 struct ecore_ptt *p_ptt)
477 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
479 enum _ecore_status_t rc;
481 /* qm_info is allocated in ecore_init_qm_info() which is already called
482 * from ecore_resc_alloc() or previous call of ecore_qm_reconf().
483 * The allocated size may change each init, so we free it before next
486 ecore_qm_info_free(p_hwfn);
488 /* initialize ecore's qm data structure */
489 rc = ecore_init_qm_info(p_hwfn, false);
490 if (rc != ECORE_SUCCESS)
493 /* stop PF's qm queues */
494 OSAL_SPIN_LOCK(&qm_lock);
495 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
496 qm_info->start_pq, qm_info->num_pqs);
497 OSAL_SPIN_UNLOCK(&qm_lock);
501 /* clear the QM_PF runtime phase leftovers from previous init */
502 ecore_init_clear_rt_data(p_hwfn);
504 /* prepare QM portion of runtime array */
505 ecore_qm_init_pf(p_hwfn);
507 /* activate init tool on runtime array */
508 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
509 p_hwfn->hw_info.hw_mode);
510 if (rc != ECORE_SUCCESS)
513 /* start PF's qm queues */
514 OSAL_SPIN_LOCK(&qm_lock);
515 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
516 qm_info->start_pq, qm_info->num_pqs);
517 OSAL_SPIN_UNLOCK(&qm_lock);
521 return ECORE_SUCCESS;
524 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
526 struct ecore_consq *p_consq;
527 struct ecore_eq *p_eq;
528 #ifdef CONFIG_ECORE_LL2
529 struct ecore_ll2_info *p_ll2_info;
531 enum _ecore_status_t rc = ECORE_SUCCESS;
537 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
538 sizeof(*p_dev->fw_data));
542 /* Allocate Memory for the Queue->CID mapping */
543 for_each_hwfn(p_dev, i) {
544 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
545 u32 num_tx_conns = RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
546 int tx_size, rx_size;
548 /* @@@TMP - resc management, change to actual required size */
549 if (p_hwfn->pf_params.eth_pf_params.num_cons > num_tx_conns)
550 num_tx_conns = p_hwfn->pf_params.eth_pf_params.num_cons;
551 tx_size = sizeof(struct ecore_hw_cid_data) * num_tx_conns;
552 rx_size = sizeof(struct ecore_hw_cid_data) *
553 RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
555 p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
557 if (!p_hwfn->p_tx_cids) {
558 DP_NOTICE(p_hwfn, true,
559 "Failed to allocate memory for Tx Cids\n");
563 p_hwfn->p_rx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
565 if (!p_hwfn->p_rx_cids) {
566 DP_NOTICE(p_hwfn, true,
567 "Failed to allocate memory for Rx Cids\n");
572 for_each_hwfn(p_dev, i) {
573 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
574 u32 n_eqes, num_cons;
576 /* First allocate the context manager structure */
577 rc = ecore_cxt_mngr_alloc(p_hwfn);
581 /* Set the HW cid/tid numbers (in the contest manager)
582 * Must be done prior to any further computations.
584 rc = ecore_cxt_set_pf_params(p_hwfn);
588 /* Prepare and process QM requirements */
589 rc = ecore_init_qm_info(p_hwfn, true);
593 /* Compute the ILT client partition */
594 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
598 /* CID map / ILT shadow table / T2
599 * The talbes sizes are determined by the computations above
601 rc = ecore_cxt_tables_alloc(p_hwfn);
605 /* SPQ, must follow ILT because initializes SPQ context */
606 rc = ecore_spq_alloc(p_hwfn);
610 /* SP status block allocation */
611 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
614 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
618 rc = ecore_iov_alloc(p_hwfn);
623 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
624 if ((p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) ||
625 (p_hwfn->hw_info.personality == ECORE_PCI_IWARP)) {
626 /* Calculate the EQ size
627 * ---------------------
628 * Each ICID may generate up to one event at a time i.e.
629 * the event must be handled/cleared before a new one
630 * can be generated. We calculate the sum of events per
631 * protocol and create an EQ deep enough to handle the
633 * - Core - according to SPQ.
634 * - RoCE - per QP there are a couple of ICIDs, one
635 * responder and one requester, each can
636 * generate an EQE => n_eqes_qp = 2 * n_qp.
637 * Each CQ can generate an EQE. There are 2 CQs
638 * per QP => n_eqes_cq = 2 * n_qp.
639 * Hence the RoCE total is 4 * n_qp or
641 * - ENet - There can be up to two events per VF. One
642 * for VF-PF channel and another for VF FLR
643 * initial cleanup. The number of VFs is
644 * bounded by MAX_NUM_VFS_BB, and is much
645 * smaller than RoCE's so we avoid exact
648 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
650 ecore_cxt_get_proto_cid_count(
656 num_cons = ecore_cxt_get_proto_cid_count(
661 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
662 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
664 ecore_cxt_get_proto_cid_count(p_hwfn,
665 PROTOCOLID_ISCSI, 0);
666 n_eqes += 2 * num_cons;
669 if (n_eqes > 0xFFFF) {
670 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
671 "The maximum of a u16 chain is 0x%x\n",
677 p_eq = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
682 p_consq = ecore_consq_alloc(p_hwfn);
685 p_hwfn->p_consq = p_consq;
687 #ifdef CONFIG_ECORE_LL2
688 if (p_hwfn->using_ll2) {
689 p_ll2_info = ecore_ll2_alloc(p_hwfn);
692 p_hwfn->p_ll2_info = p_ll2_info;
696 /* DMA info initialization */
697 rc = ecore_dmae_info_alloc(p_hwfn);
699 DP_NOTICE(p_hwfn, true,
700 "Failed to allocate memory for dmae_info structure\n");
704 /* DCBX initialization */
705 rc = ecore_dcbx_info_alloc(p_hwfn);
707 DP_NOTICE(p_hwfn, true,
708 "Failed to allocate memory for dcbx structure\n");
713 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
714 sizeof(struct ecore_eth_stats));
715 if (!p_dev->reset_stats) {
716 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
720 return ECORE_SUCCESS;
725 ecore_resc_free(p_dev);
729 void ecore_resc_setup(struct ecore_dev *p_dev)
736 for_each_hwfn(p_dev, i) {
737 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
739 ecore_cxt_mngr_setup(p_hwfn);
740 ecore_spq_setup(p_hwfn);
741 ecore_eq_setup(p_hwfn, p_hwfn->p_eq);
742 ecore_consq_setup(p_hwfn, p_hwfn->p_consq);
744 /* Read shadow of current MFW mailbox */
745 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
746 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
747 p_hwfn->mcp_info->mfw_mb_cur,
748 p_hwfn->mcp_info->mfw_mb_length);
750 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
752 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
753 #ifdef CONFIG_ECORE_LL2
754 if (p_hwfn->using_ll2)
755 ecore_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
760 #define FINAL_CLEANUP_POLL_CNT (100)
761 #define FINAL_CLEANUP_POLL_TIME (10)
762 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
763 struct ecore_ptt *p_ptt,
766 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
767 enum _ecore_status_t rc = ECORE_TIMEOUT;
770 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
771 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
772 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
773 return ECORE_SUCCESS;
777 addr = GTT_BAR0_MAP_REG_USDM_RAM +
778 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
783 command |= X_FINAL_CLEANUP_AGG_INT <<
784 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
785 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
786 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
787 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
789 /* Make sure notification is not set before initiating final cleanup */
791 if (REG_RD(p_hwfn, addr)) {
792 DP_NOTICE(p_hwfn, false,
793 "Unexpected; Found final cleanup notification");
794 DP_NOTICE(p_hwfn, false,
795 " before initiating final cleanup\n");
796 REG_WR(p_hwfn, addr, 0);
799 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
800 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
801 id, OSAL_CPU_TO_LE32(command));
803 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN,
804 OSAL_CPU_TO_LE32(command));
806 /* Poll until completion */
807 while (!REG_RD(p_hwfn, addr) && count--)
808 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
810 if (REG_RD(p_hwfn, addr))
813 DP_NOTICE(p_hwfn, true,
814 "Failed to receive FW final cleanup notification\n");
816 /* Cleanup afterwards */
817 REG_WR(p_hwfn, addr, 0);
822 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
826 if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
827 hw_mode |= 1 << MODE_BB_A0;
828 } else if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
829 hw_mode |= 1 << MODE_BB_B0;
830 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
831 hw_mode |= 1 << MODE_K2;
833 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
834 p_hwfn->p_dev->type);
838 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
839 switch (p_hwfn->p_dev->num_ports_in_engines) {
841 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
844 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
847 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
850 DP_NOTICE(p_hwfn, true,
851 "num_ports_in_engine = %d not supported\n",
852 p_hwfn->p_dev->num_ports_in_engines);
856 switch (p_hwfn->p_dev->mf_mode) {
857 case ECORE_MF_DEFAULT:
859 hw_mode |= 1 << MODE_MF_SI;
862 hw_mode |= 1 << MODE_MF_SD;
865 DP_NOTICE(p_hwfn, true,
866 "Unsupported MF mode, init as DEFAULT\n");
867 hw_mode |= 1 << MODE_MF_SI;
871 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
872 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
873 hw_mode |= 1 << MODE_FPGA;
875 if (p_hwfn->p_dev->b_is_emul_full)
876 hw_mode |= 1 << MODE_EMUL_FULL;
878 hw_mode |= 1 << MODE_EMUL_REDUCED;
882 hw_mode |= 1 << MODE_ASIC;
884 #ifndef REAL_ASIC_ONLY
885 if (ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn))
886 hw_mode |= 1 << MODE_EAGLE_ENG1_WORKAROUND;
889 if (p_hwfn->p_dev->num_hwfns > 1)
890 hw_mode |= 1 << MODE_100G;
892 p_hwfn->hw_info.hw_mode = hw_mode;
894 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
895 "Configuring function for hw_mode: 0x%08x\n",
896 p_hwfn->hw_info.hw_mode);
898 return ECORE_SUCCESS;
902 /* MFW-replacement initializations for non-ASIC */
903 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
904 struct ecore_ptt *p_ptt)
909 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
912 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
914 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
915 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2, 0x3ffffff);
917 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
918 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
919 if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))
920 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0, 4);
922 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
923 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
924 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
925 (p_hwfn->p_dev->num_ports_in_engines >> 1));
927 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
928 p_hwfn->p_dev->num_ports_in_engines == 4 ? 0 : 3);
932 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
933 for (i = 0; i < 100; i++) {
935 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
939 DP_NOTICE(p_hwfn, true,
940 "RBC done failed to complete in PSWRQ2\n");
942 return ECORE_SUCCESS;
946 /* Init run time data for all PFs and their VFs on an engine.
947 * TBD - for VFs - Once we have parent PF info for each VF in
948 * shmem available as CAU requires knowledge of parent PF for each VF.
950 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
952 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
955 for_each_hwfn(p_dev, i) {
956 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
957 struct ecore_igu_info *p_igu_info;
958 struct ecore_igu_block *p_block;
959 struct cau_sb_entry sb_entry;
961 p_igu_info = p_hwfn->hw_info.p_igu_info;
963 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
965 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
970 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
971 p_block->function_id, 0, 0);
972 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
977 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
978 struct ecore_ptt *p_ptt,
981 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
982 struct ecore_dev *p_dev = p_hwfn->p_dev;
983 u8 vf_id, max_num_vfs;
986 enum _ecore_status_t rc = ECORE_SUCCESS;
988 ecore_init_cau_rt_data(p_dev);
990 /* Program GTT windows */
991 ecore_gtt_init(p_hwfn);
994 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
995 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
996 if (rc != ECORE_SUCCESS)
1001 if (p_hwfn->mcp_info) {
1002 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1003 qm_info->pf_rl_en = 1;
1004 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1005 qm_info->pf_wfq_en = 1;
1008 ecore_qm_common_rt_init(p_hwfn,
1009 p_hwfn->p_dev->num_ports_in_engines,
1010 qm_info->max_phys_tcs_per_port,
1011 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1012 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1013 qm_info->qm_port_params);
1015 ecore_cxt_hw_init_common(p_hwfn);
1017 /* Close gate from NIG to BRB/Storm; By default they are open, but
1018 * we close them to prevent NIG from passing data to reset blocks.
1019 * Should have been done in the ENGINE phase, but init-tool lacks
1020 * proper port-pretend capabilities.
1022 ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1023 ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1024 ecore_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
1025 ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1026 ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1027 ecore_port_unpretend(p_hwfn, p_ptt);
1029 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1030 if (rc != ECORE_SUCCESS)
1033 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1034 * need to decide with which value, maybe runtime
1036 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1037 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1039 if (ECORE_IS_BB(p_hwfn->p_dev)) {
1040 /* Workaround clears ROCE search for all functions to prevent
1041 * involving non initialized function in processing ROCE packet.
1043 num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
1044 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1045 ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1046 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1047 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1049 /* pretend to original PF */
1050 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1053 /* Workaround for avoiding CCFC execution error when getting packets
1054 * with CRC errors, and allowing instead the invoking of the FW error
1056 * This is not done inside the init tool since it currently can't
1057 * perform a pretending to VFs.
1059 max_num_vfs = ECORE_IS_AH(p_hwfn->p_dev) ? MAX_NUM_VFS_K2
1061 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1062 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1063 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1064 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1065 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1066 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1067 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1069 /* pretend to original PF */
1070 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1076 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1077 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1079 #define PMEG_IF_BYTE_COUNT 8
1081 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1082 struct ecore_ptt *p_ptt,
1083 u32 addr, u64 data, u8 reg_type, u8 port)
1085 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1086 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1087 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) |
1088 (8 << PMEG_IF_BYTE_COUNT),
1089 (reg_type << 25) | (addr << 8) | port,
1090 (u32)((data >> 32) & 0xffffffff),
1091 (u32)(data & 0xffffffff));
1093 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0,
1094 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) &
1095 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1096 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB_B0,
1097 (reg_type << 25) | (addr << 8) | port);
1098 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
1100 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
1101 (data >> 32) & 0xffffffff);
1104 #define XLPORT_MODE_REG (0x20a)
1105 #define XLPORT_MAC_CONTROL (0x210)
1106 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1107 #define XLPORT_ENABLE_REG (0x20b)
1109 #define XLMAC_CTRL (0x600)
1110 #define XLMAC_MODE (0x601)
1111 #define XLMAC_RX_MAX_SIZE (0x608)
1112 #define XLMAC_TX_CTRL (0x604)
1113 #define XLMAC_PAUSE_CTRL (0x60d)
1114 #define XLMAC_PFC_CTRL (0x60e)
1116 static void ecore_emul_link_init_ah(struct ecore_hwfn *p_hwfn,
1117 struct ecore_ptt *p_ptt)
1119 u8 port = p_hwfn->port_id;
1120 u32 mac_base = NWM_REG_MAC0 + (port << 2) * NWM_REG_MAC0_SIZE;
1122 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2 + (port << 2),
1123 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_SHIFT) |
1124 (port << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_SHIFT)
1125 | (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_SHIFT));
1127 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE,
1128 1 << ETH_MAC_REG_XIF_MODE_XGMII_SHIFT);
1130 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH,
1131 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_SHIFT);
1133 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH,
1134 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_SHIFT);
1136 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS,
1137 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_SHIFT);
1139 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS,
1140 (0xA << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_SHIFT) |
1141 (8 << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_SHIFT));
1143 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG, 0xa853);
1146 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1147 struct ecore_ptt *p_ptt)
1149 u8 loopback = 0, port = p_hwfn->port_id * 2;
1151 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1153 if (ECORE_IS_AH(p_hwfn->p_dev)) {
1154 ecore_emul_link_init_ah(p_hwfn, p_ptt);
1158 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1159 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1161 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1162 /* XLMAC: SOFT RESET */
1163 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1164 /* XLMAC: Port Speed >= 10Gbps */
1165 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1166 /* XLMAC: Max Size */
1167 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1168 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1169 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1171 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1172 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1173 0x30ffffc000ULL, 0, port);
1174 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1175 port); /* XLMAC: TX_EN, RX_EN */
1176 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1177 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1178 0x1003 | (loopback << 2), 0, port);
1179 /* Enabled Parallel PFC interface */
1180 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1182 /* XLPORT port enable */
1183 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1186 static void ecore_link_init(struct ecore_hwfn *p_hwfn,
1187 struct ecore_ptt *p_ptt, u8 port)
1189 int port_offset = port ? 0x800 : 0;
1190 u32 xmac_rxctrl = 0;
1193 /* FIXME: move to common start */
1194 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1195 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
1197 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1198 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
1200 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1202 /* Set the number of ports on the Warp Core to 10G */
1203 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1205 /* Soft reset of XMAC */
1206 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1207 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1209 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1210 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1212 /* FIXME: move to common end */
1213 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1214 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE + port_offset, 0x20);
1216 /* Set Max packet size: initialize XMAC block register for port 0 */
1217 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE + port_offset, 0x2710);
1219 /* CRC append for Tx packets: init XMAC block register for port 1 */
1220 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO + port_offset, 0xC800);
1222 /* Enable TX and RX: initialize XMAC block register for port 1 */
1223 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL + port_offset,
1224 XMAC_REG_CTRL_TX_EN | XMAC_REG_CTRL_RX_EN);
1225 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset);
1226 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE;
1227 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset, xmac_rxctrl);
1231 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1232 struct ecore_ptt *p_ptt,
1235 enum _ecore_status_t rc = ECORE_SUCCESS;
1237 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1239 if (rc != ECORE_SUCCESS)
1242 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1243 return ECORE_SUCCESS;
1245 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1246 if (ECORE_IS_AH(p_hwfn->p_dev))
1247 return ECORE_SUCCESS;
1248 ecore_link_init(p_hwfn, p_ptt, p_hwfn->port_id);
1249 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1250 if (p_hwfn->p_dev->num_hwfns > 1) {
1251 /* Activate OPTE in CMT */
1254 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1256 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1257 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1258 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1259 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1260 ecore_wr(p_hwfn, p_ptt,
1261 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1262 ecore_wr(p_hwfn, p_ptt,
1263 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1264 ecore_wr(p_hwfn, p_ptt,
1265 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1269 ecore_emul_link_init(p_hwfn, p_ptt);
1271 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1278 static enum _ecore_status_t
1279 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1280 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1282 u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1283 u32 dpi_bit_shift, dpi_count;
1286 /* Calculate DPI size
1287 * ------------------
1288 * The PWM region contains Doorbell Pages. The first is reserverd for
1289 * the kernel for, e.g, L2. The others are free to be used by non-
1290 * trusted applications, typically from user space. Each page, called a
1291 * doorbell page is sectioned into windows that allow doorbells to be
1292 * issued in parallel by the kernel/application. The size of such a
1293 * window (a.k.a. WID) is 1kB.
1295 * 1kB WID x N WIDS = DPI page size
1296 * DPI page size x N DPIs = PWM region size
1298 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1299 * in order to ensure that two applications won't share the same page.
1300 * It also must contain at least one WID per CPU to allow parallelism.
1301 * It also must be a power of 2, since it is stored as a bit shift.
1303 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1304 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1305 * containing 4 WIDs.
1307 dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1308 dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1309 dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1310 dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1311 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1313 dpi_count = pwm_region_size / dpi_page_size;
1315 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1316 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1319 p_hwfn->dpi_size = dpi_page_size;
1320 p_hwfn->dpi_count = dpi_count;
1322 /* Update registers */
1323 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1325 if (dpi_count < min_dpis)
1326 return ECORE_NORESOURCES;
1328 return ECORE_SUCCESS;
1331 enum ECORE_ROCE_EDPM_MODE {
1332 ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1333 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1334 ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1337 static enum _ecore_status_t
1338 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1339 struct ecore_ptt *p_ptt)
1341 u32 pwm_regsize, norm_regsize;
1342 u32 non_pwm_conn, min_addr_reg1;
1343 u32 db_bar_size, n_cpus;
1346 int rc = ECORE_SUCCESS;
1349 db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1350 if (p_hwfn->p_dev->num_hwfns > 1)
1353 /* Calculate doorbell regions
1354 * -----------------------------------
1355 * The doorbell BAR is made of two regions. The first is called normal
1356 * region and the second is called PWM region. In the normal region
1357 * each ICID has its own set of addresses so that writing to that
1358 * specific address identifies the ICID. In the Process Window Mode
1359 * region the ICID is given in the data written to the doorbell. The
1360 * above per PF register denotes the offset in the doorbell BAR in which
1361 * the PWM region begins.
1362 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1363 * non-PWM connection. The calculation below computes the total non-PWM
1364 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1365 * in units of 4,096 bytes.
1367 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1368 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1370 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1371 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1372 min_addr_reg1 = norm_regsize / 4096;
1373 pwm_regsize = db_bar_size - norm_regsize;
1375 /* Check that the normal and PWM sizes are valid */
1376 if (db_bar_size < norm_regsize) {
1377 DP_ERR(p_hwfn->p_dev,
1378 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1379 db_bar_size, norm_regsize);
1380 return ECORE_NORESOURCES;
1382 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1383 DP_ERR(p_hwfn->p_dev,
1384 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1385 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1387 return ECORE_NORESOURCES;
1390 /* Calculate number of DPIs */
1391 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1392 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1393 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1394 /* Either EDPM is mandatory, or we are attempting to allocate a
1397 n_cpus = OSAL_NUM_ACTIVE_CPU();
1398 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1401 cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1402 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1403 if (cond || p_hwfn->dcbx_no_edpm) {
1404 /* Either EDPM is disabled from user configuration, or it is
1405 * disabled via DCBx, or it is not mandatory and we failed to
1406 * allocated a WID per CPU.
1409 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1411 /* If we entered this flow due to DCBX then the DPM register is
1412 * already configured.
1417 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1418 norm_regsize, pwm_regsize);
1420 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1421 p_hwfn->dpi_size, p_hwfn->dpi_count,
1422 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1423 "disabled" : "enabled");
1425 /* Check return codes from above calls */
1428 "Failed to allocate enough DPIs\n");
1429 return ECORE_NORESOURCES;
1433 p_hwfn->dpi_start_offset = norm_regsize;
1435 /* Update registers */
1436 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1437 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1438 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1439 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1441 return ECORE_SUCCESS;
1444 static enum _ecore_status_t
1445 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1446 struct ecore_ptt *p_ptt,
1447 struct ecore_tunn_start_params *p_tunn,
1450 enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1452 u8 rel_pf_id = p_hwfn->rel_pf_id;
1454 enum _ecore_status_t rc = ECORE_SUCCESS;
1458 if (p_hwfn->mcp_info) {
1459 struct ecore_mcp_function_info *p_info;
1461 p_info = &p_hwfn->mcp_info->func_info;
1462 if (p_info->bandwidth_min)
1463 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1465 /* Update rate limit once we'll actually have a link */
1466 p_hwfn->qm_info.pf_rl = 100000;
1468 ecore_cxt_hw_init_pf(p_hwfn);
1470 ecore_int_igu_init_rt(p_hwfn);
1472 /* Set VLAN in NIG if needed */
1473 if (hw_mode & (1 << MODE_MF_SD)) {
1474 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1475 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1476 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1477 p_hwfn->hw_info.ovlan);
1480 /* Enable classification by MAC if needed */
1481 if (hw_mode & (1 << MODE_MF_SI)) {
1482 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1483 "Configuring TAGMAC_CLS_TYPE\n");
1484 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1488 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
1489 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1490 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1491 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1492 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1493 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1495 /* perform debug configuration when chip is out of reset */
1496 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1498 /* Cleanup chip from previous driver if such remains exist */
1499 rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1500 if (rc != ECORE_SUCCESS) {
1501 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1505 /* PF Init sequence */
1506 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1510 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1511 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1515 /* Pure runtime initializations - directly to the HW */
1516 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1518 /* PCI relaxed ordering causes a decrease in the performance on some
1519 * systems. Till a root cause is found, disable this attribute in the
1523 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1525 * DP_NOTICE(p_hwfn, true,
1526 * "Failed to find the PCIe Cap\n");
1529 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1530 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1531 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1534 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1538 /* enable interrupts */
1539 ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1541 /* send function start command */
1542 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1543 allow_npar_tx_switch);
1545 DP_NOTICE(p_hwfn, true,
1546 "Function start ramrod failed\n");
1548 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1549 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1550 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1552 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1553 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1555 ecore_wr(p_hwfn, p_ptt,
1556 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1559 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1560 "PRS_REG_SEARCH registers after start PFn\n");
1561 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1562 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1563 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1564 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1565 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1566 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1567 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1568 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1569 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1570 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1571 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1572 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1573 prs_reg = ecore_rd(p_hwfn, p_ptt,
1574 PRS_REG_SEARCH_TCP_FIRST_FRAG);
1575 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1576 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1578 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1579 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1580 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1586 static enum _ecore_status_t
1587 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1588 struct ecore_ptt *p_ptt, u8 enable)
1590 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1592 /* Change PF in PXP */
1593 ecore_wr(p_hwfn, p_ptt,
1594 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1596 /* wait until value is set - try for 1 second every 50us */
1597 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1598 val = ecore_rd(p_hwfn, p_ptt,
1599 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1606 if (val != set_val) {
1607 DP_NOTICE(p_hwfn, true,
1608 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1609 return ECORE_UNKNOWN_ERROR;
1612 return ECORE_SUCCESS;
1615 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1616 struct ecore_ptt *p_main_ptt)
1618 /* Read shadow of current MFW mailbox */
1619 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1620 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1621 p_hwfn->mcp_info->mfw_mb_cur,
1622 p_hwfn->mcp_info->mfw_mb_length);
1625 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1626 struct ecore_hw_init_params *p_params)
1628 enum _ecore_status_t rc, mfw_rc;
1629 u32 load_code, param;
1632 if (p_params->int_mode == ECORE_INT_MODE_MSI && p_dev->num_hwfns > 1) {
1633 DP_NOTICE(p_dev, false,
1634 "MSI mode is not supported for CMT devices\n");
1639 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1640 if (rc != ECORE_SUCCESS)
1644 for_each_hwfn(p_dev, i) {
1645 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1648 p_hwfn->b_int_enabled = 1;
1652 /* Enable DMAE in PXP */
1653 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1654 if (rc != ECORE_SUCCESS)
1657 rc = ecore_calc_hw_mode(p_hwfn);
1658 if (rc != ECORE_SUCCESS)
1661 /* @@@TBD need to add here:
1662 * Check for fan failure
1665 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1667 DP_NOTICE(p_hwfn, true,
1668 "Failed sending LOAD_REQ command\n");
1673 * When coming back from hiberbate state, the registers from
1674 * which shadow is read initially are not initialized. It turns
1675 * out that these registers get initialized during the call to
1676 * ecore_mcp_load_req request. So we need to reread them here
1677 * to get the proper shadow register value.
1678 * Note: This is a workaround for the missinginig MFW
1679 * initialization. It may be removed once the implementation
1682 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1684 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1685 "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1688 /* Only relevant for recovery:
1689 * Clear the indication after the LOAD_REQ command is responded
1692 p_dev->recov_in_prog = false;
1694 p_hwfn->first_on_engine = (load_code ==
1695 FW_MSG_CODE_DRV_LOAD_ENGINE);
1697 if (!qm_lock_init) {
1698 OSAL_SPIN_LOCK_INIT(&qm_lock);
1699 qm_lock_init = true;
1702 switch (load_code) {
1703 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1704 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1705 p_hwfn->hw_info.hw_mode);
1709 case FW_MSG_CODE_DRV_LOAD_PORT:
1710 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1711 p_hwfn->hw_info.hw_mode);
1715 #ifndef REAL_ASIC_ONLY
1716 if (ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn)) {
1717 struct init_nig_pri_tc_map_req tc_map;
1719 OSAL_MEM_ZERO(&tc_map, sizeof(tc_map));
1721 /* remove this once flow control is
1724 for (j = 0; j < NUM_OF_VLAN_PRIORITIES; j++) {
1725 tc_map.pri[j].tc_id = 0;
1726 tc_map.pri[j].valid = 1;
1728 ecore_init_nig_pri_tc_map(p_hwfn,
1734 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1735 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1737 p_hwfn->hw_info.hw_mode,
1738 p_params->b_hw_start,
1740 p_params->allow_npar_tx_switch);
1747 if (rc != ECORE_SUCCESS)
1748 DP_NOTICE(p_hwfn, true,
1749 "init phase failed for loadcode 0x%x (rc %d)\n",
1752 /* ACK mfw regardless of success or failure of initialization */
1753 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1754 DRV_MSG_CODE_LOAD_DONE,
1755 0, &load_code, ¶m);
1756 if (rc != ECORE_SUCCESS)
1758 if (mfw_rc != ECORE_SUCCESS) {
1759 DP_NOTICE(p_hwfn, true,
1760 "Failed sending LOAD_DONE command\n");
1764 /* send DCBX attention request command */
1765 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1766 "sending phony dcbx set command to trigger DCBx attention handling\n");
1767 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1768 DRV_MSG_CODE_SET_DCBX,
1769 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1770 &load_code, ¶m);
1771 if (mfw_rc != ECORE_SUCCESS) {
1772 DP_NOTICE(p_hwfn, true,
1773 "Failed to send DCBX attention request\n");
1777 p_hwfn->hw_init_done = true;
1780 return ECORE_SUCCESS;
1783 #define ECORE_HW_STOP_RETRY_LIMIT (10)
1784 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
1785 struct ecore_hwfn *p_hwfn,
1786 struct ecore_ptt *p_ptt)
1791 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1792 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1793 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
1795 if ((!ecore_rd(p_hwfn, p_ptt,
1796 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1797 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1800 /* Dependent on number of connection/tasks, possibly
1801 * 1ms sleep is required between polls
1805 if (i == ECORE_HW_STOP_RETRY_LIMIT)
1806 DP_NOTICE(p_hwfn, true,
1807 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1808 (u8)ecore_rd(p_hwfn, p_ptt,
1809 TM_REG_PF_SCAN_ACTIVE_CONN),
1810 (u8)ecore_rd(p_hwfn, p_ptt,
1811 TM_REG_PF_SCAN_ACTIVE_TASK));
1814 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
1818 for_each_hwfn(p_dev, j) {
1819 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1820 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1822 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1826 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
1828 enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
1831 for_each_hwfn(p_dev, j) {
1832 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1833 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1835 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
1838 ecore_vf_pf_int_cleanup(p_hwfn);
1842 /* mark the hw as uninitialized... */
1843 p_hwfn->hw_init_done = false;
1845 rc = ecore_sp_pf_stop(p_hwfn);
1847 DP_NOTICE(p_hwfn, true,
1848 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
1850 /* perform debug action after PF stop was sent */
1851 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
1853 /* close NIG to BRB gate */
1854 ecore_wr(p_hwfn, p_ptt,
1855 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1858 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1859 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1860 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1861 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1862 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1864 /* @@@TBD - clean transmission queues (5.b) */
1865 /* @@@TBD - clean BTB (5.c) */
1867 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1869 /* @@@TBD - verify DMAE requests are done (8) */
1871 /* Disable Attention Generation */
1872 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1873 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1874 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1875 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1876 /* Need to wait 1ms to guarantee SBs are cleared */
1881 /* Disable DMAE in PXP - in CMT, this should only be done for
1882 * first hw-function, and only after all transactions have
1883 * stopped for all active hw-functions.
1885 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
1886 p_dev->hwfns[0].p_main_ptt, false);
1887 if (t_rc != ECORE_SUCCESS)
1894 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
1898 for_each_hwfn(p_dev, j) {
1899 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1900 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1903 ecore_vf_pf_int_cleanup(p_hwfn);
1907 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1908 "Shutting down the fastpath\n");
1910 ecore_wr(p_hwfn, p_ptt,
1911 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1913 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1914 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1915 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1916 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1917 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1919 /* @@@TBD - clean transmission queues (5.b) */
1920 /* @@@TBD - clean BTB (5.c) */
1922 /* @@@TBD - verify DMAE requests are done (8) */
1924 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1925 /* Need to wait 1ms to guarantee SBs are cleared */
1930 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
1932 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1934 if (IS_VF(p_hwfn->p_dev))
1937 /* If roce info is allocated it means roce is initialized and should
1938 * be enabled in searcher.
1940 if (p_hwfn->p_rdma_info) {
1941 if (p_hwfn->b_rdma_enabled_in_prs)
1942 ecore_wr(p_hwfn, p_ptt,
1943 p_hwfn->rdma_prs_search_reg, 0x1);
1944 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
1947 /* Re-open incoming traffic */
1948 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1949 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1952 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
1953 struct ecore_ptt *p_ptt, u32 reg,
1956 u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
1958 if (assert_val != expected) {
1959 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
1961 return ECORE_UNKNOWN_ERROR;
1967 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
1969 enum _ecore_status_t rc = ECORE_SUCCESS;
1970 u32 unload_resp, unload_param;
1973 for_each_hwfn(p_dev, i) {
1974 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1977 rc = ecore_vf_pf_reset(p_hwfn);
1983 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
1985 /* Check for incorrect states */
1986 if (!p_dev->recov_in_prog) {
1987 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1988 QM_REG_USG_CNT_PF_TX, 0);
1989 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1990 QM_REG_USG_CNT_PF_OTHER, 0);
1991 /* @@@TBD - assert on incorrect xCFC values (10.b) */
1994 /* Disable PF in HW blocks */
1995 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1996 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1998 if (p_dev->recov_in_prog) {
1999 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2000 "Recovery is in progress -> skip sending unload_req/done\n");
2004 /* Send unload command to MCP */
2005 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2006 DRV_MSG_CODE_UNLOAD_REQ,
2007 DRV_MB_PARAM_UNLOAD_WOL_MCP,
2008 &unload_resp, &unload_param);
2009 if (rc != ECORE_SUCCESS) {
2010 DP_NOTICE(p_hwfn, true,
2011 "ecore_hw_reset: UNLOAD_REQ failed\n");
2012 /* @@TBD - what to do? for now, assume ENG. */
2013 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
2016 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2017 DRV_MSG_CODE_UNLOAD_DONE,
2018 0, &unload_resp, &unload_param);
2019 if (rc != ECORE_SUCCESS) {
2021 true, "ecore_hw_reset: UNLOAD_DONE failed\n");
2022 /* @@@TBD - Should it really ASSERT here ? */
2030 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2031 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2033 ecore_ptt_pool_free(p_hwfn);
2034 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2037 /* Setup bar access */
2038 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2040 /* clear indirect access */
2041 if (ECORE_IS_AH(p_hwfn->p_dev)) {
2042 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2043 PGLUE_B_REG_PGL_ADDR_E8_F0, 0);
2044 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2045 PGLUE_B_REG_PGL_ADDR_EC_F0, 0);
2046 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2047 PGLUE_B_REG_PGL_ADDR_F0_F0, 0);
2048 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2049 PGLUE_B_REG_PGL_ADDR_F4_F0, 0);
2051 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2052 PGLUE_B_REG_PGL_ADDR_88_F0, 0);
2053 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2054 PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
2055 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2056 PGLUE_B_REG_PGL_ADDR_90_F0, 0);
2057 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2058 PGLUE_B_REG_PGL_ADDR_94_F0, 0);
2061 /* Clean Previous errors if such exist */
2062 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2063 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2065 /* enable internal target-read */
2066 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2067 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2070 static void get_function_id(struct ecore_hwfn *p_hwfn)
2073 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2074 PXP_PF_ME_OPAQUE_ADDR);
2076 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2078 /* Bits 16-19 from the ME registers are the pf_num */
2079 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2080 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2081 PXP_CONCRETE_FID_PFID);
2082 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2083 PXP_CONCRETE_FID_PORT);
2085 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2086 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2087 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2090 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2092 u32 *feat_num = p_hwfn->hw_info.feat_num;
2093 int num_features = 1;
2095 /* L2 Queues require each: 1 status block. 1 L2 queue */
2096 feat_num[ECORE_PF_L2_QUE] =
2098 RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2099 RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2101 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2102 "#PF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d num_features=%d\n",
2103 feat_num[ECORE_PF_L2_QUE],
2104 feat_num[ECORE_RDMA_CNQ],
2105 RESC_NUM(p_hwfn, ECORE_SB), num_features);
2108 static enum resource_id_enum
2109 ecore_hw_get_mfw_res_id(enum ecore_resources res_id)
2111 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2115 mfw_res_id = RESOURCE_NUM_SB_E;
2117 case ECORE_L2_QUEUE:
2118 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2121 mfw_res_id = RESOURCE_NUM_VPORT_E;
2124 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2127 mfw_res_id = RESOURCE_NUM_PQ_E;
2130 mfw_res_id = RESOURCE_NUM_RL_E;
2134 /* Each VFC resource can accommodate both a MAC and a VLAN */
2135 mfw_res_id = RESOURCE_VFC_FILTER_E;
2138 mfw_res_id = RESOURCE_ILT_E;
2140 case ECORE_LL2_QUEUE:
2141 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2143 case ECORE_RDMA_CNQ_RAM:
2144 case ECORE_CMDQS_CQS:
2145 /* CNQ/CMDQS are the same resource */
2146 mfw_res_id = RESOURCE_CQS_E;
2148 case ECORE_RDMA_STATS_QUEUE:
2149 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2158 static u32 ecore_hw_get_dflt_resc_num(struct ecore_hwfn *p_hwfn,
2159 enum ecore_resources res_id)
2161 u8 num_funcs = p_hwfn->num_funcs_on_engine;
2162 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2163 struct ecore_sb_cnt_info sb_cnt_info;
2164 u32 dflt_resc_num = 0;
2168 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2169 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2170 dflt_resc_num = sb_cnt_info.sb_cnt;
2172 case ECORE_L2_QUEUE:
2173 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2174 MAX_NUM_L2_QUEUES_BB) / num_funcs;
2177 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2178 MAX_NUM_VPORTS_BB) / num_funcs;
2181 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2182 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2185 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2186 MAX_QM_TX_QUEUES_BB) / num_funcs;
2189 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2193 /* Each VFC resource can accommodate both a MAC and a VLAN */
2194 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2197 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2198 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2200 case ECORE_LL2_QUEUE:
2201 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2203 case ECORE_RDMA_CNQ_RAM:
2204 case ECORE_CMDQS_CQS:
2205 /* CNQ/CMDQS are the same resource */
2207 dflt_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2209 case ECORE_RDMA_STATS_QUEUE:
2211 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2212 MAX_NUM_VPORTS_BB) / num_funcs;
2218 return dflt_resc_num;
2221 static const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2226 case ECORE_L2_QUEUE:
2240 case ECORE_RDMA_CNQ_RAM:
2241 return "RDMA_CNQ_RAM";
2244 case ECORE_LL2_QUEUE:
2246 case ECORE_CMDQS_CQS:
2248 case ECORE_RDMA_STATS_QUEUE:
2249 return "RDMA_STATS_QUEUE";
2251 return "UNKNOWN_RESOURCE";
2255 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2256 enum ecore_resources res_id,
2257 bool drv_resc_alloc)
2259 u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
2260 u32 *p_resc_num, *p_resc_start;
2261 struct resource_info resc_info;
2262 enum _ecore_status_t rc;
2264 p_resc_num = &RESC_NUM(p_hwfn, res_id);
2265 p_resc_start = &RESC_START(p_hwfn, res_id);
2267 dflt_resc_num = ecore_hw_get_dflt_resc_num(p_hwfn, res_id);
2268 if (!dflt_resc_num) {
2270 "Failed to get default amount for resource %d [%s]\n",
2271 res_id, ecore_hw_get_resc_name(res_id));
2274 dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
2277 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2278 *p_resc_num = dflt_resc_num;
2279 *p_resc_start = dflt_resc_start;
2284 OSAL_MEM_ZERO(&resc_info, sizeof(resc_info));
2285 resc_info.res_id = ecore_hw_get_mfw_res_id(res_id);
2286 if (resc_info.res_id == RESOURCE_NUM_INVALID) {
2288 "Failed to match resource %d with MFW resources\n",
2293 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
2294 &mcp_resp, &mcp_param);
2295 if (rc != ECORE_SUCCESS) {
2296 DP_NOTICE(p_hwfn, true,
2297 "MFW response failure for an allocation request for"
2298 " resource %d [%s]\n",
2299 res_id, ecore_hw_get_resc_name(res_id));
2303 /* Default driver values are applied in the following cases:
2304 * - The resource allocation MB command is not supported by the MFW
2305 * - There is an internal error in the MFW while processing the request
2306 * - The resource ID is unknown to the MFW
2308 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
2309 mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
2312 "Resource %d [%s]: No allocation info was received"
2313 " [mcp_resp 0x%x]. Applying default values"
2314 " [num %d, start %d].\n",
2315 res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2316 dflt_resc_num, dflt_resc_start);
2318 *p_resc_num = dflt_resc_num;
2319 *p_resc_start = dflt_resc_start;
2323 /* TBD - remove this when revising the handling of the SB resource */
2324 if (res_id == ECORE_SB) {
2325 /* Excluding the slowpath SB */
2326 resc_info.size -= 1;
2327 resc_info.offset -= p_hwfn->enabled_func_idx;
2330 *p_resc_num = resc_info.size;
2331 *p_resc_start = resc_info.offset;
2333 if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2334 DP_NOTICE(p_hwfn, false,
2335 "Resource %d [%s]: MFW allocation [num %d, start %d]"
2336 " differs from default values [num %d, start %d]%s\n",
2337 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2338 *p_resc_start, dflt_resc_num, dflt_resc_start,
2339 drv_resc_alloc ? " - Applying default values" : "");
2340 if (drv_resc_alloc) {
2341 *p_resc_num = dflt_resc_num;
2342 *p_resc_start = dflt_resc_start;
2346 return ECORE_SUCCESS;
2349 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2350 bool drv_resc_alloc)
2352 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2353 enum _ecore_status_t rc;
2356 u32 *resc_start = p_hwfn->hw_info.resc_start;
2357 u32 *resc_num = p_hwfn->hw_info.resc_num;
2358 /* For AH, an equal share of the ILT lines between the maximal number of
2359 * PFs is not enough for RoCE. This would be solved by the future
2360 * resource allocation scheme, but isn't currently present for
2361 * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2362 * to work - the BB number of ILT lines divided by its max PFs number.
2364 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2367 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2369 * Force the driver's default resource allocation in case there
2370 * is a diff with the MFW allocation value.
2372 rc = ecore_hw_set_resc_info(p_hwfn, res_id,
2373 b_ah || drv_resc_alloc);
2374 if (rc != ECORE_SUCCESS)
2379 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2380 /* Reduced build contains less PQs */
2381 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2382 resc_num[ECORE_PQ] = 32;
2383 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2384 p_hwfn->enabled_func_idx;
2387 /* For AH emulation, since we have a possible maximal number of
2388 * 16 enabled PFs, in case there are not enough ILT lines -
2389 * allocate only first PF as RoCE and have all the other ETH
2390 * only with less ILT lines.
2392 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2393 resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2394 resc_num[ECORE_ILT],
2395 roce_min_ilt_lines);
2398 /* Correct the common ILT calculation if PF0 has more */
2399 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2400 p_hwfn->p_dev->b_is_emul_full &&
2401 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2402 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2403 resc_num[ECORE_ILT];
2406 /* Sanity for ILT */
2407 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2408 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2409 DP_NOTICE(p_hwfn, true,
2410 "Can't assign ILT pages [%08x,...,%08x]\n",
2411 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2417 ecore_hw_set_feat(p_hwfn);
2419 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2420 "The numbers for each resource are:\n");
2421 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2422 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2423 ecore_hw_get_resc_name(res_id),
2424 RESC_NUM(p_hwfn, res_id),
2425 RESC_START(p_hwfn, res_id));
2427 return ECORE_SUCCESS;
2430 static enum _ecore_status_t ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2431 struct ecore_ptt *p_ptt)
2433 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
2434 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2435 struct ecore_mcp_link_params *link;
2437 /* Read global nvm_cfg address */
2438 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2440 /* Verify MCP has initialized it */
2441 if (!nvm_cfg_addr) {
2442 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2446 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
2448 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2450 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2451 OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2454 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2456 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2457 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2458 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2459 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2461 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2462 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2464 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2465 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2467 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2468 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2470 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2471 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2473 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2474 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2476 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2477 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2479 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2480 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2482 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2483 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
2485 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2486 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2488 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2489 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2492 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2497 /* Read default link configuration */
2498 link = &p_hwfn->mcp_info->link_input;
2499 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2500 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2501 link_temp = ecore_rd(p_hwfn, p_ptt,
2503 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2504 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2505 link->speed.advertised_speeds = link_temp;
2507 link_temp = link->speed.advertised_speeds;
2508 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2510 link_temp = ecore_rd(p_hwfn, p_ptt,
2512 OFFSETOF(struct nvm_cfg1_port, link_settings));
2513 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2514 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2515 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2516 link->speed.autoneg = true;
2518 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2519 link->speed.forced_speed = 1000;
2521 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2522 link->speed.forced_speed = 10000;
2524 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2525 link->speed.forced_speed = 25000;
2527 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2528 link->speed.forced_speed = 40000;
2530 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2531 link->speed.forced_speed = 50000;
2533 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2534 link->speed.forced_speed = 100000;
2537 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
2540 p_hwfn->mcp_info->link_capabilities.default_speed =
2541 link->speed.forced_speed;
2542 p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2543 link->speed.autoneg;
2545 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2546 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2547 link->pause.autoneg = !!(link_temp &
2548 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2549 link->pause.forced_rx = !!(link_temp &
2550 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2551 link->pause.forced_tx = !!(link_temp &
2552 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2553 link->loopback_mode = 0;
2555 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2556 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2557 link->speed.forced_speed, link->speed.advertised_speeds,
2558 link->speed.autoneg, link->pause.autoneg);
2560 /* Read Multi-function information from shmem */
2561 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2562 OFFSETOF(struct nvm_cfg1, glob) +
2563 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
2565 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
2567 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2568 NVM_CFG1_GLOB_MF_MODE_OFFSET;
2571 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2572 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
2574 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2575 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
2577 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2578 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
2581 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2582 p_hwfn->p_dev->mf_mode);
2584 /* Read Multi-function information from shmem */
2585 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2586 OFFSETOF(struct nvm_cfg1, glob) +
2587 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
2589 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
2590 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2591 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
2592 &p_hwfn->hw_info.device_capabilities);
2593 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2594 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
2595 &p_hwfn->hw_info.device_capabilities);
2596 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2597 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
2598 &p_hwfn->hw_info.device_capabilities);
2599 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2600 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
2601 &p_hwfn->hw_info.device_capabilities);
2602 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
2603 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
2604 &p_hwfn->hw_info.device_capabilities);
2606 return ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2609 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
2610 struct ecore_ptt *p_ptt)
2612 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2613 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2614 struct ecore_dev *p_dev = p_hwfn->p_dev;
2616 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2618 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2619 * in the other bits are selected.
2620 * Bits 1-15 are for functions 1-15, respectively, and their value is
2621 * '0' only for enabled functions (function 0 always exists and
2623 * In case of CMT in BB, only the "even" functions are enabled, and thus
2624 * the number of functions for both hwfns is learnt from the same bits.
2626 reg_function_hide = ecore_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2628 if (reg_function_hide & 0x1) {
2629 if (ECORE_IS_BB(p_dev)) {
2630 if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
2642 /* Get the number of the enabled functions on the engine */
2643 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2650 /* Get the PF index within the enabled functions */
2651 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2652 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2660 p_hwfn->num_funcs_on_engine = num_funcs;
2661 p_hwfn->enabled_func_idx = enabled_func_idx;
2664 if (CHIP_REV_IS_FPGA(p_dev)) {
2665 DP_NOTICE(p_hwfn, false,
2666 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
2667 p_hwfn->num_funcs_on_engine = 4;
2671 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2672 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2673 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
2674 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2677 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
2678 struct ecore_ptt *p_ptt)
2683 /* Read the port mode */
2684 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
2686 else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
2687 (p_hwfn->p_dev->num_hwfns > 1))
2688 /* In CMT on emulation, assume 1 port */
2692 port_mode = ecore_rd(p_hwfn, p_ptt,
2693 CNIG_REG_NW_PORT_MODE_BB_B0);
2695 if (port_mode < 3) {
2696 p_hwfn->p_dev->num_ports_in_engines = 1;
2697 } else if (port_mode <= 5) {
2698 p_hwfn->p_dev->num_ports_in_engines = 2;
2700 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
2701 p_hwfn->p_dev->num_ports_in_engines);
2703 /* Default num_ports_in_engines to something */
2704 p_hwfn->p_dev->num_ports_in_engines = 1;
2708 static void ecore_hw_info_port_num_ah(struct ecore_hwfn *p_hwfn,
2709 struct ecore_ptt *p_ptt)
2714 p_hwfn->p_dev->num_ports_in_engines = 0;
2717 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2718 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
2719 switch ((port & 0xf000) >> 12) {
2721 p_hwfn->p_dev->num_ports_in_engines = 1;
2724 p_hwfn->p_dev->num_ports_in_engines = 2;
2727 p_hwfn->p_dev->num_ports_in_engines = 4;
2730 DP_NOTICE(p_hwfn, false,
2731 "Unknown port mode in ECO_RESERVED %08x\n",
2736 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2737 port = ecore_rd(p_hwfn, p_ptt,
2738 CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2740 p_hwfn->p_dev->num_ports_in_engines++;
2744 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
2745 struct ecore_ptt *p_ptt)
2747 if (ECORE_IS_BB(p_hwfn->p_dev))
2748 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
2750 ecore_hw_info_port_num_ah(p_hwfn, p_ptt);
2753 static enum _ecore_status_t
2754 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2755 enum ecore_pci_personality personality, bool drv_resc_alloc)
2757 enum _ecore_status_t rc;
2759 /* Since all information is common, only first hwfns should do this */
2760 if (IS_LEAD_HWFN(p_hwfn)) {
2761 rc = ecore_iov_hw_info(p_hwfn);
2762 if (rc != ECORE_SUCCESS)
2766 /* TODO In get_hw_info, amoungst others:
2767 * Get MCP FW revision and determine according to it the supported
2768 * featrues (e.g. DCB)
2770 * ecore_get_pcie_width_speed, WOL capability.
2771 * Number of global CQ-s (for storage
2773 ecore_hw_info_port_num(p_hwfn, p_ptt);
2776 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
2778 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt);
2779 if (rc != ECORE_SUCCESS)
2785 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
2786 if (rc != ECORE_SUCCESS)
2790 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
2792 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
2793 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
2796 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
2798 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
2799 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
2803 if (ecore_mcp_is_init(p_hwfn)) {
2804 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
2805 p_hwfn->hw_info.ovlan =
2806 p_hwfn->mcp_info->func_info.ovlan;
2808 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
2811 if (personality != ECORE_PCI_DEFAULT)
2812 p_hwfn->hw_info.personality = personality;
2813 else if (ecore_mcp_is_init(p_hwfn))
2814 p_hwfn->hw_info.personality =
2815 p_hwfn->mcp_info->func_info.protocol;
2818 /* To overcome ILT lack for emulation, until at least until we'll have
2819 * a definite answer from system about it, allow only PF0 to be RoCE.
2821 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
2822 if (!p_hwfn->rel_pf_id)
2823 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
2825 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
2829 /* although in BB some constellations may support more than 4 tcs,
2830 * that can result in performance penalty in some cases. 4
2831 * represents a good tradeoff between performance and flexibility.
2833 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2835 /* start out with a single active tc. This can be increased either
2836 * by dcbx negotiation or by upper layer driver
2838 p_hwfn->hw_info.num_active_tc = 1;
2840 ecore_get_num_funcs(p_hwfn, p_ptt);
2842 /* In case of forcing the driver's default resource allocation, calling
2843 * ecore_hw_get_resc() should come after initializing the personality
2844 * and after getting the number of functions, since the calculation of
2845 * the resources/features depends on them.
2846 * This order is not harmful if not forcing.
2848 return ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
2851 #define ECORE_DEV_ID_MASK 0xff00
2852 #define ECORE_DEV_ID_MASK_BB 0x1600
2853 #define ECORE_DEV_ID_MASK_AH 0x8000
2855 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
2857 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2860 /* Read Vendor Id / Device Id */
2861 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
2863 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
2866 /* Determine type */
2867 if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
2868 p_dev->type = ECORE_DEV_TYPE_AH;
2870 p_dev->type = ECORE_DEV_TYPE_BB;
2872 p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2873 MISCS_REG_CHIP_NUM);
2874 p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2875 MISCS_REG_CHIP_REV);
2877 MASK_FIELD(CHIP_REV, p_dev->chip_rev);
2879 /* Learn number of HW-functions */
2880 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2881 MISCS_REG_CMT_ENABLED_FOR_PAIR);
2883 if (tmp & (1 << p_hwfn->rel_pf_id)) {
2884 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
2885 p_dev->num_hwfns = 2;
2887 p_dev->num_hwfns = 1;
2891 if (CHIP_REV_IS_EMUL(p_dev)) {
2892 /* For some reason we have problems with this register
2893 * in B0 emulation; Simply assume no CMT
2895 DP_NOTICE(p_dev->hwfns, false,
2896 "device on emul - assume no CMT\n");
2897 p_dev->num_hwfns = 1;
2901 p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2902 MISCS_REG_CHIP_TEST_REG) >> 4;
2903 MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
2904 p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2905 MISCS_REG_CHIP_METAL);
2906 MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
2907 DP_INFO(p_dev->hwfns,
2908 "Chip details - %s%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2909 ECORE_IS_BB(p_dev) ? "BB" : "AH",
2910 CHIP_REV_IS_A0(p_dev) ? 0 : 1,
2911 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
2914 if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
2915 DP_NOTICE(p_dev->hwfns, false,
2916 "The chip type/rev (BB A0) is not supported!\n");
2917 return ECORE_ABORTED;
2920 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
2921 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2922 MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
2924 if (CHIP_REV_IS_EMUL(p_dev)) {
2925 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2926 MISCS_REG_ECO_RESERVED);
2927 if (tmp & (1 << 29)) {
2928 DP_NOTICE(p_hwfn, false,
2929 "Emulation: Running on a FULL build\n");
2930 p_dev->b_is_emul_full = true;
2932 DP_NOTICE(p_hwfn, false,
2933 "Emulation: Running on a REDUCED build\n");
2938 return ECORE_SUCCESS;
2941 #ifndef LINUX_REMOVE
2942 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
2949 for_each_hwfn(p_dev, j) {
2950 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2952 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2953 "Mark hw/fw uninitialized\n");
2955 p_hwfn->hw_init_done = false;
2956 p_hwfn->first_on_engine = false;
2958 ecore_ptt_invalidate(p_hwfn);
2963 static enum _ecore_status_t
2964 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview,
2965 void OSAL_IOMEM *p_doorbells,
2966 struct ecore_hw_prepare_params *p_params)
2968 struct ecore_dev *p_dev = p_hwfn->p_dev;
2969 struct ecore_mdump_info mdump_info;
2970 enum _ecore_status_t rc = ECORE_SUCCESS;
2972 /* Split PCI bars evenly between hwfns */
2973 p_hwfn->regview = p_regview;
2974 p_hwfn->doorbells = p_doorbells;
2977 return ecore_vf_hw_prepare(p_hwfn);
2979 /* Validate that chip access is feasible */
2980 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2982 "Reading the ME register returns all Fs; Preventing further chip access\n");
2986 get_function_id(p_hwfn);
2988 /* Allocate PTT pool */
2989 rc = ecore_ptt_pool_alloc(p_hwfn);
2991 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
2995 /* Allocate the main PTT */
2996 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2998 /* First hwfn learns basic information, e.g., number of hwfns */
2999 if (!p_hwfn->my_id) {
3000 rc = ecore_get_dev_info(p_dev);
3001 if (rc != ECORE_SUCCESS)
3005 ecore_hw_hwfn_prepare(p_hwfn);
3007 /* Initialize MCP structure */
3008 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3010 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3014 /* Read the device configuration information from the HW and SHMEM */
3015 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3016 p_params->personality, p_params->drv_resc_alloc);
3018 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3022 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3023 * called, since among others it sets the ports number in an engine.
3025 if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3026 !p_dev->recov_in_prog) {
3027 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3028 if (rc != ECORE_SUCCESS)
3029 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3032 /* Check if mdump logs are present and update the epoch value */
3033 if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) {
3034 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3036 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) {
3037 DP_NOTICE(p_hwfn, false,
3038 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3041 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3045 /* Allocate the init RT array and initialize the init-ops engine */
3046 rc = ecore_init_alloc(p_hwfn);
3048 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3052 if (CHIP_REV_IS_FPGA(p_dev)) {
3053 DP_NOTICE(p_hwfn, false,
3054 "FPGA: workaround; Prevent DMAE parities\n");
3055 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK, 7);
3057 DP_NOTICE(p_hwfn, false,
3058 "FPGA: workaround: Set VF bar0 size\n");
3059 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3060 PGLUE_B_REG_VF_BAR0_SIZE, 4);
3066 if (IS_LEAD_HWFN(p_hwfn))
3067 ecore_iov_free_hw_info(p_dev);
3068 ecore_mcp_free(p_hwfn);
3070 ecore_hw_hwfn_free(p_hwfn);
3075 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3076 struct ecore_hw_prepare_params *p_params)
3078 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3079 enum _ecore_status_t rc;
3081 p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3083 /* Store the precompiled init data ptrs */
3085 ecore_init_iro_array(p_dev);
3087 /* Initialize the first hwfn - will learn number of hwfns */
3088 rc = ecore_hw_prepare_single(p_hwfn,
3090 p_dev->doorbells, p_params);
3091 if (rc != ECORE_SUCCESS)
3094 p_params->personality = p_hwfn->hw_info.personality;
3096 /* initilalize 2nd hwfn if necessary */
3097 if (p_dev->num_hwfns > 1) {
3098 void OSAL_IOMEM *p_regview, *p_doorbell;
3099 u8 OSAL_IOMEM *addr;
3101 /* adjust bar offset for second engine */
3102 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3103 ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3104 p_regview = (void OSAL_IOMEM *)addr;
3106 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3107 ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3108 p_doorbell = (void OSAL_IOMEM *)addr;
3110 /* prepare second hw function */
3111 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3112 p_doorbell, p_params);
3114 /* in case of error, need to free the previously
3115 * initiliazed hwfn 0.
3117 if (rc != ECORE_SUCCESS) {
3119 ecore_init_free(p_hwfn);
3120 ecore_mcp_free(p_hwfn);
3121 ecore_hw_hwfn_free(p_hwfn);
3123 DP_NOTICE(p_dev, true,
3124 "What do we need to free when VF hwfn1 init fails\n");
3130 return ECORE_SUCCESS;
3133 void ecore_hw_remove(struct ecore_dev *p_dev)
3137 for_each_hwfn(p_dev, i) {
3138 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3141 ecore_vf_pf_release(p_hwfn);
3145 ecore_init_free(p_hwfn);
3146 ecore_hw_hwfn_free(p_hwfn);
3147 ecore_mcp_free(p_hwfn);
3149 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3152 ecore_iov_free_hw_info(p_dev);
3155 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3156 struct ecore_chain *p_chain)
3158 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3159 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3160 struct ecore_chain_next *p_next;
3166 size = p_chain->elem_size * p_chain->usable_per_page;
3168 for (i = 0; i < p_chain->page_cnt; i++) {
3172 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3173 p_virt_next = p_next->next_virt;
3174 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3176 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3177 ECORE_CHAIN_PAGE_SIZE);
3179 p_virt = p_virt_next;
3180 p_phys = p_phys_next;
3184 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3185 struct ecore_chain *p_chain)
3187 if (!p_chain->p_virt_addr)
3190 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3191 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3194 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3195 struct ecore_chain *p_chain)
3197 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3198 u8 *p_pbl_virt = (u8 *)p_chain->pbl.p_virt_table;
3199 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3201 if (!pp_virt_addr_tbl)
3204 if (!p_chain->pbl.p_virt_table)
3207 for (i = 0; i < page_cnt; i++) {
3208 if (!pp_virt_addr_tbl[i])
3211 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3212 *(dma_addr_t *)p_pbl_virt,
3213 ECORE_CHAIN_PAGE_SIZE);
3215 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3218 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3220 if (!p_chain->pbl.external)
3221 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table,
3222 p_chain->pbl.p_phys_table, pbl_size);
3224 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3227 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3229 switch (p_chain->mode) {
3230 case ECORE_CHAIN_MODE_NEXT_PTR:
3231 ecore_chain_free_next_ptr(p_dev, p_chain);
3233 case ECORE_CHAIN_MODE_SINGLE:
3234 ecore_chain_free_single(p_dev, p_chain);
3236 case ECORE_CHAIN_MODE_PBL:
3237 ecore_chain_free_pbl(p_dev, p_chain);
3242 static enum _ecore_status_t
3243 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3244 enum ecore_chain_cnt_type cnt_type,
3245 osal_size_t elem_size, u32 page_cnt)
3247 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3249 /* The actual chain size can be larger than the maximal possible value
3250 * after rounding up the requested elements number to pages, and after
3251 * taking into acount the unusuable elements (next-ptr elements).
3252 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3253 * size/capacity fields are of a u32 type.
3255 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3256 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3257 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3258 chain_size > ECORE_U32_MAX)) {
3259 DP_NOTICE(p_dev, true,
3260 "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3261 (unsigned long)chain_size);
3265 return ECORE_SUCCESS;
3268 static enum _ecore_status_t
3269 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3271 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3272 dma_addr_t p_phys = 0;
3275 for (i = 0; i < p_chain->page_cnt; i++) {
3276 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3277 ECORE_CHAIN_PAGE_SIZE);
3279 DP_NOTICE(p_dev, true,
3280 "Failed to allocate chain memory\n");
3285 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3286 ecore_chain_reset(p_chain);
3288 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3292 p_virt_prev = p_virt;
3294 /* Last page's next element should point to the beginning of the
3297 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3298 p_chain->p_virt_addr,
3299 p_chain->p_phys_addr);
3301 return ECORE_SUCCESS;
3304 static enum _ecore_status_t
3305 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3307 void *p_virt = OSAL_NULL;
3308 dma_addr_t p_phys = 0;
3310 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3312 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3316 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3317 ecore_chain_reset(p_chain);
3319 return ECORE_SUCCESS;
3322 static enum _ecore_status_t
3323 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3324 struct ecore_chain *p_chain,
3325 struct ecore_chain_ext_pbl *ext_pbl)
3327 void *p_virt = OSAL_NULL;
3328 u8 *p_pbl_virt = OSAL_NULL;
3329 void **pp_virt_addr_tbl = OSAL_NULL;
3330 dma_addr_t p_phys = 0, p_pbl_phys = 0;
3331 u32 page_cnt = p_chain->page_cnt, size, i;
3333 size = page_cnt * sizeof(*pp_virt_addr_tbl);
3334 pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
3335 if (!pp_virt_addr_tbl) {
3336 DP_NOTICE(p_dev, true,
3337 "Failed to allocate memory for the chain virtual addresses table\n");
3340 OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
3342 /* The allocation of the PBL table is done with its full size, since it
3343 * is expected to be successive.
3344 * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3345 * failure, since pp_virt_addr_tbl was previously allocated, and it
3346 * should be saved to allow its freeing during the error flow.
3348 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3350 if (ext_pbl == OSAL_NULL) {
3351 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3353 p_pbl_virt = ext_pbl->p_pbl_virt;
3354 p_pbl_phys = ext_pbl->p_pbl_phys;
3355 p_chain->pbl.external = true;
3358 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3361 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3365 for (i = 0; i < page_cnt; i++) {
3366 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3367 ECORE_CHAIN_PAGE_SIZE);
3369 DP_NOTICE(p_dev, true,
3370 "Failed to allocate chain memory\n");
3375 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3376 ecore_chain_reset(p_chain);
3379 /* Fill the PBL table with the physical address of the page */
3380 *(dma_addr_t *)p_pbl_virt = p_phys;
3381 /* Keep the virtual address of the page */
3382 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3384 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3387 return ECORE_SUCCESS;
3390 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3391 enum ecore_chain_use_mode intended_use,
3392 enum ecore_chain_mode mode,
3393 enum ecore_chain_cnt_type cnt_type,
3394 u32 num_elems, osal_size_t elem_size,
3395 struct ecore_chain *p_chain,
3396 struct ecore_chain_ext_pbl *ext_pbl)
3399 enum _ecore_status_t rc = ECORE_SUCCESS;
3401 if (mode == ECORE_CHAIN_MODE_SINGLE)
3404 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3406 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3409 DP_NOTICE(p_dev, true,
3410 "Cannot allocate a chain with the given arguments:\n"
3411 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3412 intended_use, mode, cnt_type, num_elems, elem_size);
3416 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3417 mode, cnt_type, p_dev->dp_ctx);
3420 case ECORE_CHAIN_MODE_NEXT_PTR:
3421 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3423 case ECORE_CHAIN_MODE_SINGLE:
3424 rc = ecore_chain_alloc_single(p_dev, p_chain);
3426 case ECORE_CHAIN_MODE_PBL:
3427 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
3433 return ECORE_SUCCESS;
3436 ecore_chain_free(p_dev, p_chain);
3440 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3441 u16 src_id, u16 *dst_id)
3443 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3446 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3447 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3448 DP_NOTICE(p_hwfn, true,
3449 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3455 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3457 return ECORE_SUCCESS;
3460 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3461 u8 src_id, u8 *dst_id)
3463 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3466 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3467 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3468 DP_NOTICE(p_hwfn, true,
3469 "vport id [%d] is not valid, available indices [%d - %d]\n",
3475 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3477 return ECORE_SUCCESS;
3480 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
3481 u8 src_id, u8 *dst_id)
3483 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
3486 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
3487 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
3488 DP_NOTICE(p_hwfn, true,
3489 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3495 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
3497 return ECORE_SUCCESS;
3500 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
3501 struct ecore_ptt *p_ptt,
3507 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3508 return ECORE_SUCCESS;
3510 high = p_filter[1] | (p_filter[0] << 8);
3511 low = p_filter[5] | (p_filter[4] << 8) |
3512 (p_filter[3] << 16) | (p_filter[2] << 24);
3514 /* Find a free entry and utilize it */
3515 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3516 en = ecore_rd(p_hwfn, p_ptt,
3517 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3520 ecore_wr(p_hwfn, p_ptt,
3521 NIG_REG_LLH_FUNC_FILTER_VALUE +
3522 2 * i * sizeof(u32), low);
3523 ecore_wr(p_hwfn, p_ptt,
3524 NIG_REG_LLH_FUNC_FILTER_VALUE +
3525 (2 * i + 1) * sizeof(u32), high);
3526 ecore_wr(p_hwfn, p_ptt,
3527 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3528 ecore_wr(p_hwfn, p_ptt,
3529 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3530 i * sizeof(u32), 0);
3531 ecore_wr(p_hwfn, p_ptt,
3532 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3535 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3536 DP_NOTICE(p_hwfn, false,
3537 "Failed to find an empty LLH filter to utilize\n");
3541 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3542 "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
3543 p_filter[0], p_filter[1], p_filter[2],
3544 p_filter[3], p_filter[4], p_filter[5], i);
3546 return ECORE_SUCCESS;
3549 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
3550 struct ecore_ptt *p_ptt, u8 *p_filter)
3555 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3558 high = p_filter[1] | (p_filter[0] << 8);
3559 low = p_filter[5] | (p_filter[4] << 8) |
3560 (p_filter[3] << 16) | (p_filter[2] << 24);
3562 /* Find the entry and clean it */
3563 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3564 if (ecore_rd(p_hwfn, p_ptt,
3565 NIG_REG_LLH_FUNC_FILTER_VALUE +
3566 2 * i * sizeof(u32)) != low)
3568 if (ecore_rd(p_hwfn, p_ptt,
3569 NIG_REG_LLH_FUNC_FILTER_VALUE +
3570 (2 * i + 1) * sizeof(u32)) != high)
3573 ecore_wr(p_hwfn, p_ptt,
3574 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3575 ecore_wr(p_hwfn, p_ptt,
3576 NIG_REG_LLH_FUNC_FILTER_VALUE +
3577 2 * i * sizeof(u32), 0);
3578 ecore_wr(p_hwfn, p_ptt,
3579 NIG_REG_LLH_FUNC_FILTER_VALUE +
3580 (2 * i + 1) * sizeof(u32), 0);
3583 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3584 DP_NOTICE(p_hwfn, false,
3585 "Tried to remove a non-configured filter\n");
3588 enum _ecore_status_t
3589 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
3590 struct ecore_ptt *p_ptt,
3591 u16 source_port_or_eth_type,
3593 enum ecore_llh_port_filter_type_t type)
3598 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3599 return ECORE_SUCCESS;
3604 case ECORE_LLH_FILTER_ETHERTYPE:
3605 high = source_port_or_eth_type;
3607 case ECORE_LLH_FILTER_TCP_SRC_PORT:
3608 case ECORE_LLH_FILTER_UDP_SRC_PORT:
3609 low = source_port_or_eth_type << 16;
3611 case ECORE_LLH_FILTER_TCP_DEST_PORT:
3612 case ECORE_LLH_FILTER_UDP_DEST_PORT:
3615 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3616 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3617 low = (source_port_or_eth_type << 16) | dest_port;
3620 DP_NOTICE(p_hwfn, true,
3621 "Non valid LLH protocol filter type %d\n", type);
3624 /* Find a free entry and utilize it */
3625 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3626 en = ecore_rd(p_hwfn, p_ptt,
3627 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3630 ecore_wr(p_hwfn, p_ptt,
3631 NIG_REG_LLH_FUNC_FILTER_VALUE +
3632 2 * i * sizeof(u32), low);
3633 ecore_wr(p_hwfn, p_ptt,
3634 NIG_REG_LLH_FUNC_FILTER_VALUE +
3635 (2 * i + 1) * sizeof(u32), high);
3636 ecore_wr(p_hwfn, p_ptt,
3637 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3638 ecore_wr(p_hwfn, p_ptt,
3639 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3640 i * sizeof(u32), 1 << type);
3641 ecore_wr(p_hwfn, p_ptt,
3642 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3645 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3646 DP_NOTICE(p_hwfn, false,
3647 "Failed to find an empty LLH filter to utilize\n");
3648 return ECORE_NORESOURCES;
3651 case ECORE_LLH_FILTER_ETHERTYPE:
3652 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3653 "ETH type %x is added at %d\n",
3654 source_port_or_eth_type, i);
3656 case ECORE_LLH_FILTER_TCP_SRC_PORT:
3657 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3658 "TCP src port %x is added at %d\n",
3659 source_port_or_eth_type, i);
3661 case ECORE_LLH_FILTER_UDP_SRC_PORT:
3662 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3663 "UDP src port %x is added at %d\n",
3664 source_port_or_eth_type, i);
3666 case ECORE_LLH_FILTER_TCP_DEST_PORT:
3667 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3668 "TCP dst port %x is added at %d\n", dest_port, i);
3670 case ECORE_LLH_FILTER_UDP_DEST_PORT:
3671 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3672 "UDP dst port %x is added at %d\n", dest_port, i);
3674 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3675 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3676 "TCP src/dst ports %x/%x are added at %d\n",
3677 source_port_or_eth_type, dest_port, i);
3679 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3680 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3681 "UDP src/dst ports %x/%x are added at %d\n",
3682 source_port_or_eth_type, dest_port, i);
3685 return ECORE_SUCCESS;
3689 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
3690 struct ecore_ptt *p_ptt,
3691 u16 source_port_or_eth_type,
3693 enum ecore_llh_port_filter_type_t type)
3698 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3704 case ECORE_LLH_FILTER_ETHERTYPE:
3705 high = source_port_or_eth_type;
3707 case ECORE_LLH_FILTER_TCP_SRC_PORT:
3708 case ECORE_LLH_FILTER_UDP_SRC_PORT:
3709 low = source_port_or_eth_type << 16;
3711 case ECORE_LLH_FILTER_TCP_DEST_PORT:
3712 case ECORE_LLH_FILTER_UDP_DEST_PORT:
3715 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3716 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3717 low = (source_port_or_eth_type << 16) | dest_port;
3720 DP_NOTICE(p_hwfn, true,
3721 "Non valid LLH protocol filter type %d\n", type);
3725 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3726 if (!ecore_rd(p_hwfn, p_ptt,
3727 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3729 if (!ecore_rd(p_hwfn, p_ptt,
3730 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3732 if (!(ecore_rd(p_hwfn, p_ptt,
3733 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3734 i * sizeof(u32)) & (1 << type)))
3736 if (ecore_rd(p_hwfn, p_ptt,
3737 NIG_REG_LLH_FUNC_FILTER_VALUE +
3738 2 * i * sizeof(u32)) != low)
3740 if (ecore_rd(p_hwfn, p_ptt,
3741 NIG_REG_LLH_FUNC_FILTER_VALUE +
3742 (2 * i + 1) * sizeof(u32)) != high)
3745 ecore_wr(p_hwfn, p_ptt,
3746 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3747 ecore_wr(p_hwfn, p_ptt,
3748 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3749 ecore_wr(p_hwfn, p_ptt,
3750 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3751 i * sizeof(u32), 0);
3752 ecore_wr(p_hwfn, p_ptt,
3753 NIG_REG_LLH_FUNC_FILTER_VALUE +
3754 2 * i * sizeof(u32), 0);
3755 ecore_wr(p_hwfn, p_ptt,
3756 NIG_REG_LLH_FUNC_FILTER_VALUE +
3757 (2 * i + 1) * sizeof(u32), 0);
3761 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3762 DP_NOTICE(p_hwfn, false,
3763 "Tried to remove a non-configured filter\n");
3766 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
3767 struct ecore_ptt *p_ptt)
3771 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3774 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3775 ecore_wr(p_hwfn, p_ptt,
3776 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3777 ecore_wr(p_hwfn, p_ptt,
3778 NIG_REG_LLH_FUNC_FILTER_VALUE +
3779 2 * i * sizeof(u32), 0);
3780 ecore_wr(p_hwfn, p_ptt,
3781 NIG_REG_LLH_FUNC_FILTER_VALUE +
3782 (2 * i + 1) * sizeof(u32), 0);
3786 enum _ecore_status_t
3787 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
3788 struct ecore_ptt *p_ptt)
3790 if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
3791 ecore_wr(p_hwfn, p_ptt,
3792 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
3793 1 << p_hwfn->abs_pf_id / 2);
3794 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
3795 return ECORE_SUCCESS;
3798 DP_NOTICE(p_hwfn, false,
3799 "This function can't be set as default\n");
3803 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
3804 struct ecore_ptt *p_ptt,
3805 u32 hw_addr, void *p_eth_qzone,
3806 osal_size_t eth_qzone_size,
3809 struct coalescing_timeset *p_coal_timeset;
3811 if (IS_VF(p_hwfn->p_dev)) {
3812 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n");
3816 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
3817 DP_NOTICE(p_hwfn, true,
3818 "Coalescing configuration not enabled\n");
3822 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
3823 p_coal_timeset = p_eth_qzone;
3824 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3825 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3826 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3828 return ECORE_SUCCESS;
3831 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
3832 struct ecore_ptt *p_ptt,
3833 u16 coalesce, u8 qid, u16 sb_id)
3835 struct ustorm_eth_queue_zone eth_qzone;
3838 enum _ecore_status_t rc;
3839 u8 timeset, timer_res;
3841 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3842 if (coalesce <= 0x7F) {
3844 } else if (coalesce <= 0xFF) {
3846 } else if (coalesce <= 0x1FF) {
3849 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3852 timeset = (u8)(coalesce >> timer_res);
3854 rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3855 if (rc != ECORE_SUCCESS)
3858 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
3859 if (rc != ECORE_SUCCESS)
3862 address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3864 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
3865 sizeof(struct ustorm_eth_queue_zone), timeset);
3866 if (rc != ECORE_SUCCESS)
3869 p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
3874 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
3875 struct ecore_ptt *p_ptt,
3876 u16 coalesce, u8 qid, u16 sb_id)
3878 struct xstorm_eth_queue_zone eth_qzone;
3881 enum _ecore_status_t rc;
3882 u8 timeset, timer_res;
3884 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3885 if (coalesce <= 0x7F) {
3887 } else if (coalesce <= 0xFF) {
3889 } else if (coalesce <= 0x1FF) {
3892 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3896 timeset = (u8)(coalesce >> timer_res);
3898 rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3899 if (rc != ECORE_SUCCESS)
3902 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
3903 if (rc != ECORE_SUCCESS)
3906 address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3908 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
3909 sizeof(struct xstorm_eth_queue_zone), timeset);
3910 if (rc != ECORE_SUCCESS)
3913 p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
3918 /* Calculate final WFQ values for all vports and configure it.
3919 * After this configuration each vport must have
3920 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
3922 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3923 struct ecore_ptt *p_ptt,
3926 struct init_qm_vport_params *vport_params;
3929 vport_params = p_hwfn->qm_info.qm_vport_params;
3931 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3932 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3934 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
3936 ecore_init_vport_wfq(p_hwfn, p_ptt,
3937 vport_params[i].first_tx_pq_id,
3938 vport_params[i].vport_wfq);
3943 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
3947 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3948 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3951 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3952 struct ecore_ptt *p_ptt,
3955 struct init_qm_vport_params *vport_params;
3958 vport_params = p_hwfn->qm_info.qm_vport_params;
3960 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3961 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
3962 ecore_init_vport_wfq(p_hwfn, p_ptt,
3963 vport_params[i].first_tx_pq_id,
3964 vport_params[i].vport_wfq);
3968 /* This function performs several validations for WFQ
3969 * configuration and required min rate for a given vport
3970 * 1. req_rate must be greater than one percent of min_pf_rate.
3971 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
3972 * rates to get less than one percent of min_pf_rate.
3973 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
3975 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
3976 u16 vport_id, u32 req_rate,
3979 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3980 int non_requested_count = 0, req_count = 0, i, num_vports;
3982 num_vports = p_hwfn->qm_info.num_vports;
3984 /* Accounting for the vports which are configured for WFQ explicitly */
3986 for (i = 0; i < num_vports; i++) {
3989 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
3991 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3992 total_req_min_rate += tmp_speed;
3996 /* Include current vport data as well */
3998 total_req_min_rate += req_rate;
3999 non_requested_count = num_vports - req_count;
4001 /* validate possible error cases */
4002 if (req_rate > min_pf_rate) {
4003 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4004 "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4005 vport_id, req_rate, min_pf_rate);
4009 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
4010 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4011 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4012 vport_id, req_rate, min_pf_rate);
4016 /* TBD - for number of vports greater than 100 */
4017 if (num_vports > ECORE_WFQ_UNIT) {
4018 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4019 "Number of vports is greater than %d\n",
4024 if (total_req_min_rate > min_pf_rate) {
4025 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4026 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4027 total_req_min_rate, min_pf_rate);
4031 /* Data left for non requested vports */
4032 total_left_rate = min_pf_rate - total_req_min_rate;
4033 left_rate_per_vp = total_left_rate / non_requested_count;
4035 /* validate if non requested get < 1% of min bw */
4036 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4037 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4038 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4039 left_rate_per_vp, min_pf_rate);
4043 /* now req_rate for given vport passes all scenarios.
4044 * assign final wfq rates to all vports.
4046 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4047 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4049 for (i = 0; i < num_vports; i++) {
4050 if (p_hwfn->qm_info.wfq_data[i].configured)
4053 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4056 return ECORE_SUCCESS;
4059 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4060 struct ecore_ptt *p_ptt,
4061 u16 vp_id, u32 rate)
4063 struct ecore_mcp_link_state *p_link;
4064 int rc = ECORE_SUCCESS;
4066 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4068 if (!p_link->min_pf_rate) {
4069 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4070 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4074 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4076 if (rc == ECORE_SUCCESS)
4077 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4078 p_link->min_pf_rate);
4080 DP_NOTICE(p_hwfn, false,
4081 "Validation failed while configuring min rate\n");
4086 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4087 struct ecore_ptt *p_ptt,
4090 bool use_wfq = false;
4091 int rc = ECORE_SUCCESS;
4094 /* Validate all pre configured vports for wfq */
4095 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4098 if (!p_hwfn->qm_info.wfq_data[i].configured)
4101 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4104 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4105 if (rc != ECORE_SUCCESS) {
4106 DP_NOTICE(p_hwfn, false,
4107 "WFQ validation failed while configuring min rate\n");
4112 if (rc == ECORE_SUCCESS && use_wfq)
4113 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4115 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4120 /* Main API for ecore clients to configure vport min rate.
4121 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4122 * rate - Speed in Mbps needs to be assigned to a given vport.
4124 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4126 int i, rc = ECORE_INVAL;
4128 /* TBD - for multiple hardware functions - that is 100 gig */
4129 if (p_dev->num_hwfns > 1) {
4130 DP_NOTICE(p_dev, false,
4131 "WFQ configuration is not supported for this device\n");
4135 for_each_hwfn(p_dev, i) {
4136 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4137 struct ecore_ptt *p_ptt;
4139 p_ptt = ecore_ptt_acquire(p_hwfn);
4141 return ECORE_TIMEOUT;
4143 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4145 if (rc != ECORE_SUCCESS) {
4146 ecore_ptt_release(p_hwfn, p_ptt);
4150 ecore_ptt_release(p_hwfn, p_ptt);
4156 /* API to configure WFQ from mcp link change */
4157 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4162 /* TBD - for multiple hardware functions - that is 100 gig */
4163 if (p_dev->num_hwfns > 1) {
4164 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4165 "WFQ configuration is not supported for this device\n");
4169 for_each_hwfn(p_dev, i) {
4170 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4172 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4178 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4179 struct ecore_ptt *p_ptt,
4180 struct ecore_mcp_link_state *p_link,
4183 int rc = ECORE_SUCCESS;
4185 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4187 if (!p_link->line_speed && (max_bw != 100))
4190 p_link->speed = (p_link->line_speed * max_bw) / 100;
4191 p_hwfn->qm_info.pf_rl = p_link->speed;
4193 /* Since the limiter also affects Tx-switched traffic, we don't want it
4194 * to limit such traffic in case there's no actual limit.
4195 * In that case, set limit to imaginary high boundary.
4198 p_hwfn->qm_info.pf_rl = 100000;
4200 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4201 p_hwfn->qm_info.pf_rl);
4203 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4204 "Configured MAX bandwidth to be %08x Mb/sec\n",
4210 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4211 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4213 int i, rc = ECORE_INVAL;
4215 if (max_bw < 1 || max_bw > 100) {
4216 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4220 for_each_hwfn(p_dev, i) {
4221 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4222 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4223 struct ecore_mcp_link_state *p_link;
4224 struct ecore_ptt *p_ptt;
4226 p_link = &p_lead->mcp_info->link_output;
4228 p_ptt = ecore_ptt_acquire(p_hwfn);
4230 return ECORE_TIMEOUT;
4232 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4235 ecore_ptt_release(p_hwfn, p_ptt);
4237 if (rc != ECORE_SUCCESS)
4244 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4245 struct ecore_ptt *p_ptt,
4246 struct ecore_mcp_link_state *p_link,
4249 int rc = ECORE_SUCCESS;
4251 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4252 p_hwfn->qm_info.pf_wfq = min_bw;
4254 if (!p_link->line_speed)
4257 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4259 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4261 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4262 "Configured MIN bandwidth to be %d Mb/sec\n",
4263 p_link->min_pf_rate);
4268 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4269 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4271 int i, rc = ECORE_INVAL;
4273 if (min_bw < 1 || min_bw > 100) {
4274 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4278 for_each_hwfn(p_dev, i) {
4279 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4280 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4281 struct ecore_mcp_link_state *p_link;
4282 struct ecore_ptt *p_ptt;
4284 p_link = &p_lead->mcp_info->link_output;
4286 p_ptt = ecore_ptt_acquire(p_hwfn);
4288 return ECORE_TIMEOUT;
4290 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4292 if (rc != ECORE_SUCCESS) {
4293 ecore_ptt_release(p_hwfn, p_ptt);
4297 if (p_link->min_pf_rate) {
4298 u32 min_rate = p_link->min_pf_rate;
4300 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4305 ecore_ptt_release(p_hwfn, p_ptt);
4311 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4313 struct ecore_mcp_link_state *p_link;
4315 p_link = &p_hwfn->mcp_info->link_output;
4317 if (p_link->min_pf_rate)
4318 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4319 p_link->min_pf_rate);
4321 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4322 sizeof(*p_hwfn->qm_info.wfq_data) *
4323 p_hwfn->qm_info.num_vports);
4326 int ecore_device_num_engines(struct ecore_dev *p_dev)
4328 return ECORE_IS_BB(p_dev) ? 2 : 1;
4331 int ecore_device_num_ports(struct ecore_dev *p_dev)
4333 /* in CMT always only one port */
4334 if (p_dev->num_hwfns > 1)
4337 return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
4340 void ecore_set_fw_mac_addr(__le16 *fw_msb,
4345 ((u8 *)fw_msb)[0] = mac[1];
4346 ((u8 *)fw_msb)[1] = mac[0];
4347 ((u8 *)fw_mid)[0] = mac[3];
4348 ((u8 *)fw_mid)[1] = mac[2];
4349 ((u8 *)fw_lsb)[0] = mac[5];
4350 ((u8 *)fw_lsb)[1] = mac[4];