2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_gtt_reg_addr.h"
13 #include "ecore_chain.h"
14 #include "ecore_status.h"
16 #include "ecore_rt_defs.h"
17 #include "ecore_init_ops.h"
18 #include "ecore_int.h"
19 #include "ecore_cxt.h"
20 #include "ecore_spq.h"
21 #include "ecore_init_fw_funcs.h"
22 #include "ecore_sp_commands.h"
23 #include "ecore_dev_api.h"
24 #include "ecore_sriov.h"
26 #include "ecore_mcp.h"
27 #include "ecore_hw_defs.h"
28 #include "mcp_public.h"
29 #include "ecore_iro.h"
31 #include "ecore_dev_api.h"
32 #include "ecore_dcbx.h"
34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
35 * registers involved are not split and thus configuration is a race where
36 * some of the PFs configuration might be lost.
37 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
38 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
39 * there's more than a single compiled ecore component in system].
41 static osal_spinlock_t qm_lock;
42 static bool qm_lock_init;
45 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to
46 * load the driver. The number was
51 #define ECORE_MIN_PWM_REGION ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
54 BAR_ID_0, /* used for GRC */
55 BAR_ID_1 /* Used for doorbells */
58 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
60 u32 bar_reg = (bar_id == BAR_ID_0 ?
61 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
64 if (IS_VF(p_hwfn->p_dev)) {
65 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
66 * read from actual register, but we're currently not using
67 * it for actual doorbelling.
72 val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
74 return 1 << (val + 15);
76 /* The above registers were updated in the past only in CMT mode. Since
77 * they were found to be useful MFW started updating them from 8.7.7.0.
78 * In older MFW versions they are set to 0 which means disabled.
80 if (p_hwfn->p_dev->num_hwfns > 1) {
81 DP_NOTICE(p_hwfn, false,
82 "BAR size not configured. Assuming BAR size of 256kB"
83 " for GRC and 512kB for DB\n");
84 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
86 DP_NOTICE(p_hwfn, false,
87 "BAR size not configured. Assuming BAR size of 512kB"
88 " for GRC and 512kB for DB\n");
95 void ecore_init_dp(struct ecore_dev *p_dev,
96 u32 dp_module, u8 dp_level, void *dp_ctx)
100 p_dev->dp_level = dp_level;
101 p_dev->dp_module = dp_module;
102 p_dev->dp_ctx = dp_ctx;
103 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
104 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
106 p_hwfn->dp_level = dp_level;
107 p_hwfn->dp_module = dp_module;
108 p_hwfn->dp_ctx = dp_ctx;
112 void ecore_init_struct(struct ecore_dev *p_dev)
116 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
117 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
119 p_hwfn->p_dev = p_dev;
121 p_hwfn->b_active = false;
123 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
124 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
127 /* hwfn 0 is always active */
128 p_dev->hwfns[0].b_active = true;
130 /* set the default cache alignment to 128 (may be overridden later) */
131 p_dev->cache_shift = 7;
134 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
136 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
138 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
139 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
140 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
141 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
144 void ecore_resc_free(struct ecore_dev *p_dev)
151 OSAL_FREE(p_dev, p_dev->fw_data);
153 OSAL_FREE(p_dev, p_dev->reset_stats);
155 for_each_hwfn(p_dev, i) {
156 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
158 OSAL_FREE(p_dev, p_hwfn->p_tx_cids);
159 OSAL_FREE(p_dev, p_hwfn->p_rx_cids);
162 for_each_hwfn(p_dev, i) {
163 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
165 ecore_cxt_mngr_free(p_hwfn);
166 ecore_qm_info_free(p_hwfn);
167 ecore_spq_free(p_hwfn);
168 ecore_eq_free(p_hwfn, p_hwfn->p_eq);
169 ecore_consq_free(p_hwfn, p_hwfn->p_consq);
170 ecore_int_free(p_hwfn);
171 #ifdef CONFIG_ECORE_LL2
172 ecore_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
174 ecore_iov_free(p_hwfn);
175 ecore_dmae_info_free(p_hwfn);
176 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
177 /* @@@TBD Flush work-queue ? */
181 static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn,
184 u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue;
185 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
186 struct init_qm_port_params *p_qm_port;
187 bool init_rdma_offload_pq = false;
188 bool init_pure_ack_pq = false;
189 bool init_ooo_pq = false;
190 u16 num_pqs, protocol_pqs;
196 /* @TMP - saving the existing min/max bw config before resetting the
197 * qm_info to restore them.
199 pf_rl = qm_info->pf_rl;
200 pf_wfq = qm_info->pf_wfq;
202 #ifdef CONFIG_ECORE_SRIOV
203 if (p_hwfn->p_dev->p_iov_info)
204 num_vfs = p_hwfn->p_dev->p_iov_info->total_vfs;
206 OSAL_MEM_ZERO(qm_info, sizeof(*qm_info));
209 /* @TMP - Don't allocate QM queues for VFs on emulation */
210 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
211 DP_NOTICE(p_hwfn, false,
212 "Emulation - skip configuring QM queues for VFs\n");
217 /* ethernet PFs require a pq per tc. Even if only a subset of the TCs
218 * active, we want physical queues allocated for all of them, since we
219 * don't have a good recycle flow. Non ethernet PFs require only a
220 * single physical queue.
222 if (ECORE_IS_L2_PERSONALITY(p_hwfn))
223 protocol_pqs = p_hwfn->hw_info.num_hw_tc;
227 num_pqs = protocol_pqs + num_vfs + 1; /* The '1' is for pure-LB */
228 num_vports = (u8)RESC_NUM(p_hwfn, ECORE_VPORT);
230 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
231 num_pqs++; /* for RoCE queue */
232 init_rdma_offload_pq = true;
233 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn) {
234 /* Due to FW assumption that rl==vport, we limit the
235 * number of rate limiters by the minimum between its
236 * allocated number and the allocated number of vports.
237 * Another limitation is the number of supported qps
238 * with rate limiters in FW.
241 (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
242 RESC_NUM(p_hwfn, ECORE_VPORT));
244 /* we subtract num_vfs because each one requires a rate
245 * limiter, and one default rate limiter.
247 if (num_pf_rls < num_vfs + 1) {
248 DP_ERR(p_hwfn, "No RL for DCQCN");
249 DP_ERR(p_hwfn, "[num_pf_rls %d num_vfs %d]\n",
250 num_pf_rls, num_vfs);
253 num_pf_rls -= num_vfs + 1;
256 num_pqs += num_pf_rls;
257 qm_info->num_pf_rls = (u8)num_pf_rls;
260 if (ECORE_IS_IWARP_PERSONALITY(p_hwfn)) {
261 num_pqs += 3; /* for iwarp queue / pure-ack / ooo */
262 init_rdma_offload_pq = true;
263 init_pure_ack_pq = true;
267 if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
268 num_pqs += 2; /* for iSCSI pure-ACK / OOO queue */
269 init_pure_ack_pq = true;
273 /* Sanity checking that setup requires legal number of resources */
274 if (num_pqs > RESC_NUM(p_hwfn, ECORE_PQ)) {
276 "Need too many Physical queues - 0x%04x avail %04x",
277 num_pqs, RESC_NUM(p_hwfn, ECORE_PQ));
281 /* PQs will be arranged as follows: First per-TC PQ, then pure-LB queue,
282 * then special queues (iSCSI pure-ACK / RoCE), then per-VF PQ.
284 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev,
285 b_sleepable ? GFP_KERNEL :
287 sizeof(struct init_qm_pq_params) *
289 if (!qm_info->qm_pq_params)
292 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev,
293 b_sleepable ? GFP_KERNEL :
296 init_qm_vport_params) *
298 if (!qm_info->qm_vport_params)
301 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev,
302 b_sleepable ? GFP_KERNEL :
304 sizeof(struct init_qm_port_params)
306 if (!qm_info->qm_port_params)
309 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev,
310 b_sleepable ? GFP_KERNEL :
312 sizeof(struct ecore_wfq_data) *
315 if (!qm_info->wfq_data)
318 vport_id = (u8)RESC_START(p_hwfn, ECORE_VPORT);
320 /* First init rate limited queues ( Due to RoCE assumption of
323 for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
324 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
325 qm_info->qm_pq_params[curr_queue].tc_id =
326 p_hwfn->hw_info.offload_tc;
327 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
328 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
332 for (i = 0; i < protocol_pqs; i++) {
333 struct init_qm_pq_params *params =
334 &qm_info->qm_pq_params[curr_queue++];
336 if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
337 params->vport_id = vport_id;
339 /* Note: this assumes that if we had a configuration
340 * with N tcs and subsequently another configuration
341 * With Fewer TCs, the in flight traffic (in QM queues,
342 * in FW, from driver to FW) will still trickle out and
343 * not get "stuck" in the QM. This is determined by the
344 * NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ. Unused TCs are
345 * supposed to be cleared in this map, allowing traffic
346 * to flush out. If this is not the case, we would need
347 * to set the TC of unused queues to 0, and reconfigure
348 * QM every time num of TCs changes. Unused queues in
349 * this context would mean those intended for TCs where
350 * tc_id > hw_info.num_active_tcs.
352 params->wrr_group = 1; /* @@@TBD ECORE_WRR_MEDIUM */
354 params->vport_id = vport_id;
355 params->tc_id = p_hwfn->hw_info.offload_tc;
356 params->wrr_group = 1; /* @@@TBD ECORE_WRR_MEDIUM */
360 /* Then init pure-LB PQ */
361 qm_info->pure_lb_pq = curr_queue;
362 qm_info->qm_pq_params[curr_queue].vport_id =
363 (u8)RESC_START(p_hwfn, ECORE_VPORT);
364 qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
365 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
368 qm_info->offload_pq = 0; /* Already initialized for iSCSI/FCoE */
369 if (init_rdma_offload_pq) {
370 qm_info->offload_pq = curr_queue;
371 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
372 qm_info->qm_pq_params[curr_queue].tc_id =
373 p_hwfn->hw_info.offload_tc;
374 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
378 if (init_pure_ack_pq) {
379 qm_info->pure_ack_pq = curr_queue;
380 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
381 qm_info->qm_pq_params[curr_queue].tc_id =
382 p_hwfn->hw_info.offload_tc;
383 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
388 qm_info->ooo_pq = curr_queue;
389 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
390 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
391 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
395 /* Then init per-VF PQs */
396 vf_offset = curr_queue;
397 for (i = 0; i < num_vfs; i++) {
398 /* First vport is used by the PF */
399 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
400 /* @@@TBD VF Multi-cos */
401 qm_info->qm_pq_params[curr_queue].tc_id = 0;
402 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
403 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
407 qm_info->vf_queues_offset = vf_offset;
408 qm_info->num_pqs = num_pqs;
409 qm_info->num_vports = num_vports;
411 /* Initialize qm port parameters */
412 num_ports = p_hwfn->p_dev->num_ports_in_engines;
413 for (i = 0; i < num_ports; i++) {
414 p_qm_port = &qm_info->qm_port_params[i];
415 p_qm_port->active = 1;
416 /* @@@TMP - was NUM_OF_PHYS_TCS; Changed until dcbx will
420 p_qm_port->active_phys_tcs = 0xf;
422 p_qm_port->active_phys_tcs = 0x9f;
423 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
424 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
427 if (ECORE_IS_AH(p_hwfn->p_dev) && (num_ports == 4))
428 qm_info->max_phys_tcs_per_port = NUM_PHYS_TCS_4PORT_K2;
430 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
432 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
434 qm_info->num_vf_pqs = num_vfs;
435 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
437 for (i = 0; i < qm_info->num_vports; i++)
438 qm_info->qm_vport_params[i].vport_wfq = 1;
440 qm_info->vport_rl_en = 1;
441 qm_info->vport_wfq_en = 1;
442 qm_info->pf_rl = pf_rl;
443 qm_info->pf_wfq = pf_wfq;
445 return ECORE_SUCCESS;
448 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
449 ecore_qm_info_free(p_hwfn);
453 /* This function reconfigures the QM pf on the fly.
454 * For this purpose we:
455 * 1. reconfigure the QM database
456 * 2. set new values to runtime arrat
457 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
458 * 4. activate init tool in QM_PF stage
459 * 5. send an sdm_qm_cmd through rbc interface to release the QM
461 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
462 struct ecore_ptt *p_ptt)
464 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
466 enum _ecore_status_t rc;
468 /* qm_info is allocated in ecore_init_qm_info() which is already called
469 * from ecore_resc_alloc() or previous call of ecore_qm_reconf().
470 * The allocated size may change each init, so we free it before next
473 ecore_qm_info_free(p_hwfn);
475 /* initialize ecore's qm data structure */
476 rc = ecore_init_qm_info(p_hwfn, false);
477 if (rc != ECORE_SUCCESS)
480 /* stop PF's qm queues */
481 OSAL_SPIN_LOCK(&qm_lock);
482 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
483 qm_info->start_pq, qm_info->num_pqs);
484 OSAL_SPIN_UNLOCK(&qm_lock);
488 /* clear the QM_PF runtime phase leftovers from previous init */
489 ecore_init_clear_rt_data(p_hwfn);
491 /* prepare QM portion of runtime array */
492 ecore_qm_init_pf(p_hwfn);
494 /* activate init tool on runtime array */
495 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
496 p_hwfn->hw_info.hw_mode);
497 if (rc != ECORE_SUCCESS)
500 /* start PF's qm queues */
501 OSAL_SPIN_LOCK(&qm_lock);
502 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
503 qm_info->start_pq, qm_info->num_pqs);
504 OSAL_SPIN_UNLOCK(&qm_lock);
508 return ECORE_SUCCESS;
511 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
513 struct ecore_consq *p_consq;
514 struct ecore_eq *p_eq;
515 #ifdef CONFIG_ECORE_LL2
516 struct ecore_ll2_info *p_ll2_info;
518 enum _ecore_status_t rc = ECORE_SUCCESS;
524 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
525 sizeof(*p_dev->fw_data));
529 /* Allocate Memory for the Queue->CID mapping */
530 for_each_hwfn(p_dev, i) {
531 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
532 u32 num_tx_conns = RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
533 int tx_size, rx_size;
535 /* @@@TMP - resc management, change to actual required size */
536 if (p_hwfn->pf_params.eth_pf_params.num_cons > num_tx_conns)
537 num_tx_conns = p_hwfn->pf_params.eth_pf_params.num_cons;
538 tx_size = sizeof(struct ecore_hw_cid_data) * num_tx_conns;
539 rx_size = sizeof(struct ecore_hw_cid_data) *
540 RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
542 p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
544 if (!p_hwfn->p_tx_cids) {
545 DP_NOTICE(p_hwfn, true,
546 "Failed to allocate memory for Tx Cids\n");
550 p_hwfn->p_rx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
552 if (!p_hwfn->p_rx_cids) {
553 DP_NOTICE(p_hwfn, true,
554 "Failed to allocate memory for Rx Cids\n");
559 for_each_hwfn(p_dev, i) {
560 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
561 u32 n_eqes, num_cons;
563 /* First allocate the context manager structure */
564 rc = ecore_cxt_mngr_alloc(p_hwfn);
568 /* Set the HW cid/tid numbers (in the contest manager)
569 * Must be done prior to any further computations.
571 rc = ecore_cxt_set_pf_params(p_hwfn);
575 /* Prepare and process QM requirements */
576 rc = ecore_init_qm_info(p_hwfn, true);
580 /* Compute the ILT client partition */
581 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
585 /* CID map / ILT shadow table / T2
586 * The talbes sizes are determined by the computations above
588 rc = ecore_cxt_tables_alloc(p_hwfn);
592 /* SPQ, must follow ILT because initializes SPQ context */
593 rc = ecore_spq_alloc(p_hwfn);
597 /* SP status block allocation */
598 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
601 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
605 rc = ecore_iov_alloc(p_hwfn);
610 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
611 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
612 /* Calculate the EQ size
613 * ---------------------
614 * Each ICID may generate up to one event at a time i.e.
615 * the event must be handled/cleared before a new one
616 * can be generated. We calculate the sum of events per
617 * protocol and create an EQ deep enough to handle the
619 * - Core - according to SPQ.
620 * - RoCE - per QP there are a couple of ICIDs, one
621 * responder and one requester, each can
622 * generate an EQE => n_eqes_qp = 2 * n_qp.
623 * Each CQ can generate an EQE. There are 2 CQs
624 * per QP => n_eqes_cq = 2 * n_qp.
625 * Hence the RoCE total is 4 * n_qp or
627 * - ENet - There can be up to two events per VF. One
628 * for VF-PF channel and another for VF FLR
629 * initial cleanup. The number of VFs is
630 * bounded by MAX_NUM_VFS_BB, and is much
631 * smaller than RoCE's so we avoid exact
634 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
636 ecore_cxt_get_proto_cid_count(
642 num_cons = ecore_cxt_get_proto_cid_count(
647 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
648 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
650 ecore_cxt_get_proto_cid_count(p_hwfn,
653 n_eqes += 2 * num_cons;
656 if (n_eqes > 0xFFFF) {
657 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
658 "The maximum of a u16 chain is 0x%x\n",
663 p_eq = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
668 p_consq = ecore_consq_alloc(p_hwfn);
671 p_hwfn->p_consq = p_consq;
673 #ifdef CONFIG_ECORE_LL2
674 if (p_hwfn->using_ll2) {
675 p_ll2_info = ecore_ll2_alloc(p_hwfn);
678 p_hwfn->p_ll2_info = p_ll2_info;
682 /* DMA info initialization */
683 rc = ecore_dmae_info_alloc(p_hwfn);
685 DP_NOTICE(p_hwfn, true,
686 "Failed to allocate memory for dmae_info structure\n");
690 /* DCBX initialization */
691 rc = ecore_dcbx_info_alloc(p_hwfn);
693 DP_NOTICE(p_hwfn, true,
694 "Failed to allocate memory for dcbx structure\n");
699 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
700 sizeof(*p_dev->reset_stats));
701 if (!p_dev->reset_stats) {
702 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
706 return ECORE_SUCCESS;
711 ecore_resc_free(p_dev);
715 void ecore_resc_setup(struct ecore_dev *p_dev)
722 for_each_hwfn(p_dev, i) {
723 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
725 ecore_cxt_mngr_setup(p_hwfn);
726 ecore_spq_setup(p_hwfn);
727 ecore_eq_setup(p_hwfn, p_hwfn->p_eq);
728 ecore_consq_setup(p_hwfn, p_hwfn->p_consq);
730 /* Read shadow of current MFW mailbox */
731 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
732 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
733 p_hwfn->mcp_info->mfw_mb_cur,
734 p_hwfn->mcp_info->mfw_mb_length);
736 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
738 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
739 #ifdef CONFIG_ECORE_LL2
740 if (p_hwfn->using_ll2)
741 ecore_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
746 #define FINAL_CLEANUP_POLL_CNT (100)
747 #define FINAL_CLEANUP_POLL_TIME (10)
748 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
749 struct ecore_ptt *p_ptt,
752 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
753 enum _ecore_status_t rc = ECORE_TIMEOUT;
756 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
757 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
758 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
759 return ECORE_SUCCESS;
763 addr = GTT_BAR0_MAP_REG_USDM_RAM +
764 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
769 command |= X_FINAL_CLEANUP_AGG_INT <<
770 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
771 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
772 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
773 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
775 /* Make sure notification is not set before initiating final cleanup */
777 if (REG_RD(p_hwfn, addr)) {
778 DP_NOTICE(p_hwfn, false,
779 "Unexpected; Found final cleanup notification");
780 DP_NOTICE(p_hwfn, false,
781 " before initiating final cleanup\n");
782 REG_WR(p_hwfn, addr, 0);
785 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
786 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
789 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
791 /* Poll until completion */
792 while (!REG_RD(p_hwfn, addr) && count--)
793 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
795 if (REG_RD(p_hwfn, addr))
798 DP_NOTICE(p_hwfn, true,
799 "Failed to receive FW final cleanup notification\n");
801 /* Cleanup afterwards */
802 REG_WR(p_hwfn, addr, 0);
807 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
811 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
812 hw_mode |= 1 << MODE_BB;
813 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
814 hw_mode |= 1 << MODE_K2;
816 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
817 p_hwfn->p_dev->type);
821 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
822 switch (p_hwfn->p_dev->num_ports_in_engines) {
824 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
827 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
830 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
833 DP_NOTICE(p_hwfn, true,
834 "num_ports_in_engine = %d not supported\n",
835 p_hwfn->p_dev->num_ports_in_engines);
839 switch (p_hwfn->p_dev->mf_mode) {
840 case ECORE_MF_DEFAULT:
842 hw_mode |= 1 << MODE_MF_SI;
845 hw_mode |= 1 << MODE_MF_SD;
848 DP_NOTICE(p_hwfn, true,
849 "Unsupported MF mode, init as DEFAULT\n");
850 hw_mode |= 1 << MODE_MF_SI;
854 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
855 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
856 hw_mode |= 1 << MODE_FPGA;
858 if (p_hwfn->p_dev->b_is_emul_full)
859 hw_mode |= 1 << MODE_EMUL_FULL;
861 hw_mode |= 1 << MODE_EMUL_REDUCED;
865 hw_mode |= 1 << MODE_ASIC;
867 if (p_hwfn->p_dev->num_hwfns > 1)
868 hw_mode |= 1 << MODE_100G;
870 p_hwfn->hw_info.hw_mode = hw_mode;
872 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
873 "Configuring function for hw_mode: 0x%08x\n",
874 p_hwfn->hw_info.hw_mode);
876 return ECORE_SUCCESS;
880 /* MFW-replacement initializations for non-ASIC */
881 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
882 struct ecore_ptt *p_ptt)
884 struct ecore_dev *p_dev = p_hwfn->p_dev;
888 if (CHIP_REV_IS_EMUL(p_dev)) {
889 if (ECORE_IS_AH(p_dev))
893 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
895 if (CHIP_REV_IS_EMUL(p_dev) &&
896 (ECORE_IS_AH(p_dev)))
897 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
900 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
901 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
902 if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
903 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
905 if (CHIP_REV_IS_EMUL(p_dev)) {
906 if (ECORE_IS_AH(p_dev)) {
907 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
908 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
909 (p_dev->num_ports_in_engines >> 1));
911 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
912 p_dev->num_ports_in_engines == 4 ? 0 : 3);
917 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
918 for (i = 0; i < 100; i++) {
920 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
924 DP_NOTICE(p_hwfn, true,
925 "RBC done failed to complete in PSWRQ2\n");
927 return ECORE_SUCCESS;
931 /* Init run time data for all PFs and their VFs on an engine.
932 * TBD - for VFs - Once we have parent PF info for each VF in
933 * shmem available as CAU requires knowledge of parent PF for each VF.
935 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
937 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
940 for_each_hwfn(p_dev, i) {
941 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
942 struct ecore_igu_info *p_igu_info;
943 struct ecore_igu_block *p_block;
944 struct cau_sb_entry sb_entry;
946 p_igu_info = p_hwfn->hw_info.p_igu_info;
948 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
950 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
955 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
956 p_block->function_id, 0, 0);
957 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
962 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
963 struct ecore_ptt *p_ptt,
966 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
967 struct ecore_dev *p_dev = p_hwfn->p_dev;
968 u8 vf_id, max_num_vfs;
971 enum _ecore_status_t rc = ECORE_SUCCESS;
973 ecore_init_cau_rt_data(p_dev);
975 /* Program GTT windows */
976 ecore_gtt_init(p_hwfn);
979 if (CHIP_REV_IS_EMUL(p_dev)) {
980 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
981 if (rc != ECORE_SUCCESS)
986 if (p_hwfn->mcp_info) {
987 if (p_hwfn->mcp_info->func_info.bandwidth_max)
988 qm_info->pf_rl_en = 1;
989 if (p_hwfn->mcp_info->func_info.bandwidth_min)
990 qm_info->pf_wfq_en = 1;
993 ecore_qm_common_rt_init(p_hwfn,
994 p_dev->num_ports_in_engines,
995 qm_info->max_phys_tcs_per_port,
996 qm_info->pf_rl_en, qm_info->pf_wfq_en,
997 qm_info->vport_rl_en, qm_info->vport_wfq_en,
998 qm_info->qm_port_params);
1000 ecore_cxt_hw_init_common(p_hwfn);
1002 /* Close gate from NIG to BRB/Storm; By default they are open, but
1003 * we close them to prevent NIG from passing data to reset blocks.
1004 * Should have been done in the ENGINE phase, but init-tool lacks
1005 * proper port-pretend capabilities.
1007 ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1008 ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1009 ecore_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
1010 ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1011 ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1012 ecore_port_unpretend(p_hwfn, p_ptt);
1014 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1015 if (rc != ECORE_SUCCESS)
1018 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1019 * need to decide with which value, maybe runtime
1021 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1022 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1024 if (ECORE_IS_BB(p_dev)) {
1025 /* Workaround clears ROCE search for all functions to prevent
1026 * involving non initialized function in processing ROCE packet.
1028 num_pfs = NUM_OF_ENG_PFS(p_dev);
1029 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1030 ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1031 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1032 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1034 /* pretend to original PF */
1035 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1038 /* Workaround for avoiding CCFC execution error when getting packets
1039 * with CRC errors, and allowing instead the invoking of the FW error
1041 * This is not done inside the init tool since it currently can't
1042 * perform a pretending to VFs.
1044 max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1045 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1046 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1047 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1048 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1049 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1050 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1051 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1053 /* pretend to original PF */
1054 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1060 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1061 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1063 #define PMEG_IF_BYTE_COUNT 8
1065 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1066 struct ecore_ptt *p_ptt,
1067 u32 addr, u64 data, u8 reg_type, u8 port)
1069 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1070 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1071 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1072 (8 << PMEG_IF_BYTE_COUNT),
1073 (reg_type << 25) | (addr << 8) | port,
1074 (u32)((data >> 32) & 0xffffffff),
1075 (u32)(data & 0xffffffff));
1077 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1078 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1079 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1080 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1081 (reg_type << 25) | (addr << 8) | port);
1082 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1083 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1084 (data >> 32) & 0xffffffff);
1087 #define XLPORT_MODE_REG (0x20a)
1088 #define XLPORT_MAC_CONTROL (0x210)
1089 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1090 #define XLPORT_ENABLE_REG (0x20b)
1092 #define XLMAC_CTRL (0x600)
1093 #define XLMAC_MODE (0x601)
1094 #define XLMAC_RX_MAX_SIZE (0x608)
1095 #define XLMAC_TX_CTRL (0x604)
1096 #define XLMAC_PAUSE_CTRL (0x60d)
1097 #define XLMAC_PFC_CTRL (0x60e)
1099 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1100 struct ecore_ptt *p_ptt)
1102 u8 loopback = 0, port = p_hwfn->port_id * 2;
1104 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1106 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1107 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1109 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1110 /* XLMAC: SOFT RESET */
1111 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1112 /* XLMAC: Port Speed >= 10Gbps */
1113 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1114 /* XLMAC: Max Size */
1115 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1116 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1117 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1119 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1120 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1121 0x30ffffc000ULL, 0, port);
1122 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1123 port); /* XLMAC: TX_EN, RX_EN */
1124 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1125 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1126 0x1003 | (loopback << 2), 0, port);
1127 /* Enabled Parallel PFC interface */
1128 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1130 /* XLPORT port enable */
1131 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1134 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1135 struct ecore_ptt *p_ptt)
1137 u8 port = p_hwfn->port_id;
1138 u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1140 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1142 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1143 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1145 CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1146 (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1148 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1149 1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1151 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1152 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1154 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1155 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1157 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1158 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1160 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1162 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1164 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1166 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1170 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1171 struct ecore_ptt *p_ptt)
1173 if (ECORE_IS_AH(p_hwfn->p_dev))
1174 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1176 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1179 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1180 struct ecore_ptt *p_ptt, u8 port)
1182 int port_offset = port ? 0x800 : 0;
1183 u32 xmac_rxctrl = 0;
1186 /* FIXME: move to common start */
1187 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1188 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
1190 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1191 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
1193 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1195 /* Set the number of ports on the Warp Core to 10G */
1196 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1198 /* Soft reset of XMAC */
1199 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1200 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1202 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1203 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1205 /* FIXME: move to common end */
1206 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1207 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1209 /* Set Max packet size: initialize XMAC block register for port 0 */
1210 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1212 /* CRC append for Tx packets: init XMAC block register for port 1 */
1213 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1215 /* Enable TX and RX: initialize XMAC block register for port 1 */
1216 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1217 XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1218 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1219 XMAC_REG_RX_CTRL_BB + port_offset);
1220 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1221 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1225 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1226 struct ecore_ptt *p_ptt,
1229 enum _ecore_status_t rc = ECORE_SUCCESS;
1231 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1233 if (rc != ECORE_SUCCESS)
1236 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1237 return ECORE_SUCCESS;
1239 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1240 if (ECORE_IS_AH(p_hwfn->p_dev))
1241 return ECORE_SUCCESS;
1242 else if (ECORE_IS_BB(p_hwfn->p_dev))
1243 ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
1244 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1245 if (p_hwfn->p_dev->num_hwfns > 1) {
1246 /* Activate OPTE in CMT */
1249 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1251 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1252 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1253 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1254 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1255 ecore_wr(p_hwfn, p_ptt,
1256 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1257 ecore_wr(p_hwfn, p_ptt,
1258 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1259 ecore_wr(p_hwfn, p_ptt,
1260 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1264 ecore_emul_link_init(p_hwfn, p_ptt);
1266 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1273 static enum _ecore_status_t
1274 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1275 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1277 u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1278 u32 dpi_bit_shift, dpi_count;
1281 /* Calculate DPI size
1282 * ------------------
1283 * The PWM region contains Doorbell Pages. The first is reserverd for
1284 * the kernel for, e.g, L2. The others are free to be used by non-
1285 * trusted applications, typically from user space. Each page, called a
1286 * doorbell page is sectioned into windows that allow doorbells to be
1287 * issued in parallel by the kernel/application. The size of such a
1288 * window (a.k.a. WID) is 1kB.
1290 * 1kB WID x N WIDS = DPI page size
1291 * DPI page size x N DPIs = PWM region size
1293 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1294 * in order to ensure that two applications won't share the same page.
1295 * It also must contain at least one WID per CPU to allow parallelism.
1296 * It also must be a power of 2, since it is stored as a bit shift.
1298 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1299 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1300 * containing 4 WIDs.
1302 dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1303 dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1304 dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1305 dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1306 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1308 dpi_count = pwm_region_size / dpi_page_size;
1310 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1311 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1314 p_hwfn->dpi_size = dpi_page_size;
1315 p_hwfn->dpi_count = dpi_count;
1317 /* Update registers */
1318 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1320 if (dpi_count < min_dpis)
1321 return ECORE_NORESOURCES;
1323 return ECORE_SUCCESS;
1326 enum ECORE_ROCE_EDPM_MODE {
1327 ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1328 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1329 ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1332 static enum _ecore_status_t
1333 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1334 struct ecore_ptt *p_ptt)
1336 u32 pwm_regsize, norm_regsize;
1337 u32 non_pwm_conn, min_addr_reg1;
1338 u32 db_bar_size, n_cpus;
1341 int rc = ECORE_SUCCESS;
1344 db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1345 if (p_hwfn->p_dev->num_hwfns > 1)
1348 /* Calculate doorbell regions
1349 * -----------------------------------
1350 * The doorbell BAR is made of two regions. The first is called normal
1351 * region and the second is called PWM region. In the normal region
1352 * each ICID has its own set of addresses so that writing to that
1353 * specific address identifies the ICID. In the Process Window Mode
1354 * region the ICID is given in the data written to the doorbell. The
1355 * above per PF register denotes the offset in the doorbell BAR in which
1356 * the PWM region begins.
1357 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1358 * non-PWM connection. The calculation below computes the total non-PWM
1359 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1360 * in units of 4,096 bytes.
1362 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1363 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1365 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1366 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1367 min_addr_reg1 = norm_regsize / 4096;
1368 pwm_regsize = db_bar_size - norm_regsize;
1370 /* Check that the normal and PWM sizes are valid */
1371 if (db_bar_size < norm_regsize) {
1372 DP_ERR(p_hwfn->p_dev,
1373 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1374 db_bar_size, norm_regsize);
1375 return ECORE_NORESOURCES;
1377 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1378 DP_ERR(p_hwfn->p_dev,
1379 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1380 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1382 return ECORE_NORESOURCES;
1385 /* Calculate number of DPIs */
1386 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1387 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1388 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1389 /* Either EDPM is mandatory, or we are attempting to allocate a
1392 n_cpus = OSAL_NUM_ACTIVE_CPU();
1393 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1396 cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1397 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1398 if (cond || p_hwfn->dcbx_no_edpm) {
1399 /* Either EDPM is disabled from user configuration, or it is
1400 * disabled via DCBx, or it is not mandatory and we failed to
1401 * allocated a WID per CPU.
1404 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1406 /* If we entered this flow due to DCBX then the DPM register is
1407 * already configured.
1412 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1413 norm_regsize, pwm_regsize);
1415 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1416 p_hwfn->dpi_size, p_hwfn->dpi_count,
1417 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1418 "disabled" : "enabled");
1420 /* Check return codes from above calls */
1423 "Failed to allocate enough DPIs\n");
1424 return ECORE_NORESOURCES;
1428 p_hwfn->dpi_start_offset = norm_regsize;
1430 /* Update registers */
1431 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1432 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1433 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1434 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1436 return ECORE_SUCCESS;
1439 static enum _ecore_status_t
1440 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1441 struct ecore_ptt *p_ptt,
1442 struct ecore_tunn_start_params *p_tunn,
1445 enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1447 u8 rel_pf_id = p_hwfn->rel_pf_id;
1449 enum _ecore_status_t rc = ECORE_SUCCESS;
1453 if (p_hwfn->mcp_info) {
1454 struct ecore_mcp_function_info *p_info;
1456 p_info = &p_hwfn->mcp_info->func_info;
1457 if (p_info->bandwidth_min)
1458 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1460 /* Update rate limit once we'll actually have a link */
1461 p_hwfn->qm_info.pf_rl = 100000;
1463 ecore_cxt_hw_init_pf(p_hwfn);
1465 ecore_int_igu_init_rt(p_hwfn);
1467 /* Set VLAN in NIG if needed */
1468 if (hw_mode & (1 << MODE_MF_SD)) {
1469 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1470 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1471 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1472 p_hwfn->hw_info.ovlan);
1475 /* Enable classification by MAC if needed */
1476 if (hw_mode & (1 << MODE_MF_SI)) {
1477 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1478 "Configuring TAGMAC_CLS_TYPE\n");
1479 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1483 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
1484 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1485 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1486 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1487 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1488 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1490 /* perform debug configuration when chip is out of reset */
1491 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1493 /* Cleanup chip from previous driver if such remains exist */
1494 rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1495 if (rc != ECORE_SUCCESS) {
1496 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1500 /* PF Init sequence */
1501 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1505 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1506 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1510 /* Pure runtime initializations - directly to the HW */
1511 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1513 /* PCI relaxed ordering causes a decrease in the performance on some
1514 * systems. Till a root cause is found, disable this attribute in the
1518 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1520 * DP_NOTICE(p_hwfn, true,
1521 * "Failed to find the PCIe Cap\n");
1524 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1525 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1526 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1529 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1533 /* enable interrupts */
1534 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1535 if (rc != ECORE_SUCCESS)
1538 /* send function start command */
1539 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1540 allow_npar_tx_switch);
1542 DP_NOTICE(p_hwfn, true,
1543 "Function start ramrod failed\n");
1545 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1546 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1547 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1549 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1550 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1552 ecore_wr(p_hwfn, p_ptt,
1553 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1556 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1557 "PRS_REG_SEARCH registers after start PFn\n");
1558 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1559 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1560 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1561 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1562 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1563 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1564 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1565 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1566 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1567 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1568 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1569 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1570 prs_reg = ecore_rd(p_hwfn, p_ptt,
1571 PRS_REG_SEARCH_TCP_FIRST_FRAG);
1572 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1573 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1575 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1576 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1577 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1583 static enum _ecore_status_t
1584 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1585 struct ecore_ptt *p_ptt, u8 enable)
1587 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1589 /* Change PF in PXP */
1590 ecore_wr(p_hwfn, p_ptt,
1591 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1593 /* wait until value is set - try for 1 second every 50us */
1594 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1595 val = ecore_rd(p_hwfn, p_ptt,
1596 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1603 if (val != set_val) {
1604 DP_NOTICE(p_hwfn, true,
1605 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1606 return ECORE_UNKNOWN_ERROR;
1609 return ECORE_SUCCESS;
1612 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1613 struct ecore_ptt *p_main_ptt)
1615 /* Read shadow of current MFW mailbox */
1616 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1617 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1618 p_hwfn->mcp_info->mfw_mb_cur,
1619 p_hwfn->mcp_info->mfw_mb_length);
1622 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1623 struct ecore_hw_init_params *p_params)
1625 enum _ecore_status_t rc = ECORE_SUCCESS, mfw_rc;
1626 u32 load_code, param, drv_mb_param;
1627 bool b_default_mtu = true;
1628 struct ecore_hwfn *p_hwfn;
1631 if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
1632 (p_dev->num_hwfns > 1)) {
1633 DP_NOTICE(p_dev, false,
1634 "MSI mode is not supported for CMT devices\n");
1639 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1640 if (rc != ECORE_SUCCESS)
1644 for_each_hwfn(p_dev, i) {
1645 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1647 /* If management didn't provide a default, set one of our own */
1648 if (!p_hwfn->hw_info.mtu) {
1649 p_hwfn->hw_info.mtu = 1500;
1650 b_default_mtu = false;
1654 p_hwfn->b_int_enabled = 1;
1658 /* Enable DMAE in PXP */
1659 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1660 if (rc != ECORE_SUCCESS)
1663 rc = ecore_calc_hw_mode(p_hwfn);
1664 if (rc != ECORE_SUCCESS)
1667 /* @@@TBD need to add here:
1668 * Check for fan failure
1671 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1673 DP_NOTICE(p_hwfn, true,
1674 "Failed sending LOAD_REQ command\n");
1679 * When coming back from hiberbate state, the registers from
1680 * which shadow is read initially are not initialized. It turns
1681 * out that these registers get initialized during the call to
1682 * ecore_mcp_load_req request. So we need to reread them here
1683 * to get the proper shadow register value.
1684 * Note: This is a workaround for the missing MFW
1685 * initialization. It may be removed once the implementation
1688 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1690 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1691 "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1694 /* Only relevant for recovery:
1695 * Clear the indication after the LOAD_REQ command is responded
1698 p_dev->recov_in_prog = false;
1700 p_hwfn->first_on_engine = (load_code ==
1701 FW_MSG_CODE_DRV_LOAD_ENGINE);
1703 if (!qm_lock_init) {
1704 OSAL_SPIN_LOCK_INIT(&qm_lock);
1705 qm_lock_init = true;
1708 switch (load_code) {
1709 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1710 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1711 p_hwfn->hw_info.hw_mode);
1715 case FW_MSG_CODE_DRV_LOAD_PORT:
1716 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1717 p_hwfn->hw_info.hw_mode);
1721 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1722 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1724 p_hwfn->hw_info.hw_mode,
1725 p_params->b_hw_start,
1727 p_params->allow_npar_tx_switch);
1734 if (rc != ECORE_SUCCESS)
1735 DP_NOTICE(p_hwfn, true,
1736 "init phase failed for loadcode 0x%x (rc %d)\n",
1739 /* ACK mfw regardless of success or failure of initialization */
1740 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1741 DRV_MSG_CODE_LOAD_DONE,
1742 0, &load_code, ¶m);
1743 if (rc != ECORE_SUCCESS)
1745 if (mfw_rc != ECORE_SUCCESS) {
1746 DP_NOTICE(p_hwfn, true,
1747 "Failed sending LOAD_DONE command\n");
1751 /* send DCBX attention request command */
1752 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1753 "sending phony dcbx set command to trigger DCBx attention handling\n");
1754 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1755 DRV_MSG_CODE_SET_DCBX,
1756 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1757 &load_code, ¶m);
1758 if (mfw_rc != ECORE_SUCCESS) {
1759 DP_NOTICE(p_hwfn, true,
1760 "Failed to send DCBX attention request\n");
1764 p_hwfn->hw_init_done = true;
1768 p_hwfn = ECORE_LEADING_HWFN(p_dev);
1769 drv_mb_param = (FW_MAJOR_VERSION << 24) |
1770 (FW_MINOR_VERSION << 16) |
1771 (FW_REVISION_VERSION << 8) |
1772 (FW_ENGINEERING_VERSION);
1773 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1774 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1775 drv_mb_param, &load_code, ¶m);
1776 if (rc != ECORE_SUCCESS)
1777 DP_INFO(p_hwfn, "Failed to update firmware version\n");
1780 rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
1781 p_hwfn->hw_info.mtu);
1782 if (rc != ECORE_SUCCESS)
1783 DP_INFO(p_hwfn, "Failed to update default mtu\n");
1785 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
1787 ECORE_OV_DRIVER_STATE_DISABLED);
1788 if (rc != ECORE_SUCCESS)
1789 DP_INFO(p_hwfn, "Failed to update driver state\n");
1795 #define ECORE_HW_STOP_RETRY_LIMIT (10)
1796 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
1797 struct ecore_hwfn *p_hwfn,
1798 struct ecore_ptt *p_ptt)
1803 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1804 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1805 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
1807 if ((!ecore_rd(p_hwfn, p_ptt,
1808 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1809 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1812 /* Dependent on number of connection/tasks, possibly
1813 * 1ms sleep is required between polls
1818 if (i < ECORE_HW_STOP_RETRY_LIMIT)
1821 DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
1822 " [Connection %02x Tasks %02x]\n",
1823 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1824 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1827 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
1831 for_each_hwfn(p_dev, j) {
1832 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1833 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1835 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1839 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
1841 enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
1844 for_each_hwfn(p_dev, j) {
1845 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1846 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1848 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
1851 ecore_vf_pf_int_cleanup(p_hwfn);
1855 /* mark the hw as uninitialized... */
1856 p_hwfn->hw_init_done = false;
1858 rc = ecore_sp_pf_stop(p_hwfn);
1860 DP_NOTICE(p_hwfn, true,
1861 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
1863 /* perform debug action after PF stop was sent */
1864 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
1866 /* close NIG to BRB gate */
1867 ecore_wr(p_hwfn, p_ptt,
1868 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1871 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1872 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1873 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1874 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1875 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1877 /* @@@TBD - clean transmission queues (5.b) */
1878 /* @@@TBD - clean BTB (5.c) */
1880 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1882 /* @@@TBD - verify DMAE requests are done (8) */
1884 /* Disable Attention Generation */
1885 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1886 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1887 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1888 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1889 /* Need to wait 1ms to guarantee SBs are cleared */
1894 /* Disable DMAE in PXP - in CMT, this should only be done for
1895 * first hw-function, and only after all transactions have
1896 * stopped for all active hw-functions.
1898 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
1899 p_dev->hwfns[0].p_main_ptt, false);
1900 if (t_rc != ECORE_SUCCESS)
1907 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
1911 for_each_hwfn(p_dev, j) {
1912 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1913 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1916 ecore_vf_pf_int_cleanup(p_hwfn);
1920 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1921 "Shutting down the fastpath\n");
1923 ecore_wr(p_hwfn, p_ptt,
1924 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1926 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1927 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1928 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1929 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1930 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1932 /* @@@TBD - clean transmission queues (5.b) */
1933 /* @@@TBD - clean BTB (5.c) */
1935 /* @@@TBD - verify DMAE requests are done (8) */
1937 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1938 /* Need to wait 1ms to guarantee SBs are cleared */
1943 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
1945 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1947 if (IS_VF(p_hwfn->p_dev))
1950 /* If roce info is allocated it means roce is initialized and should
1951 * be enabled in searcher.
1953 if (p_hwfn->p_rdma_info) {
1954 if (p_hwfn->b_rdma_enabled_in_prs)
1955 ecore_wr(p_hwfn, p_ptt,
1956 p_hwfn->rdma_prs_search_reg, 0x1);
1957 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
1960 /* Re-open incoming traffic */
1961 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1962 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1965 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
1966 struct ecore_ptt *p_ptt, u32 reg,
1969 u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
1971 if (assert_val != expected) {
1972 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
1974 return ECORE_UNKNOWN_ERROR;
1980 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
1982 enum _ecore_status_t rc = ECORE_SUCCESS;
1983 u32 unload_resp, unload_param;
1986 for_each_hwfn(p_dev, i) {
1987 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1990 rc = ecore_vf_pf_reset(p_hwfn);
1996 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
1998 /* Check for incorrect states */
1999 if (!p_dev->recov_in_prog) {
2000 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
2001 QM_REG_USG_CNT_PF_TX, 0);
2002 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
2003 QM_REG_USG_CNT_PF_OTHER, 0);
2004 /* @@@TBD - assert on incorrect xCFC values (10.b) */
2007 /* Disable PF in HW blocks */
2008 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2009 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
2011 if (p_dev->recov_in_prog) {
2012 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2013 "Recovery is in progress -> skip sending unload_req/done\n");
2017 /* Send unload command to MCP */
2018 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2019 DRV_MSG_CODE_UNLOAD_REQ,
2020 DRV_MB_PARAM_UNLOAD_WOL_MCP,
2021 &unload_resp, &unload_param);
2022 if (rc != ECORE_SUCCESS) {
2023 DP_NOTICE(p_hwfn, true,
2024 "ecore_hw_reset: UNLOAD_REQ failed\n");
2025 /* @@TBD - what to do? for now, assume ENG. */
2026 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
2029 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2030 DRV_MSG_CODE_UNLOAD_DONE,
2031 0, &unload_resp, &unload_param);
2032 if (rc != ECORE_SUCCESS) {
2034 true, "ecore_hw_reset: UNLOAD_DONE failed\n");
2035 /* @@@TBD - Should it really ASSERT here ? */
2043 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2044 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2046 ecore_ptt_pool_free(p_hwfn);
2047 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2050 /* Setup bar access */
2051 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2053 /* clear indirect access */
2054 if (ECORE_IS_AH(p_hwfn->p_dev)) {
2055 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2056 PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2057 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2058 PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2059 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2060 PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2061 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2062 PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2064 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2065 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2066 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2067 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2068 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2069 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2070 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2071 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2074 /* Clean Previous errors if such exist */
2075 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2076 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2078 /* enable internal target-read */
2079 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2080 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2083 static void get_function_id(struct ecore_hwfn *p_hwfn)
2086 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2087 PXP_PF_ME_OPAQUE_ADDR);
2089 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2091 /* Bits 16-19 from the ME registers are the pf_num */
2092 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2093 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2094 PXP_CONCRETE_FID_PFID);
2095 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2096 PXP_CONCRETE_FID_PORT);
2098 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2099 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2100 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2103 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2105 u32 *feat_num = p_hwfn->hw_info.feat_num;
2106 struct ecore_sb_cnt_info sb_cnt_info;
2107 int num_features = 1;
2109 /* L2 Queues require each: 1 status block. 1 L2 queue */
2110 feat_num[ECORE_PF_L2_QUE] =
2112 RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2113 RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2115 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2116 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2117 feat_num[ECORE_VF_L2_QUE] =
2119 RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2120 FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2121 sb_cnt_info.sb_iov_cnt);
2123 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2124 "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d num_features=%d\n",
2125 (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2126 (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2127 (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2128 RESC_NUM(p_hwfn, ECORE_SB),
2132 static enum resource_id_enum
2133 ecore_hw_get_mfw_res_id(enum ecore_resources res_id)
2135 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2139 mfw_res_id = RESOURCE_NUM_SB_E;
2141 case ECORE_L2_QUEUE:
2142 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2145 mfw_res_id = RESOURCE_NUM_VPORT_E;
2148 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2151 mfw_res_id = RESOURCE_NUM_PQ_E;
2154 mfw_res_id = RESOURCE_NUM_RL_E;
2158 /* Each VFC resource can accommodate both a MAC and a VLAN */
2159 mfw_res_id = RESOURCE_VFC_FILTER_E;
2162 mfw_res_id = RESOURCE_ILT_E;
2164 case ECORE_LL2_QUEUE:
2165 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2167 case ECORE_RDMA_CNQ_RAM:
2168 case ECORE_CMDQS_CQS:
2169 /* CNQ/CMDQS are the same resource */
2170 mfw_res_id = RESOURCE_CQS_E;
2172 case ECORE_RDMA_STATS_QUEUE:
2173 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2182 static u32 ecore_hw_get_dflt_resc_num(struct ecore_hwfn *p_hwfn,
2183 enum ecore_resources res_id)
2185 u8 num_funcs = p_hwfn->num_funcs_on_engine;
2186 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2187 struct ecore_sb_cnt_info sb_cnt_info;
2188 u32 dflt_resc_num = 0;
2192 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2193 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2194 dflt_resc_num = sb_cnt_info.sb_cnt;
2196 case ECORE_L2_QUEUE:
2197 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2198 MAX_NUM_L2_QUEUES_BB) / num_funcs;
2201 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2202 MAX_NUM_VPORTS_BB) / num_funcs;
2205 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2206 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2209 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2210 MAX_QM_TX_QUEUES_BB) / num_funcs;
2213 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2217 /* Each VFC resource can accommodate both a MAC and a VLAN */
2218 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2221 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2222 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2224 case ECORE_LL2_QUEUE:
2225 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2227 case ECORE_RDMA_CNQ_RAM:
2228 case ECORE_CMDQS_CQS:
2229 /* CNQ/CMDQS are the same resource */
2231 dflt_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2233 case ECORE_RDMA_STATS_QUEUE:
2235 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2236 MAX_NUM_VPORTS_BB) / num_funcs;
2242 return dflt_resc_num;
2245 static const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2250 case ECORE_L2_QUEUE:
2264 case ECORE_RDMA_CNQ_RAM:
2265 return "RDMA_CNQ_RAM";
2268 case ECORE_LL2_QUEUE:
2270 case ECORE_CMDQS_CQS:
2272 case ECORE_RDMA_STATS_QUEUE:
2273 return "RDMA_STATS_QUEUE";
2275 return "UNKNOWN_RESOURCE";
2279 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2280 enum ecore_resources res_id,
2281 bool drv_resc_alloc)
2283 u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
2284 u32 *p_resc_num, *p_resc_start;
2285 struct resource_info resc_info;
2286 enum _ecore_status_t rc;
2288 p_resc_num = &RESC_NUM(p_hwfn, res_id);
2289 p_resc_start = &RESC_START(p_hwfn, res_id);
2291 dflt_resc_num = ecore_hw_get_dflt_resc_num(p_hwfn, res_id);
2292 if (!dflt_resc_num) {
2294 "Failed to get default amount for resource %d [%s]\n",
2295 res_id, ecore_hw_get_resc_name(res_id));
2298 dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
2301 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2302 *p_resc_num = dflt_resc_num;
2303 *p_resc_start = dflt_resc_start;
2308 OSAL_MEM_ZERO(&resc_info, sizeof(resc_info));
2309 resc_info.res_id = ecore_hw_get_mfw_res_id(res_id);
2310 if (resc_info.res_id == RESOURCE_NUM_INVALID) {
2312 "Failed to match resource %d with MFW resources\n",
2317 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
2318 &mcp_resp, &mcp_param);
2319 if (rc != ECORE_SUCCESS) {
2320 DP_NOTICE(p_hwfn, true,
2321 "MFW response failure for an allocation request for"
2322 " resource %d [%s]\n",
2323 res_id, ecore_hw_get_resc_name(res_id));
2327 /* Default driver values are applied in the following cases:
2328 * - The resource allocation MB command is not supported by the MFW
2329 * - There is an internal error in the MFW while processing the request
2330 * - The resource ID is unknown to the MFW
2332 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
2333 mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
2336 "Resource %d [%s]: No allocation info was received"
2337 " [mcp_resp 0x%x]. Applying default values"
2338 " [num %d, start %d].\n",
2339 res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2340 dflt_resc_num, dflt_resc_start);
2342 *p_resc_num = dflt_resc_num;
2343 *p_resc_start = dflt_resc_start;
2347 /* TBD - remove this when revising the handling of the SB resource */
2348 if (res_id == ECORE_SB) {
2349 /* Excluding the slowpath SB */
2350 resc_info.size -= 1;
2351 resc_info.offset -= p_hwfn->enabled_func_idx;
2354 *p_resc_num = resc_info.size;
2355 *p_resc_start = resc_info.offset;
2357 if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2359 "Resource %d [%s]: MFW allocation [num %d, start %d] differs from default values [num %d, start %d]%s\n",
2360 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2361 *p_resc_start, dflt_resc_num, dflt_resc_start,
2362 drv_resc_alloc ? " - Applying default values" : "");
2363 if (drv_resc_alloc) {
2364 *p_resc_num = dflt_resc_num;
2365 *p_resc_start = dflt_resc_start;
2369 return ECORE_SUCCESS;
2372 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2373 bool drv_resc_alloc)
2375 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2376 enum _ecore_status_t rc;
2379 u32 *resc_start = p_hwfn->hw_info.resc_start;
2380 u32 *resc_num = p_hwfn->hw_info.resc_num;
2381 /* For AH, an equal share of the ILT lines between the maximal number of
2382 * PFs is not enough for RoCE. This would be solved by the future
2383 * resource allocation scheme, but isn't currently present for
2384 * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2385 * to work - the BB number of ILT lines divided by its max PFs number.
2387 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2390 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2391 rc = ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2392 if (rc != ECORE_SUCCESS)
2397 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2398 /* Reduced build contains less PQs */
2399 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2400 resc_num[ECORE_PQ] = 32;
2401 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2402 p_hwfn->enabled_func_idx;
2405 /* For AH emulation, since we have a possible maximal number of
2406 * 16 enabled PFs, in case there are not enough ILT lines -
2407 * allocate only first PF as RoCE and have all the other ETH
2408 * only with less ILT lines.
2410 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2411 resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2412 resc_num[ECORE_ILT],
2413 roce_min_ilt_lines);
2416 /* Correct the common ILT calculation if PF0 has more */
2417 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2418 p_hwfn->p_dev->b_is_emul_full &&
2419 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2420 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2421 resc_num[ECORE_ILT];
2424 /* Sanity for ILT */
2425 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2426 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2427 DP_NOTICE(p_hwfn, true,
2428 "Can't assign ILT pages [%08x,...,%08x]\n",
2429 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2435 ecore_hw_set_feat(p_hwfn);
2437 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2438 "The numbers for each resource are:\n");
2439 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2440 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2441 ecore_hw_get_resc_name(res_id),
2442 RESC_NUM(p_hwfn, res_id),
2443 RESC_START(p_hwfn, res_id));
2445 return ECORE_SUCCESS;
2448 static enum _ecore_status_t
2449 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2450 struct ecore_ptt *p_ptt,
2451 struct ecore_hw_prepare_params *p_params)
2453 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
2454 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2455 struct ecore_mcp_link_params *link;
2456 enum _ecore_status_t rc;
2458 /* Read global nvm_cfg address */
2459 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2461 /* Verify MCP has initialized it */
2462 if (!nvm_cfg_addr) {
2463 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2464 if (p_params->b_relaxed_probe)
2465 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
2469 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
2471 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2473 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2474 OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2477 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2479 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2480 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2481 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2482 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2484 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2485 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2487 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2488 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2490 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2491 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2493 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2494 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2496 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2497 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2499 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2500 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2502 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2503 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2505 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2506 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
2508 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2509 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2511 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2512 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2515 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2520 /* Read DCBX configuration */
2521 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2522 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2523 dcbx_mode = ecore_rd(p_hwfn, p_ptt,
2525 OFFSETOF(struct nvm_cfg1_port, generic_cont0));
2526 dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
2527 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
2528 switch (dcbx_mode) {
2529 case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
2530 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
2532 case NVM_CFG1_PORT_DCBX_MODE_CEE:
2533 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
2535 case NVM_CFG1_PORT_DCBX_MODE_IEEE:
2536 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
2539 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
2542 /* Read default link configuration */
2543 link = &p_hwfn->mcp_info->link_input;
2544 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2545 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2546 link_temp = ecore_rd(p_hwfn, p_ptt,
2548 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2549 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2550 link->speed.advertised_speeds = link_temp;
2552 link_temp = link->speed.advertised_speeds;
2553 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2555 link_temp = ecore_rd(p_hwfn, p_ptt,
2557 OFFSETOF(struct nvm_cfg1_port, link_settings));
2558 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2559 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2560 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2561 link->speed.autoneg = true;
2563 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2564 link->speed.forced_speed = 1000;
2566 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2567 link->speed.forced_speed = 10000;
2569 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2570 link->speed.forced_speed = 25000;
2572 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2573 link->speed.forced_speed = 40000;
2575 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2576 link->speed.forced_speed = 50000;
2578 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2579 link->speed.forced_speed = 100000;
2582 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
2585 p_hwfn->mcp_info->link_capabilities.default_speed =
2586 link->speed.forced_speed;
2587 p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2588 link->speed.autoneg;
2590 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2591 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2592 link->pause.autoneg = !!(link_temp &
2593 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2594 link->pause.forced_rx = !!(link_temp &
2595 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2596 link->pause.forced_tx = !!(link_temp &
2597 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2598 link->loopback_mode = 0;
2600 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2601 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2602 link->speed.forced_speed, link->speed.advertised_speeds,
2603 link->speed.autoneg, link->pause.autoneg);
2605 /* Read Multi-function information from shmem */
2606 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2607 OFFSETOF(struct nvm_cfg1, glob) +
2608 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
2610 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
2612 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2613 NVM_CFG1_GLOB_MF_MODE_OFFSET;
2616 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2617 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
2619 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2620 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
2622 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2623 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
2626 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2627 p_hwfn->p_dev->mf_mode);
2629 /* Read Multi-function information from shmem */
2630 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2631 OFFSETOF(struct nvm_cfg1, glob) +
2632 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
2634 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
2635 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2636 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
2637 &p_hwfn->hw_info.device_capabilities);
2638 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2639 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
2640 &p_hwfn->hw_info.device_capabilities);
2641 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2642 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
2643 &p_hwfn->hw_info.device_capabilities);
2644 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2645 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
2646 &p_hwfn->hw_info.device_capabilities);
2647 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
2648 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
2649 &p_hwfn->hw_info.device_capabilities);
2651 rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2652 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
2654 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
2660 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
2661 struct ecore_ptt *p_ptt)
2663 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2664 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2665 struct ecore_dev *p_dev = p_hwfn->p_dev;
2667 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2669 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2670 * in the other bits are selected.
2671 * Bits 1-15 are for functions 1-15, respectively, and their value is
2672 * '0' only for enabled functions (function 0 always exists and
2674 * In case of CMT in BB, only the "even" functions are enabled, and thus
2675 * the number of functions for both hwfns is learnt from the same bits.
2677 if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
2678 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
2679 MISCS_REG_FUNCTION_HIDE_BB_K2);
2681 reg_function_hide = 0;
2684 if (reg_function_hide & 0x1) {
2685 if (ECORE_IS_BB(p_dev)) {
2686 if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
2698 /* Get the number of the enabled functions on the engine */
2699 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2706 /* Get the PF index within the enabled functions */
2707 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2708 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2716 p_hwfn->num_funcs_on_engine = num_funcs;
2717 p_hwfn->enabled_func_idx = enabled_func_idx;
2720 if (CHIP_REV_IS_FPGA(p_dev)) {
2721 DP_NOTICE(p_hwfn, false,
2722 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
2723 p_hwfn->num_funcs_on_engine = 4;
2727 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2728 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2729 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
2730 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2733 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
2734 struct ecore_ptt *p_ptt)
2739 /* Read the port mode */
2740 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
2742 else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
2743 (p_hwfn->p_dev->num_hwfns > 1))
2744 /* In CMT on emulation, assume 1 port */
2748 port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
2750 if (port_mode < 3) {
2751 p_hwfn->p_dev->num_ports_in_engines = 1;
2752 } else if (port_mode <= 5) {
2753 p_hwfn->p_dev->num_ports_in_engines = 2;
2755 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
2756 p_hwfn->p_dev->num_ports_in_engines);
2758 /* Default num_ports_in_engines to something */
2759 p_hwfn->p_dev->num_ports_in_engines = 1;
2763 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
2764 struct ecore_ptt *p_ptt)
2769 p_hwfn->p_dev->num_ports_in_engines = 0;
2772 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2773 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
2774 switch ((port & 0xf000) >> 12) {
2776 p_hwfn->p_dev->num_ports_in_engines = 1;
2779 p_hwfn->p_dev->num_ports_in_engines = 2;
2782 p_hwfn->p_dev->num_ports_in_engines = 4;
2785 DP_NOTICE(p_hwfn, false,
2786 "Unknown port mode in ECO_RESERVED %08x\n",
2791 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2792 port = ecore_rd(p_hwfn, p_ptt,
2793 CNIG_REG_NIG_PORT0_CONF_K2_E5 +
2796 p_hwfn->p_dev->num_ports_in_engines++;
2800 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
2801 struct ecore_ptt *p_ptt)
2803 if (ECORE_IS_BB(p_hwfn->p_dev))
2804 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
2806 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
2809 static enum _ecore_status_t
2810 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2811 enum ecore_pci_personality personality,
2812 struct ecore_hw_prepare_params *p_params)
2814 bool drv_resc_alloc = p_params->drv_resc_alloc;
2815 enum _ecore_status_t rc;
2817 /* Since all information is common, only first hwfns should do this */
2818 if (IS_LEAD_HWFN(p_hwfn)) {
2819 rc = ecore_iov_hw_info(p_hwfn);
2820 if (rc != ECORE_SUCCESS) {
2821 if (p_params->b_relaxed_probe)
2822 p_params->p_relaxed_res =
2823 ECORE_HW_PREPARE_BAD_IOV;
2829 /* TODO In get_hw_info, amoungst others:
2830 * Get MCP FW revision and determine according to it the supported
2831 * featrues (e.g. DCB)
2833 * ecore_get_pcie_width_speed, WOL capability.
2834 * Number of global CQ-s (for storage
2836 ecore_hw_info_port_num(p_hwfn, p_ptt);
2839 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
2841 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
2842 if (rc != ECORE_SUCCESS)
2848 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
2849 if (rc != ECORE_SUCCESS) {
2850 if (p_params->b_relaxed_probe)
2851 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
2857 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
2859 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
2860 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
2863 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
2865 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
2866 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
2870 if (ecore_mcp_is_init(p_hwfn)) {
2871 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
2872 p_hwfn->hw_info.ovlan =
2873 p_hwfn->mcp_info->func_info.ovlan;
2875 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
2878 if (personality != ECORE_PCI_DEFAULT) {
2879 p_hwfn->hw_info.personality = personality;
2880 } else if (ecore_mcp_is_init(p_hwfn)) {
2881 enum ecore_pci_personality protocol;
2883 protocol = p_hwfn->mcp_info->func_info.protocol;
2884 p_hwfn->hw_info.personality = protocol;
2888 /* To overcome ILT lack for emulation, until at least until we'll have
2889 * a definite answer from system about it, allow only PF0 to be RoCE.
2891 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
2892 if (!p_hwfn->rel_pf_id)
2893 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
2895 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
2899 /* although in BB some constellations may support more than 4 tcs,
2900 * that can result in performance penalty in some cases. 4
2901 * represents a good tradeoff between performance and flexibility.
2903 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2905 /* start out with a single active tc. This can be increased either
2906 * by dcbx negotiation or by upper layer driver
2908 p_hwfn->hw_info.num_active_tc = 1;
2910 ecore_get_num_funcs(p_hwfn, p_ptt);
2912 if (ecore_mcp_is_init(p_hwfn))
2913 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
2915 /* In case of forcing the driver's default resource allocation, calling
2916 * ecore_hw_get_resc() should come after initializing the personality
2917 * and after getting the number of functions, since the calculation of
2918 * the resources/features depends on them.
2919 * This order is not harmful if not forcing.
2921 rc = ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
2922 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
2924 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
2930 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
2932 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2935 /* Read Vendor Id / Device Id */
2936 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
2938 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
2941 /* Determine type */
2942 if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
2943 p_dev->type = ECORE_DEV_TYPE_AH;
2945 p_dev->type = ECORE_DEV_TYPE_BB;
2947 p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2948 MISCS_REG_CHIP_NUM);
2949 p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2950 MISCS_REG_CHIP_REV);
2952 MASK_FIELD(CHIP_REV, p_dev->chip_rev);
2954 /* Learn number of HW-functions */
2955 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2956 MISCS_REG_CMT_ENABLED_FOR_PAIR);
2958 if (tmp & (1 << p_hwfn->rel_pf_id)) {
2959 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
2960 p_dev->num_hwfns = 2;
2962 p_dev->num_hwfns = 1;
2966 if (CHIP_REV_IS_EMUL(p_dev)) {
2967 /* For some reason we have problems with this register
2968 * in B0 emulation; Simply assume no CMT
2970 DP_NOTICE(p_dev->hwfns, false,
2971 "device on emul - assume no CMT\n");
2972 p_dev->num_hwfns = 1;
2976 p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2977 MISCS_REG_CHIP_TEST_REG) >> 4;
2978 MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
2979 p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2980 MISCS_REG_CHIP_METAL);
2981 MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
2982 DP_INFO(p_dev->hwfns,
2983 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2984 ECORE_IS_BB(p_dev) ? "BB" : "AH",
2985 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
2986 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
2989 if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
2990 DP_NOTICE(p_dev->hwfns, false,
2991 "The chip type/rev (BB A0) is not supported!\n");
2992 return ECORE_ABORTED;
2995 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
2996 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2997 MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
2999 if (CHIP_REV_IS_EMUL(p_dev)) {
3000 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3001 MISCS_REG_ECO_RESERVED);
3002 if (tmp & (1 << 29)) {
3003 DP_NOTICE(p_hwfn, false,
3004 "Emulation: Running on a FULL build\n");
3005 p_dev->b_is_emul_full = true;
3007 DP_NOTICE(p_hwfn, false,
3008 "Emulation: Running on a REDUCED build\n");
3013 return ECORE_SUCCESS;
3016 #ifndef LINUX_REMOVE
3017 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3024 for_each_hwfn(p_dev, j) {
3025 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3027 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
3028 "Mark hw/fw uninitialized\n");
3030 p_hwfn->hw_init_done = false;
3031 p_hwfn->first_on_engine = false;
3033 ecore_ptt_invalidate(p_hwfn);
3038 static enum _ecore_status_t
3039 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
3040 void OSAL_IOMEM * p_regview,
3041 void OSAL_IOMEM * p_doorbells,
3042 struct ecore_hw_prepare_params *p_params)
3044 struct ecore_dev *p_dev = p_hwfn->p_dev;
3045 struct ecore_mdump_info mdump_info;
3046 enum _ecore_status_t rc = ECORE_SUCCESS;
3048 /* Split PCI bars evenly between hwfns */
3049 p_hwfn->regview = p_regview;
3050 p_hwfn->doorbells = p_doorbells;
3053 return ecore_vf_hw_prepare(p_hwfn);
3055 /* Validate that chip access is feasible */
3056 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3058 "Reading the ME register returns all Fs; Preventing further chip access\n");
3059 if (p_params->b_relaxed_probe)
3060 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
3064 get_function_id(p_hwfn);
3066 /* Allocate PTT pool */
3067 rc = ecore_ptt_pool_alloc(p_hwfn);
3069 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
3070 if (p_params->b_relaxed_probe)
3071 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3075 /* Allocate the main PTT */
3076 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3078 /* First hwfn learns basic information, e.g., number of hwfns */
3079 if (!p_hwfn->my_id) {
3080 rc = ecore_get_dev_info(p_dev);
3081 if (rc != ECORE_SUCCESS) {
3082 if (p_params->b_relaxed_probe)
3083 p_params->p_relaxed_res =
3084 ECORE_HW_PREPARE_FAILED_DEV;
3089 ecore_hw_hwfn_prepare(p_hwfn);
3091 /* Initialize MCP structure */
3092 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3094 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3095 if (p_params->b_relaxed_probe)
3096 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3100 /* Read the device configuration information from the HW and SHMEM */
3101 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3102 p_params->personality, p_params);
3104 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3108 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3109 * called, since among others it sets the ports number in an engine.
3111 if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3112 !p_dev->recov_in_prog) {
3113 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3114 if (rc != ECORE_SUCCESS)
3115 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3118 /* Check if mdump logs are present and update the epoch value */
3119 if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) {
3120 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3122 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) {
3123 DP_NOTICE(p_hwfn, false,
3124 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3127 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3131 /* Allocate the init RT array and initialize the init-ops engine */
3132 rc = ecore_init_alloc(p_hwfn);
3134 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3135 if (p_params->b_relaxed_probe)
3136 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3140 if (CHIP_REV_IS_FPGA(p_dev)) {
3141 DP_NOTICE(p_hwfn, false,
3142 "FPGA: workaround; Prevent DMAE parities\n");
3143 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
3146 DP_NOTICE(p_hwfn, false,
3147 "FPGA: workaround: Set VF bar0 size\n");
3148 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3149 PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
3155 if (IS_LEAD_HWFN(p_hwfn))
3156 ecore_iov_free_hw_info(p_dev);
3157 ecore_mcp_free(p_hwfn);
3159 ecore_hw_hwfn_free(p_hwfn);
3164 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3165 struct ecore_hw_prepare_params *p_params)
3167 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3168 enum _ecore_status_t rc;
3170 p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3172 if (p_params->b_relaxed_probe)
3173 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
3175 /* Store the precompiled init data ptrs */
3177 ecore_init_iro_array(p_dev);
3179 /* Initialize the first hwfn - will learn number of hwfns */
3180 rc = ecore_hw_prepare_single(p_hwfn,
3182 p_dev->doorbells, p_params);
3183 if (rc != ECORE_SUCCESS)
3186 p_params->personality = p_hwfn->hw_info.personality;
3188 /* initilalize 2nd hwfn if necessary */
3189 if (p_dev->num_hwfns > 1) {
3190 void OSAL_IOMEM *p_regview, *p_doorbell;
3191 u8 OSAL_IOMEM *addr;
3193 /* adjust bar offset for second engine */
3194 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3195 ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3196 p_regview = (void OSAL_IOMEM *)addr;
3198 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3199 ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3200 p_doorbell = (void OSAL_IOMEM *)addr;
3202 /* prepare second hw function */
3203 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3204 p_doorbell, p_params);
3206 /* in case of error, need to free the previously
3207 * initiliazed hwfn 0.
3209 if (rc != ECORE_SUCCESS) {
3210 if (p_params->b_relaxed_probe)
3211 p_params->p_relaxed_res =
3212 ECORE_HW_PREPARE_FAILED_ENG2;
3215 ecore_init_free(p_hwfn);
3216 ecore_mcp_free(p_hwfn);
3217 ecore_hw_hwfn_free(p_hwfn);
3219 DP_NOTICE(p_dev, true,
3220 "What do we need to free when VF hwfn1 init fails\n");
3229 void ecore_hw_remove(struct ecore_dev *p_dev)
3231 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3235 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3236 ECORE_OV_DRIVER_STATE_NOT_LOADED);
3238 for_each_hwfn(p_dev, i) {
3239 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3242 ecore_vf_pf_release(p_hwfn);
3246 ecore_init_free(p_hwfn);
3247 ecore_hw_hwfn_free(p_hwfn);
3248 ecore_mcp_free(p_hwfn);
3250 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3253 ecore_iov_free_hw_info(p_dev);
3256 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3257 struct ecore_chain *p_chain)
3259 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3260 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3261 struct ecore_chain_next *p_next;
3267 size = p_chain->elem_size * p_chain->usable_per_page;
3269 for (i = 0; i < p_chain->page_cnt; i++) {
3273 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3274 p_virt_next = p_next->next_virt;
3275 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3277 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3278 ECORE_CHAIN_PAGE_SIZE);
3280 p_virt = p_virt_next;
3281 p_phys = p_phys_next;
3285 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3286 struct ecore_chain *p_chain)
3288 if (!p_chain->p_virt_addr)
3291 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3292 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3295 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3296 struct ecore_chain *p_chain)
3298 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3299 u8 *p_pbl_virt = (u8 *)p_chain->pbl.p_virt_table;
3300 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3302 if (!pp_virt_addr_tbl)
3305 if (!p_chain->pbl.p_virt_table)
3308 for (i = 0; i < page_cnt; i++) {
3309 if (!pp_virt_addr_tbl[i])
3312 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3313 *(dma_addr_t *)p_pbl_virt,
3314 ECORE_CHAIN_PAGE_SIZE);
3316 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3319 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3321 if (!p_chain->pbl.external)
3322 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table,
3323 p_chain->pbl.p_phys_table, pbl_size);
3325 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3328 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3330 switch (p_chain->mode) {
3331 case ECORE_CHAIN_MODE_NEXT_PTR:
3332 ecore_chain_free_next_ptr(p_dev, p_chain);
3334 case ECORE_CHAIN_MODE_SINGLE:
3335 ecore_chain_free_single(p_dev, p_chain);
3337 case ECORE_CHAIN_MODE_PBL:
3338 ecore_chain_free_pbl(p_dev, p_chain);
3343 static enum _ecore_status_t
3344 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3345 enum ecore_chain_cnt_type cnt_type,
3346 osal_size_t elem_size, u32 page_cnt)
3348 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3350 /* The actual chain size can be larger than the maximal possible value
3351 * after rounding up the requested elements number to pages, and after
3352 * taking into acount the unusuable elements (next-ptr elements).
3353 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3354 * size/capacity fields are of a u32 type.
3356 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3357 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3358 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3359 chain_size > ECORE_U32_MAX)) {
3360 DP_NOTICE(p_dev, true,
3361 "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3362 (unsigned long)chain_size);
3366 return ECORE_SUCCESS;
3369 static enum _ecore_status_t
3370 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3372 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3373 dma_addr_t p_phys = 0;
3376 for (i = 0; i < p_chain->page_cnt; i++) {
3377 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3378 ECORE_CHAIN_PAGE_SIZE);
3380 DP_NOTICE(p_dev, true,
3381 "Failed to allocate chain memory\n");
3386 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3387 ecore_chain_reset(p_chain);
3389 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3393 p_virt_prev = p_virt;
3395 /* Last page's next element should point to the beginning of the
3398 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3399 p_chain->p_virt_addr,
3400 p_chain->p_phys_addr);
3402 return ECORE_SUCCESS;
3405 static enum _ecore_status_t
3406 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3408 dma_addr_t p_phys = 0;
3409 void *p_virt = OSAL_NULL;
3411 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3413 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3417 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3418 ecore_chain_reset(p_chain);
3420 return ECORE_SUCCESS;
3423 static enum _ecore_status_t
3424 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3425 struct ecore_chain *p_chain,
3426 struct ecore_chain_ext_pbl *ext_pbl)
3428 void *p_virt = OSAL_NULL;
3429 u8 *p_pbl_virt = OSAL_NULL;
3430 void **pp_virt_addr_tbl = OSAL_NULL;
3431 dma_addr_t p_phys = 0, p_pbl_phys = 0;
3432 u32 page_cnt = p_chain->page_cnt, size, i;
3434 size = page_cnt * sizeof(*pp_virt_addr_tbl);
3435 pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
3436 if (!pp_virt_addr_tbl) {
3437 DP_NOTICE(p_dev, true,
3438 "Failed to allocate memory for the chain virtual addresses table\n");
3441 OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
3443 /* The allocation of the PBL table is done with its full size, since it
3444 * is expected to be successive.
3445 * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3446 * failure, since pp_virt_addr_tbl was previously allocated, and it
3447 * should be saved to allow its freeing during the error flow.
3449 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3451 if (ext_pbl == OSAL_NULL) {
3452 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3454 p_pbl_virt = ext_pbl->p_pbl_virt;
3455 p_pbl_phys = ext_pbl->p_pbl_phys;
3456 p_chain->pbl.external = true;
3459 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3462 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3466 for (i = 0; i < page_cnt; i++) {
3467 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3468 ECORE_CHAIN_PAGE_SIZE);
3470 DP_NOTICE(p_dev, true,
3471 "Failed to allocate chain memory\n");
3476 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3477 ecore_chain_reset(p_chain);
3480 /* Fill the PBL table with the physical address of the page */
3481 *(dma_addr_t *)p_pbl_virt = p_phys;
3482 /* Keep the virtual address of the page */
3483 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3485 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3488 return ECORE_SUCCESS;
3491 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3492 enum ecore_chain_use_mode intended_use,
3493 enum ecore_chain_mode mode,
3494 enum ecore_chain_cnt_type cnt_type,
3495 u32 num_elems, osal_size_t elem_size,
3496 struct ecore_chain *p_chain,
3497 struct ecore_chain_ext_pbl *ext_pbl)
3500 enum _ecore_status_t rc = ECORE_SUCCESS;
3502 if (mode == ECORE_CHAIN_MODE_SINGLE)
3505 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3507 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3510 DP_NOTICE(p_dev, true,
3511 "Cannot allocate a chain with the given arguments:\n"
3512 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3513 intended_use, mode, cnt_type, num_elems, elem_size);
3517 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3518 mode, cnt_type, p_dev->dp_ctx);
3521 case ECORE_CHAIN_MODE_NEXT_PTR:
3522 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3524 case ECORE_CHAIN_MODE_SINGLE:
3525 rc = ecore_chain_alloc_single(p_dev, p_chain);
3527 case ECORE_CHAIN_MODE_PBL:
3528 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
3534 return ECORE_SUCCESS;
3537 ecore_chain_free(p_dev, p_chain);
3541 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3542 u16 src_id, u16 *dst_id)
3544 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3547 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3548 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3549 DP_NOTICE(p_hwfn, true,
3550 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3556 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3558 return ECORE_SUCCESS;
3561 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3562 u8 src_id, u8 *dst_id)
3564 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3567 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3568 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3569 DP_NOTICE(p_hwfn, true,
3570 "vport id [%d] is not valid, available indices [%d - %d]\n",
3576 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3578 return ECORE_SUCCESS;
3581 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
3582 u8 src_id, u8 *dst_id)
3584 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
3587 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
3588 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
3589 DP_NOTICE(p_hwfn, true,
3590 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3596 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
3598 return ECORE_SUCCESS;
3601 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
3602 struct ecore_ptt *p_ptt,
3608 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3609 return ECORE_SUCCESS;
3611 high = p_filter[1] | (p_filter[0] << 8);
3612 low = p_filter[5] | (p_filter[4] << 8) |
3613 (p_filter[3] << 16) | (p_filter[2] << 24);
3615 /* Find a free entry and utilize it */
3616 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3617 en = ecore_rd(p_hwfn, p_ptt,
3618 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3621 ecore_wr(p_hwfn, p_ptt,
3622 NIG_REG_LLH_FUNC_FILTER_VALUE +
3623 2 * i * sizeof(u32), low);
3624 ecore_wr(p_hwfn, p_ptt,
3625 NIG_REG_LLH_FUNC_FILTER_VALUE +
3626 (2 * i + 1) * sizeof(u32), high);
3627 ecore_wr(p_hwfn, p_ptt,
3628 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3629 ecore_wr(p_hwfn, p_ptt,
3630 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3631 i * sizeof(u32), 0);
3632 ecore_wr(p_hwfn, p_ptt,
3633 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3636 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3637 DP_NOTICE(p_hwfn, false,
3638 "Failed to find an empty LLH filter to utilize\n");
3642 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3643 "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
3644 p_filter[0], p_filter[1], p_filter[2],
3645 p_filter[3], p_filter[4], p_filter[5], i);
3647 return ECORE_SUCCESS;
3650 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
3651 struct ecore_ptt *p_ptt, u8 *p_filter)
3656 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3659 high = p_filter[1] | (p_filter[0] << 8);
3660 low = p_filter[5] | (p_filter[4] << 8) |
3661 (p_filter[3] << 16) | (p_filter[2] << 24);
3663 /* Find the entry and clean it */
3664 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3665 if (ecore_rd(p_hwfn, p_ptt,
3666 NIG_REG_LLH_FUNC_FILTER_VALUE +
3667 2 * i * sizeof(u32)) != low)
3669 if (ecore_rd(p_hwfn, p_ptt,
3670 NIG_REG_LLH_FUNC_FILTER_VALUE +
3671 (2 * i + 1) * sizeof(u32)) != high)
3674 ecore_wr(p_hwfn, p_ptt,
3675 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3676 ecore_wr(p_hwfn, p_ptt,
3677 NIG_REG_LLH_FUNC_FILTER_VALUE +
3678 2 * i * sizeof(u32), 0);
3679 ecore_wr(p_hwfn, p_ptt,
3680 NIG_REG_LLH_FUNC_FILTER_VALUE +
3681 (2 * i + 1) * sizeof(u32), 0);
3684 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3685 DP_NOTICE(p_hwfn, false,
3686 "Tried to remove a non-configured filter\n");
3689 enum _ecore_status_t
3690 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
3691 struct ecore_ptt *p_ptt,
3692 u16 source_port_or_eth_type,
3694 enum ecore_llh_port_filter_type_t type)
3699 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3700 return ECORE_SUCCESS;
3705 case ECORE_LLH_FILTER_ETHERTYPE:
3706 high = source_port_or_eth_type;
3708 case ECORE_LLH_FILTER_TCP_SRC_PORT:
3709 case ECORE_LLH_FILTER_UDP_SRC_PORT:
3710 low = source_port_or_eth_type << 16;
3712 case ECORE_LLH_FILTER_TCP_DEST_PORT:
3713 case ECORE_LLH_FILTER_UDP_DEST_PORT:
3716 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3717 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3718 low = (source_port_or_eth_type << 16) | dest_port;
3721 DP_NOTICE(p_hwfn, true,
3722 "Non valid LLH protocol filter type %d\n", type);
3725 /* Find a free entry and utilize it */
3726 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3727 en = ecore_rd(p_hwfn, p_ptt,
3728 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3731 ecore_wr(p_hwfn, p_ptt,
3732 NIG_REG_LLH_FUNC_FILTER_VALUE +
3733 2 * i * sizeof(u32), low);
3734 ecore_wr(p_hwfn, p_ptt,
3735 NIG_REG_LLH_FUNC_FILTER_VALUE +
3736 (2 * i + 1) * sizeof(u32), high);
3737 ecore_wr(p_hwfn, p_ptt,
3738 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3739 ecore_wr(p_hwfn, p_ptt,
3740 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3741 i * sizeof(u32), 1 << type);
3742 ecore_wr(p_hwfn, p_ptt,
3743 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3746 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3747 DP_NOTICE(p_hwfn, false,
3748 "Failed to find an empty LLH filter to utilize\n");
3749 return ECORE_NORESOURCES;
3752 case ECORE_LLH_FILTER_ETHERTYPE:
3753 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3754 "ETH type %x is added at %d\n",
3755 source_port_or_eth_type, i);
3757 case ECORE_LLH_FILTER_TCP_SRC_PORT:
3758 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3759 "TCP src port %x is added at %d\n",
3760 source_port_or_eth_type, i);
3762 case ECORE_LLH_FILTER_UDP_SRC_PORT:
3763 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3764 "UDP src port %x is added at %d\n",
3765 source_port_or_eth_type, i);
3767 case ECORE_LLH_FILTER_TCP_DEST_PORT:
3768 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3769 "TCP dst port %x is added at %d\n", dest_port, i);
3771 case ECORE_LLH_FILTER_UDP_DEST_PORT:
3772 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3773 "UDP dst port %x is added at %d\n", dest_port, i);
3775 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3776 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3777 "TCP src/dst ports %x/%x are added at %d\n",
3778 source_port_or_eth_type, dest_port, i);
3780 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3781 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3782 "UDP src/dst ports %x/%x are added at %d\n",
3783 source_port_or_eth_type, dest_port, i);
3786 return ECORE_SUCCESS;
3790 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
3791 struct ecore_ptt *p_ptt,
3792 u16 source_port_or_eth_type,
3794 enum ecore_llh_port_filter_type_t type)
3799 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3805 case ECORE_LLH_FILTER_ETHERTYPE:
3806 high = source_port_or_eth_type;
3808 case ECORE_LLH_FILTER_TCP_SRC_PORT:
3809 case ECORE_LLH_FILTER_UDP_SRC_PORT:
3810 low = source_port_or_eth_type << 16;
3812 case ECORE_LLH_FILTER_TCP_DEST_PORT:
3813 case ECORE_LLH_FILTER_UDP_DEST_PORT:
3816 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3817 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3818 low = (source_port_or_eth_type << 16) | dest_port;
3821 DP_NOTICE(p_hwfn, true,
3822 "Non valid LLH protocol filter type %d\n", type);
3826 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3827 if (!ecore_rd(p_hwfn, p_ptt,
3828 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3830 if (!ecore_rd(p_hwfn, p_ptt,
3831 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3833 if (!(ecore_rd(p_hwfn, p_ptt,
3834 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3835 i * sizeof(u32)) & (1 << type)))
3837 if (ecore_rd(p_hwfn, p_ptt,
3838 NIG_REG_LLH_FUNC_FILTER_VALUE +
3839 2 * i * sizeof(u32)) != low)
3841 if (ecore_rd(p_hwfn, p_ptt,
3842 NIG_REG_LLH_FUNC_FILTER_VALUE +
3843 (2 * i + 1) * sizeof(u32)) != high)
3846 ecore_wr(p_hwfn, p_ptt,
3847 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3848 ecore_wr(p_hwfn, p_ptt,
3849 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3850 ecore_wr(p_hwfn, p_ptt,
3851 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3852 i * sizeof(u32), 0);
3853 ecore_wr(p_hwfn, p_ptt,
3854 NIG_REG_LLH_FUNC_FILTER_VALUE +
3855 2 * i * sizeof(u32), 0);
3856 ecore_wr(p_hwfn, p_ptt,
3857 NIG_REG_LLH_FUNC_FILTER_VALUE +
3858 (2 * i + 1) * sizeof(u32), 0);
3862 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3863 DP_NOTICE(p_hwfn, false,
3864 "Tried to remove a non-configured filter\n");
3867 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
3868 struct ecore_ptt *p_ptt)
3872 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3875 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3876 ecore_wr(p_hwfn, p_ptt,
3877 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3878 ecore_wr(p_hwfn, p_ptt,
3879 NIG_REG_LLH_FUNC_FILTER_VALUE +
3880 2 * i * sizeof(u32), 0);
3881 ecore_wr(p_hwfn, p_ptt,
3882 NIG_REG_LLH_FUNC_FILTER_VALUE +
3883 (2 * i + 1) * sizeof(u32), 0);
3887 enum _ecore_status_t
3888 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
3889 struct ecore_ptt *p_ptt)
3891 if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
3892 ecore_wr(p_hwfn, p_ptt,
3893 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
3894 1 << p_hwfn->abs_pf_id / 2);
3895 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
3896 return ECORE_SUCCESS;
3899 DP_NOTICE(p_hwfn, false,
3900 "This function can't be set as default\n");
3904 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
3905 struct ecore_ptt *p_ptt,
3906 u32 hw_addr, void *p_eth_qzone,
3907 osal_size_t eth_qzone_size,
3910 struct coalescing_timeset *p_coal_timeset;
3912 if (IS_VF(p_hwfn->p_dev)) {
3913 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n");
3917 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
3918 DP_NOTICE(p_hwfn, true,
3919 "Coalescing configuration not enabled\n");
3923 p_coal_timeset = p_eth_qzone;
3924 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
3925 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3926 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3927 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3929 return ECORE_SUCCESS;
3932 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
3933 struct ecore_ptt *p_ptt,
3934 u16 coalesce, u16 qid, u16 sb_id)
3936 struct ustorm_eth_queue_zone eth_qzone;
3937 u8 timeset, timer_res;
3940 enum _ecore_status_t rc;
3942 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3943 if (coalesce <= 0x7F) {
3945 } else if (coalesce <= 0xFF) {
3947 } else if (coalesce <= 0x1FF) {
3950 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3953 timeset = (u8)(coalesce >> timer_res);
3955 rc = ecore_fw_l2_queue(p_hwfn, qid, &fw_qid);
3956 if (rc != ECORE_SUCCESS)
3959 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
3960 if (rc != ECORE_SUCCESS)
3963 address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3965 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
3966 sizeof(struct ustorm_eth_queue_zone), timeset);
3967 if (rc != ECORE_SUCCESS)
3970 p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
3975 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
3976 struct ecore_ptt *p_ptt,
3977 u16 coalesce, u16 qid, u16 sb_id)
3979 struct xstorm_eth_queue_zone eth_qzone;
3980 u8 timeset, timer_res;
3983 enum _ecore_status_t rc;
3985 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3986 if (coalesce <= 0x7F) {
3988 } else if (coalesce <= 0xFF) {
3990 } else if (coalesce <= 0x1FF) {
3993 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3997 timeset = (u8)(coalesce >> timer_res);
3999 rc = ecore_fw_l2_queue(p_hwfn, qid, &fw_qid);
4000 if (rc != ECORE_SUCCESS)
4003 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
4004 if (rc != ECORE_SUCCESS)
4007 address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
4009 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
4010 sizeof(struct xstorm_eth_queue_zone), timeset);
4011 if (rc != ECORE_SUCCESS)
4014 p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
4019 /* Calculate final WFQ values for all vports and configure it.
4020 * After this configuration each vport must have
4021 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
4023 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4024 struct ecore_ptt *p_ptt,
4027 struct init_qm_vport_params *vport_params;
4030 vport_params = p_hwfn->qm_info.qm_vport_params;
4032 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4033 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4035 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
4037 ecore_init_vport_wfq(p_hwfn, p_ptt,
4038 vport_params[i].first_tx_pq_id,
4039 vport_params[i].vport_wfq);
4044 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
4048 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4049 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4052 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4053 struct ecore_ptt *p_ptt,
4056 struct init_qm_vport_params *vport_params;
4059 vport_params = p_hwfn->qm_info.qm_vport_params;
4061 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4062 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
4063 ecore_init_vport_wfq(p_hwfn, p_ptt,
4064 vport_params[i].first_tx_pq_id,
4065 vport_params[i].vport_wfq);
4069 /* This function performs several validations for WFQ
4070 * configuration and required min rate for a given vport
4071 * 1. req_rate must be greater than one percent of min_pf_rate.
4072 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4073 * rates to get less than one percent of min_pf_rate.
4074 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4076 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
4077 u16 vport_id, u32 req_rate,
4080 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4081 int non_requested_count = 0, req_count = 0, i, num_vports;
4083 num_vports = p_hwfn->qm_info.num_vports;
4085 /* Accounting for the vports which are configured for WFQ explicitly */
4087 for (i = 0; i < num_vports; i++) {
4090 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
4092 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4093 total_req_min_rate += tmp_speed;
4097 /* Include current vport data as well */
4099 total_req_min_rate += req_rate;
4100 non_requested_count = num_vports - req_count;
4102 /* validate possible error cases */
4103 if (req_rate > min_pf_rate) {
4104 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4105 "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4106 vport_id, req_rate, min_pf_rate);
4110 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
4111 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4112 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4113 vport_id, req_rate, min_pf_rate);
4117 /* TBD - for number of vports greater than 100 */
4118 if (num_vports > ECORE_WFQ_UNIT) {
4119 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4120 "Number of vports is greater than %d\n",
4125 if (total_req_min_rate > min_pf_rate) {
4126 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4127 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4128 total_req_min_rate, min_pf_rate);
4132 /* Data left for non requested vports */
4133 total_left_rate = min_pf_rate - total_req_min_rate;
4134 left_rate_per_vp = total_left_rate / non_requested_count;
4136 /* validate if non requested get < 1% of min bw */
4137 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4138 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4139 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4140 left_rate_per_vp, min_pf_rate);
4144 /* now req_rate for given vport passes all scenarios.
4145 * assign final wfq rates to all vports.
4147 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4148 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4150 for (i = 0; i < num_vports; i++) {
4151 if (p_hwfn->qm_info.wfq_data[i].configured)
4154 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4157 return ECORE_SUCCESS;
4160 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4161 struct ecore_ptt *p_ptt,
4162 u16 vp_id, u32 rate)
4164 struct ecore_mcp_link_state *p_link;
4165 int rc = ECORE_SUCCESS;
4167 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4169 if (!p_link->min_pf_rate) {
4170 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4171 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4175 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4177 if (rc == ECORE_SUCCESS)
4178 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4179 p_link->min_pf_rate);
4181 DP_NOTICE(p_hwfn, false,
4182 "Validation failed while configuring min rate\n");
4187 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4188 struct ecore_ptt *p_ptt,
4191 bool use_wfq = false;
4192 int rc = ECORE_SUCCESS;
4195 /* Validate all pre configured vports for wfq */
4196 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4199 if (!p_hwfn->qm_info.wfq_data[i].configured)
4202 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4205 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4206 if (rc != ECORE_SUCCESS) {
4207 DP_NOTICE(p_hwfn, false,
4208 "WFQ validation failed while configuring min rate\n");
4213 if (rc == ECORE_SUCCESS && use_wfq)
4214 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4216 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4221 /* Main API for ecore clients to configure vport min rate.
4222 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4223 * rate - Speed in Mbps needs to be assigned to a given vport.
4225 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4227 int i, rc = ECORE_INVAL;
4229 /* TBD - for multiple hardware functions - that is 100 gig */
4230 if (p_dev->num_hwfns > 1) {
4231 DP_NOTICE(p_dev, false,
4232 "WFQ configuration is not supported for this device\n");
4236 for_each_hwfn(p_dev, i) {
4237 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4238 struct ecore_ptt *p_ptt;
4240 p_ptt = ecore_ptt_acquire(p_hwfn);
4242 return ECORE_TIMEOUT;
4244 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4246 if (rc != ECORE_SUCCESS) {
4247 ecore_ptt_release(p_hwfn, p_ptt);
4251 ecore_ptt_release(p_hwfn, p_ptt);
4257 /* API to configure WFQ from mcp link change */
4258 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4263 /* TBD - for multiple hardware functions - that is 100 gig */
4264 if (p_dev->num_hwfns > 1) {
4265 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4266 "WFQ configuration is not supported for this device\n");
4270 for_each_hwfn(p_dev, i) {
4271 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4273 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4279 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4280 struct ecore_ptt *p_ptt,
4281 struct ecore_mcp_link_state *p_link,
4284 int rc = ECORE_SUCCESS;
4286 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4288 if (!p_link->line_speed && (max_bw != 100))
4291 p_link->speed = (p_link->line_speed * max_bw) / 100;
4292 p_hwfn->qm_info.pf_rl = p_link->speed;
4294 /* Since the limiter also affects Tx-switched traffic, we don't want it
4295 * to limit such traffic in case there's no actual limit.
4296 * In that case, set limit to imaginary high boundary.
4299 p_hwfn->qm_info.pf_rl = 100000;
4301 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4302 p_hwfn->qm_info.pf_rl);
4304 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4305 "Configured MAX bandwidth to be %08x Mb/sec\n",
4311 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4312 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4314 int i, rc = ECORE_INVAL;
4316 if (max_bw < 1 || max_bw > 100) {
4317 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4321 for_each_hwfn(p_dev, i) {
4322 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4323 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4324 struct ecore_mcp_link_state *p_link;
4325 struct ecore_ptt *p_ptt;
4327 p_link = &p_lead->mcp_info->link_output;
4329 p_ptt = ecore_ptt_acquire(p_hwfn);
4331 return ECORE_TIMEOUT;
4333 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4336 ecore_ptt_release(p_hwfn, p_ptt);
4338 if (rc != ECORE_SUCCESS)
4345 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4346 struct ecore_ptt *p_ptt,
4347 struct ecore_mcp_link_state *p_link,
4350 int rc = ECORE_SUCCESS;
4352 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4353 p_hwfn->qm_info.pf_wfq = min_bw;
4355 if (!p_link->line_speed)
4358 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4360 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4362 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4363 "Configured MIN bandwidth to be %d Mb/sec\n",
4364 p_link->min_pf_rate);
4369 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4370 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4372 int i, rc = ECORE_INVAL;
4374 if (min_bw < 1 || min_bw > 100) {
4375 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4379 for_each_hwfn(p_dev, i) {
4380 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4381 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4382 struct ecore_mcp_link_state *p_link;
4383 struct ecore_ptt *p_ptt;
4385 p_link = &p_lead->mcp_info->link_output;
4387 p_ptt = ecore_ptt_acquire(p_hwfn);
4389 return ECORE_TIMEOUT;
4391 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4393 if (rc != ECORE_SUCCESS) {
4394 ecore_ptt_release(p_hwfn, p_ptt);
4398 if (p_link->min_pf_rate) {
4399 u32 min_rate = p_link->min_pf_rate;
4401 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4406 ecore_ptt_release(p_hwfn, p_ptt);
4412 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4414 struct ecore_mcp_link_state *p_link;
4416 p_link = &p_hwfn->mcp_info->link_output;
4418 if (p_link->min_pf_rate)
4419 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4420 p_link->min_pf_rate);
4422 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4423 sizeof(*p_hwfn->qm_info.wfq_data) *
4424 p_hwfn->qm_info.num_vports);
4427 int ecore_device_num_engines(struct ecore_dev *p_dev)
4429 return ECORE_IS_BB(p_dev) ? 2 : 1;
4432 int ecore_device_num_ports(struct ecore_dev *p_dev)
4434 /* in CMT always only one port */
4435 if (p_dev->num_hwfns > 1)
4438 return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
4441 void ecore_set_fw_mac_addr(__le16 *fw_msb,
4446 ((u8 *)fw_msb)[0] = mac[1];
4447 ((u8 *)fw_msb)[1] = mac[0];
4448 ((u8 *)fw_mid)[0] = mac[3];
4449 ((u8 *)fw_mid)[1] = mac[2];
4450 ((u8 *)fw_lsb)[0] = mac[5];
4451 ((u8 *)fw_lsb)[1] = mac[4];