drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dev_api.h"
  32 #include "ecore_dcbx.h"
  33
  34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  35  * registers involved are not split and thus configuration is a race where
  36  * some of the PFs configuration might be lost.
  37  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  38  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  39  * there's more than a single compiled ecore component in system].
  40  */
  41 static osal_spinlock_t qm_lock;
  42 static bool qm_lock_init;
  43
  44 /* Configurable */
  45 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
  46                                          * load the driver. The number was
  47                                          * arbitrarily set.
  48                                          */
  49
  50 /* Derived */
  51 #define ECORE_MIN_PWM_REGION    ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
  52
  53 enum BAR_ID {
  54         BAR_ID_0,               /* used for GRC */
  55         BAR_ID_1                /* Used for doorbells */
  56 };
  57
  58 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
  59 {
  60         u32 bar_reg = (bar_id == BAR_ID_0 ?
  61                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  62         u32 val;
  63
  64         if (IS_VF(p_hwfn->p_dev)) {
  65                 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
  66                  * read from actual register, but we're currently not using
  67                  * it for actual doorbelling.
  68                  */
  69                 return 1 << 17;
  70         }
  71
  72         val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
  73         if (val)
  74                 return 1 << (val + 15);
  75
  76         /* The above registers were updated in the past only in CMT mode. Since
  77          * they were found to be useful MFW started updating them from 8.7.7.0.
  78          * In older MFW versions they are set to 0 which means disabled.
  79          */
  80         if (p_hwfn->p_dev->num_hwfns > 1) {
  81                 DP_NOTICE(p_hwfn, false,
  82                           "BAR size not configured. Assuming BAR size of 256kB"
  83                           " for GRC and 512kB for DB\n");
  84                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  85         } else {
  86                 DP_NOTICE(p_hwfn, false,
  87                           "BAR size not configured. Assuming BAR size of 512kB"
  88                           " for GRC and 512kB for DB\n");
  89                 val = 512 * 1024;
  90         }
  91
  92         return val;
  93 }
  94
  95 void ecore_init_dp(struct ecore_dev *p_dev,
  96                    u32 dp_module, u8 dp_level, void *dp_ctx)
  97 {
  98         u32 i;
  99
 100         p_dev->dp_level = dp_level;
 101         p_dev->dp_module = dp_module;
 102         p_dev->dp_ctx = dp_ctx;
 103         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 104                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 105
 106                 p_hwfn->dp_level = dp_level;
 107                 p_hwfn->dp_module = dp_module;
 108                 p_hwfn->dp_ctx = dp_ctx;
 109         }
 110 }
 111
 112 void ecore_init_struct(struct ecore_dev *p_dev)
 113 {
 114         u8 i;
 115
 116         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 117                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 118
 119                 p_hwfn->p_dev = p_dev;
 120                 p_hwfn->my_id = i;
 121                 p_hwfn->b_active = false;
 122
 123                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 124                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 125         }
 126
 127         /* hwfn 0 is always active */
 128         p_dev->hwfns[0].b_active = true;
 129
 130         /* set the default cache alignment to 128 (may be overridden later) */
 131         p_dev->cache_shift = 7;
 132 }
 133
 134 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 135 {
 136         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 137
 138         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 139         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 140         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 141         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 142 }
 143
 144 void ecore_resc_free(struct ecore_dev *p_dev)
 145 {
 146         int i;
 147
 148         if (IS_VF(p_dev))
 149                 return;
 150
 151         OSAL_FREE(p_dev, p_dev->fw_data);
 152
 153         OSAL_FREE(p_dev, p_dev->reset_stats);
 154
 155         for_each_hwfn(p_dev, i) {
 156                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 157
 158                 OSAL_FREE(p_dev, p_hwfn->p_tx_cids);
 159                 OSAL_FREE(p_dev, p_hwfn->p_rx_cids);
 160         }
 161
 162         for_each_hwfn(p_dev, i) {
 163                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 164
 165                 ecore_cxt_mngr_free(p_hwfn);
 166                 ecore_qm_info_free(p_hwfn);
 167                 ecore_spq_free(p_hwfn);
 168                 ecore_eq_free(p_hwfn, p_hwfn->p_eq);
 169                 ecore_consq_free(p_hwfn, p_hwfn->p_consq);
 170                 ecore_int_free(p_hwfn);
 171 #ifdef CONFIG_ECORE_LL2
 172                 ecore_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
 173 #endif
 174                 ecore_iov_free(p_hwfn);
 175                 ecore_dmae_info_free(p_hwfn);
 176                 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 177                 /* @@@TBD Flush work-queue ? */
 178         }
 179 }
 180
 181 static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn,
 182                                                bool b_sleepable)
 183 {
 184         u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue;
 185         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 186         struct init_qm_port_params *p_qm_port;
 187         bool init_rdma_offload_pq = false;
 188         bool init_pure_ack_pq = false;
 189         bool init_ooo_pq = false;
 190         u16 num_pqs, protocol_pqs;
 191         u16 num_pf_rls = 0;
 192         u16 num_vfs = 0;
 193         u32 pf_rl;
 194         u8 pf_wfq;
 195
 196         /* @TMP - saving the existing min/max bw config before resetting the
 197          * qm_info to restore them.
 198          */
 199         pf_rl = qm_info->pf_rl;
 200         pf_wfq = qm_info->pf_wfq;
 201
 202 #ifdef CONFIG_ECORE_SRIOV
 203         if (p_hwfn->p_dev->p_iov_info)
 204                 num_vfs = p_hwfn->p_dev->p_iov_info->total_vfs;
 205 #endif
 206         OSAL_MEM_ZERO(qm_info, sizeof(*qm_info));
 207
 208 #ifndef ASIC_ONLY
 209         /* @TMP - Don't allocate QM queues for VFs on emulation */
 210         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 211                 DP_NOTICE(p_hwfn, false,
 212                           "Emulation - skip configuring QM queues for VFs\n");
 213                 num_vfs = 0;
 214         }
 215 #endif
 216
 217         /* ethernet PFs require a pq per tc. Even if only a subset of the TCs
 218          * active, we want physical queues allocated for all of them, since we
 219          * don't have a good recycle flow. Non ethernet PFs require only a
 220          * single physical queue.
 221          */
 222         if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE ||
 223             p_hwfn->hw_info.personality == ECORE_PCI_IWARP ||
 224             p_hwfn->hw_info.personality == ECORE_PCI_ETH)
 225                 protocol_pqs = p_hwfn->hw_info.num_hw_tc;
 226         else
 227                 protocol_pqs = 1;
 228
 229         num_pqs = protocol_pqs + num_vfs + 1;   /* The '1' is for pure-LB */
 230         num_vports = (u8)RESC_NUM(p_hwfn, ECORE_VPORT);
 231
 232         if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
 233                 num_pqs++;      /* for RoCE queue */
 234                 init_rdma_offload_pq = true;
 235                 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn) {
 236                         /* Due to FW assumption that rl==vport, we limit the
 237                          * number of rate limiters by the minimum between its
 238                          * allocated number and the allocated number of vports.
 239                          * Another limitation is the number of supported qps
 240                          * with rate limiters in FW.
 241                          */
 242                         num_pf_rls =
 243                             (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 244                                              RESC_NUM(p_hwfn, ECORE_VPORT));
 245
 246                         /* we subtract num_vfs because each one requires a rate
 247                          * limiter, and one default rate limiter.
 248                          */
 249                         if (num_pf_rls < num_vfs + 1) {
 250                                 DP_ERR(p_hwfn, "No RL for DCQCN");
 251                                 DP_ERR(p_hwfn, "[num_pf_rls %d num_vfs %d]\n",
 252                                        num_pf_rls, num_vfs);
 253                                 return ECORE_INVAL;
 254                         }
 255                         num_pf_rls -= num_vfs + 1;
 256                 }
 257
 258                 num_pqs += num_pf_rls;
 259                 qm_info->num_pf_rls = (u8)num_pf_rls;
 260         }
 261
 262         if (p_hwfn->hw_info.personality == ECORE_PCI_IWARP) {
 263                 num_pqs += 3;   /* for iwarp queue / pure-ack / ooo */
 264                 init_rdma_offload_pq = true;
 265                 init_pure_ack_pq = true;
 266                 init_ooo_pq = true;
 267         }
 268
 269         if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 270                 num_pqs += 2;   /* for iSCSI pure-ACK / OOO queue */
 271                 init_pure_ack_pq = true;
 272                 init_ooo_pq = true;
 273         }
 274
 275         /* Sanity checking that setup requires legal number of resources */
 276         if (num_pqs > RESC_NUM(p_hwfn, ECORE_PQ)) {
 277                 DP_ERR(p_hwfn,
 278                        "Need too many Physical queues - 0x%04x avail %04x",
 279                        num_pqs, RESC_NUM(p_hwfn, ECORE_PQ));
 280                 return ECORE_INVAL;
 281         }
 282
 283         /* PQs will be arranged as follows: First per-TC PQ, then pure-LB queue,
 284          * then special queues (iSCSI pure-ACK / RoCE), then per-VF PQ.
 285          */
 286         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev,
 287                                             b_sleepable ? GFP_KERNEL :
 288                                             GFP_ATOMIC,
 289                                             sizeof(struct init_qm_pq_params) *
 290                                             num_pqs);
 291         if (!qm_info->qm_pq_params)
 292                 goto alloc_err;
 293
 294         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev,
 295                                                b_sleepable ? GFP_KERNEL :
 296                                                GFP_ATOMIC,
 297                                                sizeof(struct
 298                                                       init_qm_vport_params) *
 299                                                num_vports);
 300         if (!qm_info->qm_vport_params)
 301                 goto alloc_err;
 302
 303         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev,
 304                                               b_sleepable ? GFP_KERNEL :
 305                                               GFP_ATOMIC,
 306                                               sizeof(struct init_qm_port_params)
 307                                               * MAX_NUM_PORTS);
 308         if (!qm_info->qm_port_params)
 309                 goto alloc_err;
 310
 311         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev,
 312                                         b_sleepable ? GFP_KERNEL :
 313                                         GFP_ATOMIC,
 314                                         sizeof(struct ecore_wfq_data) *
 315                                         num_vports);
 316
 317         if (!qm_info->wfq_data)
 318                 goto alloc_err;
 319
 320         vport_id = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 321
 322         /* First init rate limited queues ( Due to RoCE assumption of
 323          * qpid=rlid )
 324          */
 325         for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
 326                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
 327                 qm_info->qm_pq_params[curr_queue].tc_id =
 328                     p_hwfn->hw_info.offload_tc;
 329                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 330                 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
 331         };
 332
 333         /* Protocol PQs */
 334         for (i = 0; i < protocol_pqs; i++) {
 335                 struct init_qm_pq_params *params =
 336                     &qm_info->qm_pq_params[curr_queue++];
 337
 338                 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE ||
 339                     p_hwfn->hw_info.personality == ECORE_PCI_IWARP ||
 340                     p_hwfn->hw_info.personality == ECORE_PCI_ETH) {
 341                         params->vport_id = vport_id;
 342                         params->tc_id = i;
 343                         /* Note: this assumes that if we had a configuration
 344                          * with N tcs and subsequently another configuration
 345                          * With Fewer TCs, the in flight traffic (in QM queues,
 346                          * in FW, from driver to FW) will still trickle out and
 347                          * not get "stuck" in the QM. This is determined by the
 348                          * NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ. Unused TCs are
 349                          * supposed to be cleared in this map, allowing traffic
 350                          * to flush out. If this is not the case, we would need
 351                          * to set the TC of unused queues to 0, and reconfigure
 352                          * QM every time num of TCs changes. Unused queues in
 353                          * this context would mean those intended for TCs where
 354                          * tc_id > hw_info.num_active_tcs.
 355                          */
 356                         params->wrr_group = 1;  /* @@@TBD ECORE_WRR_MEDIUM */
 357                 } else {
 358                         params->vport_id = vport_id;
 359                         params->tc_id = p_hwfn->hw_info.offload_tc;
 360                         params->wrr_group = 1;  /* @@@TBD ECORE_WRR_MEDIUM */
 361                 }
 362         }
 363
 364         /* Then init pure-LB PQ */
 365         qm_info->pure_lb_pq = curr_queue;
 366         qm_info->qm_pq_params[curr_queue].vport_id =
 367             (u8)RESC_START(p_hwfn, ECORE_VPORT);
 368         qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
 369         qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 370         curr_queue++;
 371
 372         qm_info->offload_pq = 0;        /* Already initialized for iSCSI/FCoE */
 373         if (init_rdma_offload_pq) {
 374                 qm_info->offload_pq = curr_queue;
 375                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 376                 qm_info->qm_pq_params[curr_queue].tc_id =
 377                     p_hwfn->hw_info.offload_tc;
 378                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 379                 curr_queue++;
 380         }
 381
 382         if (init_pure_ack_pq) {
 383                 qm_info->pure_ack_pq = curr_queue;
 384                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 385                 qm_info->qm_pq_params[curr_queue].tc_id =
 386                     p_hwfn->hw_info.offload_tc;
 387                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 388                 curr_queue++;
 389         }
 390
 391         if (init_ooo_pq) {
 392                 qm_info->ooo_pq = curr_queue;
 393                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
 394                 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
 395                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 396                 curr_queue++;
 397         }
 398
 399         /* Then init per-VF PQs */
 400         vf_offset = curr_queue;
 401         for (i = 0; i < num_vfs; i++) {
 402                 /* First vport is used by the PF */
 403                 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
 404                 /* @@@TBD VF Multi-cos */
 405                 qm_info->qm_pq_params[curr_queue].tc_id = 0;
 406                 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
 407                 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
 408                 curr_queue++;
 409         };
 410
 411         qm_info->vf_queues_offset = vf_offset;
 412         qm_info->num_pqs = num_pqs;
 413         qm_info->num_vports = num_vports;
 414
 415         /* Initialize qm port parameters */
 416         num_ports = p_hwfn->p_dev->num_ports_in_engines;
 417         for (i = 0; i < num_ports; i++) {
 418                 p_qm_port = &qm_info->qm_port_params[i];
 419                 p_qm_port->active = 1;
 420                 /* @@@TMP - was NUM_OF_PHYS_TCS; Changed until dcbx will
 421                  * be in place
 422                  */
 423                 if (num_ports == 4)
 424                         p_qm_port->active_phys_tcs = 0xf;
 425                 else
 426                         p_qm_port->active_phys_tcs = 0x9f;
 427                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 428                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 429         }
 430
 431         if (ECORE_IS_AH(p_hwfn->p_dev) && (num_ports == 4))
 432                 qm_info->max_phys_tcs_per_port = NUM_PHYS_TCS_4PORT_K2;
 433         else
 434                 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
 435
 436         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 437
 438         qm_info->num_vf_pqs = num_vfs;
 439         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 440
 441         for (i = 0; i < qm_info->num_vports; i++)
 442                 qm_info->qm_vport_params[i].vport_wfq = 1;
 443
 444         qm_info->vport_rl_en = 1;
 445         qm_info->vport_wfq_en = 1;
 446         qm_info->pf_rl = pf_rl;
 447         qm_info->pf_wfq = pf_wfq;
 448
 449         return ECORE_SUCCESS;
 450
 451  alloc_err:
 452         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
 453         ecore_qm_info_free(p_hwfn);
 454         return ECORE_NOMEM;
 455 }
 456
 457 /* This function reconfigures the QM pf on the fly.
 458  * For this purpose we:
 459  * 1. reconfigure the QM database
 460  * 2. set new values to runtime arrat
 461  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 462  * 4. activate init tool in QM_PF stage
 463  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 464  */
 465 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
 466                                      struct ecore_ptt *p_ptt)
 467 {
 468         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 469         bool b_rc;
 470         enum _ecore_status_t rc;
 471
 472         /* qm_info is allocated in ecore_init_qm_info() which is already called
 473          * from ecore_resc_alloc() or previous call of ecore_qm_reconf().
 474          * The allocated size may change each init, so we free it before next
 475          * allocation.
 476          */
 477         ecore_qm_info_free(p_hwfn);
 478
 479         /* initialize ecore's qm data structure */
 480         rc = ecore_init_qm_info(p_hwfn, false);
 481         if (rc != ECORE_SUCCESS)
 482                 return rc;
 483
 484         /* stop PF's qm queues */
 485         OSAL_SPIN_LOCK(&qm_lock);
 486         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 487                                       qm_info->start_pq, qm_info->num_pqs);
 488         OSAL_SPIN_UNLOCK(&qm_lock);
 489         if (!b_rc)
 490                 return ECORE_INVAL;
 491
 492         /* clear the QM_PF runtime phase leftovers from previous init */
 493         ecore_init_clear_rt_data(p_hwfn);
 494
 495         /* prepare QM portion of runtime array */
 496         ecore_qm_init_pf(p_hwfn);
 497
 498         /* activate init tool on runtime array */
 499         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 500                             p_hwfn->hw_info.hw_mode);
 501         if (rc != ECORE_SUCCESS)
 502                 return rc;
 503
 504         /* start PF's qm queues */
 505         OSAL_SPIN_LOCK(&qm_lock);
 506         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 507                                       qm_info->start_pq, qm_info->num_pqs);
 508         OSAL_SPIN_UNLOCK(&qm_lock);
 509         if (!b_rc)
 510                 return ECORE_INVAL;
 511
 512         return ECORE_SUCCESS;
 513 }
 514
 515 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
 516 {
 517         struct ecore_consq *p_consq;
 518         struct ecore_eq *p_eq;
 519 #ifdef  CONFIG_ECORE_LL2
 520         struct ecore_ll2_info *p_ll2_info;
 521 #endif
 522         enum _ecore_status_t rc = ECORE_SUCCESS;
 523         int i;
 524
 525         if (IS_VF(p_dev))
 526                 return rc;
 527
 528         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 529                                      sizeof(*p_dev->fw_data));
 530         if (!p_dev->fw_data)
 531                 return ECORE_NOMEM;
 532
 533         /* Allocate Memory for the Queue->CID mapping */
 534         for_each_hwfn(p_dev, i) {
 535                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 536                 u32 num_tx_conns = RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 537                 int tx_size, rx_size;
 538
 539                 /* @@@TMP - resc management, change to actual required size */
 540                 if (p_hwfn->pf_params.eth_pf_params.num_cons > num_tx_conns)
 541                         num_tx_conns = p_hwfn->pf_params.eth_pf_params.num_cons;
 542                 tx_size = sizeof(struct ecore_hw_cid_data) * num_tx_conns;
 543                 rx_size = sizeof(struct ecore_hw_cid_data) *
 544                     RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 545
 546                 p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 547                                                 tx_size);
 548                 if (!p_hwfn->p_tx_cids) {
 549                         DP_NOTICE(p_hwfn, true,
 550                                   "Failed to allocate memory for Tx Cids\n");
 551                         goto alloc_no_mem;
 552                 }
 553
 554                 p_hwfn->p_rx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 555                                                 rx_size);
 556                 if (!p_hwfn->p_rx_cids) {
 557                         DP_NOTICE(p_hwfn, true,
 558                                   "Failed to allocate memory for Rx Cids\n");
 559                         goto alloc_no_mem;
 560                 }
 561         }
 562
 563         for_each_hwfn(p_dev, i) {
 564                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 565                 u32 n_eqes, num_cons;
 566
 567                 /* First allocate the context manager structure */
 568                 rc = ecore_cxt_mngr_alloc(p_hwfn);
 569                 if (rc)
 570                         goto alloc_err;
 571
 572                 /* Set the HW cid/tid numbers (in the contest manager)
 573                  * Must be done prior to any further computations.
 574                  */
 575                 rc = ecore_cxt_set_pf_params(p_hwfn);
 576                 if (rc)
 577                         goto alloc_err;
 578
 579                 /* Prepare and process QM requirements */
 580                 rc = ecore_init_qm_info(p_hwfn, true);
 581                 if (rc)
 582                         goto alloc_err;
 583
 584                 /* Compute the ILT client partition */
 585                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
 586                 if (rc)
 587                         goto alloc_err;
 588
 589                 /* CID map / ILT shadow table / T2
 590                  * The talbes sizes are determined by the computations above
 591                  */
 592                 rc = ecore_cxt_tables_alloc(p_hwfn);
 593                 if (rc)
 594                         goto alloc_err;
 595
 596                 /* SPQ, must follow ILT because initializes SPQ context */
 597                 rc = ecore_spq_alloc(p_hwfn);
 598                 if (rc)
 599                         goto alloc_err;
 600
 601                 /* SP status block allocation */
 602                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
 603                                                            RESERVED_PTT_DPC);
 604
 605                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 606                 if (rc)
 607                         goto alloc_err;
 608
 609                 rc = ecore_iov_alloc(p_hwfn);
 610                 if (rc)
 611                         goto alloc_err;
 612
 613                 /* EQ */
 614                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
 615                 if ((p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) ||
 616                     (p_hwfn->hw_info.personality == ECORE_PCI_IWARP)) {
 617                         /* Calculate the EQ size
 618                          * ---------------------
 619                          * Each ICID may generate up to one event at a time i.e.
 620                          * the event must be handled/cleared before a new one
 621                          * can be generated. We calculate the sum of events per
 622                          * protocol and create an EQ deep enough to handle the
 623                          * worst case:
 624                          * - Core - according to SPQ.
 625                          * - RoCE - per QP there are a couple of ICIDs, one
 626                          *          responder and one requester, each can
 627                          *          generate an EQE => n_eqes_qp = 2 * n_qp.
 628                          *          Each CQ can generate an EQE. There are 2 CQs
 629                          *          per QP => n_eqes_cq = 2 * n_qp.
 630                          *          Hence the RoCE total is 4 * n_qp or
 631                          *          2 * num_cons.
 632                          * - ENet - There can be up to two events per VF. One
 633                          *          for VF-PF channel and another for VF FLR
 634                          *          initial cleanup. The number of VFs is
 635                          *          bounded by MAX_NUM_VFS_BB, and is much
 636                          *          smaller than RoCE's so we avoid exact
 637                          *          calculation.
 638                          */
 639                         if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
 640                                 num_cons =
 641                                     ecore_cxt_get_proto_cid_count(
 642                                                 p_hwfn,
 643                                                 PROTOCOLID_ROCE,
 644                                                 OSAL_NULL);
 645                                 num_cons *= 2;
 646                         } else {
 647                                 num_cons = ecore_cxt_get_proto_cid_count(
 648                                                 p_hwfn,
 649                                                 PROTOCOLID_IWARP,
 650                                                 OSAL_NULL);
 651                         }
 652                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 653                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 654                         num_cons =
 655                             ecore_cxt_get_proto_cid_count(p_hwfn,
 656                                                           PROTOCOLID_ISCSI,
 657                                                           OSAL_NULL);
 658                         n_eqes += 2 * num_cons;
 659                 }
 660
 661                 if (n_eqes > 0xFFFF) {
 662                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
 663                                        "The maximum of a u16 chain is 0x%x\n",
 664                                n_eqes, 0xFFFF);
 665                         goto alloc_no_mem;
 666                 }
 667
 668                 p_eq = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
 669                 if (!p_eq)
 670                         goto alloc_no_mem;
 671                 p_hwfn->p_eq = p_eq;
 672
 673                 p_consq = ecore_consq_alloc(p_hwfn);
 674                 if (!p_consq)
 675                         goto alloc_no_mem;
 676                 p_hwfn->p_consq = p_consq;
 677
 678 #ifdef CONFIG_ECORE_LL2
 679                 if (p_hwfn->using_ll2) {
 680                         p_ll2_info = ecore_ll2_alloc(p_hwfn);
 681                         if (!p_ll2_info)
 682                                 goto alloc_no_mem;
 683                         p_hwfn->p_ll2_info = p_ll2_info;
 684                 }
 685 #endif
 686
 687                 /* DMA info initialization */
 688                 rc = ecore_dmae_info_alloc(p_hwfn);
 689                 if (rc) {
 690                         DP_NOTICE(p_hwfn, true,
 691                                   "Failed to allocate memory for dmae_info structure\n");
 692                         goto alloc_err;
 693                 }
 694
 695                 /* DCBX initialization */
 696                 rc = ecore_dcbx_info_alloc(p_hwfn);
 697                 if (rc) {
 698                         DP_NOTICE(p_hwfn, true,
 699                                   "Failed to allocate memory for dcbx structure\n");
 700                         goto alloc_err;
 701                 }
 702         }
 703
 704         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 705                                          sizeof(*p_dev->reset_stats));
 706         if (!p_dev->reset_stats) {
 707                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
 708                 goto alloc_no_mem;
 709         }
 710
 711         return ECORE_SUCCESS;
 712
 713  alloc_no_mem:
 714         rc = ECORE_NOMEM;
 715  alloc_err:
 716         ecore_resc_free(p_dev);
 717         return rc;
 718 }
 719
 720 void ecore_resc_setup(struct ecore_dev *p_dev)
 721 {
 722         int i;
 723
 724         if (IS_VF(p_dev))
 725                 return;
 726
 727         for_each_hwfn(p_dev, i) {
 728                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 729
 730                 ecore_cxt_mngr_setup(p_hwfn);
 731                 ecore_spq_setup(p_hwfn);
 732                 ecore_eq_setup(p_hwfn, p_hwfn->p_eq);
 733                 ecore_consq_setup(p_hwfn, p_hwfn->p_consq);
 734
 735                 /* Read shadow of current MFW mailbox */
 736                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
 737                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
 738                             p_hwfn->mcp_info->mfw_mb_cur,
 739                             p_hwfn->mcp_info->mfw_mb_length);
 740
 741                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
 742
 743                 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
 744 #ifdef CONFIG_ECORE_LL2
 745                 if (p_hwfn->using_ll2)
 746                         ecore_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
 747 #endif
 748         }
 749 }
 750
 751 #define FINAL_CLEANUP_POLL_CNT  (100)
 752 #define FINAL_CLEANUP_POLL_TIME (10)
 753 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
 754                                          struct ecore_ptt *p_ptt,
 755                                          u16 id, bool is_vf)
 756 {
 757         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
 758         enum _ecore_status_t rc = ECORE_TIMEOUT;
 759
 760 #ifndef ASIC_ONLY
 761         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
 762             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 763                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
 764                 return ECORE_SUCCESS;
 765         }
 766 #endif
 767
 768         addr = GTT_BAR0_MAP_REG_USDM_RAM +
 769             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
 770
 771         if (is_vf)
 772                 id += 0x10;
 773
 774         command |= X_FINAL_CLEANUP_AGG_INT <<
 775             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
 776         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
 777         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
 778         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
 779
 780 /* Make sure notification is not set before initiating final cleanup */
 781
 782         if (REG_RD(p_hwfn, addr)) {
 783                 DP_NOTICE(p_hwfn, false,
 784                           "Unexpected; Found final cleanup notification");
 785                 DP_NOTICE(p_hwfn, false,
 786                           " before initiating final cleanup\n");
 787                 REG_WR(p_hwfn, addr, 0);
 788         }
 789
 790         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
 791                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
 792                    id, command);
 793
 794         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
 795
 796         /* Poll until completion */
 797         while (!REG_RD(p_hwfn, addr) && count--)
 798                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
 799
 800         if (REG_RD(p_hwfn, addr))
 801                 rc = ECORE_SUCCESS;
 802         else
 803                 DP_NOTICE(p_hwfn, true,
 804                           "Failed to receive FW final cleanup notification\n");
 805
 806         /* Cleanup afterwards */
 807         REG_WR(p_hwfn, addr, 0);
 808
 809         return rc;
 810 }
 811
 812 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
 813 {
 814         int hw_mode = 0;
 815
 816         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
 817                 hw_mode |= 1 << MODE_BB;
 818         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
 819                 hw_mode |= 1 << MODE_K2;
 820         } else {
 821                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
 822                           p_hwfn->p_dev->type);
 823                 return ECORE_INVAL;
 824         }
 825
 826         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
 827         switch (p_hwfn->p_dev->num_ports_in_engines) {
 828         case 1:
 829                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
 830                 break;
 831         case 2:
 832                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
 833                 break;
 834         case 4:
 835                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
 836                 break;
 837         default:
 838                 DP_NOTICE(p_hwfn, true,
 839                           "num_ports_in_engine = %d not supported\n",
 840                           p_hwfn->p_dev->num_ports_in_engines);
 841                 return ECORE_INVAL;
 842         }
 843
 844         switch (p_hwfn->p_dev->mf_mode) {
 845         case ECORE_MF_DEFAULT:
 846         case ECORE_MF_NPAR:
 847                 hw_mode |= 1 << MODE_MF_SI;
 848                 break;
 849         case ECORE_MF_OVLAN:
 850                 hw_mode |= 1 << MODE_MF_SD;
 851                 break;
 852         default:
 853                 DP_NOTICE(p_hwfn, true,
 854                           "Unsupported MF mode, init as DEFAULT\n");
 855                 hw_mode |= 1 << MODE_MF_SI;
 856         }
 857
 858 #ifndef ASIC_ONLY
 859         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 860                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
 861                         hw_mode |= 1 << MODE_FPGA;
 862                 } else {
 863                         if (p_hwfn->p_dev->b_is_emul_full)
 864                                 hw_mode |= 1 << MODE_EMUL_FULL;
 865                         else
 866                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
 867                 }
 868         } else
 869 #endif
 870                 hw_mode |= 1 << MODE_ASIC;
 871
 872         if (p_hwfn->p_dev->num_hwfns > 1)
 873                 hw_mode |= 1 << MODE_100G;
 874
 875         p_hwfn->hw_info.hw_mode = hw_mode;
 876
 877         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
 878                    "Configuring function for hw_mode: 0x%08x\n",
 879                    p_hwfn->hw_info.hw_mode);
 880
 881         return ECORE_SUCCESS;
 882 }
 883
 884 #ifndef ASIC_ONLY
 885 /* MFW-replacement initializations for non-ASIC */
 886 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
 887                                                struct ecore_ptt *p_ptt)
 888 {
 889         struct ecore_dev *p_dev = p_hwfn->p_dev;
 890         u32 pl_hv = 1;
 891         int i;
 892
 893         if (CHIP_REV_IS_EMUL(p_dev)) {
 894                 if (ECORE_IS_AH(p_dev))
 895                         pl_hv |= 0x600;
 896         }
 897
 898         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
 899
 900         if (CHIP_REV_IS_EMUL(p_dev) &&
 901             (ECORE_IS_AH(p_dev)))
 902                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
 903                          0x3ffffff);
 904
 905         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
 906         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
 907         if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
 908                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
 909
 910         if (CHIP_REV_IS_EMUL(p_dev)) {
 911                 if (ECORE_IS_AH(p_dev)) {
 912                         /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
 913                         ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
 914                                  (p_dev->num_ports_in_engines >> 1));
 915
 916                         ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
 917                                  p_dev->num_ports_in_engines == 4 ? 0 : 3);
 918                 }
 919         }
 920
 921         /* Poll on RBC */
 922         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
 923         for (i = 0; i < 100; i++) {
 924                 OSAL_UDELAY(50);
 925                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
 926                         break;
 927         }
 928         if (i == 100)
 929                 DP_NOTICE(p_hwfn, true,
 930                           "RBC done failed to complete in PSWRQ2\n");
 931
 932         return ECORE_SUCCESS;
 933 }
 934 #endif
 935
 936 /* Init run time data for all PFs and their VFs on an engine.
 937  * TBD - for VFs - Once we have parent PF info for each VF in
 938  * shmem available as CAU requires knowledge of parent PF for each VF.
 939  */
 940 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
 941 {
 942         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
 943         int i, sb_id;
 944
 945         for_each_hwfn(p_dev, i) {
 946                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 947                 struct ecore_igu_info *p_igu_info;
 948                 struct ecore_igu_block *p_block;
 949                 struct cau_sb_entry sb_entry;
 950
 951                 p_igu_info = p_hwfn->hw_info.p_igu_info;
 952
 953                 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
 954                      sb_id++) {
 955                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
 956
 957                         if (!p_block->is_pf)
 958                                 continue;
 959
 960                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
 961                                                 p_block->function_id, 0, 0);
 962                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
 963                 }
 964         }
 965 }
 966
 967 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
 968                                                  struct ecore_ptt *p_ptt,
 969                                                  int hw_mode)
 970 {
 971         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 972         struct ecore_dev *p_dev = p_hwfn->p_dev;
 973         u8 vf_id, max_num_vfs;
 974         u16 num_pfs, pf_id;
 975         u32 concrete_fid;
 976         enum _ecore_status_t rc = ECORE_SUCCESS;
 977
 978         ecore_init_cau_rt_data(p_dev);
 979
 980         /* Program GTT windows */
 981         ecore_gtt_init(p_hwfn);
 982
 983 #ifndef ASIC_ONLY
 984         if (CHIP_REV_IS_EMUL(p_dev)) {
 985                 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
 986                 if (rc != ECORE_SUCCESS)
 987                         return rc;
 988         }
 989 #endif
 990
 991         if (p_hwfn->mcp_info) {
 992                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
 993                         qm_info->pf_rl_en = 1;
 994                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
 995                         qm_info->pf_wfq_en = 1;
 996         }
 997
 998         ecore_qm_common_rt_init(p_hwfn,
 999                                 p_dev->num_ports_in_engines,
1000                                 qm_info->max_phys_tcs_per_port,
1001                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1002                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1003                                 qm_info->qm_port_params);
1004
1005         ecore_cxt_hw_init_common(p_hwfn);
1006
1007         /* Close gate from NIG to BRB/Storm; By default they are open, but
1008          * we close them to prevent NIG from passing data to reset blocks.
1009          * Should have been done in the ENGINE phase, but init-tool lacks
1010          * proper port-pretend capabilities.
1011          */
1012         ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1013         ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1014         ecore_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
1015         ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1016         ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1017         ecore_port_unpretend(p_hwfn, p_ptt);
1018
1019         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1020         if (rc != ECORE_SUCCESS)
1021                 return rc;
1022
1023         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1024          * need to decide with which value, maybe runtime
1025          */
1026         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1027         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1028
1029         if (ECORE_IS_BB(p_dev)) {
1030                 /* Workaround clears ROCE search for all functions to prevent
1031                  * involving non initialized function in processing ROCE packet.
1032                  */
1033                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1034                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1035                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1036                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1037                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1038                 }
1039                 /* pretend to original PF */
1040                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1041         }
1042
1043         /* Workaround for avoiding CCFC execution error when getting packets
1044          * with CRC errors, and allowing instead the invoking of the FW error
1045          * handler.
1046          * This is not done inside the init tool since it currently can't
1047          * perform a pretending to VFs.
1048          */
1049         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1050         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1051                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1052                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1053                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1054                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1055                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1056                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1057         }
1058         /* pretend to original PF */
1059         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1060
1061         return rc;
1062 }
1063
1064 #ifndef ASIC_ONLY
1065 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1066 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1067
1068 #define PMEG_IF_BYTE_COUNT      8
1069
1070 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1071                              struct ecore_ptt *p_ptt,
1072                              u32 addr, u64 data, u8 reg_type, u8 port)
1073 {
1074         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1075                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1076                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1077                    (8 << PMEG_IF_BYTE_COUNT),
1078                    (reg_type << 25) | (addr << 8) | port,
1079                    (u32)((data >> 32) & 0xffffffff),
1080                    (u32)(data & 0xffffffff));
1081
1082         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1083                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1084                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1085         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1086                  (reg_type << 25) | (addr << 8) | port);
1087         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1088         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1089                  (data >> 32) & 0xffffffff);
1090 }
1091
1092 #define XLPORT_MODE_REG (0x20a)
1093 #define XLPORT_MAC_CONTROL (0x210)
1094 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1095 #define XLPORT_ENABLE_REG (0x20b)
1096
1097 #define XLMAC_CTRL (0x600)
1098 #define XLMAC_MODE (0x601)
1099 #define XLMAC_RX_MAX_SIZE (0x608)
1100 #define XLMAC_TX_CTRL (0x604)
1101 #define XLMAC_PAUSE_CTRL (0x60d)
1102 #define XLMAC_PFC_CTRL (0x60e)
1103
1104 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1105                                     struct ecore_ptt *p_ptt)
1106 {
1107         u8 loopback = 0, port = p_hwfn->port_id * 2;
1108
1109         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1110
1111         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1112         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1113                          port);
1114         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1115         /* XLMAC: SOFT RESET */
1116         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1117         /* XLMAC: Port Speed >= 10Gbps */
1118         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1119         /* XLMAC: Max Size */
1120         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1121         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1122                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1123                          0, port);
1124         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1125         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1126                          0x30ffffc000ULL, 0, port);
1127         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1128                          port); /* XLMAC: TX_EN, RX_EN */
1129         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1130         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1131                          0x1003 | (loopback << 2), 0, port);
1132         /* Enabled Parallel PFC interface */
1133         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1134
1135         /* XLPORT port enable */
1136         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1137 }
1138
1139 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1140                                        struct ecore_ptt *p_ptt)
1141 {
1142         u8 port = p_hwfn->port_id;
1143         u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1144
1145         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1146
1147         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1148                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1149                  (port <<
1150                   CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1151                  (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1152
1153         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1154                  1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1155
1156         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1157                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1158
1159         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1160                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1161
1162         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1163                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1164
1165         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1166                  (0xA <<
1167                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1168                  (8 <<
1169                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1170
1171         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1172                  0xa853);
1173 }
1174
1175 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1176                                  struct ecore_ptt *p_ptt)
1177 {
1178         if (ECORE_IS_AH(p_hwfn->p_dev))
1179                 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1180         else /* BB */
1181                 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1182 }
1183
1184 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1185                                struct ecore_ptt *p_ptt,  u8 port)
1186 {
1187         int port_offset = port ? 0x800 : 0;
1188         u32 xmac_rxctrl = 0;
1189
1190         /* Reset of XMAC */
1191         /* FIXME: move to common start */
1192         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1193                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1194         OSAL_MSLEEP(1);
1195         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1196                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1197
1198         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1199
1200         /* Set the number of ports on the Warp Core to 10G */
1201         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1202
1203         /* Soft reset of XMAC */
1204         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1205                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1206         OSAL_MSLEEP(1);
1207         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1208                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1209
1210         /* FIXME: move to common end */
1211         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1212                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1213
1214         /* Set Max packet size: initialize XMAC block register for port 0 */
1215         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1216
1217         /* CRC append for Tx packets: init XMAC block register for port 1 */
1218         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1219
1220         /* Enable TX and RX: initialize XMAC block register for port 1 */
1221         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1222                  XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1223         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1224                                XMAC_REG_RX_CTRL_BB + port_offset);
1225         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1226         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1227 }
1228 #endif
1229
1230 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1231                                                struct ecore_ptt *p_ptt,
1232                                                int hw_mode)
1233 {
1234         enum _ecore_status_t rc = ECORE_SUCCESS;
1235
1236         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1237                             hw_mode);
1238         if (rc != ECORE_SUCCESS)
1239                 return rc;
1240 #ifndef ASIC_ONLY
1241         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1242                 return ECORE_SUCCESS;
1243
1244         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1245                 if (ECORE_IS_AH(p_hwfn->p_dev))
1246                         return ECORE_SUCCESS;
1247                 else if (ECORE_IS_BB(p_hwfn->p_dev))
1248                         ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
1249         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1250                 if (p_hwfn->p_dev->num_hwfns > 1) {
1251                         /* Activate OPTE in CMT */
1252                         u32 val;
1253
1254                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1255                         val |= 0x10;
1256                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1257                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1258                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1259                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1260                         ecore_wr(p_hwfn, p_ptt,
1261                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1262                         ecore_wr(p_hwfn, p_ptt,
1263                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1264                         ecore_wr(p_hwfn, p_ptt,
1265                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1266                                  0x55555555);
1267                 }
1268
1269                 ecore_emul_link_init(p_hwfn, p_ptt);
1270         } else {
1271                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1272         }
1273 #endif
1274
1275         return rc;
1276 }
1277
1278 static enum _ecore_status_t
1279 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1280                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1281 {
1282         u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1283         u32 dpi_bit_shift, dpi_count;
1284         u32 min_dpis;
1285
1286         /* Calculate DPI size
1287          * ------------------
1288          * The PWM region contains Doorbell Pages. The first is reserverd for
1289          * the kernel for, e.g, L2. The others are free to be used by non-
1290          * trusted applications, typically from user space. Each page, called a
1291          * doorbell page is sectioned into windows that allow doorbells to be
1292          * issued in parallel by the kernel/application. The size of such a
1293          * window (a.k.a. WID) is 1kB.
1294          * Summary:
1295          *    1kB WID x N WIDS = DPI page size
1296          *    DPI page size x N DPIs = PWM region size
1297          * Notes:
1298          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1299          * in order to ensure that two applications won't share the same page.
1300          * It also must contain at least one WID per CPU to allow parallelism.
1301          * It also must be a power of 2, since it is stored as a bit shift.
1302          *
1303          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1304          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1305          * containing 4 WIDs.
1306          */
1307         dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1308         dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1309         dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1310         dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1311         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1312
1313         dpi_count = pwm_region_size / dpi_page_size;
1314
1315         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1316         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1317
1318         /* Update hwfn */
1319         p_hwfn->dpi_size = dpi_page_size;
1320         p_hwfn->dpi_count = dpi_count;
1321
1322         /* Update registers */
1323         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1324
1325         if (dpi_count < min_dpis)
1326                 return ECORE_NORESOURCES;
1327
1328         return ECORE_SUCCESS;
1329 }
1330
1331 enum ECORE_ROCE_EDPM_MODE {
1332         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1333         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1334         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1335 };
1336
1337 static enum _ecore_status_t
1338 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1339                               struct ecore_ptt *p_ptt)
1340 {
1341         u32 pwm_regsize, norm_regsize;
1342         u32 non_pwm_conn, min_addr_reg1;
1343         u32 db_bar_size, n_cpus;
1344         u32 roce_edpm_mode;
1345         u32 pf_dems_shift;
1346         int rc = ECORE_SUCCESS;
1347         u8 cond;
1348
1349         db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1350         if (p_hwfn->p_dev->num_hwfns > 1)
1351                 db_bar_size /= 2;
1352
1353         /* Calculate doorbell regions
1354          * -----------------------------------
1355          * The doorbell BAR is made of two regions. The first is called normal
1356          * region and the second is called PWM region. In the normal region
1357          * each ICID has its own set of addresses so that writing to that
1358          * specific address identifies the ICID. In the Process Window Mode
1359          * region the ICID is given in the data written to the doorbell. The
1360          * above per PF register denotes the offset in the doorbell BAR in which
1361          * the PWM region begins.
1362          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1363          * non-PWM connection. The calculation below computes the total non-PWM
1364          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1365          * in units of 4,096 bytes.
1366          */
1367         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1368             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1369                                           OSAL_NULL) +
1370             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1371         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1372         min_addr_reg1 = norm_regsize / 4096;
1373         pwm_regsize = db_bar_size - norm_regsize;
1374
1375         /* Check that the normal and PWM sizes are valid */
1376         if (db_bar_size < norm_regsize) {
1377                 DP_ERR(p_hwfn->p_dev,
1378                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1379                        db_bar_size, norm_regsize);
1380                 return ECORE_NORESOURCES;
1381         }
1382         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1383                 DP_ERR(p_hwfn->p_dev,
1384                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1385                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1386                        norm_regsize);
1387                 return ECORE_NORESOURCES;
1388         }
1389
1390         /* Calculate number of DPIs */
1391         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1392         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1393             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1394                 /* Either EDPM is mandatory, or we are attempting to allocate a
1395                  * WID per CPU.
1396                  */
1397                 n_cpus = OSAL_NUM_ACTIVE_CPU();
1398                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1399         }
1400
1401         cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1402             (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1403         if (cond || p_hwfn->dcbx_no_edpm) {
1404                 /* Either EDPM is disabled from user configuration, or it is
1405                  * disabled via DCBx, or it is not mandatory and we failed to
1406                  * allocated a WID per CPU.
1407                  */
1408                 n_cpus = 1;
1409                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1410
1411                 /* If we entered this flow due to DCBX then the DPM register is
1412                  * already configured.
1413                  */
1414         }
1415
1416         DP_INFO(p_hwfn,
1417                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1418                 norm_regsize, pwm_regsize);
1419         DP_INFO(p_hwfn,
1420                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1421                 p_hwfn->dpi_size, p_hwfn->dpi_count,
1422                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1423                 "disabled" : "enabled");
1424
1425         /* Check return codes from above calls */
1426         if (rc) {
1427                 DP_ERR(p_hwfn,
1428                        "Failed to allocate enough DPIs\n");
1429                 return ECORE_NORESOURCES;
1430         }
1431
1432         /* Update hwfn */
1433         p_hwfn->dpi_start_offset = norm_regsize;
1434
1435         /* Update registers */
1436         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1437         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1438         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1439         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1440
1441         return ECORE_SUCCESS;
1442 }
1443
1444 static enum _ecore_status_t
1445 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1446                  struct ecore_ptt *p_ptt,
1447                  struct ecore_tunn_start_params *p_tunn,
1448                  int hw_mode,
1449                  bool b_hw_start,
1450                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1451 {
1452         u8 rel_pf_id = p_hwfn->rel_pf_id;
1453         u32 prs_reg;
1454         enum _ecore_status_t rc = ECORE_SUCCESS;
1455         u16 ctrl;
1456         int pos;
1457
1458         if (p_hwfn->mcp_info) {
1459                 struct ecore_mcp_function_info *p_info;
1460
1461                 p_info = &p_hwfn->mcp_info->func_info;
1462                 if (p_info->bandwidth_min)
1463                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1464
1465                 /* Update rate limit once we'll actually have a link */
1466                 p_hwfn->qm_info.pf_rl = 100000;
1467         }
1468         ecore_cxt_hw_init_pf(p_hwfn);
1469
1470         ecore_int_igu_init_rt(p_hwfn);
1471
1472         /* Set VLAN in NIG if needed */
1473         if (hw_mode & (1 << MODE_MF_SD)) {
1474                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1475                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1476                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1477                              p_hwfn->hw_info.ovlan);
1478         }
1479
1480         /* Enable classification by MAC if needed */
1481         if (hw_mode & (1 << MODE_MF_SI)) {
1482                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1483                            "Configuring TAGMAC_CLS_TYPE\n");
1484                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1485                              1);
1486         }
1487
1488         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
1489         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1490                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1491         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1492                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1493         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1494
1495         /* perform debug configuration when chip is out of reset */
1496         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1497
1498         /* Cleanup chip from previous driver if such remains exist */
1499         rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1500         if (rc != ECORE_SUCCESS) {
1501                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1502                 return rc;
1503         }
1504
1505         /* PF Init sequence */
1506         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1507         if (rc)
1508                 return rc;
1509
1510         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1511         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1512         if (rc)
1513                 return rc;
1514
1515         /* Pure runtime initializations - directly to the HW  */
1516         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1517
1518         /* PCI relaxed ordering causes a decrease in the performance on some
1519          * systems. Till a root cause is found, disable this attribute in the
1520          * PCI config space.
1521          */
1522         /* Not in use @DPDK
1523         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1524         * if (!pos) {
1525         *       DP_NOTICE(p_hwfn, true,
1526         *                 "Failed to find the PCIe Cap\n");
1527         *       return ECORE_IO;
1528         * }
1529         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1530         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1531         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1532         */
1533
1534         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1535         if (rc)
1536                 return rc;
1537         if (b_hw_start) {
1538                 /* enable interrupts */
1539                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1540                 if (rc != ECORE_SUCCESS)
1541                         return rc;
1542
1543                 /* send function start command */
1544                 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1545                                        allow_npar_tx_switch);
1546                 if (rc) {
1547                         DP_NOTICE(p_hwfn, true,
1548                                   "Function start ramrod failed\n");
1549                 } else {
1550                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1551                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1552                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1553
1554                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1555                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1556                                          (1 << 2));
1557                                 ecore_wr(p_hwfn, p_ptt,
1558                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1559                                     0x100);
1560                         }
1561                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1562                                    "PRS_REG_SEARCH registers after start PFn\n");
1563                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1564                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1565                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1566                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1567                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1568                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1569                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1570                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1571                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1572                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1573                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1574                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1575                         prs_reg = ecore_rd(p_hwfn, p_ptt,
1576                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
1577                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1578                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1579                                    prs_reg);
1580                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1581                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1582                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1583                 }
1584         }
1585         return rc;
1586 }
1587
1588 static enum _ecore_status_t
1589 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1590                       struct ecore_ptt *p_ptt, u8 enable)
1591 {
1592         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1593
1594         /* Change PF in PXP */
1595         ecore_wr(p_hwfn, p_ptt,
1596                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1597
1598         /* wait until value is set - try for 1 second every 50us */
1599         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1600                 val = ecore_rd(p_hwfn, p_ptt,
1601                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1602                 if (val == set_val)
1603                         break;
1604
1605                 OSAL_UDELAY(50);
1606         }
1607
1608         if (val != set_val) {
1609                 DP_NOTICE(p_hwfn, true,
1610                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1611                 return ECORE_UNKNOWN_ERROR;
1612         }
1613
1614         return ECORE_SUCCESS;
1615 }
1616
1617 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1618                                   struct ecore_ptt *p_main_ptt)
1619 {
1620         /* Read shadow of current MFW mailbox */
1621         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1622         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1623                     p_hwfn->mcp_info->mfw_mb_cur,
1624                     p_hwfn->mcp_info->mfw_mb_length);
1625 }
1626
1627 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1628                                    struct ecore_hw_init_params *p_params)
1629 {
1630         enum _ecore_status_t rc = ECORE_SUCCESS, mfw_rc;
1631         u32 load_code, param, drv_mb_param;
1632         struct ecore_hwfn *p_hwfn;
1633         int i;
1634
1635         if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
1636             (p_dev->num_hwfns > 1)) {
1637                 DP_NOTICE(p_dev, false,
1638                           "MSI mode is not supported for CMT devices\n");
1639                 return ECORE_INVAL;
1640         }
1641
1642         if (IS_PF(p_dev)) {
1643                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1644                 if (rc != ECORE_SUCCESS)
1645                         return rc;
1646         }
1647
1648         for_each_hwfn(p_dev, i) {
1649                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1650
1651                 if (IS_VF(p_dev)) {
1652                         p_hwfn->b_int_enabled = 1;
1653                         continue;
1654                 }
1655
1656                 /* Enable DMAE in PXP */
1657                 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1658                 if (rc != ECORE_SUCCESS)
1659                         return rc;
1660
1661                 rc = ecore_calc_hw_mode(p_hwfn);
1662                 if (rc != ECORE_SUCCESS)
1663                         return rc;
1664
1665                 /* @@@TBD need to add here:
1666                  * Check for fan failure
1667                  * Prev_unload
1668                  */
1669                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1670                 if (rc) {
1671                         DP_NOTICE(p_hwfn, true,
1672                                   "Failed sending LOAD_REQ command\n");
1673                         return rc;
1674                 }
1675
1676                 /* CQ75580:
1677                  * When coming back from hiberbate state, the registers from
1678                  * which shadow is read initially are not initialized. It turns
1679                  * out that these registers get initialized during the call to
1680                  * ecore_mcp_load_req request. So we need to reread them here
1681                  * to get the proper shadow register value.
1682                  * Note: This is a workaround for the missing MFW
1683                  * initialization. It may be removed once the implementation
1684                  * is done.
1685                  */
1686                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1687
1688                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1689                            "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1690                            rc, load_code);
1691
1692                 /* Only relevant for recovery:
1693                  * Clear the indication after the LOAD_REQ command is responded
1694                  * by the MFW.
1695                  */
1696                 p_dev->recov_in_prog = false;
1697
1698                 p_hwfn->first_on_engine = (load_code ==
1699                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1700
1701                 if (!qm_lock_init) {
1702                         OSAL_SPIN_LOCK_INIT(&qm_lock);
1703                         qm_lock_init = true;
1704                 }
1705
1706                 switch (load_code) {
1707                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1708                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1709                                                   p_hwfn->hw_info.hw_mode);
1710                         if (rc)
1711                                 break;
1712                         /* Fall into */
1713                 case FW_MSG_CODE_DRV_LOAD_PORT:
1714                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1715                                                 p_hwfn->hw_info.hw_mode);
1716                         if (rc)
1717                                 break;
1718                         /* Fall into */
1719                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1720                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1721                                               p_params->p_tunn,
1722                                               p_hwfn->hw_info.hw_mode,
1723                                               p_params->b_hw_start,
1724                                               p_params->int_mode,
1725                                               p_params->allow_npar_tx_switch);
1726                         break;
1727                 default:
1728                         rc = ECORE_NOTIMPL;
1729                         break;
1730                 }
1731
1732                 if (rc != ECORE_SUCCESS)
1733                         DP_NOTICE(p_hwfn, true,
1734                                   "init phase failed for loadcode 0x%x (rc %d)\n",
1735                                   load_code, rc);
1736
1737                 /* ACK mfw regardless of success or failure of initialization */
1738                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1739                                        DRV_MSG_CODE_LOAD_DONE,
1740                                        0, &load_code, &param);
1741                 if (rc != ECORE_SUCCESS)
1742                         return rc;
1743                 if (mfw_rc != ECORE_SUCCESS) {
1744                         DP_NOTICE(p_hwfn, true,
1745                                   "Failed sending LOAD_DONE command\n");
1746                         return mfw_rc;
1747                 }
1748
1749                 /* send DCBX attention request command */
1750                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1751                            "sending phony dcbx set command to trigger DCBx attention handling\n");
1752                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1753                                        DRV_MSG_CODE_SET_DCBX,
1754                                        1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1755                                        &load_code, &param);
1756                 if (mfw_rc != ECORE_SUCCESS) {
1757                         DP_NOTICE(p_hwfn, true,
1758                                   "Failed to send DCBX attention request\n");
1759                         return mfw_rc;
1760                 }
1761
1762                 p_hwfn->hw_init_done = true;
1763         }
1764
1765         if (IS_PF(p_dev)) {
1766                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
1767                 drv_mb_param = (FW_MAJOR_VERSION << 24) |
1768                                (FW_MINOR_VERSION << 16) |
1769                                (FW_REVISION_VERSION << 8) |
1770                                (FW_ENGINEERING_VERSION);
1771                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1772                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1773                                    drv_mb_param, &load_code, &param);
1774                 if (rc != ECORE_SUCCESS) {
1775                         DP_ERR(p_hwfn, "Failed to send firmware version\n");
1776                         return rc;
1777                 }
1778
1779                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
1780                                                       p_hwfn->p_main_ptt,
1781                                                 ECORE_OV_DRIVER_STATE_DISABLED);
1782         }
1783
1784         return rc;
1785 }
1786
1787 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
1788 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
1789                                  struct ecore_hwfn *p_hwfn,
1790                                  struct ecore_ptt *p_ptt)
1791 {
1792         int i;
1793
1794         /* close timers */
1795         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1796         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1797         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
1798                                                                         i++) {
1799                 if ((!ecore_rd(p_hwfn, p_ptt,
1800                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1801                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1802                         break;
1803
1804                 /* Dependent on number of connection/tasks, possibly
1805                  * 1ms sleep is required between polls
1806                  */
1807                 OSAL_MSLEEP(1);
1808         }
1809
1810         if (i < ECORE_HW_STOP_RETRY_LIMIT)
1811                 return;
1812
1813         DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
1814                   " [Connection %02x Tasks %02x]\n",
1815                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1816                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1817 }
1818
1819 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
1820 {
1821         int j;
1822
1823         for_each_hwfn(p_dev, j) {
1824                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1825                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1826
1827                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1828         }
1829 }
1830
1831 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
1832 {
1833         enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
1834         int j;
1835
1836         for_each_hwfn(p_dev, j) {
1837                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1838                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1839
1840                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
1841
1842                 if (IS_VF(p_dev)) {
1843                         ecore_vf_pf_int_cleanup(p_hwfn);
1844                         continue;
1845                 }
1846
1847                 /* mark the hw as uninitialized... */
1848                 p_hwfn->hw_init_done = false;
1849
1850                 rc = ecore_sp_pf_stop(p_hwfn);
1851                 if (rc)
1852                         DP_NOTICE(p_hwfn, true,
1853                                   "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
1854
1855                 /* perform debug action after PF stop was sent */
1856                 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
1857
1858                 /* close NIG to BRB gate */
1859                 ecore_wr(p_hwfn, p_ptt,
1860                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1861
1862                 /* close parser */
1863                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1864                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1865                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1866                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1867                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1868
1869                 /* @@@TBD - clean transmission queues (5.b) */
1870                 /* @@@TBD - clean BTB (5.c) */
1871
1872                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1873
1874                 /* @@@TBD - verify DMAE requests are done (8) */
1875
1876                 /* Disable Attention Generation */
1877                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1878                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1879                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1880                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1881                 /* Need to wait 1ms to guarantee SBs are cleared */
1882                 OSAL_MSLEEP(1);
1883         }
1884
1885         if (IS_PF(p_dev)) {
1886                 /* Disable DMAE in PXP - in CMT, this should only be done for
1887                  * first hw-function, and only after all transactions have
1888                  * stopped for all active hw-functions.
1889                  */
1890                 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
1891                                              p_dev->hwfns[0].p_main_ptt, false);
1892                 if (t_rc != ECORE_SUCCESS)
1893                         rc = t_rc;
1894         }
1895
1896         return rc;
1897 }
1898
1899 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
1900 {
1901         int j;
1902
1903         for_each_hwfn(p_dev, j) {
1904                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1905                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1906
1907                 if (IS_VF(p_dev)) {
1908                         ecore_vf_pf_int_cleanup(p_hwfn);
1909                         continue;
1910                 }
1911
1912                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1913                            "Shutting down the fastpath\n");
1914
1915                 ecore_wr(p_hwfn, p_ptt,
1916                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1917
1918                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1919                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1920                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1921                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1922                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1923
1924                 /* @@@TBD - clean transmission queues (5.b) */
1925                 /* @@@TBD - clean BTB (5.c) */
1926
1927                 /* @@@TBD - verify DMAE requests are done (8) */
1928
1929                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1930                 /* Need to wait 1ms to guarantee SBs are cleared */
1931                 OSAL_MSLEEP(1);
1932         }
1933 }
1934
1935 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
1936 {
1937         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1938
1939         if (IS_VF(p_hwfn->p_dev))
1940                 return;
1941
1942         /* If roce info is allocated it means roce is initialized and should
1943          * be enabled in searcher.
1944          */
1945         if (p_hwfn->p_rdma_info) {
1946                 if (p_hwfn->b_rdma_enabled_in_prs)
1947                         ecore_wr(p_hwfn, p_ptt,
1948                                  p_hwfn->rdma_prs_search_reg, 0x1);
1949                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
1950         }
1951
1952         /* Re-open incoming traffic */
1953         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1954                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1955 }
1956
1957 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
1958                                              struct ecore_ptt *p_ptt, u32 reg,
1959                                              bool expected)
1960 {
1961         u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
1962
1963         if (assert_val != expected) {
1964                 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
1965                           reg, expected);
1966                 return ECORE_UNKNOWN_ERROR;
1967         }
1968
1969         return 0;
1970 }
1971
1972 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
1973 {
1974         enum _ecore_status_t rc = ECORE_SUCCESS;
1975         u32 unload_resp, unload_param;
1976         int i;
1977
1978         for_each_hwfn(p_dev, i) {
1979                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1980
1981                 if (IS_VF(p_dev)) {
1982                         rc = ecore_vf_pf_reset(p_hwfn);
1983                         if (rc)
1984                                 return rc;
1985                         continue;
1986                 }
1987
1988                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
1989
1990                 /* Check for incorrect states */
1991                 if (!p_dev->recov_in_prog) {
1992                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1993                                          QM_REG_USG_CNT_PF_TX, 0);
1994                         ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1995                                          QM_REG_USG_CNT_PF_OTHER, 0);
1996                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
1997                 }
1998
1999                 /* Disable PF in HW blocks */
2000                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2001                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
2002
2003                 if (p_dev->recov_in_prog) {
2004                         DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2005                                    "Recovery is in progress -> skip sending unload_req/done\n");
2006                         break;
2007                 }
2008
2009                 /* Send unload command to MCP */
2010                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2011                                    DRV_MSG_CODE_UNLOAD_REQ,
2012                                    DRV_MB_PARAM_UNLOAD_WOL_MCP,
2013                                    &unload_resp, &unload_param);
2014                 if (rc != ECORE_SUCCESS) {
2015                         DP_NOTICE(p_hwfn, true,
2016                                   "ecore_hw_reset: UNLOAD_REQ failed\n");
2017                         /* @@TBD - what to do? for now, assume ENG. */
2018                         unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
2019                 }
2020
2021                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2022                                    DRV_MSG_CODE_UNLOAD_DONE,
2023                                    0, &unload_resp, &unload_param);
2024                 if (rc != ECORE_SUCCESS) {
2025                         DP_NOTICE(p_hwfn,
2026                                   true, "ecore_hw_reset: UNLOAD_DONE failed\n");
2027                         /* @@@TBD - Should it really ASSERT here ? */
2028                         return rc;
2029                 }
2030         }
2031
2032         return rc;
2033 }
2034
2035 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2036 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2037 {
2038         ecore_ptt_pool_free(p_hwfn);
2039         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2040 }
2041
2042 /* Setup bar access */
2043 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2044 {
2045         /* clear indirect access */
2046         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2047                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2048                          PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2049                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2050                          PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2051                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2052                          PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2053                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2054                          PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2055         } else {
2056                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2057                          PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2058                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2059                          PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2060                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2061                          PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2062                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2063                          PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2064         }
2065
2066         /* Clean Previous errors if such exist */
2067         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2068                  PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2069
2070         /* enable internal target-read */
2071         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2072                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2073 }
2074
2075 static void get_function_id(struct ecore_hwfn *p_hwfn)
2076 {
2077         /* ME Register */
2078         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2079                                                   PXP_PF_ME_OPAQUE_ADDR);
2080
2081         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2082
2083         /* Bits 16-19 from the ME registers are the pf_num */
2084         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2085         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2086                                       PXP_CONCRETE_FID_PFID);
2087         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2088                                     PXP_CONCRETE_FID_PORT);
2089
2090         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2091                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2092                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2093 }
2094
2095 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2096 {
2097         u32 *feat_num = p_hwfn->hw_info.feat_num;
2098         struct ecore_sb_cnt_info sb_cnt_info;
2099         int num_features = 1;
2100
2101         /* L2 Queues require each: 1 status block. 1 L2 queue */
2102         feat_num[ECORE_PF_L2_QUE] =
2103             OSAL_MIN_T(u32,
2104                        RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2105                        RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2106
2107         OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2108         ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2109         feat_num[ECORE_VF_L2_QUE] =
2110                 OSAL_MIN_T(u32,
2111                            RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2112                            FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2113                            sb_cnt_info.sb_iov_cnt);
2114
2115         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2116                    "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d num_features=%d\n",
2117                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2118                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2119                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2120                    RESC_NUM(p_hwfn, ECORE_SB),
2121                    num_features);
2122 }
2123
2124 static enum resource_id_enum
2125 ecore_hw_get_mfw_res_id(enum ecore_resources res_id)
2126 {
2127         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2128
2129         switch (res_id) {
2130         case ECORE_SB:
2131                 mfw_res_id = RESOURCE_NUM_SB_E;
2132                 break;
2133         case ECORE_L2_QUEUE:
2134                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2135                 break;
2136         case ECORE_VPORT:
2137                 mfw_res_id = RESOURCE_NUM_VPORT_E;
2138                 break;
2139         case ECORE_RSS_ENG:
2140                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2141                 break;
2142         case ECORE_PQ:
2143                 mfw_res_id = RESOURCE_NUM_PQ_E;
2144                 break;
2145         case ECORE_RL:
2146                 mfw_res_id = RESOURCE_NUM_RL_E;
2147                 break;
2148         case ECORE_MAC:
2149         case ECORE_VLAN:
2150                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2151                 mfw_res_id = RESOURCE_VFC_FILTER_E;
2152                 break;
2153         case ECORE_ILT:
2154                 mfw_res_id = RESOURCE_ILT_E;
2155                 break;
2156         case ECORE_LL2_QUEUE:
2157                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2158                 break;
2159         case ECORE_RDMA_CNQ_RAM:
2160         case ECORE_CMDQS_CQS:
2161                 /* CNQ/CMDQS are the same resource */
2162                 mfw_res_id = RESOURCE_CQS_E;
2163                 break;
2164         case ECORE_RDMA_STATS_QUEUE:
2165                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2166                 break;
2167         default:
2168                 break;
2169         }
2170
2171         return mfw_res_id;
2172 }
2173
2174 static u32 ecore_hw_get_dflt_resc_num(struct ecore_hwfn *p_hwfn,
2175                                       enum ecore_resources res_id)
2176 {
2177         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2178         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2179         struct ecore_sb_cnt_info sb_cnt_info;
2180         u32 dflt_resc_num = 0;
2181
2182         switch (res_id) {
2183         case ECORE_SB:
2184                 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2185                 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2186                 dflt_resc_num = sb_cnt_info.sb_cnt;
2187                 break;
2188         case ECORE_L2_QUEUE:
2189                 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2190                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
2191                 break;
2192         case ECORE_VPORT:
2193                 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2194                                  MAX_NUM_VPORTS_BB) / num_funcs;
2195                 break;
2196         case ECORE_RSS_ENG:
2197                 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2198                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2199                 break;
2200         case ECORE_PQ:
2201                 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2202                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
2203                 break;
2204         case ECORE_RL:
2205                 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2206                 break;
2207         case ECORE_MAC:
2208         case ECORE_VLAN:
2209                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2210                 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2211                 break;
2212         case ECORE_ILT:
2213                 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2214                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2215                 break;
2216         case ECORE_LL2_QUEUE:
2217                 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2218                 break;
2219         case ECORE_RDMA_CNQ_RAM:
2220         case ECORE_CMDQS_CQS:
2221                 /* CNQ/CMDQS are the same resource */
2222                 /* @DPDK */
2223                 dflt_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2224                 break;
2225         case ECORE_RDMA_STATS_QUEUE:
2226                 /* @DPDK */
2227                 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2228                                  MAX_NUM_VPORTS_BB) / num_funcs;
2229                 break;
2230         default:
2231                 break;
2232         }
2233
2234         return dflt_resc_num;
2235 }
2236
2237 static const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2238 {
2239         switch (res_id) {
2240         case ECORE_SB:
2241                 return "SB";
2242         case ECORE_L2_QUEUE:
2243                 return "L2_QUEUE";
2244         case ECORE_VPORT:
2245                 return "VPORT";
2246         case ECORE_RSS_ENG:
2247                 return "RSS_ENG";
2248         case ECORE_PQ:
2249                 return "PQ";
2250         case ECORE_RL:
2251                 return "RL";
2252         case ECORE_MAC:
2253                 return "MAC";
2254         case ECORE_VLAN:
2255                 return "VLAN";
2256         case ECORE_RDMA_CNQ_RAM:
2257                 return "RDMA_CNQ_RAM";
2258         case ECORE_ILT:
2259                 return "ILT";
2260         case ECORE_LL2_QUEUE:
2261                 return "LL2_QUEUE";
2262         case ECORE_CMDQS_CQS:
2263                 return "CMDQS_CQS";
2264         case ECORE_RDMA_STATS_QUEUE:
2265                 return "RDMA_STATS_QUEUE";
2266         default:
2267                 return "UNKNOWN_RESOURCE";
2268         }
2269 }
2270
2271 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2272                                                    enum ecore_resources res_id,
2273                                                    bool drv_resc_alloc)
2274 {
2275         u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
2276         u32 *p_resc_num, *p_resc_start;
2277         struct resource_info resc_info;
2278         enum _ecore_status_t rc;
2279
2280         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2281         p_resc_start = &RESC_START(p_hwfn, res_id);
2282
2283         dflt_resc_num = ecore_hw_get_dflt_resc_num(p_hwfn, res_id);
2284         if (!dflt_resc_num) {
2285                 DP_ERR(p_hwfn,
2286                        "Failed to get default amount for resource %d [%s]\n",
2287                         res_id, ecore_hw_get_resc_name(res_id));
2288                 return ECORE_INVAL;
2289         }
2290         dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
2291
2292 #ifndef ASIC_ONLY
2293         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2294                 *p_resc_num = dflt_resc_num;
2295                 *p_resc_start = dflt_resc_start;
2296                 goto out;
2297         }
2298 #endif
2299
2300         OSAL_MEM_ZERO(&resc_info, sizeof(resc_info));
2301         resc_info.res_id = ecore_hw_get_mfw_res_id(res_id);
2302         if (resc_info.res_id == RESOURCE_NUM_INVALID) {
2303                 DP_ERR(p_hwfn,
2304                        "Failed to match resource %d with MFW resources\n",
2305                        res_id);
2306                 return ECORE_INVAL;
2307         }
2308
2309         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
2310                                      &mcp_resp, &mcp_param);
2311         if (rc != ECORE_SUCCESS) {
2312                 DP_NOTICE(p_hwfn, true,
2313                           "MFW response failure for an allocation request for"
2314                           " resource %d [%s]\n",
2315                           res_id, ecore_hw_get_resc_name(res_id));
2316                 return rc;
2317         }
2318
2319         /* Default driver values are applied in the following cases:
2320          * - The resource allocation MB command is not supported by the MFW
2321          * - There is an internal error in the MFW while processing the request
2322          * - The resource ID is unknown to the MFW
2323          */
2324         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
2325             mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
2326                 /* @DPDK */
2327                 DP_INFO(p_hwfn,
2328                         "Resource %d [%s]: No allocation info was received"
2329                         " [mcp_resp 0x%x]. Applying default values"
2330                         " [num %d, start %d].\n",
2331                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2332                         dflt_resc_num, dflt_resc_start);
2333
2334                 *p_resc_num = dflt_resc_num;
2335                 *p_resc_start = dflt_resc_start;
2336                 goto out;
2337         }
2338
2339         /* TBD - remove this when revising the handling of the SB resource */
2340         if (res_id == ECORE_SB) {
2341                 /* Excluding the slowpath SB */
2342                 resc_info.size -= 1;
2343                 resc_info.offset -= p_hwfn->enabled_func_idx;
2344         }
2345
2346         *p_resc_num = resc_info.size;
2347         *p_resc_start = resc_info.offset;
2348
2349         if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2350                 DP_INFO(p_hwfn,
2351                         "Resource %d [%s]: MFW allocation [num %d, start %d] differs from default values [num %d, start %d]%s\n",
2352                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2353                         *p_resc_start, dflt_resc_num, dflt_resc_start,
2354                         drv_resc_alloc ? " - Applying default values" : "");
2355                 if (drv_resc_alloc) {
2356                         *p_resc_num = dflt_resc_num;
2357                         *p_resc_start = dflt_resc_start;
2358                 }
2359         }
2360  out:
2361         return ECORE_SUCCESS;
2362 }
2363
2364 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2365                                               bool drv_resc_alloc)
2366 {
2367         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2368         enum _ecore_status_t rc;
2369         u8 res_id;
2370 #ifndef ASIC_ONLY
2371         u32 *resc_start = p_hwfn->hw_info.resc_start;
2372         u32 *resc_num = p_hwfn->hw_info.resc_num;
2373         /* For AH, an equal share of the ILT lines between the maximal number of
2374          * PFs is not enough for RoCE. This would be solved by the future
2375          * resource allocation scheme, but isn't currently present for
2376          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2377          * to work - the BB number of ILT lines divided by its max PFs number.
2378          */
2379         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2380 #endif
2381
2382         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2383                 rc = ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2384                 if (rc != ECORE_SUCCESS)
2385                         return rc;
2386         }
2387
2388 #ifndef ASIC_ONLY
2389         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2390                 /* Reduced build contains less PQs */
2391                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2392                         resc_num[ECORE_PQ] = 32;
2393                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2394                             p_hwfn->enabled_func_idx;
2395                 }
2396
2397                 /* For AH emulation, since we have a possible maximal number of
2398                  * 16 enabled PFs, in case there are not enough ILT lines -
2399                  * allocate only first PF as RoCE and have all the other ETH
2400                  * only with less ILT lines.
2401                  */
2402                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2403                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2404                                                          resc_num[ECORE_ILT],
2405                                                          roce_min_ilt_lines);
2406         }
2407
2408         /* Correct the common ILT calculation if PF0 has more */
2409         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2410             p_hwfn->p_dev->b_is_emul_full &&
2411             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2412                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2413                     resc_num[ECORE_ILT];
2414 #endif
2415
2416         /* Sanity for ILT */
2417         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2418             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2419                 DP_NOTICE(p_hwfn, true,
2420                           "Can't assign ILT pages [%08x,...,%08x]\n",
2421                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2422                                                                   ECORE_ILT) -
2423                           1);
2424                 return ECORE_INVAL;
2425         }
2426
2427         ecore_hw_set_feat(p_hwfn);
2428
2429         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2430                    "The numbers for each resource are:\n");
2431         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2432                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2433                            ecore_hw_get_resc_name(res_id),
2434                            RESC_NUM(p_hwfn, res_id),
2435                            RESC_START(p_hwfn, res_id));
2436
2437         return ECORE_SUCCESS;
2438 }
2439
2440 static enum _ecore_status_t ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2441                                                   struct ecore_ptt *p_ptt)
2442 {
2443         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
2444         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2445         struct ecore_mcp_link_params *link;
2446
2447         /* Read global nvm_cfg address */
2448         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2449
2450         /* Verify MCP has initialized it */
2451         if (!nvm_cfg_addr) {
2452                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2453                 return ECORE_INVAL;
2454         }
2455
2456 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2457
2458         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2459
2460         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2461             OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2462                                                        core_cfg);
2463
2464         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2465
2466         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2467                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2468         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2469                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2470                 break;
2471         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2472                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2473                 break;
2474         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2475                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2476                 break;
2477         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2478                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2479                 break;
2480         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2481                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2482                 break;
2483         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2484                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2485                 break;
2486         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2487                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2488                 break;
2489         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2490                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2491                 break;
2492         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2493                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
2494                 break;
2495         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2496                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2497                 break;
2498         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2499                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2500                 break;
2501         default:
2502                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2503                           core_cfg);
2504                 break;
2505         }
2506
2507         /* Read DCBX configuration */
2508         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2509                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2510         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
2511                              port_cfg_addr +
2512                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
2513         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
2514                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
2515         switch (dcbx_mode) {
2516         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
2517                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
2518                 break;
2519         case NVM_CFG1_PORT_DCBX_MODE_CEE:
2520                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
2521                 break;
2522         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
2523                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
2524                 break;
2525         default:
2526                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
2527         }
2528
2529         /* Read default link configuration */
2530         link = &p_hwfn->mcp_info->link_input;
2531         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2532             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2533         link_temp = ecore_rd(p_hwfn, p_ptt,
2534                              port_cfg_addr +
2535                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2536         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2537         link->speed.advertised_speeds = link_temp;
2538
2539         link_temp = link->speed.advertised_speeds;
2540         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2541
2542         link_temp = ecore_rd(p_hwfn, p_ptt,
2543                              port_cfg_addr +
2544                              OFFSETOF(struct nvm_cfg1_port, link_settings));
2545         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2546                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2547         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2548                 link->speed.autoneg = true;
2549                 break;
2550         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2551                 link->speed.forced_speed = 1000;
2552                 break;
2553         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2554                 link->speed.forced_speed = 10000;
2555                 break;
2556         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2557                 link->speed.forced_speed = 25000;
2558                 break;
2559         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2560                 link->speed.forced_speed = 40000;
2561                 break;
2562         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2563                 link->speed.forced_speed = 50000;
2564                 break;
2565         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2566                 link->speed.forced_speed = 100000;
2567                 break;
2568         default:
2569                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
2570         }
2571
2572         p_hwfn->mcp_info->link_capabilities.default_speed =
2573             link->speed.forced_speed;
2574         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2575             link->speed.autoneg;
2576
2577         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2578         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2579         link->pause.autoneg = !!(link_temp &
2580                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2581         link->pause.forced_rx = !!(link_temp &
2582                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2583         link->pause.forced_tx = !!(link_temp &
2584                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2585         link->loopback_mode = 0;
2586
2587         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2588                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2589                    link->speed.forced_speed, link->speed.advertised_speeds,
2590                    link->speed.autoneg, link->pause.autoneg);
2591
2592         /* Read Multi-function information from shmem */
2593         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2594             OFFSETOF(struct nvm_cfg1, glob) +
2595             OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
2596
2597         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
2598
2599         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2600             NVM_CFG1_GLOB_MF_MODE_OFFSET;
2601
2602         switch (mf_mode) {
2603         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2604                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
2605                 break;
2606         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2607                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
2608                 break;
2609         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2610                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
2611                 break;
2612         }
2613         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2614                 p_hwfn->p_dev->mf_mode);
2615
2616         /* Read Multi-function information from shmem */
2617         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2618             OFFSETOF(struct nvm_cfg1, glob) +
2619             OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
2620
2621         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
2622         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2623                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
2624                              &p_hwfn->hw_info.device_capabilities);
2625         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2626                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
2627                              &p_hwfn->hw_info.device_capabilities);
2628         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2629                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
2630                              &p_hwfn->hw_info.device_capabilities);
2631         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2632                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
2633                              &p_hwfn->hw_info.device_capabilities);
2634         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
2635                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
2636                              &p_hwfn->hw_info.device_capabilities);
2637
2638         return ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2639 }
2640
2641 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
2642                                 struct ecore_ptt *p_ptt)
2643 {
2644         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2645         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2646         struct ecore_dev *p_dev = p_hwfn->p_dev;
2647
2648         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2649
2650         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2651          * in the other bits are selected.
2652          * Bits 1-15 are for functions 1-15, respectively, and their value is
2653          * '0' only for enabled functions (function 0 always exists and
2654          * enabled).
2655          * In case of CMT in BB, only the "even" functions are enabled, and thus
2656          * the number of functions for both hwfns is learnt from the same bits.
2657          */
2658         if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
2659                 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
2660                                              MISCS_REG_FUNCTION_HIDE_BB_K2);
2661         } else { /* E5 */
2662                 reg_function_hide = 0;
2663         }
2664
2665         if (reg_function_hide & 0x1) {
2666                 if (ECORE_IS_BB(p_dev)) {
2667                         if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
2668                                 num_funcs = 0;
2669                                 eng_mask = 0xaaaa;
2670                         } else {
2671                                 num_funcs = 1;
2672                                 eng_mask = 0x5554;
2673                         }
2674                 } else {
2675                         num_funcs = 1;
2676                         eng_mask = 0xfffe;
2677                 }
2678
2679                 /* Get the number of the enabled functions on the engine */
2680                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2681                 while (tmp) {
2682                         if (tmp & 0x1)
2683                                 num_funcs++;
2684                         tmp >>= 0x1;
2685                 }
2686
2687                 /* Get the PF index within the enabled functions */
2688                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2689                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2690                 while (tmp) {
2691                         if (tmp & 0x1)
2692                                 enabled_func_idx--;
2693                         tmp >>= 0x1;
2694                 }
2695         }
2696
2697         p_hwfn->num_funcs_on_engine = num_funcs;
2698         p_hwfn->enabled_func_idx = enabled_func_idx;
2699
2700 #ifndef ASIC_ONLY
2701         if (CHIP_REV_IS_FPGA(p_dev)) {
2702                 DP_NOTICE(p_hwfn, false,
2703                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
2704                 p_hwfn->num_funcs_on_engine = 4;
2705         }
2706 #endif
2707
2708         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2709                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2710                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
2711                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2712 }
2713
2714 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
2715                                       struct ecore_ptt *p_ptt)
2716 {
2717         u32 port_mode;
2718
2719 #ifndef ASIC_ONLY
2720         /* Read the port mode */
2721         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
2722                 port_mode = 4;
2723         else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
2724                  (p_hwfn->p_dev->num_hwfns > 1))
2725                 /* In CMT on emulation, assume 1 port */
2726                 port_mode = 1;
2727         else
2728 #endif
2729         port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
2730
2731         if (port_mode < 3) {
2732                 p_hwfn->p_dev->num_ports_in_engines = 1;
2733         } else if (port_mode <= 5) {
2734                 p_hwfn->p_dev->num_ports_in_engines = 2;
2735         } else {
2736                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
2737                           p_hwfn->p_dev->num_ports_in_engines);
2738
2739                 /* Default num_ports_in_engines to something */
2740                 p_hwfn->p_dev->num_ports_in_engines = 1;
2741         }
2742 }
2743
2744 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
2745                                          struct ecore_ptt *p_ptt)
2746 {
2747         u32 port;
2748         int i;
2749
2750         p_hwfn->p_dev->num_ports_in_engines = 0;
2751
2752 #ifndef ASIC_ONLY
2753         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2754                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
2755                 switch ((port & 0xf000) >> 12) {
2756                 case 1:
2757                         p_hwfn->p_dev->num_ports_in_engines = 1;
2758                         break;
2759                 case 3:
2760                         p_hwfn->p_dev->num_ports_in_engines = 2;
2761                         break;
2762                 case 0xf:
2763                         p_hwfn->p_dev->num_ports_in_engines = 4;
2764                         break;
2765                 default:
2766                         DP_NOTICE(p_hwfn, false,
2767                                   "Unknown port mode in ECO_RESERVED %08x\n",
2768                                   port);
2769                 }
2770         } else
2771 #endif
2772                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2773                         port = ecore_rd(p_hwfn, p_ptt,
2774                                         CNIG_REG_NIG_PORT0_CONF_K2_E5 +
2775                                         (i * 4));
2776                         if (port & 1)
2777                                 p_hwfn->p_dev->num_ports_in_engines++;
2778                 }
2779 }
2780
2781 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
2782                                    struct ecore_ptt *p_ptt)
2783 {
2784         if (ECORE_IS_BB(p_hwfn->p_dev))
2785                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
2786         else
2787                 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
2788 }
2789
2790 static enum _ecore_status_t
2791 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2792                   enum ecore_pci_personality personality, bool drv_resc_alloc)
2793 {
2794         enum _ecore_status_t rc;
2795
2796         /* Since all information is common, only first hwfns should do this */
2797         if (IS_LEAD_HWFN(p_hwfn)) {
2798                 rc = ecore_iov_hw_info(p_hwfn);
2799                 if (rc != ECORE_SUCCESS)
2800                         return rc;
2801         }
2802
2803         /* TODO In get_hw_info, amoungst others:
2804          * Get MCP FW revision and determine according to it the supported
2805          * featrues (e.g. DCB)
2806          * Get boot mode
2807          * ecore_get_pcie_width_speed, WOL capability.
2808          * Number of global CQ-s (for storage
2809          */
2810         ecore_hw_info_port_num(p_hwfn, p_ptt);
2811
2812 #ifndef ASIC_ONLY
2813         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
2814 #endif
2815         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt);
2816         if (rc != ECORE_SUCCESS)
2817                 return rc;
2818 #ifndef ASIC_ONLY
2819         }
2820 #endif
2821
2822         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
2823         if (rc != ECORE_SUCCESS)
2824                 return rc;
2825
2826 #ifndef ASIC_ONLY
2827         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
2828 #endif
2829                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
2830                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
2831 #ifndef ASIC_ONLY
2832         } else {
2833                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
2834
2835                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
2836                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
2837         }
2838 #endif
2839
2840         if (ecore_mcp_is_init(p_hwfn)) {
2841                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
2842                         p_hwfn->hw_info.ovlan =
2843                             p_hwfn->mcp_info->func_info.ovlan;
2844
2845                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
2846         }
2847
2848         if (personality != ECORE_PCI_DEFAULT) {
2849                 p_hwfn->hw_info.personality = personality;
2850         } else if (ecore_mcp_is_init(p_hwfn)) {
2851                 enum ecore_pci_personality protocol;
2852
2853                 protocol = p_hwfn->mcp_info->func_info.protocol;
2854                 p_hwfn->hw_info.personality = protocol;
2855         }
2856
2857 #ifndef ASIC_ONLY
2858         /* To overcome ILT lack for emulation, until at least until we'll have
2859          * a definite answer from system about it, allow only PF0 to be RoCE.
2860          */
2861         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
2862                 if (!p_hwfn->rel_pf_id)
2863                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
2864                 else
2865                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
2866         }
2867 #endif
2868
2869         /* although in BB some constellations may support more than 4 tcs,
2870          * that can result in performance penalty in some cases. 4
2871          * represents a good tradeoff between performance and flexibility.
2872          */
2873         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2874
2875         /* start out with a single active tc. This can be increased either
2876          * by dcbx negotiation or by upper layer driver
2877          */
2878         p_hwfn->hw_info.num_active_tc = 1;
2879
2880         ecore_get_num_funcs(p_hwfn, p_ptt);
2881
2882         /* In case of forcing the driver's default resource allocation, calling
2883          * ecore_hw_get_resc() should come after initializing the personality
2884          * and after getting the number of functions, since the calculation of
2885          * the resources/features depends on them.
2886          * This order is not harmful if not forcing.
2887          */
2888         return ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
2889 }
2890
2891 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
2892 {
2893         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2894         u32 tmp;
2895
2896         /* Read Vendor Id / Device Id */
2897         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
2898                                   &p_dev->vendor_id);
2899         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
2900                                   &p_dev->device_id);
2901
2902         /* Determine type */
2903         if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
2904                 p_dev->type = ECORE_DEV_TYPE_AH;
2905         else
2906                 p_dev->type = ECORE_DEV_TYPE_BB;
2907
2908         p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2909                                          MISCS_REG_CHIP_NUM);
2910         p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2911                                          MISCS_REG_CHIP_REV);
2912
2913         MASK_FIELD(CHIP_REV, p_dev->chip_rev);
2914
2915         /* Learn number of HW-functions */
2916         tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2917                        MISCS_REG_CMT_ENABLED_FOR_PAIR);
2918
2919         if (tmp & (1 << p_hwfn->rel_pf_id)) {
2920                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
2921                 p_dev->num_hwfns = 2;
2922         } else {
2923                 p_dev->num_hwfns = 1;
2924         }
2925
2926 #ifndef ASIC_ONLY
2927         if (CHIP_REV_IS_EMUL(p_dev)) {
2928                 /* For some reason we have problems with this register
2929                  * in B0 emulation; Simply assume no CMT
2930                  */
2931                 DP_NOTICE(p_dev->hwfns, false,
2932                           "device on emul - assume no CMT\n");
2933                 p_dev->num_hwfns = 1;
2934         }
2935 #endif
2936
2937         p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2938                                        MISCS_REG_CHIP_TEST_REG) >> 4;
2939         MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
2940         p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2941                                            MISCS_REG_CHIP_METAL);
2942         MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
2943         DP_INFO(p_dev->hwfns,
2944                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2945                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
2946                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
2947                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
2948                 p_dev->chip_metal);
2949
2950         if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
2951                 DP_NOTICE(p_dev->hwfns, false,
2952                           "The chip type/rev (BB A0) is not supported!\n");
2953                 return ECORE_ABORTED;
2954         }
2955 #ifndef ASIC_ONLY
2956         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
2957                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2958                          MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
2959
2960         if (CHIP_REV_IS_EMUL(p_dev)) {
2961                 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2962                                MISCS_REG_ECO_RESERVED);
2963                 if (tmp & (1 << 29)) {
2964                         DP_NOTICE(p_hwfn, false,
2965                                   "Emulation: Running on a FULL build\n");
2966                         p_dev->b_is_emul_full = true;
2967                 } else {
2968                         DP_NOTICE(p_hwfn, false,
2969                                   "Emulation: Running on a REDUCED build\n");
2970                 }
2971         }
2972 #endif
2973
2974         return ECORE_SUCCESS;
2975 }
2976
2977 #ifndef LINUX_REMOVE
2978 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
2979 {
2980         int j;
2981
2982         if (IS_VF(p_dev))
2983                 return;
2984
2985         for_each_hwfn(p_dev, j) {
2986                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2987
2988                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2989                            "Mark hw/fw uninitialized\n");
2990
2991                 p_hwfn->hw_init_done = false;
2992                 p_hwfn->first_on_engine = false;
2993
2994                 ecore_ptt_invalidate(p_hwfn);
2995         }
2996 }
2997 #endif
2998
2999 static enum _ecore_status_t
3000 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
3001                         void OSAL_IOMEM * p_regview,
3002                         void OSAL_IOMEM * p_doorbells,
3003                         struct ecore_hw_prepare_params *p_params)
3004 {
3005         struct ecore_dev *p_dev = p_hwfn->p_dev;
3006         struct ecore_mdump_info mdump_info;
3007         enum _ecore_status_t rc = ECORE_SUCCESS;
3008
3009         /* Split PCI bars evenly between hwfns */
3010         p_hwfn->regview = p_regview;
3011         p_hwfn->doorbells = p_doorbells;
3012
3013         if (IS_VF(p_dev))
3014                 return ecore_vf_hw_prepare(p_hwfn);
3015
3016         /* Validate that chip access is feasible */
3017         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3018                 DP_ERR(p_hwfn,
3019                        "Reading the ME register returns all Fs; Preventing further chip access\n");
3020                 return ECORE_INVAL;
3021         }
3022
3023         get_function_id(p_hwfn);
3024
3025         /* Allocate PTT pool */
3026         rc = ecore_ptt_pool_alloc(p_hwfn);
3027         if (rc) {
3028                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
3029                 goto err0;
3030         }
3031
3032         /* Allocate the main PTT */
3033         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3034
3035         /* First hwfn learns basic information, e.g., number of hwfns */
3036         if (!p_hwfn->my_id) {
3037                 rc = ecore_get_dev_info(p_dev);
3038                 if (rc != ECORE_SUCCESS)
3039                         goto err1;
3040         }
3041
3042         ecore_hw_hwfn_prepare(p_hwfn);
3043
3044         /* Initialize MCP structure */
3045         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3046         if (rc) {
3047                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3048                 goto err1;
3049         }
3050
3051         /* Read the device configuration information from the HW and SHMEM */
3052         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3053                                p_params->personality, p_params->drv_resc_alloc);
3054         if (rc) {
3055                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3056                 goto err2;
3057         }
3058
3059         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3060          * called, since among others it sets the ports number in an engine.
3061          */
3062         if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3063             !p_dev->recov_in_prog) {
3064                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3065                 if (rc != ECORE_SUCCESS)
3066                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3067         }
3068
3069         /* Check if mdump logs are present and update the epoch value */
3070         if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) {
3071                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3072                                               &mdump_info);
3073                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) {
3074                         DP_NOTICE(p_hwfn, false,
3075                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3076                 }
3077
3078                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3079                                            p_params->epoch);
3080         }
3081
3082         /* Allocate the init RT array and initialize the init-ops engine */
3083         rc = ecore_init_alloc(p_hwfn);
3084         if (rc) {
3085                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3086                 goto err2;
3087         }
3088 #ifndef ASIC_ONLY
3089         if (CHIP_REV_IS_FPGA(p_dev)) {
3090                 DP_NOTICE(p_hwfn, false,
3091                           "FPGA: workaround; Prevent DMAE parities\n");
3092                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
3093                          7);
3094
3095                 DP_NOTICE(p_hwfn, false,
3096                           "FPGA: workaround: Set VF bar0 size\n");
3097                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3098                          PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
3099         }
3100 #endif
3101
3102         return rc;
3103  err2:
3104         if (IS_LEAD_HWFN(p_hwfn))
3105                 ecore_iov_free_hw_info(p_dev);
3106         ecore_mcp_free(p_hwfn);
3107  err1:
3108         ecore_hw_hwfn_free(p_hwfn);
3109  err0:
3110         return rc;
3111 }
3112
3113 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3114                                       struct ecore_hw_prepare_params *p_params)
3115 {
3116         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3117         enum _ecore_status_t rc;
3118
3119         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3120
3121         /* Store the precompiled init data ptrs */
3122         if (IS_PF(p_dev))
3123                 ecore_init_iro_array(p_dev);
3124
3125         /* Initialize the first hwfn - will learn number of hwfns */
3126         rc = ecore_hw_prepare_single(p_hwfn,
3127                                      p_dev->regview,
3128                                      p_dev->doorbells, p_params);
3129         if (rc != ECORE_SUCCESS)
3130                 return rc;
3131
3132         p_params->personality = p_hwfn->hw_info.personality;
3133
3134         /* initilalize 2nd hwfn if necessary */
3135         if (p_dev->num_hwfns > 1) {
3136                 void OSAL_IOMEM *p_regview, *p_doorbell;
3137                 u8 OSAL_IOMEM *addr;
3138
3139                 /* adjust bar offset for second engine */
3140                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3141                     ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3142                 p_regview = (void OSAL_IOMEM *)addr;
3143
3144                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3145                     ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3146                 p_doorbell = (void OSAL_IOMEM *)addr;
3147
3148                 /* prepare second hw function */
3149                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3150                                              p_doorbell, p_params);
3151
3152                 /* in case of error, need to free the previously
3153                  * initiliazed hwfn 0.
3154                  */
3155                 if (rc != ECORE_SUCCESS) {
3156                         if (IS_PF(p_dev)) {
3157                                 ecore_init_free(p_hwfn);
3158                                 ecore_mcp_free(p_hwfn);
3159                                 ecore_hw_hwfn_free(p_hwfn);
3160                         } else {
3161                                 DP_NOTICE(p_dev, true,
3162                                           "What do we need to free when VF hwfn1 init fails\n");
3163                         }
3164                         return rc;
3165                 }
3166         }
3167
3168         return rc;
3169 }
3170
3171 void ecore_hw_remove(struct ecore_dev *p_dev)
3172 {
3173         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3174         int i;
3175
3176         if (IS_PF(p_dev))
3177                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3178                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
3179
3180         for_each_hwfn(p_dev, i) {
3181                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3182
3183                 if (IS_VF(p_dev)) {
3184                         ecore_vf_pf_release(p_hwfn);
3185                         continue;
3186                 }
3187
3188                 ecore_init_free(p_hwfn);
3189                 ecore_hw_hwfn_free(p_hwfn);
3190                 ecore_mcp_free(p_hwfn);
3191
3192                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3193         }
3194
3195         ecore_iov_free_hw_info(p_dev);
3196 }
3197
3198 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3199                                       struct ecore_chain *p_chain)
3200 {
3201         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3202         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3203         struct ecore_chain_next *p_next;
3204         u32 size, i;
3205
3206         if (!p_virt)
3207                 return;
3208
3209         size = p_chain->elem_size * p_chain->usable_per_page;
3210
3211         for (i = 0; i < p_chain->page_cnt; i++) {
3212                 if (!p_virt)
3213                         break;
3214
3215                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3216                 p_virt_next = p_next->next_virt;
3217                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3218
3219                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3220                                        ECORE_CHAIN_PAGE_SIZE);
3221
3222                 p_virt = p_virt_next;
3223                 p_phys = p_phys_next;
3224         }
3225 }
3226
3227 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3228                                     struct ecore_chain *p_chain)
3229 {
3230         if (!p_chain->p_virt_addr)
3231                 return;
3232
3233         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3234                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3235 }
3236
3237 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3238                                  struct ecore_chain *p_chain)
3239 {
3240         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3241         u8 *p_pbl_virt = (u8 *)p_chain->pbl.p_virt_table;
3242         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3243
3244         if (!pp_virt_addr_tbl)
3245                 return;
3246
3247         if (!p_chain->pbl.p_virt_table)
3248                 goto out;
3249
3250         for (i = 0; i < page_cnt; i++) {
3251                 if (!pp_virt_addr_tbl[i])
3252                         break;
3253
3254                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3255                                        *(dma_addr_t *)p_pbl_virt,
3256                                        ECORE_CHAIN_PAGE_SIZE);
3257
3258                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3259         }
3260
3261         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3262
3263         if (!p_chain->pbl.external)
3264                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table,
3265                                        p_chain->pbl.p_phys_table, pbl_size);
3266  out:
3267         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3268 }
3269
3270 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3271 {
3272         switch (p_chain->mode) {
3273         case ECORE_CHAIN_MODE_NEXT_PTR:
3274                 ecore_chain_free_next_ptr(p_dev, p_chain);
3275                 break;
3276         case ECORE_CHAIN_MODE_SINGLE:
3277                 ecore_chain_free_single(p_dev, p_chain);
3278                 break;
3279         case ECORE_CHAIN_MODE_PBL:
3280                 ecore_chain_free_pbl(p_dev, p_chain);
3281                 break;
3282         }
3283 }
3284
3285 static enum _ecore_status_t
3286 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3287                                enum ecore_chain_cnt_type cnt_type,
3288                                osal_size_t elem_size, u32 page_cnt)
3289 {
3290         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3291
3292         /* The actual chain size can be larger than the maximal possible value
3293          * after rounding up the requested elements number to pages, and after
3294          * taking into acount the unusuable elements (next-ptr elements).
3295          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3296          * size/capacity fields are of a u32 type.
3297          */
3298         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3299              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3300             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3301              chain_size > ECORE_U32_MAX)) {
3302                 DP_NOTICE(p_dev, true,
3303                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3304                           (unsigned long)chain_size);
3305                 return ECORE_INVAL;
3306         }
3307
3308         return ECORE_SUCCESS;
3309 }
3310
3311 static enum _ecore_status_t
3312 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3313 {
3314         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3315         dma_addr_t p_phys = 0;
3316         u32 i;
3317
3318         for (i = 0; i < p_chain->page_cnt; i++) {
3319                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3320                                                  ECORE_CHAIN_PAGE_SIZE);
3321                 if (!p_virt) {
3322                         DP_NOTICE(p_dev, true,
3323                                   "Failed to allocate chain memory\n");
3324                         return ECORE_NOMEM;
3325                 }
3326
3327                 if (i == 0) {
3328                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3329                         ecore_chain_reset(p_chain);
3330                 } else {
3331                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3332                                                        p_virt, p_phys);
3333                 }
3334
3335                 p_virt_prev = p_virt;
3336         }
3337         /* Last page's next element should point to the beginning of the
3338          * chain.
3339          */
3340         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3341                                        p_chain->p_virt_addr,
3342                                        p_chain->p_phys_addr);
3343
3344         return ECORE_SUCCESS;
3345 }
3346
3347 static enum _ecore_status_t
3348 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3349 {
3350         dma_addr_t p_phys = 0;
3351         void *p_virt = OSAL_NULL;
3352
3353         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3354         if (!p_virt) {
3355                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3356                 return ECORE_NOMEM;
3357         }
3358
3359         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3360         ecore_chain_reset(p_chain);
3361
3362         return ECORE_SUCCESS;
3363 }
3364
3365 static enum _ecore_status_t
3366 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3367                       struct ecore_chain *p_chain,
3368                       struct ecore_chain_ext_pbl *ext_pbl)
3369 {
3370         void *p_virt = OSAL_NULL;
3371         u8 *p_pbl_virt = OSAL_NULL;
3372         void **pp_virt_addr_tbl = OSAL_NULL;
3373         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3374         u32 page_cnt = p_chain->page_cnt, size, i;
3375
3376         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3377         pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
3378         if (!pp_virt_addr_tbl) {
3379                 DP_NOTICE(p_dev, true,
3380                           "Failed to allocate memory for the chain virtual addresses table\n");
3381                 return ECORE_NOMEM;
3382         }
3383         OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
3384
3385         /* The allocation of the PBL table is done with its full size, since it
3386          * is expected to be successive.
3387          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3388          * failure, since pp_virt_addr_tbl was previously allocated, and it
3389          * should be saved to allow its freeing during the error flow.
3390          */
3391         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3392
3393         if (ext_pbl == OSAL_NULL) {
3394                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3395         } else {
3396                 p_pbl_virt = ext_pbl->p_pbl_virt;
3397                 p_pbl_phys = ext_pbl->p_pbl_phys;
3398                 p_chain->pbl.external = true;
3399         }
3400
3401         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3402                                  pp_virt_addr_tbl);
3403         if (!p_pbl_virt) {
3404                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3405                 return ECORE_NOMEM;
3406         }
3407
3408         for (i = 0; i < page_cnt; i++) {
3409                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3410                                                  ECORE_CHAIN_PAGE_SIZE);
3411                 if (!p_virt) {
3412                         DP_NOTICE(p_dev, true,
3413                                   "Failed to allocate chain memory\n");
3414                         return ECORE_NOMEM;
3415                 }
3416
3417                 if (i == 0) {
3418                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3419                         ecore_chain_reset(p_chain);
3420                 }
3421
3422                 /* Fill the PBL table with the physical address of the page */
3423                 *(dma_addr_t *)p_pbl_virt = p_phys;
3424                 /* Keep the virtual address of the page */
3425                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3426
3427                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3428         }
3429
3430         return ECORE_SUCCESS;
3431 }
3432
3433 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3434                                        enum ecore_chain_use_mode intended_use,
3435                                        enum ecore_chain_mode mode,
3436                                        enum ecore_chain_cnt_type cnt_type,
3437                                        u32 num_elems, osal_size_t elem_size,
3438                                        struct ecore_chain *p_chain,
3439                                        struct ecore_chain_ext_pbl *ext_pbl)
3440 {
3441         u32 page_cnt;
3442         enum _ecore_status_t rc = ECORE_SUCCESS;
3443
3444         if (mode == ECORE_CHAIN_MODE_SINGLE)
3445                 page_cnt = 1;
3446         else
3447                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3448
3449         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3450                                             page_cnt);
3451         if (rc) {
3452                 DP_NOTICE(p_dev, true,
3453                           "Cannot allocate a chain with the given arguments:\n"
3454                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3455                           intended_use, mode, cnt_type, num_elems, elem_size);
3456                 return rc;
3457         }
3458
3459         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3460                                 mode, cnt_type, p_dev->dp_ctx);
3461
3462         switch (mode) {
3463         case ECORE_CHAIN_MODE_NEXT_PTR:
3464                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3465                 break;
3466         case ECORE_CHAIN_MODE_SINGLE:
3467                 rc = ecore_chain_alloc_single(p_dev, p_chain);
3468                 break;
3469         case ECORE_CHAIN_MODE_PBL:
3470                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
3471                 break;
3472         }
3473         if (rc)
3474                 goto nomem;
3475
3476         return ECORE_SUCCESS;
3477
3478  nomem:
3479         ecore_chain_free(p_dev, p_chain);
3480         return rc;
3481 }
3482
3483 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3484                                        u16 src_id, u16 *dst_id)
3485 {
3486         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3487                 u16 min, max;
3488
3489                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3490                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3491                 DP_NOTICE(p_hwfn, true,
3492                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3493                           src_id, min, max);
3494
3495                 return ECORE_INVAL;
3496         }
3497
3498         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3499
3500         return ECORE_SUCCESS;
3501 }
3502
3503 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3504                                     u8 src_id, u8 *dst_id)
3505 {
3506         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3507                 u8 min, max;
3508
3509                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3510                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3511                 DP_NOTICE(p_hwfn, true,
3512                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3513                           src_id, min, max);
3514
3515                 return ECORE_INVAL;
3516         }
3517
3518         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3519
3520         return ECORE_SUCCESS;
3521 }
3522
3523 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
3524                                       u8 src_id, u8 *dst_id)
3525 {
3526         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
3527                 u8 min, max;
3528
3529                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
3530                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
3531                 DP_NOTICE(p_hwfn, true,
3532                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3533                           src_id, min, max);
3534
3535                 return ECORE_INVAL;
3536         }
3537
3538         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
3539
3540         return ECORE_SUCCESS;
3541 }
3542
3543 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
3544                                               struct ecore_ptt *p_ptt,
3545                                               u8 *p_filter)
3546 {
3547         u32 high, low, en;
3548         int i;
3549
3550         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3551                 return ECORE_SUCCESS;
3552
3553         high = p_filter[1] | (p_filter[0] << 8);
3554         low = p_filter[5] | (p_filter[4] << 8) |
3555             (p_filter[3] << 16) | (p_filter[2] << 24);
3556
3557         /* Find a free entry and utilize it */
3558         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3559                 en = ecore_rd(p_hwfn, p_ptt,
3560                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3561                 if (en)
3562                         continue;
3563                 ecore_wr(p_hwfn, p_ptt,
3564                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3565                          2 * i * sizeof(u32), low);
3566                 ecore_wr(p_hwfn, p_ptt,
3567                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3568                          (2 * i + 1) * sizeof(u32), high);
3569                 ecore_wr(p_hwfn, p_ptt,
3570                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3571                 ecore_wr(p_hwfn, p_ptt,
3572                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3573                          i * sizeof(u32), 0);
3574                 ecore_wr(p_hwfn, p_ptt,
3575                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3576                 break;
3577         }
3578         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3579                 DP_NOTICE(p_hwfn, false,
3580                           "Failed to find an empty LLH filter to utilize\n");
3581                 return ECORE_INVAL;
3582         }
3583
3584         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3585                    "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
3586                    p_filter[0], p_filter[1], p_filter[2],
3587                    p_filter[3], p_filter[4], p_filter[5], i);
3588
3589         return ECORE_SUCCESS;
3590 }
3591
3592 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
3593                                  struct ecore_ptt *p_ptt, u8 *p_filter)
3594 {
3595         u32 high, low;
3596         int i;
3597
3598         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3599                 return;
3600
3601         high = p_filter[1] | (p_filter[0] << 8);
3602         low = p_filter[5] | (p_filter[4] << 8) |
3603             (p_filter[3] << 16) | (p_filter[2] << 24);
3604
3605         /* Find the entry and clean it */
3606         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3607                 if (ecore_rd(p_hwfn, p_ptt,
3608                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3609                              2 * i * sizeof(u32)) != low)
3610                         continue;
3611                 if (ecore_rd(p_hwfn, p_ptt,
3612                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3613                              (2 * i + 1) * sizeof(u32)) != high)
3614                         continue;
3615
3616                 ecore_wr(p_hwfn, p_ptt,
3617                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3618                 ecore_wr(p_hwfn, p_ptt,
3619                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3620                          2 * i * sizeof(u32), 0);
3621                 ecore_wr(p_hwfn, p_ptt,
3622                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3623                          (2 * i + 1) * sizeof(u32), 0);
3624                 break;
3625         }
3626         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3627                 DP_NOTICE(p_hwfn, false,
3628                           "Tried to remove a non-configured filter\n");
3629 }
3630
3631 enum _ecore_status_t
3632 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
3633                               struct ecore_ptt *p_ptt,
3634                               u16 source_port_or_eth_type,
3635                               u16 dest_port,
3636                               enum ecore_llh_port_filter_type_t type)
3637 {
3638         u32 high, low, en;
3639         int i;
3640
3641         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3642                 return ECORE_SUCCESS;
3643
3644         high = 0;
3645         low = 0;
3646         switch (type) {
3647         case ECORE_LLH_FILTER_ETHERTYPE:
3648                 high = source_port_or_eth_type;
3649                 break;
3650         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3651         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3652                 low = source_port_or_eth_type << 16;
3653                 break;
3654         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3655         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3656                 low = dest_port;
3657                 break;
3658         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3659         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3660                 low = (source_port_or_eth_type << 16) | dest_port;
3661                 break;
3662         default:
3663                 DP_NOTICE(p_hwfn, true,
3664                           "Non valid LLH protocol filter type %d\n", type);
3665                 return ECORE_INVAL;
3666         }
3667         /* Find a free entry and utilize it */
3668         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3669                 en = ecore_rd(p_hwfn, p_ptt,
3670                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3671                 if (en)
3672                         continue;
3673                 ecore_wr(p_hwfn, p_ptt,
3674                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3675                          2 * i * sizeof(u32), low);
3676                 ecore_wr(p_hwfn, p_ptt,
3677                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3678                          (2 * i + 1) * sizeof(u32), high);
3679                 ecore_wr(p_hwfn, p_ptt,
3680                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3681                 ecore_wr(p_hwfn, p_ptt,
3682                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3683                          i * sizeof(u32), 1 << type);
3684                 ecore_wr(p_hwfn, p_ptt,
3685                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3686                 break;
3687         }
3688         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3689                 DP_NOTICE(p_hwfn, false,
3690                           "Failed to find an empty LLH filter to utilize\n");
3691                 return ECORE_NORESOURCES;
3692         }
3693         switch (type) {
3694         case ECORE_LLH_FILTER_ETHERTYPE:
3695                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3696                            "ETH type %x is added at %d\n",
3697                            source_port_or_eth_type, i);
3698                 break;
3699         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3700                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3701                            "TCP src port %x is added at %d\n",
3702                            source_port_or_eth_type, i);
3703                 break;
3704         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3705                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3706                            "UDP src port %x is added at %d\n",
3707                            source_port_or_eth_type, i);
3708                 break;
3709         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3710                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3711                            "TCP dst port %x is added at %d\n", dest_port, i);
3712                 break;
3713         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3714                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3715                            "UDP dst port %x is added at %d\n", dest_port, i);
3716                 break;
3717         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3718                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3719                            "TCP src/dst ports %x/%x are added at %d\n",
3720                            source_port_or_eth_type, dest_port, i);
3721                 break;
3722         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3723                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3724                            "UDP src/dst ports %x/%x are added at %d\n",
3725                            source_port_or_eth_type, dest_port, i);
3726                 break;
3727         }
3728         return ECORE_SUCCESS;
3729 }
3730
3731 void
3732 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
3733                                  struct ecore_ptt *p_ptt,
3734                                  u16 source_port_or_eth_type,
3735                                  u16 dest_port,
3736                                  enum ecore_llh_port_filter_type_t type)
3737 {
3738         u32 high, low;
3739         int i;
3740
3741         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3742                 return;
3743
3744         high = 0;
3745         low = 0;
3746         switch (type) {
3747         case ECORE_LLH_FILTER_ETHERTYPE:
3748                 high = source_port_or_eth_type;
3749                 break;
3750         case ECORE_LLH_FILTER_TCP_SRC_PORT:
3751         case ECORE_LLH_FILTER_UDP_SRC_PORT:
3752                 low = source_port_or_eth_type << 16;
3753                 break;
3754         case ECORE_LLH_FILTER_TCP_DEST_PORT:
3755         case ECORE_LLH_FILTER_UDP_DEST_PORT:
3756                 low = dest_port;
3757                 break;
3758         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3759         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3760                 low = (source_port_or_eth_type << 16) | dest_port;
3761                 break;
3762         default:
3763                 DP_NOTICE(p_hwfn, true,
3764                           "Non valid LLH protocol filter type %d\n", type);
3765                 return;
3766         }
3767
3768         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3769                 if (!ecore_rd(p_hwfn, p_ptt,
3770                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3771                         continue;
3772                 if (!ecore_rd(p_hwfn, p_ptt,
3773                               NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3774                         continue;
3775                 if (!(ecore_rd(p_hwfn, p_ptt,
3776                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3777                                i * sizeof(u32)) & (1 << type)))
3778                         continue;
3779                 if (ecore_rd(p_hwfn, p_ptt,
3780                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3781                              2 * i * sizeof(u32)) != low)
3782                         continue;
3783                 if (ecore_rd(p_hwfn, p_ptt,
3784                              NIG_REG_LLH_FUNC_FILTER_VALUE +
3785                              (2 * i + 1) * sizeof(u32)) != high)
3786                         continue;
3787
3788                 ecore_wr(p_hwfn, p_ptt,
3789                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3790                 ecore_wr(p_hwfn, p_ptt,
3791                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3792                 ecore_wr(p_hwfn, p_ptt,
3793                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3794                          i * sizeof(u32), 0);
3795                 ecore_wr(p_hwfn, p_ptt,
3796                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3797                          2 * i * sizeof(u32), 0);
3798                 ecore_wr(p_hwfn, p_ptt,
3799                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3800                          (2 * i + 1) * sizeof(u32), 0);
3801                 break;
3802         }
3803
3804         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3805                 DP_NOTICE(p_hwfn, false,
3806                           "Tried to remove a non-configured filter\n");
3807 }
3808
3809 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
3810                                  struct ecore_ptt *p_ptt)
3811 {
3812         int i;
3813
3814         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3815                 return;
3816
3817         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3818                 ecore_wr(p_hwfn, p_ptt,
3819                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3820                 ecore_wr(p_hwfn, p_ptt,
3821                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3822                          2 * i * sizeof(u32), 0);
3823                 ecore_wr(p_hwfn, p_ptt,
3824                          NIG_REG_LLH_FUNC_FILTER_VALUE +
3825                          (2 * i + 1) * sizeof(u32), 0);
3826         }
3827 }
3828
3829 enum _ecore_status_t
3830 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
3831                                   struct ecore_ptt *p_ptt)
3832 {
3833         if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
3834                 ecore_wr(p_hwfn, p_ptt,
3835                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
3836                          1 << p_hwfn->abs_pf_id / 2);
3837                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
3838                 return ECORE_SUCCESS;
3839         }
3840
3841         DP_NOTICE(p_hwfn, false,
3842                   "This function can't be set as default\n");
3843         return ECORE_INVAL;
3844 }
3845
3846 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
3847                                                struct ecore_ptt *p_ptt,
3848                                                u32 hw_addr, void *p_eth_qzone,
3849                                                osal_size_t eth_qzone_size,
3850                                                u8 timeset)
3851 {
3852         struct coalescing_timeset *p_coal_timeset;
3853
3854         if (IS_VF(p_hwfn->p_dev)) {
3855                 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n");
3856                 return ECORE_INVAL;
3857         }
3858
3859         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
3860                 DP_NOTICE(p_hwfn, true,
3861                           "Coalescing configuration not enabled\n");
3862                 return ECORE_INVAL;
3863         }
3864
3865         p_coal_timeset = p_eth_qzone;
3866         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
3867         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3868         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3869         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3870
3871         return ECORE_SUCCESS;
3872 }
3873
3874 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
3875                                             struct ecore_ptt *p_ptt,
3876                                             u16 coalesce, u8 qid, u16 sb_id)
3877 {
3878         struct ustorm_eth_queue_zone eth_qzone;
3879         u8 timeset, timer_res;
3880         u16 fw_qid = 0;
3881         u32 address;
3882         enum _ecore_status_t rc;
3883
3884         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3885         if (coalesce <= 0x7F) {
3886                 timer_res = 0;
3887         } else if (coalesce <= 0xFF) {
3888                 timer_res = 1;
3889         } else if (coalesce <= 0x1FF) {
3890                 timer_res = 2;
3891         } else {
3892                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3893                 return ECORE_INVAL;
3894         }
3895         timeset = (u8)(coalesce >> timer_res);
3896
3897         rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3898         if (rc != ECORE_SUCCESS)
3899                 return rc;
3900
3901         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
3902         if (rc != ECORE_SUCCESS)
3903                 goto out;
3904
3905         address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3906
3907         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3908                                 sizeof(struct ustorm_eth_queue_zone), timeset);
3909         if (rc != ECORE_SUCCESS)
3910                 goto out;
3911
3912         p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
3913  out:
3914         return rc;
3915 }
3916
3917 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
3918                                             struct ecore_ptt *p_ptt,
3919                                             u16 coalesce, u8 qid, u16 sb_id)
3920 {
3921         struct xstorm_eth_queue_zone eth_qzone;
3922         u8 timeset, timer_res;
3923         u16 fw_qid = 0;
3924         u32 address;
3925         enum _ecore_status_t rc;
3926
3927         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3928         if (coalesce <= 0x7F) {
3929                 timer_res = 0;
3930         } else if (coalesce <= 0xFF) {
3931                 timer_res = 1;
3932         } else if (coalesce <= 0x1FF) {
3933                 timer_res = 2;
3934         } else {
3935                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3936                 return ECORE_INVAL;
3937         }
3938
3939         timeset = (u8)(coalesce >> timer_res);
3940
3941         rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3942         if (rc != ECORE_SUCCESS)
3943                 return rc;
3944
3945         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
3946         if (rc != ECORE_SUCCESS)
3947                 goto out;
3948
3949         address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3950
3951         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3952                                 sizeof(struct xstorm_eth_queue_zone), timeset);
3953         if (rc != ECORE_SUCCESS)
3954                 goto out;
3955
3956         p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
3957  out:
3958         return rc;
3959 }
3960
3961 /* Calculate final WFQ values for all vports and configure it.
3962  * After this configuration each vport must have
3963  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
3964  */
3965 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3966                                                struct ecore_ptt *p_ptt,
3967                                                u32 min_pf_rate)
3968 {
3969         struct init_qm_vport_params *vport_params;
3970         int i;
3971
3972         vport_params = p_hwfn->qm_info.qm_vport_params;
3973
3974         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3975                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3976
3977                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
3978                     min_pf_rate;
3979                 ecore_init_vport_wfq(p_hwfn, p_ptt,
3980                                      vport_params[i].first_tx_pq_id,
3981                                      vport_params[i].vport_wfq);
3982         }
3983 }
3984
3985 static void
3986 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
3987 {
3988         int i;
3989
3990         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3991                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3992 }
3993
3994 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3995                                              struct ecore_ptt *p_ptt,
3996                                              u32 min_pf_rate)
3997 {
3998         struct init_qm_vport_params *vport_params;
3999         int i;
4000
4001         vport_params = p_hwfn->qm_info.qm_vport_params;
4002
4003         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4004                 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
4005                 ecore_init_vport_wfq(p_hwfn, p_ptt,
4006                                      vport_params[i].first_tx_pq_id,
4007                                      vport_params[i].vport_wfq);
4008         }
4009 }
4010
4011 /* This function performs several validations for WFQ
4012  * configuration and required min rate for a given vport
4013  * 1. req_rate must be greater than one percent of min_pf_rate.
4014  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4015  *    rates to get less than one percent of min_pf_rate.
4016  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4017  */
4018 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
4019                                                  u16 vport_id, u32 req_rate,
4020                                                  u32 min_pf_rate)
4021 {
4022         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4023         int non_requested_count = 0, req_count = 0, i, num_vports;
4024
4025         num_vports = p_hwfn->qm_info.num_vports;
4026
4027 /* Accounting for the vports which are configured for WFQ explicitly */
4028
4029         for (i = 0; i < num_vports; i++) {
4030                 u32 tmp_speed;
4031
4032                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
4033                         req_count++;
4034                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4035                         total_req_min_rate += tmp_speed;
4036                 }
4037         }
4038
4039         /* Include current vport data as well */
4040         req_count++;
4041         total_req_min_rate += req_rate;
4042         non_requested_count = num_vports - req_count;
4043
4044         /* validate possible error cases */
4045         if (req_rate > min_pf_rate) {
4046                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4047                            "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4048                            vport_id, req_rate, min_pf_rate);
4049                 return ECORE_INVAL;
4050         }
4051
4052         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
4053                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4054                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4055                            vport_id, req_rate, min_pf_rate);
4056                 return ECORE_INVAL;
4057         }
4058
4059         /* TBD - for number of vports greater than 100 */
4060         if (num_vports > ECORE_WFQ_UNIT) {
4061                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4062                            "Number of vports is greater than %d\n",
4063                            ECORE_WFQ_UNIT);
4064                 return ECORE_INVAL;
4065         }
4066
4067         if (total_req_min_rate > min_pf_rate) {
4068                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4069                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4070                            total_req_min_rate, min_pf_rate);
4071                 return ECORE_INVAL;
4072         }
4073
4074         /* Data left for non requested vports */
4075         total_left_rate = min_pf_rate - total_req_min_rate;
4076         left_rate_per_vp = total_left_rate / non_requested_count;
4077
4078         /* validate if non requested get < 1% of min bw */
4079         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4080                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4081                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4082                            left_rate_per_vp, min_pf_rate);
4083                 return ECORE_INVAL;
4084         }
4085
4086         /* now req_rate for given vport passes all scenarios.
4087          * assign final wfq rates to all vports.
4088          */
4089         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4090         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4091
4092         for (i = 0; i < num_vports; i++) {
4093                 if (p_hwfn->qm_info.wfq_data[i].configured)
4094                         continue;
4095
4096                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4097         }
4098
4099         return ECORE_SUCCESS;
4100 }
4101
4102 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4103                                        struct ecore_ptt *p_ptt,
4104                                        u16 vp_id, u32 rate)
4105 {
4106         struct ecore_mcp_link_state *p_link;
4107         int rc = ECORE_SUCCESS;
4108
4109         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4110
4111         if (!p_link->min_pf_rate) {
4112                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4113                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4114                 return rc;
4115         }
4116
4117         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4118
4119         if (rc == ECORE_SUCCESS)
4120                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4121                                                    p_link->min_pf_rate);
4122         else
4123                 DP_NOTICE(p_hwfn, false,
4124                           "Validation failed while configuring min rate\n");
4125
4126         return rc;
4127 }
4128
4129 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4130                                                    struct ecore_ptt *p_ptt,
4131                                                    u32 min_pf_rate)
4132 {
4133         bool use_wfq = false;
4134         int rc = ECORE_SUCCESS;
4135         u16 i;
4136
4137         /* Validate all pre configured vports for wfq */
4138         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4139                 u32 rate;
4140
4141                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4142                         continue;
4143
4144                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4145                 use_wfq = true;
4146
4147                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4148                 if (rc != ECORE_SUCCESS) {
4149                         DP_NOTICE(p_hwfn, false,
4150                                   "WFQ validation failed while configuring min rate\n");
4151                         break;
4152                 }
4153         }
4154
4155         if (rc == ECORE_SUCCESS && use_wfq)
4156                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4157         else
4158                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4159
4160         return rc;
4161 }
4162
4163 /* Main API for ecore clients to configure vport min rate.
4164  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4165  * rate - Speed in Mbps needs to be assigned to a given vport.
4166  */
4167 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4168 {
4169         int i, rc = ECORE_INVAL;
4170
4171         /* TBD - for multiple hardware functions - that is 100 gig */
4172         if (p_dev->num_hwfns > 1) {
4173                 DP_NOTICE(p_dev, false,
4174                           "WFQ configuration is not supported for this device\n");
4175                 return rc;
4176         }
4177
4178         for_each_hwfn(p_dev, i) {
4179                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4180                 struct ecore_ptt *p_ptt;
4181
4182                 p_ptt = ecore_ptt_acquire(p_hwfn);
4183                 if (!p_ptt)
4184                         return ECORE_TIMEOUT;
4185
4186                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4187
4188                 if (rc != ECORE_SUCCESS) {
4189                         ecore_ptt_release(p_hwfn, p_ptt);
4190                         return rc;
4191                 }
4192
4193                 ecore_ptt_release(p_hwfn, p_ptt);
4194         }
4195
4196         return rc;
4197 }
4198
4199 /* API to configure WFQ from mcp link change */
4200 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4201                                            u32 min_pf_rate)
4202 {
4203         int i;
4204
4205         /* TBD - for multiple hardware functions - that is 100 gig */
4206         if (p_dev->num_hwfns > 1) {
4207                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4208                            "WFQ configuration is not supported for this device\n");
4209                 return;
4210         }
4211
4212         for_each_hwfn(p_dev, i) {
4213                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4214
4215                 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4216                                                         p_hwfn->p_dpc_ptt,
4217                                                         min_pf_rate);
4218         }
4219 }
4220
4221 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4222                                        struct ecore_ptt *p_ptt,
4223                                        struct ecore_mcp_link_state *p_link,
4224                                        u8 max_bw)
4225 {
4226         int rc = ECORE_SUCCESS;
4227
4228         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4229
4230         if (!p_link->line_speed && (max_bw != 100))
4231                 return rc;
4232
4233         p_link->speed = (p_link->line_speed * max_bw) / 100;
4234         p_hwfn->qm_info.pf_rl = p_link->speed;
4235
4236         /* Since the limiter also affects Tx-switched traffic, we don't want it
4237          * to limit such traffic in case there's no actual limit.
4238          * In that case, set limit to imaginary high boundary.
4239          */
4240         if (max_bw == 100)
4241                 p_hwfn->qm_info.pf_rl = 100000;
4242
4243         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4244                               p_hwfn->qm_info.pf_rl);
4245
4246         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4247                    "Configured MAX bandwidth to be %08x Mb/sec\n",
4248                    p_link->speed);
4249
4250         return rc;
4251 }
4252
4253 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4254 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4255 {
4256         int i, rc = ECORE_INVAL;
4257
4258         if (max_bw < 1 || max_bw > 100) {
4259                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4260                 return rc;
4261         }
4262
4263         for_each_hwfn(p_dev, i) {
4264                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4265                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4266                 struct ecore_mcp_link_state *p_link;
4267                 struct ecore_ptt *p_ptt;
4268
4269                 p_link = &p_lead->mcp_info->link_output;
4270
4271                 p_ptt = ecore_ptt_acquire(p_hwfn);
4272                 if (!p_ptt)
4273                         return ECORE_TIMEOUT;
4274
4275                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4276                                                         p_link, max_bw);
4277
4278                 ecore_ptt_release(p_hwfn, p_ptt);
4279
4280                 if (rc != ECORE_SUCCESS)
4281                         break;
4282         }
4283
4284         return rc;
4285 }
4286
4287 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4288                                        struct ecore_ptt *p_ptt,
4289                                        struct ecore_mcp_link_state *p_link,
4290                                        u8 min_bw)
4291 {
4292         int rc = ECORE_SUCCESS;
4293
4294         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4295         p_hwfn->qm_info.pf_wfq = min_bw;
4296
4297         if (!p_link->line_speed)
4298                 return rc;
4299
4300         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4301
4302         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4303
4304         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4305                    "Configured MIN bandwidth to be %d Mb/sec\n",
4306                    p_link->min_pf_rate);
4307
4308         return rc;
4309 }
4310
4311 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4312 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4313 {
4314         int i, rc = ECORE_INVAL;
4315
4316         if (min_bw < 1 || min_bw > 100) {
4317                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4318                 return rc;
4319         }
4320
4321         for_each_hwfn(p_dev, i) {
4322                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4323                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4324                 struct ecore_mcp_link_state *p_link;
4325                 struct ecore_ptt *p_ptt;
4326
4327                 p_link = &p_lead->mcp_info->link_output;
4328
4329                 p_ptt = ecore_ptt_acquire(p_hwfn);
4330                 if (!p_ptt)
4331                         return ECORE_TIMEOUT;
4332
4333                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4334                                                         p_link, min_bw);
4335                 if (rc != ECORE_SUCCESS) {
4336                         ecore_ptt_release(p_hwfn, p_ptt);
4337                         return rc;
4338                 }
4339
4340                 if (p_link->min_pf_rate) {
4341                         u32 min_rate = p_link->min_pf_rate;
4342
4343                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4344                                                                      p_ptt,
4345                                                                      min_rate);
4346                 }
4347
4348                 ecore_ptt_release(p_hwfn, p_ptt);
4349         }
4350
4351         return rc;
4352 }
4353
4354 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4355 {
4356         struct ecore_mcp_link_state *p_link;
4357
4358         p_link = &p_hwfn->mcp_info->link_output;
4359
4360         if (p_link->min_pf_rate)
4361                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4362                                                  p_link->min_pf_rate);
4363
4364         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4365                     sizeof(*p_hwfn->qm_info.wfq_data) *
4366                     p_hwfn->qm_info.num_vports);
4367 }
4368
4369 int ecore_device_num_engines(struct ecore_dev *p_dev)
4370 {
4371         return ECORE_IS_BB(p_dev) ? 2 : 1;
4372 }
4373
4374 int ecore_device_num_ports(struct ecore_dev *p_dev)
4375 {
4376         /* in CMT always only one port */
4377         if (p_dev->num_hwfns > 1)
4378                 return 1;
4379
4380         return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
4381 }
4382
4383 void ecore_set_fw_mac_addr(__le16 *fw_msb,
4384                           __le16 *fw_mid,
4385                           __le16 *fw_lsb,
4386                           u8 *mac)
4387 {
4388         ((u8 *)fw_msb)[0] = mac[1];
4389         ((u8 *)fw_msb)[1] = mac[0];
4390         ((u8 *)fw_mid)[0] = mac[3];
4391         ((u8 *)fw_mid)[1] = mac[2];
4392         ((u8 *)fw_lsb)[0] = mac[5];
4393         ((u8 *)fw_lsb)[1] = mac[4];
4394 }