drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dcbx.h"
  32 #include "ecore_l2.h"
  33
  34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  35  * registers involved are not split and thus configuration is a race where
  36  * some of the PFs configuration might be lost.
  37  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  38  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  39  * there's more than a single compiled ecore component in system].
  40  */
  41 static osal_spinlock_t qm_lock;
  42 static u32 qm_lock_ref_cnt;
  43
  44 /******************** Doorbell Recovery *******************/
  45 /* The doorbell recovery mechanism consists of a list of entries which represent
  46  * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
  47  * entity needs to register with the mechanism and provide the parameters
  48  * describing it's doorbell, including a location where last used doorbell data
  49  * can be found. The doorbell execute function will traverse the list and
  50  * doorbell all of the registered entries.
  51  */
  52 struct ecore_db_recovery_entry {
  53         osal_list_entry_t       list_entry;
  54         void OSAL_IOMEM         *db_addr;
  55         void                    *db_data;
  56         enum ecore_db_rec_width db_width;
  57         enum ecore_db_rec_space db_space;
  58         u8                      hwfn_idx;
  59 };
  60
  61 /* display a single doorbell recovery entry */
  62 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
  63                                 struct ecore_db_recovery_entry *db_entry,
  64                                 const char *action)
  65 {
  66         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
  67                    action, db_entry, db_entry->db_addr, db_entry->db_data,
  68                    db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
  69                    db_entry->db_space == DB_REC_USER ? "user" : "kernel",
  70                    db_entry->hwfn_idx);
  71 }
  72
  73 /* doorbell address sanity (address within doorbell bar range) */
  74 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
  75                          void *db_data)
  76 {
  77         /* make sure doorbell address  is within the doorbell bar */
  78         if (db_addr < p_dev->doorbells || (u8 *)db_addr >
  79                         (u8 *)p_dev->doorbells + p_dev->db_size) {
  80                 OSAL_WARN(true,
  81                           "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
  82                           db_addr, p_dev->doorbells,
  83                           (u8 *)p_dev->doorbells + p_dev->db_size);
  84                 return false;
  85         }
  86
  87         /* make sure doorbell data pointer is not null */
  88         if (!db_data) {
  89                 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
  90                 return false;
  91         }
  92
  93         return true;
  94 }
  95
  96 /* find hwfn according to the doorbell address */
  97 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
  98                                           void OSAL_IOMEM *db_addr)
  99 {
 100         struct ecore_hwfn *p_hwfn;
 101
 102         /* In CMT doorbell bar is split down the middle between engine 0 and
 103          * enigne 1
 104          */
 105         if (ECORE_IS_CMT(p_dev))
 106                 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
 107                         &p_dev->hwfns[0] : &p_dev->hwfns[1];
 108         else
 109                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
 110
 111         return p_hwfn;
 112 }
 113
 114 /* add a new entry to the doorbell recovery mechanism */
 115 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
 116                                            void OSAL_IOMEM *db_addr,
 117                                            void *db_data,
 118                                            enum ecore_db_rec_width db_width,
 119                                            enum ecore_db_rec_space db_space)
 120 {
 121         struct ecore_db_recovery_entry *db_entry;
 122         struct ecore_hwfn *p_hwfn;
 123
 124         /* shortcircuit VFs, for now */
 125         if (IS_VF(p_dev)) {
 126                 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
 127                 return ECORE_SUCCESS;
 128         }
 129
 130         /* sanitize doorbell address */
 131         if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
 132                 return ECORE_INVAL;
 133
 134         /* obtain hwfn from doorbell address */
 135         p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
 136
 137         /* create entry */
 138         db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
 139         if (!db_entry) {
 140                 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
 141                 return ECORE_NOMEM;
 142         }
 143
 144         /* populate entry */
 145         db_entry->db_addr = db_addr;
 146         db_entry->db_data = db_data;
 147         db_entry->db_width = db_width;
 148         db_entry->db_space = db_space;
 149         db_entry->hwfn_idx = p_hwfn->my_id;
 150
 151         /* display */
 152         ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
 153
 154         /* protect the list */
 155         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 156         OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
 157                             &p_hwfn->db_recovery_info.list);
 158         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 159
 160         return ECORE_SUCCESS;
 161 }
 162
 163 /* remove an entry from the doorbell recovery mechanism */
 164 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
 165                                            void OSAL_IOMEM *db_addr,
 166                                            void *db_data)
 167 {
 168         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 169         enum _ecore_status_t rc = ECORE_INVAL;
 170         struct ecore_hwfn *p_hwfn;
 171
 172         /* shortcircuit VFs, for now */
 173         if (IS_VF(p_dev)) {
 174                 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
 175                 return ECORE_SUCCESS;
 176         }
 177
 178         /* sanitize doorbell address */
 179         if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
 180                 return ECORE_INVAL;
 181
 182         /* obtain hwfn from doorbell address */
 183         p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
 184
 185         /* protect the list */
 186         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 187         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 188                                  &p_hwfn->db_recovery_info.list,
 189                                  list_entry,
 190                                  struct ecore_db_recovery_entry) {
 191                 /* search according to db_data addr since db_addr is not unique
 192                  * (roce)
 193                  */
 194                 if (db_entry->db_data == db_data) {
 195                         ecore_db_recovery_dp_entry(p_hwfn, db_entry,
 196                                                    "Deleting");
 197                         OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
 198                                                &p_hwfn->db_recovery_info.list);
 199                         rc = ECORE_SUCCESS;
 200                         break;
 201                 }
 202         }
 203
 204         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 205
 206         if (rc == ECORE_INVAL)
 207                 /*OSAL_WARN(true,*/
 208                 DP_NOTICE(p_hwfn, false,
 209                           "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
 210                           db_data, db_addr);
 211         else
 212                 OSAL_FREE(p_dev, db_entry);
 213
 214         return rc;
 215 }
 216
 217 /* initialize the doorbell recovery mechanism */
 218 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
 219 {
 220         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
 221
 222         /* make sure db_size was set in p_dev */
 223         if (!p_hwfn->p_dev->db_size) {
 224                 DP_ERR(p_hwfn->p_dev, "db_size not set\n");
 225                 return ECORE_INVAL;
 226         }
 227
 228         OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
 229 #ifdef CONFIG_ECORE_LOCK_ALLOC
 230         if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock))
 231                 return ECORE_NOMEM;
 232 #endif
 233         OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
 234         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 235
 236         return ECORE_SUCCESS;
 237 }
 238
 239 /* destroy the doorbell recovery mechanism */
 240 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
 241 {
 242         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 243
 244         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
 245         if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
 246                 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
 247                 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
 248                         db_entry = OSAL_LIST_FIRST_ENTRY(
 249                                                 &p_hwfn->db_recovery_info.list,
 250                                                 struct ecore_db_recovery_entry,
 251                                                 list_entry);
 252                         ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
 253                         OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
 254                                                &p_hwfn->db_recovery_info.list);
 255                         OSAL_FREE(p_hwfn->p_dev, db_entry);
 256                 }
 257         }
 258 #ifdef CONFIG_ECORE_LOCK_ALLOC
 259         OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
 260 #endif
 261         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 262 }
 263
 264 /* print the content of the doorbell recovery mechanism */
 265 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
 266 {
 267         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 268
 269         DP_NOTICE(p_hwfn, false,
 270                   "Dispalying doorbell recovery database. Counter was %d\n",
 271                   p_hwfn->db_recovery_info.db_recovery_counter);
 272
 273         /* protect the list */
 274         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 275         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 276                                  &p_hwfn->db_recovery_info.list,
 277                                  list_entry,
 278                                  struct ecore_db_recovery_entry) {
 279                 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
 280         }
 281
 282         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 283 }
 284
 285 /* ring the doorbell of a single doorbell recovery entry */
 286 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
 287                             struct ecore_db_recovery_entry *db_entry,
 288                             enum ecore_db_rec_exec db_exec)
 289 {
 290         /* Print according to width */
 291         if (db_entry->db_width == DB_REC_WIDTH_32B)
 292                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
 293                            db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
 294                            db_entry->db_addr, *(u32 *)db_entry->db_data);
 295         else
 296                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n",
 297                            db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
 298                            db_entry->db_addr,
 299                            *(unsigned long *)(db_entry->db_data));
 300
 301         /* Sanity */
 302         if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
 303                                  db_entry->db_data))
 304                 return;
 305
 306         /* Flush the write combined buffer. Since there are multiple doorbelling
 307          * entities using the same address, if we don't flush, a transaction
 308          * could be lost.
 309          */
 310         OSAL_WMB(p_hwfn->p_dev);
 311
 312         /* Ring the doorbell */
 313         if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
 314                 if (db_entry->db_width == DB_REC_WIDTH_32B)
 315                         DIRECT_REG_WR(p_hwfn, db_entry->db_addr,
 316                                       *(u32 *)(db_entry->db_data));
 317                 else
 318                         DIRECT_REG_WR64(p_hwfn, db_entry->db_addr,
 319                                         *(u64 *)(db_entry->db_data));
 320         }
 321
 322         /* Flush the write combined buffer. Next doorbell may come from a
 323          * different entity to the same address...
 324          */
 325         OSAL_WMB(p_hwfn->p_dev);
 326 }
 327
 328 /* traverse the doorbell recovery entry list and ring all the doorbells */
 329 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
 330                                enum ecore_db_rec_exec db_exec)
 331 {
 332         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 333
 334         if (db_exec != DB_REC_ONCE) {
 335                 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
 336                           p_hwfn->db_recovery_info.db_recovery_counter);
 337
 338                 /* track amount of times recovery was executed */
 339                 p_hwfn->db_recovery_info.db_recovery_counter++;
 340         }
 341
 342         /* protect the list */
 343         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 344         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 345                                  &p_hwfn->db_recovery_info.list,
 346                                  list_entry,
 347                                  struct ecore_db_recovery_entry) {
 348                 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
 349                 if (db_exec == DB_REC_ONCE)
 350                         break;
 351         }
 352
 353         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 354 }
 355 /******************** Doorbell Recovery end ****************/
 356
 357 /* Configurable */
 358 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
 359                                          * load the driver. The number was
 360                                          * arbitrarily set.
 361                                          */
 362
 363 /* Derived */
 364 #define ECORE_MIN_PWM_REGION    (ECORE_WID_SIZE * ECORE_MIN_DPIS)
 365
 366 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
 367                              struct ecore_ptt *p_ptt,
 368                              enum BAR_ID bar_id)
 369 {
 370         u32 bar_reg = (bar_id == BAR_ID_0 ?
 371                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
 372         u32 val;
 373
 374         if (IS_VF(p_hwfn->p_dev))
 375                 return ecore_vf_hw_bar_size(p_hwfn, bar_id);
 376
 377         val = ecore_rd(p_hwfn, p_ptt, bar_reg);
 378         if (val)
 379                 return 1 << (val + 15);
 380
 381         /* The above registers were updated in the past only in CMT mode. Since
 382          * they were found to be useful MFW started updating them from 8.7.7.0.
 383          * In older MFW versions they are set to 0 which means disabled.
 384          */
 385         if (ECORE_IS_CMT(p_hwfn->p_dev)) {
 386                 DP_INFO(p_hwfn,
 387                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
 388                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
 389         } else {
 390                 DP_INFO(p_hwfn,
 391                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
 392                 val = 512 * 1024;
 393         }
 394
 395         return val;
 396 }
 397
 398 void ecore_init_dp(struct ecore_dev *p_dev,
 399                    u32 dp_module, u8 dp_level, void *dp_ctx)
 400 {
 401         u32 i;
 402
 403         p_dev->dp_level = dp_level;
 404         p_dev->dp_module = dp_module;
 405         p_dev->dp_ctx = dp_ctx;
 406         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 407                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 408
 409                 p_hwfn->dp_level = dp_level;
 410                 p_hwfn->dp_module = dp_module;
 411                 p_hwfn->dp_ctx = dp_ctx;
 412         }
 413 }
 414
 415 enum _ecore_status_t ecore_init_struct(struct ecore_dev *p_dev)
 416 {
 417         u8 i;
 418
 419         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 420                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 421
 422                 p_hwfn->p_dev = p_dev;
 423                 p_hwfn->my_id = i;
 424                 p_hwfn->b_active = false;
 425
 426 #ifdef CONFIG_ECORE_LOCK_ALLOC
 427                 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->dmae_info.lock))
 428                         goto handle_err;
 429 #endif
 430                 OSAL_SPIN_LOCK_INIT(&p_hwfn->dmae_info.lock);
 431         }
 432
 433         /* hwfn 0 is always active */
 434         p_dev->hwfns[0].b_active = true;
 435
 436         /* set the default cache alignment to 128 (may be overridden later) */
 437         p_dev->cache_shift = 7;
 438         return ECORE_SUCCESS;
 439 #ifdef CONFIG_ECORE_LOCK_ALLOC
 440 handle_err:
 441         while (--i) {
 442                 struct ecore_hwfn *p_hwfn = OSAL_NULL;
 443
 444                 p_hwfn = &p_dev->hwfns[i];
 445                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
 446         }
 447         return ECORE_NOMEM;
 448 #endif
 449 }
 450
 451 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 452 {
 453         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 454
 455         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 456         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 457         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 458         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 459 }
 460
 461 void ecore_resc_free(struct ecore_dev *p_dev)
 462 {
 463         int i;
 464
 465         if (IS_VF(p_dev)) {
 466                 for_each_hwfn(p_dev, i)
 467                         ecore_l2_free(&p_dev->hwfns[i]);
 468                 return;
 469         }
 470
 471         OSAL_FREE(p_dev, p_dev->fw_data);
 472
 473         OSAL_FREE(p_dev, p_dev->reset_stats);
 474
 475         for_each_hwfn(p_dev, i) {
 476                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 477
 478                 ecore_cxt_mngr_free(p_hwfn);
 479                 ecore_qm_info_free(p_hwfn);
 480                 ecore_spq_free(p_hwfn);
 481                 ecore_eq_free(p_hwfn);
 482                 ecore_consq_free(p_hwfn);
 483                 ecore_int_free(p_hwfn);
 484                 ecore_iov_free(p_hwfn);
 485                 ecore_l2_free(p_hwfn);
 486                 ecore_dmae_info_free(p_hwfn);
 487                 ecore_dcbx_info_free(p_hwfn);
 488                 /* @@@TBD Flush work-queue ? */
 489
 490                 /* destroy doorbell recovery mechanism */
 491                 ecore_db_recovery_teardown(p_hwfn);
 492         }
 493 }
 494
 495 /******************** QM initialization *******************/
 496
 497 /* bitmaps for indicating active traffic classes.
 498  * Special case for Arrowhead 4 port
 499  */
 500 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
 501 #define ACTIVE_TCS_BMAP 0x9f
 502 /* 0..3 actually used, OOO and high priority stuff all use 3 */
 503 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 504
 505 /* determines the physical queue flags for a given PF. */
 506 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
 507 {
 508         u32 flags;
 509
 510         /* common flags */
 511         flags = PQ_FLAGS_LB;
 512
 513         /* feature flags */
 514         if (IS_ECORE_SRIOV(p_hwfn->p_dev))
 515                 flags |= PQ_FLAGS_VFS;
 516
 517         /* protocol flags */
 518         switch (p_hwfn->hw_info.personality) {
 519         case ECORE_PCI_ETH:
 520                 flags |= PQ_FLAGS_MCOS;
 521                 break;
 522         case ECORE_PCI_FCOE:
 523                 flags |= PQ_FLAGS_OFLD;
 524                 break;
 525         case ECORE_PCI_ISCSI:
 526                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 527                 break;
 528         case ECORE_PCI_ETH_ROCE:
 529                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
 530                 break;
 531         case ECORE_PCI_ETH_IWARP:
 532                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 533                          PQ_FLAGS_OFLD;
 534                 break;
 535         default:
 536                 DP_ERR(p_hwfn, "unknown personality %d\n",
 537                        p_hwfn->hw_info.personality);
 538                 return 0;
 539         }
 540         return flags;
 541 }
 542
 543 /* Getters for resource amounts necessary for qm initialization */
 544 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
 545 {
 546         return p_hwfn->hw_info.num_hw_tc;
 547 }
 548
 549 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
 550 {
 551         return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
 552                         p_hwfn->p_dev->p_iov_info->total_vfs : 0;
 553 }
 554
 555 #define NUM_DEFAULT_RLS 1
 556
 557 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
 558 {
 559         u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 560
 561         /* @DPDK */
 562         /* num RLs can't exceed resource amount of rls or vports or the
 563          * dcqcn qps
 564          */
 565         num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 566                                      (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
 567
 568         /* make sure after we reserve the default and VF rls we'll have
 569          * something left
 570          */
 571         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
 572                 DP_NOTICE(p_hwfn, false,
 573                           "no rate limiters left for PF rate limiting"
 574                           " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
 575                 return 0;
 576         }
 577
 578         /* subtract rls necessary for VFs and one default one for the PF */
 579         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 580
 581         return num_pf_rls;
 582 }
 583
 584 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
 585 {
 586         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 587
 588         /* all pqs share the same vport (hence the 1 below), except for vfs
 589          * and pf_rl pqs
 590          */
 591         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 592                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 593                (!!(PQ_FLAGS_VFS & pq_flags)) *
 594                 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
 595 }
 596
 597 /* calc amount of PQs according to the requested flags */
 598 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
 599 {
 600         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 601
 602         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 603                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 604                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 605                 ecore_init_qm_get_num_tcs(p_hwfn) +
 606                (!!(PQ_FLAGS_LB & pq_flags)) +
 607                (!!(PQ_FLAGS_OOO & pq_flags)) +
 608                (!!(PQ_FLAGS_ACK & pq_flags)) +
 609                (!!(PQ_FLAGS_OFLD & pq_flags)) +
 610                (!!(PQ_FLAGS_VFS & pq_flags)) *
 611                 ecore_init_qm_get_num_vfs(p_hwfn);
 612 }
 613
 614 /* initialize the top level QM params */
 615 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
 616 {
 617         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 618         bool four_port;
 619
 620         /* pq and vport bases for this PF */
 621         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 622         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 623
 624         /* rate limiting and weighted fair queueing are always enabled */
 625         qm_info->vport_rl_en = 1;
 626         qm_info->vport_wfq_en = 1;
 627
 628         /* TC config is different for AH 4 port */
 629         four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;
 630
 631         /* in AH 4 port we have fewer TCs per port */
 632         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 633                                                      NUM_OF_PHYS_TCS;
 634
 635         /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
 636          * 4 otherwise
 637          */
 638         if (!qm_info->ooo_tc)
 639                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 640                                               DCBX_TCP_OOO_TC;
 641 }
 642
 643 /* initialize qm vport params */
 644 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
 645 {
 646         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 647         u8 i;
 648
 649         /* all vports participate in weighted fair queueing */
 650         for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
 651                 qm_info->qm_vport_params[i].vport_wfq = 1;
 652 }
 653
 654 /* initialize qm port params */
 655 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
 656 {
 657         /* Initialize qm port parameters */
 658         u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
 659
 660         /* indicate how ooo and high pri traffic is dealt with */
 661         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 662                 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
 663
 664         for (i = 0; i < num_ports; i++) {
 665                 struct init_qm_port_params *p_qm_port =
 666                         &p_hwfn->qm_info.qm_port_params[i];
 667
 668                 p_qm_port->active = 1;
 669                 p_qm_port->active_phys_tcs = active_phys_tcs;
 670                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES_E4 / num_ports;
 671                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 672         }
 673 }
 674
 675 /* Reset the params which must be reset for qm init. QM init may be called as
 676  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 677  * params may be affected by the init but would simply recalculate to the same
 678  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 679  * affected as these amounts stay the same.
 680  */
 681 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
 682 {
 683         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 684
 685         qm_info->num_pqs = 0;
 686         qm_info->num_vports = 0;
 687         qm_info->num_pf_rls = 0;
 688         qm_info->num_vf_pqs = 0;
 689         qm_info->first_vf_pq = 0;
 690         qm_info->first_mcos_pq = 0;
 691         qm_info->first_rl_pq = 0;
 692 }
 693
 694 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
 695 {
 696         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 697
 698         qm_info->num_vports++;
 699
 700         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 701                 DP_ERR(p_hwfn,
 702                        "vport overflow! qm_info->num_vports %d,"
 703                        " qm_init_get_num_vports() %d\n",
 704                        qm_info->num_vports,
 705                        ecore_init_qm_get_num_vports(p_hwfn));
 706 }
 707
 708 /* initialize a single pq and manage qm_info resources accounting.
 709  * The pq_init_flags param determines whether the PQ is rate limited
 710  * (for VF or PF)
 711  * and whether a new vport is allocated to the pq or not (i.e. vport will be
 712  * shared)
 713  */
 714
 715 /* flags for pq init */
 716 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 717 #define PQ_INIT_PF_RL           (1 << 1)
 718 #define PQ_INIT_VF_RL           (1 << 2)
 719
 720 /* defines for pq init */
 721 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 722 #define PQ_INIT_DEFAULT_TC              0
 723 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 724
 725 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
 726                              struct ecore_qm_info *qm_info,
 727                              u8 tc, u32 pq_init_flags)
 728 {
 729         u16 pq_idx = qm_info->num_pqs, max_pq =
 730                                         ecore_init_qm_get_num_pqs(p_hwfn);
 731
 732         if (pq_idx > max_pq)
 733                 DP_ERR(p_hwfn,
 734                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 735
 736         /* init pq params */
 737         qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
 738         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 739                                                  qm_info->num_vports;
 740         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 741         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 742         qm_info->qm_pq_params[pq_idx].rl_valid =
 743                 (pq_init_flags & PQ_INIT_PF_RL ||
 744                  pq_init_flags & PQ_INIT_VF_RL);
 745
 746         /* qm params accounting */
 747         qm_info->num_pqs++;
 748         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 749                 qm_info->num_vports++;
 750
 751         if (pq_init_flags & PQ_INIT_PF_RL)
 752                 qm_info->num_pf_rls++;
 753
 754         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 755                 DP_ERR(p_hwfn,
 756                        "vport overflow! qm_info->num_vports %d,"
 757                        " qm_init_get_num_vports() %d\n",
 758                        qm_info->num_vports,
 759                        ecore_init_qm_get_num_vports(p_hwfn));
 760
 761         if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
 762                 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
 763                        " qm_init_get_num_pf_rls() %d\n",
 764                        qm_info->num_pf_rls,
 765                        ecore_init_qm_get_num_pf_rls(p_hwfn));
 766 }
 767
 768 /* get pq index according to PQ_FLAGS */
 769 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
 770                                              u32 pq_flags)
 771 {
 772         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 773
 774         /* Can't have multiple flags set here */
 775         if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
 776                                 sizeof(pq_flags)) > 1)
 777                 goto err;
 778
 779         switch (pq_flags) {
 780         case PQ_FLAGS_RLS:
 781                 return &qm_info->first_rl_pq;
 782         case PQ_FLAGS_MCOS:
 783                 return &qm_info->first_mcos_pq;
 784         case PQ_FLAGS_LB:
 785                 return &qm_info->pure_lb_pq;
 786         case PQ_FLAGS_OOO:
 787                 return &qm_info->ooo_pq;
 788         case PQ_FLAGS_ACK:
 789                 return &qm_info->pure_ack_pq;
 790         case PQ_FLAGS_OFLD:
 791                 return &qm_info->offload_pq;
 792         case PQ_FLAGS_VFS:
 793                 return &qm_info->first_vf_pq;
 794         default:
 795                 goto err;
 796         }
 797
 798 err:
 799         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 800         return OSAL_NULL;
 801 }
 802
 803 /* save pq index in qm info */
 804 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
 805                                   u32 pq_flags, u16 pq_val)
 806 {
 807         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 808
 809         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 810 }
 811
 812 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 813 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
 814 {
 815         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 816
 817         return *base_pq_idx + CM_TX_PQ_BASE;
 818 }
 819
 820 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
 821 {
 822         u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
 823
 824         if (tc > max_tc)
 825                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 826
 827         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 828 }
 829
 830 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
 831 {
 832         u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
 833
 834         if (vf > max_vf)
 835                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 836
 837         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 838 }
 839
 840 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
 841 {
 842         u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
 843
 844         if (rl > max_rl)
 845                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 846
 847         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 848 }
 849
 850 /* Functions for creating specific types of pqs */
 851 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
 852 {
 853         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 854
 855         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 856                 return;
 857
 858         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 859         ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 860 }
 861
 862 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
 863 {
 864         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 865
 866         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 867                 return;
 868
 869         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 870         ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 871 }
 872
 873 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
 874 {
 875         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 876
 877         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 878                 return;
 879
 880         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 881         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 882 }
 883
 884 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
 885 {
 886         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 887
 888         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 889                 return;
 890
 891         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 892         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 893 }
 894
 895 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
 896 {
 897         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 898         u8 tc_idx;
 899
 900         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 901                 return;
 902
 903         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 904         for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 905                 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 906 }
 907
 908 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
 909 {
 910         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 911         u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 912
 913         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 914                 return;
 915
 916         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 917
 918         qm_info->num_vf_pqs = num_vfs;
 919         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 920                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
 921                                  PQ_INIT_VF_RL);
 922 }
 923
 924 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
 925 {
 926         u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
 927         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 928
 929         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 930                 return;
 931
 932         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 933         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 934                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
 935                                  PQ_INIT_PF_RL);
 936 }
 937
 938 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
 939 {
 940         /* rate limited pqs, must come first (FW assumption) */
 941         ecore_init_qm_rl_pqs(p_hwfn);
 942
 943         /* pqs for multi cos */
 944         ecore_init_qm_mcos_pqs(p_hwfn);
 945
 946         /* pure loopback pq */
 947         ecore_init_qm_lb_pq(p_hwfn);
 948
 949         /* out of order pq */
 950         ecore_init_qm_ooo_pq(p_hwfn);
 951
 952         /* pure ack pq */
 953         ecore_init_qm_pure_ack_pq(p_hwfn);
 954
 955         /* pq for offloaded protocol */
 956         ecore_init_qm_offload_pq(p_hwfn);
 957
 958         /* done sharing vports */
 959         ecore_init_qm_advance_vport(p_hwfn);
 960
 961         /* pqs for vfs */
 962         ecore_init_qm_vf_pqs(p_hwfn);
 963 }
 964
 965 /* compare values of getters against resources amounts */
 966 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
 967 {
 968         if (ecore_init_qm_get_num_vports(p_hwfn) >
 969             RESC_NUM(p_hwfn, ECORE_VPORT)) {
 970                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 971                 return ECORE_INVAL;
 972         }
 973
 974         if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
 975                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 976                 return ECORE_INVAL;
 977         }
 978
 979         return ECORE_SUCCESS;
 980 }
 981
 982 /*
 983  * Function for verbose printing of the qm initialization results
 984  */
 985 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
 986 {
 987         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 988         struct init_qm_vport_params *vport;
 989         struct init_qm_port_params *port;
 990         struct init_qm_pq_params *pq;
 991         int i, tc;
 992
 993         /* top level params */
 994         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 995                    "qm init top level params: start_pq %d, start_vport %d,"
 996                    " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 997                    qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
 998                    qm_info->offload_pq, qm_info->pure_ack_pq);
 999         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1000                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
1001                    " num_vports %d, max_phys_tcs_per_port %d\n",
1002                    qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
1003                    qm_info->num_vf_pqs, qm_info->num_vports,
1004                    qm_info->max_phys_tcs_per_port);
1005         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1006                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
1007                    " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
1008                    qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
1009                    qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
1010                    qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
1011
1012         /* port table */
1013         for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
1014                 port = &qm_info->qm_port_params[i];
1015                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1016                            "port idx %d, active %d, active_phys_tcs %d,"
1017                            " num_pbf_cmd_lines %d, num_btb_blocks %d,"
1018                            " reserved %d\n",
1019                            i, port->active, port->active_phys_tcs,
1020                            port->num_pbf_cmd_lines, port->num_btb_blocks,
1021                            port->reserved);
1022         }
1023
1024         /* vport table */
1025         for (i = 0; i < qm_info->num_vports; i++) {
1026                 vport = &qm_info->qm_vport_params[i];
1027                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1028                            "vport idx %d, vport_rl %d, wfq %d,"
1029                            " first_tx_pq_id [ ",
1030                            qm_info->start_vport + i, vport->vport_rl,
1031                            vport->vport_wfq);
1032                 for (tc = 0; tc < NUM_OF_TCS; tc++)
1033                         DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
1034                                    vport->first_tx_pq_id[tc]);
1035                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
1036         }
1037
1038         /* pq table */
1039         for (i = 0; i < qm_info->num_pqs; i++) {
1040                 pq = &qm_info->qm_pq_params[i];
1041                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1042                            "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
1043                            qm_info->start_pq + i, pq->port_id, pq->vport_id,
1044                            pq->tc_id, pq->wrr_group, pq->rl_valid);
1045         }
1046 }
1047
1048 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
1049 {
1050         /* reset params required for init run */
1051         ecore_init_qm_reset_params(p_hwfn);
1052
1053         /* init QM top level params */
1054         ecore_init_qm_params(p_hwfn);
1055
1056         /* init QM port params */
1057         ecore_init_qm_port_params(p_hwfn);
1058
1059         /* init QM vport params */
1060         ecore_init_qm_vport_params(p_hwfn);
1061
1062         /* init QM physical queue params */
1063         ecore_init_qm_pq_params(p_hwfn);
1064
1065         /* display all that init */
1066         ecore_dp_init_qm_params(p_hwfn);
1067 }
1068
1069 /* This function reconfigures the QM pf on the fly.
1070  * For this purpose we:
1071  * 1. reconfigure the QM database
1072  * 2. set new values to runtime array
1073  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
1074  * 4. activate init tool in QM_PF stage
1075  * 5. send an sdm_qm_cmd through rbc interface to release the QM
1076  */
1077 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
1078                                      struct ecore_ptt *p_ptt)
1079 {
1080         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1081         bool b_rc;
1082         enum _ecore_status_t rc;
1083
1084         /* initialize ecore's qm data structure */
1085         ecore_init_qm_info(p_hwfn);
1086
1087         /* stop PF's qm queues */
1088         OSAL_SPIN_LOCK(&qm_lock);
1089         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
1090                                       qm_info->start_pq, qm_info->num_pqs);
1091         OSAL_SPIN_UNLOCK(&qm_lock);
1092         if (!b_rc)
1093                 return ECORE_INVAL;
1094
1095         /* clear the QM_PF runtime phase leftovers from previous init */
1096         ecore_init_clear_rt_data(p_hwfn);
1097
1098         /* prepare QM portion of runtime array */
1099         ecore_qm_init_pf(p_hwfn, p_ptt, false);
1100
1101         /* activate init tool on runtime array */
1102         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
1103                             p_hwfn->hw_info.hw_mode);
1104         if (rc != ECORE_SUCCESS)
1105                 return rc;
1106
1107         /* start PF's qm queues */
1108         OSAL_SPIN_LOCK(&qm_lock);
1109         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
1110                                       qm_info->start_pq, qm_info->num_pqs);
1111         OSAL_SPIN_UNLOCK(&qm_lock);
1112         if (!b_rc)
1113                 return ECORE_INVAL;
1114
1115         return ECORE_SUCCESS;
1116 }
1117
1118 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
1119 {
1120         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1121         enum _ecore_status_t rc;
1122
1123         rc = ecore_init_qm_sanity(p_hwfn);
1124         if (rc != ECORE_SUCCESS)
1125                 goto alloc_err;
1126
1127         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1128                                             sizeof(struct init_qm_pq_params) *
1129                                             ecore_init_qm_get_num_pqs(p_hwfn));
1130         if (!qm_info->qm_pq_params)
1131                 goto alloc_err;
1132
1133         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1134                                        sizeof(struct init_qm_vport_params) *
1135                                        ecore_init_qm_get_num_vports(p_hwfn));
1136         if (!qm_info->qm_vport_params)
1137                 goto alloc_err;
1138
1139         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1140                                       sizeof(struct init_qm_port_params) *
1141                                       p_hwfn->p_dev->num_ports_in_engine);
1142         if (!qm_info->qm_port_params)
1143                 goto alloc_err;
1144
1145         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1146                                         sizeof(struct ecore_wfq_data) *
1147                                         ecore_init_qm_get_num_vports(p_hwfn));
1148         if (!qm_info->wfq_data)
1149                 goto alloc_err;
1150
1151         return ECORE_SUCCESS;
1152
1153 alloc_err:
1154         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
1155         ecore_qm_info_free(p_hwfn);
1156         return ECORE_NOMEM;
1157 }
1158 /******************** End QM initialization ***************/
1159
1160 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
1161 {
1162         enum _ecore_status_t rc = ECORE_SUCCESS;
1163         int i;
1164
1165         if (IS_VF(p_dev)) {
1166                 for_each_hwfn(p_dev, i) {
1167                         rc = ecore_l2_alloc(&p_dev->hwfns[i]);
1168                         if (rc != ECORE_SUCCESS)
1169                                 return rc;
1170                 }
1171                 return rc;
1172         }
1173
1174         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1175                                      sizeof(*p_dev->fw_data));
1176         if (!p_dev->fw_data)
1177                 return ECORE_NOMEM;
1178
1179         for_each_hwfn(p_dev, i) {
1180                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1181                 u32 n_eqes, num_cons;
1182
1183                 /* initialize the doorbell recovery mechanism */
1184                 rc = ecore_db_recovery_setup(p_hwfn);
1185                 if (rc)
1186                         goto alloc_err;
1187
1188                 /* First allocate the context manager structure */
1189                 rc = ecore_cxt_mngr_alloc(p_hwfn);
1190                 if (rc)
1191                         goto alloc_err;
1192
1193                 /* Set the HW cid/tid numbers (in the context manager)
1194                  * Must be done prior to any further computations.
1195                  */
1196                 rc = ecore_cxt_set_pf_params(p_hwfn);
1197                 if (rc)
1198                         goto alloc_err;
1199
1200                 rc = ecore_alloc_qm_data(p_hwfn);
1201                 if (rc)
1202                         goto alloc_err;
1203
1204                 /* init qm info */
1205                 ecore_init_qm_info(p_hwfn);
1206
1207                 /* Compute the ILT client partition */
1208                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
1209                 if (rc)
1210                         goto alloc_err;
1211
1212                 /* CID map / ILT shadow table / T2
1213                  * The talbes sizes are determined by the computations above
1214                  */
1215                 rc = ecore_cxt_tables_alloc(p_hwfn);
1216                 if (rc)
1217                         goto alloc_err;
1218
1219                 /* SPQ, must follow ILT because initializes SPQ context */
1220                 rc = ecore_spq_alloc(p_hwfn);
1221                 if (rc)
1222                         goto alloc_err;
1223
1224                 /* SP status block allocation */
1225                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
1226                                                            RESERVED_PTT_DPC);
1227
1228                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1229                 if (rc)
1230                         goto alloc_err;
1231
1232                 rc = ecore_iov_alloc(p_hwfn);
1233                 if (rc)
1234                         goto alloc_err;
1235
1236                 /* EQ */
1237                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
1238                 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
1239                         /* Calculate the EQ size
1240                          * ---------------------
1241                          * Each ICID may generate up to one event at a time i.e.
1242                          * the event must be handled/cleared before a new one
1243                          * can be generated. We calculate the sum of events per
1244                          * protocol and create an EQ deep enough to handle the
1245                          * worst case:
1246                          * - Core - according to SPQ.
1247                          * - RoCE - per QP there are a couple of ICIDs, one
1248                          *        responder and one requester, each can
1249                          *        generate an EQE => n_eqes_qp = 2 * n_qp.
1250                          *        Each CQ can generate an EQE. There are 2 CQs
1251                          *        per QP => n_eqes_cq = 2 * n_qp.
1252                          *        Hence the RoCE total is 4 * n_qp or
1253                          *        2 * num_cons.
1254                          * - ENet - There can be up to two events per VF. One
1255                          *        for VF-PF channel and another for VF FLR
1256                          *        initial cleanup. The number of VFs is
1257                          *        bounded by MAX_NUM_VFS_BB, and is much
1258                          *        smaller than RoCE's so we avoid exact
1259                          *        calculation.
1260                          */
1261                         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
1262                                 num_cons =
1263                                     ecore_cxt_get_proto_cid_count(
1264                                                 p_hwfn,
1265                                                 PROTOCOLID_ROCE,
1266                                                 OSAL_NULL);
1267                                 num_cons *= 2;
1268                         } else {
1269                                 num_cons = ecore_cxt_get_proto_cid_count(
1270                                                 p_hwfn,
1271                                                 PROTOCOLID_IWARP,
1272                                                 OSAL_NULL);
1273                         }
1274                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1275                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
1276                         num_cons =
1277                             ecore_cxt_get_proto_cid_count(p_hwfn,
1278                                                           PROTOCOLID_ISCSI,
1279                                                           OSAL_NULL);
1280                         n_eqes += 2 * num_cons;
1281                 }
1282
1283                 if (n_eqes > 0xFFFF) {
1284                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
1285                                        "The maximum of a u16 chain is 0x%x\n",
1286                                n_eqes, 0xFFFF);
1287                         goto alloc_no_mem;
1288                 }
1289
1290                 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
1291                 if (rc)
1292                         goto alloc_err;
1293
1294                 rc = ecore_consq_alloc(p_hwfn);
1295                 if (rc)
1296                         goto alloc_err;
1297
1298                 rc = ecore_l2_alloc(p_hwfn);
1299                 if (rc != ECORE_SUCCESS)
1300                         goto alloc_err;
1301
1302                 /* DMA info initialization */
1303                 rc = ecore_dmae_info_alloc(p_hwfn);
1304                 if (rc) {
1305                         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for dmae_info structure\n");
1306                         goto alloc_err;
1307                 }
1308
1309                 /* DCBX initialization */
1310                 rc = ecore_dcbx_info_alloc(p_hwfn);
1311                 if (rc) {
1312                         DP_NOTICE(p_hwfn, false,
1313                                   "Failed to allocate memory for dcbx structure\n");
1314                         goto alloc_err;
1315                 }
1316         }
1317
1318         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1319                                          sizeof(*p_dev->reset_stats));
1320         if (!p_dev->reset_stats) {
1321                 DP_NOTICE(p_dev, false, "Failed to allocate reset statistics\n");
1322                 goto alloc_no_mem;
1323         }
1324
1325         return ECORE_SUCCESS;
1326
1327 alloc_no_mem:
1328         rc = ECORE_NOMEM;
1329 alloc_err:
1330         ecore_resc_free(p_dev);
1331         return rc;
1332 }
1333
1334 void ecore_resc_setup(struct ecore_dev *p_dev)
1335 {
1336         int i;
1337
1338         if (IS_VF(p_dev)) {
1339                 for_each_hwfn(p_dev, i)
1340                         ecore_l2_setup(&p_dev->hwfns[i]);
1341                 return;
1342         }
1343
1344         for_each_hwfn(p_dev, i) {
1345                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1346
1347                 ecore_cxt_mngr_setup(p_hwfn);
1348                 ecore_spq_setup(p_hwfn);
1349                 ecore_eq_setup(p_hwfn);
1350                 ecore_consq_setup(p_hwfn);
1351
1352                 /* Read shadow of current MFW mailbox */
1353                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1354                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1355                             p_hwfn->mcp_info->mfw_mb_cur,
1356                             p_hwfn->mcp_info->mfw_mb_length);
1357
1358                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1359
1360                 ecore_l2_setup(p_hwfn);
1361                 ecore_iov_setup(p_hwfn);
1362         }
1363 }
1364
1365 #define FINAL_CLEANUP_POLL_CNT  (100)
1366 #define FINAL_CLEANUP_POLL_TIME (10)
1367 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1368                                          struct ecore_ptt *p_ptt,
1369                                          u16 id, bool is_vf)
1370 {
1371         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1372         enum _ecore_status_t rc = ECORE_TIMEOUT;
1373
1374 #ifndef ASIC_ONLY
1375         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1376             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1377                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1378                 return ECORE_SUCCESS;
1379         }
1380 #endif
1381
1382         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1383             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1384
1385         if (is_vf)
1386                 id += 0x10;
1387
1388         command |= X_FINAL_CLEANUP_AGG_INT <<
1389             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1390         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1391         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1392         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1393
1394 /* Make sure notification is not set before initiating final cleanup */
1395
1396         if (REG_RD(p_hwfn, addr)) {
1397                 DP_NOTICE(p_hwfn, false,
1398                           "Unexpected; Found final cleanup notification");
1399                 DP_NOTICE(p_hwfn, false,
1400                           " before initiating final cleanup\n");
1401                 REG_WR(p_hwfn, addr, 0);
1402         }
1403
1404         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1405                    "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1406                    id, command);
1407
1408         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1409
1410         /* Poll until completion */
1411         while (!REG_RD(p_hwfn, addr) && count--)
1412                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1413
1414         if (REG_RD(p_hwfn, addr))
1415                 rc = ECORE_SUCCESS;
1416         else
1417                 DP_NOTICE(p_hwfn, true,
1418                           "Failed to receive FW final cleanup notification\n");
1419
1420         /* Cleanup afterwards */
1421         REG_WR(p_hwfn, addr, 0);
1422
1423         return rc;
1424 }
1425
1426 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1427 {
1428         int hw_mode = 0;
1429
1430         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1431                 hw_mode |= 1 << MODE_BB;
1432         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1433                 hw_mode |= 1 << MODE_K2;
1434         } else {
1435                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1436                           p_hwfn->p_dev->type);
1437                 return ECORE_INVAL;
1438         }
1439
1440         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1441         switch (p_hwfn->p_dev->num_ports_in_engine) {
1442         case 1:
1443                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1444                 break;
1445         case 2:
1446                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1447                 break;
1448         case 4:
1449                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1450                 break;
1451         default:
1452                 DP_NOTICE(p_hwfn, true,
1453                           "num_ports_in_engine = %d not supported\n",
1454                           p_hwfn->p_dev->num_ports_in_engine);
1455                 return ECORE_INVAL;
1456         }
1457
1458         if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS,
1459                           &p_hwfn->p_dev->mf_bits))
1460                 hw_mode |= 1 << MODE_MF_SD;
1461         else
1462                 hw_mode |= 1 << MODE_MF_SI;
1463
1464 #ifndef ASIC_ONLY
1465         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1466                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1467                         hw_mode |= 1 << MODE_FPGA;
1468                 } else {
1469                         if (p_hwfn->p_dev->b_is_emul_full)
1470                                 hw_mode |= 1 << MODE_EMUL_FULL;
1471                         else
1472                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
1473                 }
1474         } else
1475 #endif
1476                 hw_mode |= 1 << MODE_ASIC;
1477
1478         if (ECORE_IS_CMT(p_hwfn->p_dev))
1479                 hw_mode |= 1 << MODE_100G;
1480
1481         p_hwfn->hw_info.hw_mode = hw_mode;
1482
1483         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1484                    "Configuring function for hw_mode: 0x%08x\n",
1485                    p_hwfn->hw_info.hw_mode);
1486
1487         return ECORE_SUCCESS;
1488 }
1489
1490 #ifndef ASIC_ONLY
1491 /* MFW-replacement initializations for non-ASIC */
1492 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1493                                                struct ecore_ptt *p_ptt)
1494 {
1495         struct ecore_dev *p_dev = p_hwfn->p_dev;
1496         u32 pl_hv = 1;
1497         int i;
1498
1499         if (CHIP_REV_IS_EMUL(p_dev)) {
1500                 if (ECORE_IS_AH(p_dev))
1501                         pl_hv |= 0x600;
1502         }
1503
1504         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1505
1506         if (CHIP_REV_IS_EMUL(p_dev) &&
1507             (ECORE_IS_AH(p_dev)))
1508                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1509                          0x3ffffff);
1510
1511         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1512         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1513         if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1514                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1515
1516         if (CHIP_REV_IS_EMUL(p_dev)) {
1517                 if (ECORE_IS_AH(p_dev)) {
1518                         /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1519                         ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1520                                  (p_dev->num_ports_in_engine >> 1));
1521
1522                         ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1523                                  p_dev->num_ports_in_engine == 4 ? 0 : 3);
1524                 }
1525         }
1526
1527         /* Poll on RBC */
1528         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1529         for (i = 0; i < 100; i++) {
1530                 OSAL_UDELAY(50);
1531                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1532                         break;
1533         }
1534         if (i == 100)
1535                 DP_NOTICE(p_hwfn, true,
1536                           "RBC done failed to complete in PSWRQ2\n");
1537
1538         return ECORE_SUCCESS;
1539 }
1540 #endif
1541
1542 /* Init run time data for all PFs and their VFs on an engine.
1543  * TBD - for VFs - Once we have parent PF info for each VF in
1544  * shmem available as CAU requires knowledge of parent PF for each VF.
1545  */
1546 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1547 {
1548         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1549         int i, igu_sb_id;
1550
1551         for_each_hwfn(p_dev, i) {
1552                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1553                 struct ecore_igu_info *p_igu_info;
1554                 struct ecore_igu_block *p_block;
1555                 struct cau_sb_entry sb_entry;
1556
1557                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1558
1559                 for (igu_sb_id = 0;
1560                      igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1561                      igu_sb_id++) {
1562                         p_block = &p_igu_info->entry[igu_sb_id];
1563
1564                         if (!p_block->is_pf)
1565                                 continue;
1566
1567                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1568                                                 p_block->function_id, 0, 0);
1569                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1570                                          sb_entry);
1571                 }
1572         }
1573 }
1574
1575 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
1576                                        struct ecore_ptt *p_ptt)
1577 {
1578         u32 val, wr_mbs, cache_line_size;
1579
1580         val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1581         switch (val) {
1582         case 0:
1583                 wr_mbs = 128;
1584                 break;
1585         case 1:
1586                 wr_mbs = 256;
1587                 break;
1588         case 2:
1589                 wr_mbs = 512;
1590                 break;
1591         default:
1592                 DP_INFO(p_hwfn,
1593                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1594                         val);
1595                 return;
1596         }
1597
1598         cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
1599         switch (cache_line_size) {
1600         case 32:
1601                 val = 0;
1602                 break;
1603         case 64:
1604                 val = 1;
1605                 break;
1606         case 128:
1607                 val = 2;
1608                 break;
1609         case 256:
1610                 val = 3;
1611                 break;
1612         default:
1613                 DP_INFO(p_hwfn,
1614                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1615                         cache_line_size);
1616         }
1617
1618         if (wr_mbs < OSAL_CACHE_LINE_SIZE)
1619                 DP_INFO(p_hwfn,
1620                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1621                         OSAL_CACHE_LINE_SIZE, wr_mbs);
1622
1623         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1624         if (val > 0) {
1625                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1626                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1627         }
1628 }
1629
1630 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1631                                                  struct ecore_ptt *p_ptt,
1632                                                  int hw_mode)
1633 {
1634         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1635         struct ecore_dev *p_dev = p_hwfn->p_dev;
1636         u8 vf_id, max_num_vfs;
1637         u16 num_pfs, pf_id;
1638         u32 concrete_fid;
1639         enum _ecore_status_t rc = ECORE_SUCCESS;
1640
1641         ecore_init_cau_rt_data(p_dev);
1642
1643         /* Program GTT windows */
1644         ecore_gtt_init(p_hwfn, p_ptt);
1645
1646 #ifndef ASIC_ONLY
1647         if (CHIP_REV_IS_EMUL(p_dev)) {
1648                 rc = ecore_hw_init_chip(p_hwfn, p_ptt);
1649                 if (rc != ECORE_SUCCESS)
1650                         return rc;
1651         }
1652 #endif
1653
1654         if (p_hwfn->mcp_info) {
1655                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1656                         qm_info->pf_rl_en = 1;
1657                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1658                         qm_info->pf_wfq_en = 1;
1659         }
1660
1661         ecore_qm_common_rt_init(p_hwfn,
1662                                 p_dev->num_ports_in_engine,
1663                                 qm_info->max_phys_tcs_per_port,
1664                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1665                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1666                                 qm_info->qm_port_params);
1667
1668         ecore_cxt_hw_init_common(p_hwfn);
1669
1670         ecore_init_cache_line_size(p_hwfn, p_ptt);
1671
1672         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ECORE_PATH_ID(p_hwfn),
1673                             hw_mode);
1674         if (rc != ECORE_SUCCESS)
1675                 return rc;
1676
1677         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1678          * need to decide with which value, maybe runtime
1679          */
1680         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1681         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1682
1683         if (ECORE_IS_BB(p_dev)) {
1684                 /* Workaround clears ROCE search for all functions to prevent
1685                  * involving non initialized function in processing ROCE packet.
1686                  */
1687                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1688                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1689                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1690                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1691                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1692                 }
1693                 /* pretend to original PF */
1694                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1695         }
1696
1697         /* Workaround for avoiding CCFC execution error when getting packets
1698          * with CRC errors, and allowing instead the invoking of the FW error
1699          * handler.
1700          * This is not done inside the init tool since it currently can't
1701          * perform a pretending to VFs.
1702          */
1703         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1704         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1705                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1706                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1707                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1708                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1709                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1710                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1711         }
1712         /* pretend to original PF */
1713         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1714
1715         return rc;
1716 }
1717
1718 #ifndef ASIC_ONLY
1719 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1720 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1721
1722 #define PMEG_IF_BYTE_COUNT      8
1723
1724 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1725                              struct ecore_ptt *p_ptt,
1726                              u32 addr, u64 data, u8 reg_type, u8 port)
1727 {
1728         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1729                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1730                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1731                    (8 << PMEG_IF_BYTE_COUNT),
1732                    (reg_type << 25) | (addr << 8) | port,
1733                    (u32)((data >> 32) & 0xffffffff),
1734                    (u32)(data & 0xffffffff));
1735
1736         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1737                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1738                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1739         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1740                  (reg_type << 25) | (addr << 8) | port);
1741         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1742         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1743                  (data >> 32) & 0xffffffff);
1744 }
1745
1746 #define XLPORT_MODE_REG (0x20a)
1747 #define XLPORT_MAC_CONTROL (0x210)
1748 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1749 #define XLPORT_ENABLE_REG (0x20b)
1750
1751 #define XLMAC_CTRL (0x600)
1752 #define XLMAC_MODE (0x601)
1753 #define XLMAC_RX_MAX_SIZE (0x608)
1754 #define XLMAC_TX_CTRL (0x604)
1755 #define XLMAC_PAUSE_CTRL (0x60d)
1756 #define XLMAC_PFC_CTRL (0x60e)
1757
1758 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1759                                     struct ecore_ptt *p_ptt)
1760 {
1761         u8 loopback = 0, port = p_hwfn->port_id * 2;
1762
1763         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1764
1765         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1766         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1767                          port);
1768         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1769         /* XLMAC: SOFT RESET */
1770         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1771         /* XLMAC: Port Speed >= 10Gbps */
1772         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1773         /* XLMAC: Max Size */
1774         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1775         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1776                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1777                          0, port);
1778         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1779         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1780                          0x30ffffc000ULL, 0, port);
1781         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1782                          port); /* XLMAC: TX_EN, RX_EN */
1783         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1784         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1785                          0x1003 | (loopback << 2), 0, port);
1786         /* Enabled Parallel PFC interface */
1787         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1788
1789         /* XLPORT port enable */
1790         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1791 }
1792
1793 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1794                                        struct ecore_ptt *p_ptt)
1795 {
1796         u8 port = p_hwfn->port_id;
1797         u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1798
1799         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1800
1801         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1802                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1803                  (port <<
1804                   CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1805                  (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1806
1807         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1808                  1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1809
1810         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1811                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1812
1813         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1814                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1815
1816         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1817                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1818
1819         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1820                  (0xA <<
1821                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1822                  (8 <<
1823                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1824
1825         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1826                  0xa853);
1827 }
1828
1829 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1830                                  struct ecore_ptt *p_ptt)
1831 {
1832         if (ECORE_IS_AH(p_hwfn->p_dev))
1833                 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1834         else /* BB */
1835                 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1836 }
1837
1838 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1839                                struct ecore_ptt *p_ptt,  u8 port)
1840 {
1841         int port_offset = port ? 0x800 : 0;
1842         u32 xmac_rxctrl = 0;
1843
1844         /* Reset of XMAC */
1845         /* FIXME: move to common start */
1846         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1847                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1848         OSAL_MSLEEP(1);
1849         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1850                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1851
1852         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1853
1854         /* Set the number of ports on the Warp Core to 10G */
1855         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1856
1857         /* Soft reset of XMAC */
1858         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1859                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1860         OSAL_MSLEEP(1);
1861         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1862                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1863
1864         /* FIXME: move to common end */
1865         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1866                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1867
1868         /* Set Max packet size: initialize XMAC block register for port 0 */
1869         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1870
1871         /* CRC append for Tx packets: init XMAC block register for port 1 */
1872         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1873
1874         /* Enable TX and RX: initialize XMAC block register for port 1 */
1875         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1876                  XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1877         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1878                                XMAC_REG_RX_CTRL_BB + port_offset);
1879         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1880         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1881 }
1882 #endif
1883
1884 static enum _ecore_status_t
1885 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1886                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1887 {
1888         u32 dpi_bit_shift, dpi_count, dpi_page_size;
1889         u32 min_dpis;
1890         u32 n_wids;
1891
1892         /* Calculate DPI size
1893          * ------------------
1894          * The PWM region contains Doorbell Pages. The first is reserverd for
1895          * the kernel for, e.g, L2. The others are free to be used by non-
1896          * trusted applications, typically from user space. Each page, called a
1897          * doorbell page is sectioned into windows that allow doorbells to be
1898          * issued in parallel by the kernel/application. The size of such a
1899          * window (a.k.a. WID) is 1kB.
1900          * Summary:
1901          *    1kB WID x N WIDS = DPI page size
1902          *    DPI page size x N DPIs = PWM region size
1903          * Notes:
1904          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1905          * in order to ensure that two applications won't share the same page.
1906          * It also must contain at least one WID per CPU to allow parallelism.
1907          * It also must be a power of 2, since it is stored as a bit shift.
1908          *
1909          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1910          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1911          * containing 4 WIDs.
1912          */
1913         n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus);
1914         dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids);
1915         dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) &
1916                         ~(OSAL_PAGE_SIZE - 1);
1917         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1918         dpi_count = pwm_region_size / dpi_page_size;
1919
1920         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1921         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1922
1923         /* Update hwfn */
1924         p_hwfn->dpi_size = dpi_page_size;
1925         p_hwfn->dpi_count = dpi_count;
1926
1927         /* Update registers */
1928         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1929
1930         if (dpi_count < min_dpis)
1931                 return ECORE_NORESOURCES;
1932
1933         return ECORE_SUCCESS;
1934 }
1935
1936 enum ECORE_ROCE_EDPM_MODE {
1937         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1938         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1939         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1940 };
1941
1942 static enum _ecore_status_t
1943 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1944                               struct ecore_ptt *p_ptt)
1945 {
1946         u32 pwm_regsize, norm_regsize;
1947         u32 non_pwm_conn, min_addr_reg1;
1948         u32 db_bar_size, n_cpus;
1949         u32 roce_edpm_mode;
1950         u32 pf_dems_shift;
1951         enum _ecore_status_t rc = ECORE_SUCCESS;
1952         u8 cond;
1953
1954         db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1955         if (ECORE_IS_CMT(p_hwfn->p_dev))
1956                 db_bar_size /= 2;
1957
1958         /* Calculate doorbell regions
1959          * -----------------------------------
1960          * The doorbell BAR is made of two regions. The first is called normal
1961          * region and the second is called PWM region. In the normal region
1962          * each ICID has its own set of addresses so that writing to that
1963          * specific address identifies the ICID. In the Process Window Mode
1964          * region the ICID is given in the data written to the doorbell. The
1965          * above per PF register denotes the offset in the doorbell BAR in which
1966          * the PWM region begins.
1967          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1968          * non-PWM connection. The calculation below computes the total non-PWM
1969          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1970          * in units of 4,096 bytes.
1971          */
1972         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1973             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1974                                           OSAL_NULL) +
1975             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1976         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn,
1977                                OSAL_PAGE_SIZE);
1978         min_addr_reg1 = norm_regsize / 4096;
1979         pwm_regsize = db_bar_size - norm_regsize;
1980
1981         /* Check that the normal and PWM sizes are valid */
1982         if (db_bar_size < norm_regsize) {
1983                 DP_ERR(p_hwfn->p_dev,
1984                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1985                        db_bar_size, norm_regsize);
1986                 return ECORE_NORESOURCES;
1987         }
1988         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1989                 DP_ERR(p_hwfn->p_dev,
1990                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1991                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1992                        norm_regsize);
1993                 return ECORE_NORESOURCES;
1994         }
1995
1996         /* Calculate number of DPIs */
1997         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1998         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1999             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
2000                 /* Either EDPM is mandatory, or we are attempting to allocate a
2001                  * WID per CPU.
2002                  */
2003                 n_cpus = OSAL_NUM_CPUS();
2004                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2005         }
2006
2007         cond = ((rc != ECORE_SUCCESS) &&
2008                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
2009                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
2010         if (cond || p_hwfn->dcbx_no_edpm) {
2011                 /* Either EDPM is disabled from user configuration, or it is
2012                  * disabled via DCBx, or it is not mandatory and we failed to
2013                  * allocated a WID per CPU.
2014                  */
2015                 n_cpus = 1;
2016                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2017
2018                 /* If we entered this flow due to DCBX then the DPM register is
2019                  * already configured.
2020                  */
2021         }
2022
2023         DP_INFO(p_hwfn,
2024                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
2025                 norm_regsize, pwm_regsize);
2026         DP_INFO(p_hwfn,
2027                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
2028                 p_hwfn->dpi_size, p_hwfn->dpi_count,
2029                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
2030                 "disabled" : "enabled");
2031
2032         /* Check return codes from above calls */
2033         if (rc != ECORE_SUCCESS) {
2034                 DP_ERR(p_hwfn,
2035                        "Failed to allocate enough DPIs\n");
2036                 return ECORE_NORESOURCES;
2037         }
2038
2039         /* Update hwfn */
2040         p_hwfn->dpi_start_offset = norm_regsize;
2041
2042         /* Update registers */
2043         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2044         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
2045         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2046         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2047
2048         return ECORE_SUCCESS;
2049 }
2050
2051 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
2052                                                struct ecore_ptt *p_ptt,
2053                                                int hw_mode)
2054 {
2055         u32 ppf_to_eng_sel[NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE];
2056         u32 val;
2057         enum _ecore_status_t rc = ECORE_SUCCESS;
2058         u8 i;
2059
2060         /* In CMT for non-RoCE packets - use connection based classification */
2061         val = ECORE_IS_CMT(p_hwfn->p_dev) ? 0x8 : 0x0;
2062         for (i = 0; i < NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE; i++)
2063                 ppf_to_eng_sel[i] = val;
2064         STORE_RT_REG_AGG(p_hwfn, NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET,
2065                          ppf_to_eng_sel);
2066
2067         /* In CMT the gate should be cleared by the 2nd hwfn */
2068         if (!ECORE_IS_CMT(p_hwfn->p_dev) || !IS_LEAD_HWFN(p_hwfn))
2069                 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
2070
2071         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
2072                             hw_mode);
2073         if (rc != ECORE_SUCCESS)
2074                 return rc;
2075
2076         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2077
2078 #ifndef ASIC_ONLY
2079         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2080                 return ECORE_SUCCESS;
2081
2082         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2083                 if (ECORE_IS_AH(p_hwfn->p_dev))
2084                         return ECORE_SUCCESS;
2085                 else if (ECORE_IS_BB(p_hwfn->p_dev))
2086                         ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
2087         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2088                 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
2089                         /* Activate OPTE in CMT */
2090                         u32 val;
2091
2092                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
2093                         val |= 0x10;
2094                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
2095                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
2096                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
2097                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
2098                         ecore_wr(p_hwfn, p_ptt,
2099                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
2100                         ecore_wr(p_hwfn, p_ptt,
2101                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
2102                         ecore_wr(p_hwfn, p_ptt,
2103                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
2104                                  0x55555555);
2105                 }
2106
2107                 ecore_emul_link_init(p_hwfn, p_ptt);
2108         } else {
2109                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
2110         }
2111 #endif
2112
2113         return rc;
2114 }
2115
2116 static enum _ecore_status_t
2117 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
2118                  struct ecore_ptt *p_ptt,
2119                  struct ecore_tunnel_info *p_tunn,
2120                  int hw_mode,
2121                  bool b_hw_start,
2122                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
2123 {
2124         u8 rel_pf_id = p_hwfn->rel_pf_id;
2125         u32 prs_reg;
2126         enum _ecore_status_t rc = ECORE_SUCCESS;
2127         u16 ctrl;
2128         int pos;
2129
2130         if (p_hwfn->mcp_info) {
2131                 struct ecore_mcp_function_info *p_info;
2132
2133                 p_info = &p_hwfn->mcp_info->func_info;
2134                 if (p_info->bandwidth_min)
2135                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2136
2137                 /* Update rate limit once we'll actually have a link */
2138                 p_hwfn->qm_info.pf_rl = 100000;
2139         }
2140         ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
2141
2142         ecore_int_igu_init_rt(p_hwfn);
2143
2144         /* Set VLAN in NIG if needed */
2145         if (hw_mode & (1 << MODE_MF_SD)) {
2146                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2147                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2148                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2149                              p_hwfn->hw_info.ovlan);
2150
2151                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2152                            "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
2153                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
2154                              1);
2155         }
2156
2157         /* Enable classification by MAC if needed */
2158         if (hw_mode & (1 << MODE_MF_SI)) {
2159                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2160                            "Configuring TAGMAC_CLS_TYPE\n");
2161                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
2162                              1);
2163         }
2164
2165         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
2166         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2167                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
2168         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2169                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
2170         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2171
2172         /* perform debug configuration when chip is out of reset */
2173         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
2174
2175         /* Sanity check before the PF init sequence that uses DMAE */
2176         rc = ecore_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
2177         if (rc)
2178                 return rc;
2179
2180         /* PF Init sequence */
2181         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2182         if (rc)
2183                 return rc;
2184
2185         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2186         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2187         if (rc)
2188                 return rc;
2189
2190         /* Pure runtime initializations - directly to the HW  */
2191         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2192
2193         /* PCI relaxed ordering causes a decrease in the performance on some
2194          * systems. Till a root cause is found, disable this attribute in the
2195          * PCI config space.
2196          */
2197         /* Not in use @DPDK
2198         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
2199         * if (!pos) {
2200         *       DP_NOTICE(p_hwfn, true,
2201         *                 "Failed to find the PCIe Cap\n");
2202         *       return ECORE_IO;
2203         * }
2204         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
2205         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
2206         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
2207         */
2208
2209         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2210         if (rc)
2211                 return rc;
2212         if (b_hw_start) {
2213                 /* enable interrupts */
2214                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
2215                 if (rc != ECORE_SUCCESS)
2216                         return rc;
2217
2218                 /* send function start command */
2219                 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2220                                        allow_npar_tx_switch);
2221                 if (rc) {
2222                         DP_NOTICE(p_hwfn, true,
2223                                   "Function start ramrod failed\n");
2224                 } else {
2225                         return rc;
2226                 }
2227                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2228                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2229                                 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2230
2231                 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
2232                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
2233                                         (1 << 2));
2234                         ecore_wr(p_hwfn, p_ptt,
2235                                  PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2236                                  0x100);
2237                 }
2238                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2239                                 "PRS_REG_SEARCH registers after start PFn\n");
2240                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
2241                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2242                                 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
2243                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
2244                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2245                                 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
2246                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
2247                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2248                                 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
2249                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
2250                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2251                                 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
2252                 prs_reg = ecore_rd(p_hwfn, p_ptt,
2253                                 PRS_REG_SEARCH_TCP_FIRST_FRAG);
2254                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2255                                 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
2256                                 prs_reg);
2257                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2258                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2259                                 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2260         }
2261         return ECORE_SUCCESS;
2262 }
2263
2264 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
2265                                                   struct ecore_ptt *p_ptt,
2266                                                   bool b_enable)
2267 {
2268         u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2269
2270         /* Configure the PF's internal FID_enable for master transactions */
2271         ecore_wr(p_hwfn, p_ptt,
2272                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2273
2274         /* Wait until value is set - try for 1 second every 50us */
2275         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2276                 val = ecore_rd(p_hwfn, p_ptt,
2277                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2278                 if (val == set_val)
2279                         break;
2280
2281                 OSAL_UDELAY(50);
2282         }
2283
2284         if (val != set_val) {
2285                 DP_NOTICE(p_hwfn, true,
2286                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
2287                 return ECORE_UNKNOWN_ERROR;
2288         }
2289
2290         return ECORE_SUCCESS;
2291 }
2292
2293 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
2294                                   struct ecore_ptt *p_main_ptt)
2295 {
2296         /* Read shadow of current MFW mailbox */
2297         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
2298         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
2299                     p_hwfn->mcp_info->mfw_mb_cur,
2300                     p_hwfn->mcp_info->mfw_mb_length);
2301 }
2302
2303 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
2304                                    struct ecore_ptt *p_ptt)
2305 {
2306         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
2307                  1 << p_hwfn->abs_pf_id);
2308 }
2309
2310 static enum _ecore_status_t
2311 ecore_fill_load_req_params(struct ecore_hwfn *p_hwfn,
2312                            struct ecore_load_req_params *p_load_req,
2313                            struct ecore_drv_load_params *p_drv_load)
2314 {
2315         /* Make sure that if ecore-client didn't provide inputs, all the
2316          * expected defaults are indeed zero.
2317          */
2318         OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
2319         OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
2320         OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
2321
2322         OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
2323
2324         if (p_drv_load == OSAL_NULL)
2325                 goto out;
2326
2327         p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2328                                ECORE_DRV_ROLE_KDUMP :
2329                                ECORE_DRV_ROLE_OS;
2330         p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2331         p_load_req->override_force_load = p_drv_load->override_force_load;
2332
2333         /* Old MFW versions don't support timeout values other than default and
2334          * none, so these values are replaced according to the fall-back action.
2335          */
2336
2337         if (p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT ||
2338             p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_NONE ||
2339             (p_hwfn->mcp_info->capabilities &
2340              FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO)) {
2341                 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2342                 goto out;
2343         }
2344
2345         switch (p_drv_load->mfw_timeout_fallback) {
2346         case ECORE_TO_FALLBACK_TO_NONE:
2347                 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_NONE;
2348                 break;
2349         case ECORE_TO_FALLBACK_TO_DEFAULT:
2350                 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_DEFAULT;
2351                 break;
2352         case ECORE_TO_FALLBACK_FAIL_LOAD:
2353                 DP_NOTICE(p_hwfn, false,
2354                           "Received %d as a value for MFW timeout while the MFW supports only default [%d] or none [%d]. Abort.\n",
2355                           p_drv_load->mfw_timeout_val,
2356                           ECORE_LOAD_REQ_LOCK_TO_DEFAULT,
2357                           ECORE_LOAD_REQ_LOCK_TO_NONE);
2358                 return ECORE_ABORTED;
2359         }
2360
2361         DP_INFO(p_hwfn,
2362                 "Modified the MFW timeout value from %d to %s [%d] due to lack of MFW support\n",
2363                 p_drv_load->mfw_timeout_val,
2364                 (p_load_req->timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT) ?
2365                 "default" : "none",
2366                 p_load_req->timeout_val);
2367 out:
2368         return ECORE_SUCCESS;
2369 }
2370
2371 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
2372                                     struct ecore_hw_init_params *p_params)
2373 {
2374         if (p_params->p_tunn) {
2375                 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2376                 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2377         }
2378
2379         p_hwfn->b_int_enabled = 1;
2380
2381         return ECORE_SUCCESS;
2382 }
2383
2384 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
2385                                    struct ecore_hw_init_params *p_params)
2386 {
2387         struct ecore_load_req_params load_req_params;
2388         u32 load_code, resp, param, drv_mb_param;
2389         bool b_default_mtu = true;
2390         struct ecore_hwfn *p_hwfn;
2391         enum _ecore_status_t rc = ECORE_SUCCESS;
2392         int i;
2393
2394         if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) {
2395                 DP_NOTICE(p_dev, false,
2396                           "MSI mode is not supported for CMT devices\n");
2397                 return ECORE_INVAL;
2398         }
2399
2400         if (IS_PF(p_dev)) {
2401                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
2402                 if (rc != ECORE_SUCCESS)
2403                         return rc;
2404         }
2405
2406         for_each_hwfn(p_dev, i) {
2407                 p_hwfn = &p_dev->hwfns[i];
2408
2409                 /* If management didn't provide a default, set one of our own */
2410                 if (!p_hwfn->hw_info.mtu) {
2411                         p_hwfn->hw_info.mtu = 1500;
2412                         b_default_mtu = false;
2413                 }
2414
2415                 if (IS_VF(p_dev)) {
2416                         ecore_vf_start(p_hwfn, p_params);
2417                         continue;
2418                 }
2419
2420                 rc = ecore_calc_hw_mode(p_hwfn);
2421                 if (rc != ECORE_SUCCESS)
2422                         return rc;
2423
2424                 ecore_set_spq_block_timeout(p_hwfn, p_params->spq_timeout_ms);
2425
2426                 rc = ecore_fill_load_req_params(p_hwfn, &load_req_params,
2427                                                 p_params->p_drv_load_params);
2428                 if (rc != ECORE_SUCCESS)
2429                         return rc;
2430
2431                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
2432                                         &load_req_params);
2433                 if (rc != ECORE_SUCCESS) {
2434                         DP_NOTICE(p_hwfn, false,
2435                                   "Failed sending a LOAD_REQ command\n");
2436                         return rc;
2437                 }
2438
2439                 load_code = load_req_params.load_code;
2440                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2441                            "Load request was sent. Load code: 0x%x\n",
2442                            load_code);
2443
2444                 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
2445
2446                 /* CQ75580:
2447                  * When coming back from hiberbate state, the registers from
2448                  * which shadow is read initially are not initialized. It turns
2449                  * out that these registers get initialized during the call to
2450                  * ecore_mcp_load_req request. So we need to reread them here
2451                  * to get the proper shadow register value.
2452                  * Note: This is a workaround for the missing MFW
2453                  * initialization. It may be removed once the implementation
2454                  * is done.
2455                  */
2456                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2457
2458                 /* Only relevant for recovery:
2459                  * Clear the indication after the LOAD_REQ command is responded
2460                  * by the MFW.
2461                  */
2462                 p_dev->recov_in_prog = false;
2463
2464                 p_hwfn->first_on_engine = (load_code ==
2465                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
2466
2467                 if (!qm_lock_ref_cnt) {
2468 #ifdef CONFIG_ECORE_LOCK_ALLOC
2469                         rc = OSAL_SPIN_LOCK_ALLOC(p_hwfn, &qm_lock);
2470                         if (rc) {
2471                                 DP_ERR(p_hwfn, "qm_lock allocation failed\n");
2472                                 goto qm_lock_fail;
2473                         }
2474 #endif
2475                         OSAL_SPIN_LOCK_INIT(&qm_lock);
2476                 }
2477                 ++qm_lock_ref_cnt;
2478
2479                 /* Clean up chip from previous driver if such remains exist.
2480                  * This is not needed when the PF is the first one on the
2481                  * engine, since afterwards we are going to init the FW.
2482                  */
2483                 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2484                         rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2485                                                  p_hwfn->rel_pf_id, false);
2486                         if (rc != ECORE_SUCCESS) {
2487                                 ecore_hw_err_notify(p_hwfn,
2488                                                     ECORE_HW_ERR_RAMROD_FAIL);
2489                                 goto load_err;
2490                         }
2491                 }
2492
2493                 /* Log and clean previous pglue_b errors if such exist */
2494                 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
2495                 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2496
2497                 /* Enable the PF's internal FID_enable in the PXP */
2498                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2499                                                   true);
2500                 if (rc != ECORE_SUCCESS)
2501                         goto load_err;
2502
2503                 switch (load_code) {
2504                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2505                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2506                                                   p_hwfn->hw_info.hw_mode);
2507                         if (rc != ECORE_SUCCESS)
2508                                 break;
2509                         /* Fall into */
2510                 case FW_MSG_CODE_DRV_LOAD_PORT:
2511                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2512                                                 p_hwfn->hw_info.hw_mode);
2513                         if (rc != ECORE_SUCCESS)
2514                                 break;
2515                         /* Fall into */
2516                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2517                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2518                                               p_params->p_tunn,
2519                                               p_hwfn->hw_info.hw_mode,
2520                                               p_params->b_hw_start,
2521                                               p_params->int_mode,
2522                                               p_params->allow_npar_tx_switch);
2523                         break;
2524                 default:
2525                         DP_NOTICE(p_hwfn, false,
2526                                   "Unexpected load code [0x%08x]", load_code);
2527                         rc = ECORE_NOTIMPL;
2528                         break;
2529                 }
2530
2531                 if (rc != ECORE_SUCCESS) {
2532                         DP_NOTICE(p_hwfn, false,
2533                                   "init phase failed for loadcode 0x%x (rc %d)\n",
2534                                   load_code, rc);
2535                         goto load_err;
2536                 }
2537
2538                 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2539                 if (rc != ECORE_SUCCESS) {
2540                         DP_NOTICE(p_hwfn, false,
2541                                   "Sending load done failed, rc = %d\n", rc);
2542                         if (rc == ECORE_NOMEM) {
2543                                 DP_NOTICE(p_hwfn, false,
2544                                           "Sending load done was failed due to memory allocation failure\n");
2545                                 goto load_err;
2546                         }
2547                         return rc;
2548                 }
2549
2550                 /* send DCBX attention request command */
2551                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2552                            "sending phony dcbx set command to trigger DCBx attention handling\n");
2553                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2554                                    DRV_MSG_CODE_SET_DCBX,
2555                                    1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
2556                                    &param);
2557                 if (rc != ECORE_SUCCESS) {
2558                         DP_NOTICE(p_hwfn, false,
2559                                   "Failed to send DCBX attention request\n");
2560                         return rc;
2561                 }
2562
2563                 p_hwfn->hw_init_done = true;
2564         }
2565
2566         if (IS_PF(p_dev)) {
2567                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2568                 drv_mb_param = STORM_FW_VERSION;
2569                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2570                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2571                                    drv_mb_param, &resp, &param);
2572                 if (rc != ECORE_SUCCESS)
2573                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
2574
2575                 if (!b_default_mtu)
2576                         rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2577                                                       p_hwfn->hw_info.mtu);
2578                 if (rc != ECORE_SUCCESS)
2579                         DP_INFO(p_hwfn, "Failed to update default mtu\n");
2580
2581                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2582                                                       p_hwfn->p_main_ptt,
2583                                                 ECORE_OV_DRIVER_STATE_DISABLED);
2584                 if (rc != ECORE_SUCCESS)
2585                         DP_INFO(p_hwfn, "Failed to update driver state\n");
2586         }
2587
2588         return rc;
2589
2590 load_err:
2591         --qm_lock_ref_cnt;
2592 #ifdef CONFIG_ECORE_LOCK_ALLOC
2593         if (!qm_lock_ref_cnt)
2594                 OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
2595 qm_lock_fail:
2596 #endif
2597         /* The MFW load lock should be released regardless of success or failure
2598          * of initialization.
2599          * TODO: replace this with an attempt to send cancel_load.
2600          */
2601         ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2602         return rc;
2603 }
2604
2605 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
2606 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2607                                  struct ecore_hwfn *p_hwfn,
2608                                  struct ecore_ptt *p_ptt)
2609 {
2610         int i;
2611
2612         /* close timers */
2613         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2614         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2615         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2616                                                                         i++) {
2617                 if ((!ecore_rd(p_hwfn, p_ptt,
2618                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2619                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2620                         break;
2621
2622                 /* Dependent on number of connection/tasks, possibly
2623                  * 1ms sleep is required between polls
2624                  */
2625                 OSAL_MSLEEP(1);
2626         }
2627
2628         if (i < ECORE_HW_STOP_RETRY_LIMIT)
2629                 return;
2630
2631         DP_NOTICE(p_hwfn, false,
2632                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
2633                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2634                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2635 }
2636
2637 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2638 {
2639         int j;
2640
2641         for_each_hwfn(p_dev, j) {
2642                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2643                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2644
2645                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2646         }
2647 }
2648
2649 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
2650                                                  struct ecore_ptt *p_ptt,
2651                                                  u32 addr, u32 expected_val)
2652 {
2653         u32 val = ecore_rd(p_hwfn, p_ptt, addr);
2654
2655         if (val != expected_val) {
2656                 DP_NOTICE(p_hwfn, true,
2657                           "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
2658                           addr, val, expected_val);
2659                 return ECORE_UNKNOWN_ERROR;
2660         }
2661
2662         return ECORE_SUCCESS;
2663 }
2664
2665 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2666 {
2667         struct ecore_hwfn *p_hwfn;
2668         struct ecore_ptt *p_ptt;
2669         enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
2670         int j;
2671
2672         for_each_hwfn(p_dev, j) {
2673                 p_hwfn = &p_dev->hwfns[j];
2674                 p_ptt = p_hwfn->p_main_ptt;
2675
2676                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2677
2678                 if (IS_VF(p_dev)) {
2679                         ecore_vf_pf_int_cleanup(p_hwfn);
2680                         rc = ecore_vf_pf_reset(p_hwfn);
2681                         if (rc != ECORE_SUCCESS) {
2682                                 DP_NOTICE(p_hwfn, true,
2683                                           "ecore_vf_pf_reset failed. rc = %d.\n",
2684                                           rc);
2685                                 rc2 = ECORE_UNKNOWN_ERROR;
2686                         }
2687                         continue;
2688                 }
2689
2690                 /* mark the hw as uninitialized... */
2691                 p_hwfn->hw_init_done = false;
2692
2693                 /* Send unload command to MCP */
2694                 if (!p_dev->recov_in_prog) {
2695                         rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
2696                         if (rc != ECORE_SUCCESS) {
2697                                 DP_NOTICE(p_hwfn, false,
2698                                           "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2699                                           rc);
2700                                 rc2 = ECORE_UNKNOWN_ERROR;
2701                         }
2702                 }
2703
2704                 OSAL_DPC_SYNC(p_hwfn);
2705
2706                 /* After this point no MFW attentions are expected, e.g. prevent
2707                  * race between pf stop and dcbx pf update.
2708                  */
2709
2710                 rc = ecore_sp_pf_stop(p_hwfn);
2711                 if (rc != ECORE_SUCCESS) {
2712                         DP_NOTICE(p_hwfn, false,
2713                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2714                                   rc);
2715                         rc2 = ECORE_UNKNOWN_ERROR;
2716                 }
2717
2718                 /* perform debug action after PF stop was sent */
2719                 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
2720
2721                 /* close NIG to BRB gate */
2722                 ecore_wr(p_hwfn, p_ptt,
2723                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2724
2725                 /* close parser */
2726                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2727                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2728                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2729                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2730                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2731
2732                 /* @@@TBD - clean transmission queues (5.b) */
2733                 /* @@@TBD - clean BTB (5.c) */
2734
2735                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2736
2737                 /* @@@TBD - verify DMAE requests are done (8) */
2738
2739                 /* Disable Attention Generation */
2740                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2741                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2742                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2743                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2744                 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
2745                 if (rc != ECORE_SUCCESS) {
2746                         DP_NOTICE(p_hwfn, true,
2747                                   "Failed to return IGU CAM to default\n");
2748                         rc2 = ECORE_UNKNOWN_ERROR;
2749                 }
2750
2751                 /* Need to wait 1ms to guarantee SBs are cleared */
2752                 OSAL_MSLEEP(1);
2753
2754                 if (!p_dev->recov_in_prog) {
2755                         ecore_verify_reg_val(p_hwfn, p_ptt,
2756                                              QM_REG_USG_CNT_PF_TX, 0);
2757                         ecore_verify_reg_val(p_hwfn, p_ptt,
2758                                              QM_REG_USG_CNT_PF_OTHER, 0);
2759                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
2760                 }
2761
2762                 /* Disable PF in HW blocks */
2763                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2764                 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2765
2766                 --qm_lock_ref_cnt;
2767 #ifdef CONFIG_ECORE_LOCK_ALLOC
2768                 if (!qm_lock_ref_cnt)
2769                         OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
2770 #endif
2771
2772                 if (!p_dev->recov_in_prog) {
2773                         rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
2774                         if (rc == ECORE_NOMEM) {
2775                                 DP_NOTICE(p_hwfn, false,
2776                                          "Failed sending an UNLOAD_DONE command due to a memory allocation failure. Resending.\n");
2777                                 rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
2778                         }
2779                         if (rc != ECORE_SUCCESS) {
2780                                 DP_NOTICE(p_hwfn, false,
2781                                           "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2782                                           rc);
2783                                 rc2 = ECORE_UNKNOWN_ERROR;
2784                         }
2785                 }
2786         } /* hwfn loop */
2787
2788         if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
2789                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2790                 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2791
2792                  /* Clear the PF's internal FID_enable in the PXP.
2793                   * In CMT this should only be done for first hw-function, and
2794                   * only after all transactions have stopped for all active
2795                   * hw-functions.
2796                   */
2797                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2798                                                   false);
2799                 if (rc != ECORE_SUCCESS) {
2800                         DP_NOTICE(p_hwfn, true,
2801                                   "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2802                                   rc);
2803                         rc2 = ECORE_UNKNOWN_ERROR;
2804                 }
2805         }
2806
2807         return rc2;
2808 }
2809
2810 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2811 {
2812         int j;
2813
2814         for_each_hwfn(p_dev, j) {
2815                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2816                 struct ecore_ptt *p_ptt;
2817
2818                 if (IS_VF(p_dev)) {
2819                         ecore_vf_pf_int_cleanup(p_hwfn);
2820                         continue;
2821                 }
2822                 p_ptt = ecore_ptt_acquire(p_hwfn);
2823                 if (!p_ptt)
2824                         return ECORE_AGAIN;
2825
2826                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2827                            "Shutting down the fastpath\n");
2828
2829                 ecore_wr(p_hwfn, p_ptt,
2830                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2831
2832                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2833                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2834                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2835                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2836                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2837
2838                 /* @@@TBD - clean transmission queues (5.b) */
2839                 /* @@@TBD - clean BTB (5.c) */
2840
2841                 /* @@@TBD - verify DMAE requests are done (8) */
2842
2843                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2844                 /* Need to wait 1ms to guarantee SBs are cleared */
2845                 OSAL_MSLEEP(1);
2846                 ecore_ptt_release(p_hwfn, p_ptt);
2847         }
2848
2849         return ECORE_SUCCESS;
2850 }
2851
2852 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2853 {
2854         struct ecore_ptt *p_ptt;
2855
2856         if (IS_VF(p_hwfn->p_dev))
2857                 return ECORE_SUCCESS;
2858
2859         p_ptt = ecore_ptt_acquire(p_hwfn);
2860         if (!p_ptt)
2861                 return ECORE_AGAIN;
2862
2863         /* If roce info is allocated it means roce is initialized and should
2864          * be enabled in searcher.
2865          */
2866         if (p_hwfn->p_rdma_info) {
2867                 if (p_hwfn->b_rdma_enabled_in_prs)
2868                         ecore_wr(p_hwfn, p_ptt,
2869                                  p_hwfn->rdma_prs_search_reg, 0x1);
2870                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2871         }
2872
2873         /* Re-open incoming traffic */
2874         ecore_wr(p_hwfn, p_ptt,
2875                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2876         ecore_ptt_release(p_hwfn, p_ptt);
2877
2878         return ECORE_SUCCESS;
2879 }
2880
2881 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2882 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2883 {
2884         ecore_ptt_pool_free(p_hwfn);
2885         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2886 }
2887
2888 /* Setup bar access */
2889 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2890 {
2891         /* clear indirect access */
2892         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2893                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2894                          PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2895                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2896                          PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2897                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2898                          PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2899                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2900                          PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2901         } else {
2902                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2903                          PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2904                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2905                          PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2906                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2907                          PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2908                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2909                          PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2910         }
2911
2912         /* Clean previous pglue_b errors if such exist */
2913         ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2914
2915         /* enable internal target-read */
2916         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2917                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2918 }
2919
2920 static void get_function_id(struct ecore_hwfn *p_hwfn)
2921 {
2922         /* ME Register */
2923         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2924                                                   PXP_PF_ME_OPAQUE_ADDR);
2925
2926         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2927
2928         /* Bits 16-19 from the ME registers are the pf_num */
2929         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2930         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2931                                       PXP_CONCRETE_FID_PFID);
2932         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2933                                     PXP_CONCRETE_FID_PORT);
2934
2935         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2936                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2937                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2938 }
2939
2940 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2941 {
2942         u32 *feat_num = p_hwfn->hw_info.feat_num;
2943         struct ecore_sb_cnt_info sb_cnt;
2944         u32 non_l2_sbs = 0;
2945
2946         OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
2947         ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
2948
2949         /* L2 Queues require each: 1 status block. 1 L2 queue */
2950         if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
2951                 /* Start by allocating VF queues, then PF's */
2952                 feat_num[ECORE_VF_L2_QUE] =
2953                         OSAL_MIN_T(u32,
2954                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
2955                                    sb_cnt.iov_cnt);
2956                 feat_num[ECORE_PF_L2_QUE] =
2957                         OSAL_MIN_T(u32,
2958                                    sb_cnt.cnt - non_l2_sbs,
2959                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2960                                    FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
2961         }
2962
2963         if (ECORE_IS_FCOE_PERSONALITY(p_hwfn))
2964                 feat_num[ECORE_FCOE_CQ] =
2965                         OSAL_MIN_T(u32, sb_cnt.cnt, RESC_NUM(p_hwfn,
2966                                                              ECORE_CMDQS_CQS));
2967
2968         if (ECORE_IS_ISCSI_PERSONALITY(p_hwfn))
2969                 feat_num[ECORE_ISCSI_CQ] =
2970                         OSAL_MIN_T(u32, sb_cnt.cnt, RESC_NUM(p_hwfn,
2971                                                              ECORE_CMDQS_CQS));
2972
2973         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2974                    "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2975                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2976                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2977                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2978                    (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2979                    (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2980                    (int)sb_cnt.cnt);
2981 }
2982
2983 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2984 {
2985         switch (res_id) {
2986         case ECORE_L2_QUEUE:
2987                 return "L2_QUEUE";
2988         case ECORE_VPORT:
2989                 return "VPORT";
2990         case ECORE_RSS_ENG:
2991                 return "RSS_ENG";
2992         case ECORE_PQ:
2993                 return "PQ";
2994         case ECORE_RL:
2995                 return "RL";
2996         case ECORE_MAC:
2997                 return "MAC";
2998         case ECORE_VLAN:
2999                 return "VLAN";
3000         case ECORE_RDMA_CNQ_RAM:
3001                 return "RDMA_CNQ_RAM";
3002         case ECORE_ILT:
3003                 return "ILT";
3004         case ECORE_LL2_QUEUE:
3005                 return "LL2_QUEUE";
3006         case ECORE_CMDQS_CQS:
3007                 return "CMDQS_CQS";
3008         case ECORE_RDMA_STATS_QUEUE:
3009                 return "RDMA_STATS_QUEUE";
3010         case ECORE_BDQ:
3011                 return "BDQ";
3012         case ECORE_SB:
3013                 return "SB";
3014         default:
3015                 return "UNKNOWN_RESOURCE";
3016         }
3017 }
3018
3019 static enum _ecore_status_t
3020 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
3021                               struct ecore_ptt *p_ptt,
3022                               enum ecore_resources res_id,
3023                               u32 resc_max_val,
3024                               u32 *p_mcp_resp)
3025 {
3026         enum _ecore_status_t rc;
3027
3028         rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
3029                                         resc_max_val, p_mcp_resp);
3030         if (rc != ECORE_SUCCESS) {
3031                 DP_NOTICE(p_hwfn, false,
3032                           "MFW response failure for a max value setting of resource %d [%s]\n",
3033                           res_id, ecore_hw_get_resc_name(res_id));
3034                 return rc;
3035         }
3036
3037         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
3038                 DP_INFO(p_hwfn,
3039                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
3040                         res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
3041
3042         return ECORE_SUCCESS;
3043 }
3044
3045 static enum _ecore_status_t
3046 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
3047                             struct ecore_ptt *p_ptt)
3048 {
3049         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3050         u32 resc_max_val, mcp_resp;
3051         u8 res_id;
3052         enum _ecore_status_t rc;
3053
3054         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3055                 /* @DPDK */
3056                 switch (res_id) {
3057                 case ECORE_LL2_QUEUE:
3058                 case ECORE_RDMA_CNQ_RAM:
3059                 case ECORE_RDMA_STATS_QUEUE:
3060                 case ECORE_BDQ:
3061                         resc_max_val = 0;
3062                         break;
3063                 default:
3064                         continue;
3065                 }
3066
3067                 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
3068                                                    resc_max_val, &mcp_resp);
3069                 if (rc != ECORE_SUCCESS)
3070                         return rc;
3071
3072                 /* There's no point to continue to the next resource if the
3073                  * command is not supported by the MFW.
3074                  * We do continue if the command is supported but the resource
3075                  * is unknown to the MFW. Such a resource will be later
3076                  * configured with the default allocation values.
3077                  */
3078                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
3079                         return ECORE_NOTIMPL;
3080         }
3081
3082         return ECORE_SUCCESS;
3083 }
3084
3085 static
3086 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
3087                                             enum ecore_resources res_id,
3088                                             u32 *p_resc_num, u32 *p_resc_start)
3089 {
3090         u8 num_funcs = p_hwfn->num_funcs_on_engine;
3091         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3092
3093         switch (res_id) {
3094         case ECORE_L2_QUEUE:
3095                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
3096                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
3097                 break;
3098         case ECORE_VPORT:
3099                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3100                                  MAX_NUM_VPORTS_BB) / num_funcs;
3101                 break;
3102         case ECORE_RSS_ENG:
3103                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
3104                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
3105                 break;
3106         case ECORE_PQ:
3107                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
3108                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
3109                 break;
3110         case ECORE_RL:
3111                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
3112                 break;
3113         case ECORE_MAC:
3114         case ECORE_VLAN:
3115                 /* Each VFC resource can accommodate both a MAC and a VLAN */
3116                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3117                 break;
3118         case ECORE_ILT:
3119                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
3120                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
3121                 break;
3122         case ECORE_LL2_QUEUE:
3123                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
3124                 break;
3125         case ECORE_RDMA_CNQ_RAM:
3126         case ECORE_CMDQS_CQS:
3127                 /* CNQ/CMDQS are the same resource */
3128                 /* @DPDK */
3129                 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
3130                 break;
3131         case ECORE_RDMA_STATS_QUEUE:
3132                 /* @DPDK */
3133                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3134                                  MAX_NUM_VPORTS_BB) / num_funcs;
3135                 break;
3136         case ECORE_BDQ:
3137                 /* @DPDK */
3138                 *p_resc_num = 0;
3139                 break;
3140         default:
3141                 break;
3142         }
3143
3144
3145         switch (res_id) {
3146         case ECORE_BDQ:
3147                 if (!*p_resc_num)
3148                         *p_resc_start = 0;
3149                 break;
3150         case ECORE_SB:
3151                 /* Since we want its value to reflect whether MFW supports
3152                  * the new scheme, have a default of 0.
3153                  */
3154                 *p_resc_num = 0;
3155                 break;
3156         default:
3157                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3158                 break;
3159         }
3160
3161         return ECORE_SUCCESS;
3162 }
3163
3164 static enum _ecore_status_t
3165 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
3166                          bool drv_resc_alloc)
3167 {
3168         u32 dflt_resc_num = 0, dflt_resc_start = 0;
3169         u32 mcp_resp, *p_resc_num, *p_resc_start;
3170         enum _ecore_status_t rc;
3171
3172         p_resc_num = &RESC_NUM(p_hwfn, res_id);
3173         p_resc_start = &RESC_START(p_hwfn, res_id);
3174
3175         rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3176                                     &dflt_resc_start);
3177         if (rc != ECORE_SUCCESS) {
3178                 DP_ERR(p_hwfn,
3179                        "Failed to get default amount for resource %d [%s]\n",
3180                         res_id, ecore_hw_get_resc_name(res_id));
3181                 return rc;
3182         }
3183
3184 #ifndef ASIC_ONLY
3185         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3186                 *p_resc_num = dflt_resc_num;
3187                 *p_resc_start = dflt_resc_start;
3188                 goto out;
3189         }
3190 #endif
3191
3192         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3193                                      &mcp_resp, p_resc_num, p_resc_start);
3194         if (rc != ECORE_SUCCESS) {
3195                 DP_NOTICE(p_hwfn, true,
3196                           "MFW response failure for an allocation request for"
3197                           " resource %d [%s]\n",
3198                           res_id, ecore_hw_get_resc_name(res_id));
3199                 return rc;
3200         }
3201
3202         /* Default driver values are applied in the following cases:
3203          * - The resource allocation MB command is not supported by the MFW
3204          * - There is an internal error in the MFW while processing the request
3205          * - The resource ID is unknown to the MFW
3206          */
3207         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3208                 DP_INFO(p_hwfn,
3209                         "Failed to receive allocation info for resource %d [%s]."
3210                         " mcp_resp = 0x%x. Applying default values"
3211                         " [%d,%d].\n",
3212                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
3213                         dflt_resc_num, dflt_resc_start);
3214
3215                 *p_resc_num = dflt_resc_num;
3216                 *p_resc_start = dflt_resc_start;
3217                 goto out;
3218         }
3219
3220         if ((*p_resc_num != dflt_resc_num ||
3221              *p_resc_start != dflt_resc_start) &&
3222             res_id != ECORE_SB) {
3223                 DP_INFO(p_hwfn,
3224                         "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
3225                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
3226                         *p_resc_start, dflt_resc_num, dflt_resc_start,
3227                         drv_resc_alloc ? " - Applying default values" : "");
3228                 if (drv_resc_alloc) {
3229                         *p_resc_num = dflt_resc_num;
3230                         *p_resc_start = dflt_resc_start;
3231                 }
3232         }
3233 out:
3234         return ECORE_SUCCESS;
3235 }
3236
3237 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
3238                                                    bool drv_resc_alloc)
3239 {
3240         enum _ecore_status_t rc;
3241         u8 res_id;
3242
3243         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3244                 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
3245                 if (rc != ECORE_SUCCESS)
3246                         return rc;
3247         }
3248
3249         return ECORE_SUCCESS;
3250 }
3251
3252 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
3253                                               struct ecore_ptt *p_ptt,
3254                                               bool drv_resc_alloc)
3255 {
3256         struct ecore_resc_unlock_params resc_unlock_params;
3257         struct ecore_resc_lock_params resc_lock_params;
3258         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3259         u8 res_id;
3260         enum _ecore_status_t rc;
3261 #ifndef ASIC_ONLY
3262         u32 *resc_start = p_hwfn->hw_info.resc_start;
3263         u32 *resc_num = p_hwfn->hw_info.resc_num;
3264         /* For AH, an equal share of the ILT lines between the maximal number of
3265          * PFs is not enough for RoCE. This would be solved by the future
3266          * resource allocation scheme, but isn't currently present for
3267          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
3268          * to work - the BB number of ILT lines divided by its max PFs number.
3269          */
3270         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
3271 #endif
3272
3273         /* Setting the max values of the soft resources and the following
3274          * resources allocation queries should be atomic. Since several PFs can
3275          * run in parallel - a resource lock is needed.
3276          * If either the resource lock or resource set value commands are not
3277          * supported - skip the max values setting, release the lock if
3278          * needed, and proceed to the queries. Other failures, including a
3279          * failure to acquire the lock, will cause this function to fail.
3280          * Old drivers that don't acquire the lock can run in parallel, and
3281          * their allocation values won't be affected by the updated max values.
3282          */
3283         ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3284                                          ECORE_RESC_LOCK_RESC_ALLOC, false);
3285
3286         rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3287         if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3288                 return rc;
3289         } else if (rc == ECORE_NOTIMPL) {
3290                 DP_INFO(p_hwfn,
3291                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3292         } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
3293                 DP_NOTICE(p_hwfn, false,
3294                           "Failed to acquire the resource lock for the resource allocation commands\n");
3295                 rc = ECORE_BUSY;
3296                 goto unlock_and_exit;
3297         } else {
3298                 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
3299                 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3300                         DP_NOTICE(p_hwfn, false,
3301                                   "Failed to set the max values of the soft resources\n");
3302                         goto unlock_and_exit;
3303                 } else if (rc == ECORE_NOTIMPL) {
3304                         DP_INFO(p_hwfn,
3305                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3306                         rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3307                                                    &resc_unlock_params);
3308                         if (rc != ECORE_SUCCESS)
3309                                 DP_INFO(p_hwfn,
3310                                         "Failed to release the resource lock for the resource allocation commands\n");
3311                 }
3312         }
3313
3314         rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
3315         if (rc != ECORE_SUCCESS)
3316                 goto unlock_and_exit;
3317
3318         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3319                 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3320                                            &resc_unlock_params);
3321                 if (rc != ECORE_SUCCESS)
3322                         DP_INFO(p_hwfn,
3323                                 "Failed to release the resource lock for the resource allocation commands\n");
3324         }
3325
3326 #ifndef ASIC_ONLY
3327         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3328                 /* Reduced build contains less PQs */
3329                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
3330                         resc_num[ECORE_PQ] = 32;
3331                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
3332                             p_hwfn->enabled_func_idx;
3333                 }
3334
3335                 /* For AH emulation, since we have a possible maximal number of
3336                  * 16 enabled PFs, in case there are not enough ILT lines -
3337                  * allocate only first PF as RoCE and have all the other ETH
3338                  * only with less ILT lines.
3339                  */
3340                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
3341                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
3342                                                          resc_num[ECORE_ILT],
3343                                                          roce_min_ilt_lines);
3344         }
3345
3346         /* Correct the common ILT calculation if PF0 has more */
3347         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
3348             p_hwfn->p_dev->b_is_emul_full &&
3349             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
3350                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
3351                     resc_num[ECORE_ILT];
3352 #endif
3353
3354         /* Sanity for ILT */
3355         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3356             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3357                 DP_NOTICE(p_hwfn, true,
3358                           "Can't assign ILT pages [%08x,...,%08x]\n",
3359                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
3360                                                                   ECORE_ILT) -
3361                           1);
3362                 return ECORE_INVAL;
3363         }
3364
3365         /* This will also learn the number of SBs from MFW */
3366         if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
3367                 return ECORE_INVAL;
3368
3369         ecore_hw_set_feat(p_hwfn);
3370
3371         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3372                    "The numbers for each resource are:\n");
3373         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
3374                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
3375                            ecore_hw_get_resc_name(res_id),
3376                            RESC_NUM(p_hwfn, res_id),
3377                            RESC_START(p_hwfn, res_id));
3378
3379         return ECORE_SUCCESS;
3380
3381 unlock_and_exit:
3382         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3383                 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3384                                       &resc_unlock_params);
3385         return rc;
3386 }
3387
3388 static enum _ecore_status_t
3389 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
3390                       struct ecore_ptt *p_ptt,
3391                       struct ecore_hw_prepare_params *p_params)
3392 {
3393         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
3394         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
3395         struct ecore_mcp_link_capabilities *p_caps;
3396         struct ecore_mcp_link_params *link;
3397         enum _ecore_status_t rc;
3398
3399         /* Read global nvm_cfg address */
3400         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
3401
3402         /* Verify MCP has initialized it */
3403         if (!nvm_cfg_addr) {
3404                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
3405                 if (p_params->b_relaxed_probe)
3406                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
3407                 return ECORE_INVAL;
3408         }
3409
3410 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
3411
3412         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
3413
3414         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3415                    OFFSETOF(struct nvm_cfg1, glob) +
3416                    OFFSETOF(struct nvm_cfg1_glob, core_cfg);
3417
3418         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
3419
3420         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
3421                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
3422         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
3423                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
3424                 break;
3425         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
3426                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
3427                 break;
3428         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
3429                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
3430                 break;
3431         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
3432                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
3433                 break;
3434         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
3435                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
3436                 break;
3437         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
3438                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
3439                 break;
3440         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
3441                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
3442                 break;
3443         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
3444                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
3445                 break;
3446         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
3447                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
3448                 break;
3449         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
3450                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
3451                 break;
3452         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3453                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
3454                 break;
3455         default:
3456                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
3457                           core_cfg);
3458                 break;
3459         }
3460
3461         /* Read DCBX configuration */
3462         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3463                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3464         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
3465                              port_cfg_addr +
3466                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
3467         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
3468                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
3469         switch (dcbx_mode) {
3470         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
3471                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
3472                 break;
3473         case NVM_CFG1_PORT_DCBX_MODE_CEE:
3474                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
3475                 break;
3476         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
3477                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
3478                 break;
3479         default:
3480                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
3481         }
3482
3483         /* Read default link configuration */
3484         link = &p_hwfn->mcp_info->link_input;
3485         p_caps = &p_hwfn->mcp_info->link_capabilities;
3486         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3487             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3488         link_temp = ecore_rd(p_hwfn, p_ptt,
3489                              port_cfg_addr +
3490                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
3491         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
3492         link->speed.advertised_speeds = link_temp;
3493         p_caps->speed_capabilities = link->speed.advertised_speeds;
3494
3495         link_temp = ecore_rd(p_hwfn, p_ptt,
3496                                  port_cfg_addr +
3497                                  OFFSETOF(struct nvm_cfg1_port, link_settings));
3498         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
3499                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
3500         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
3501                 link->speed.autoneg = true;
3502                 break;
3503         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
3504                 link->speed.forced_speed = 1000;
3505                 break;
3506         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
3507                 link->speed.forced_speed = 10000;
3508                 break;
3509         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3510                 link->speed.forced_speed = 25000;
3511                 break;
3512         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3513                 link->speed.forced_speed = 40000;
3514                 break;
3515         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3516                 link->speed.forced_speed = 50000;
3517                 break;
3518         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3519                 link->speed.forced_speed = 100000;
3520                 break;
3521         default:
3522                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
3523         }
3524
3525         p_caps->default_speed = link->speed.forced_speed;
3526         p_caps->default_speed_autoneg = link->speed.autoneg;
3527
3528         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3529         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3530         link->pause.autoneg = !!(link_temp &
3531                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3532         link->pause.forced_rx = !!(link_temp &
3533                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3534         link->pause.forced_tx = !!(link_temp &
3535                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3536         link->loopback_mode = 0;
3537
3538         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
3539                 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
3540                                      OFFSETOF(struct nvm_cfg1_port, ext_phy));
3541                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
3542                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
3543                 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
3544                 link->eee.enable = true;
3545                 switch (link_temp) {
3546                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
3547                         p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
3548                         link->eee.enable = false;
3549                         break;
3550                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
3551                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
3552                         break;
3553                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
3554                         p_caps->eee_lpi_timer =
3555                                 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
3556                         break;
3557                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
3558                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
3559                         break;
3560                 }
3561
3562                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
3563                 link->eee.tx_lpi_enable = link->eee.enable;
3564                 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
3565         } else {
3566                 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
3567         }
3568
3569         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3570                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
3571                    link->speed.forced_speed, link->speed.advertised_speeds,
3572                    link->speed.autoneg, link->pause.autoneg,
3573                    p_caps->default_eee, p_caps->eee_lpi_timer);
3574
3575         /* Read Multi-function information from shmem */
3576         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3577                    OFFSETOF(struct nvm_cfg1, glob) +
3578                    OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3579
3580         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3581
3582         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3583             NVM_CFG1_GLOB_MF_MODE_OFFSET;
3584
3585         switch (mf_mode) {
3586         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3587                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS;
3588                 break;
3589         case NVM_CFG1_GLOB_MF_MODE_UFP:
3590                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
3591                                          1 << ECORE_MF_UFP_SPECIFIC;
3592                 break;
3593
3594         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3595                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3596                                          1 << ECORE_MF_LLH_PROTO_CLSS |
3597                                          1 << ECORE_MF_LL2_NON_UNICAST |
3598                                          1 << ECORE_MF_INTER_PF_SWITCH |
3599                                          1 << ECORE_MF_DISABLE_ARFS;
3600                 break;
3601         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3602                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3603                                          1 << ECORE_MF_LLH_PROTO_CLSS |
3604                                          1 << ECORE_MF_LL2_NON_UNICAST;
3605                 if (ECORE_IS_BB(p_hwfn->p_dev))
3606                         p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
3607                 break;
3608         }
3609         DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
3610                 p_hwfn->p_dev->mf_bits);
3611
3612         if (ECORE_IS_CMT(p_hwfn->p_dev))
3613                 p_hwfn->p_dev->mf_bits |= (1 << ECORE_MF_DISABLE_ARFS);
3614
3615         /* It's funny since we have another switch, but it's easier
3616          * to throw this away in linux this way. Long term, it might be
3617          * better to have have getters for needed ECORE_MF_* fields,
3618          * convert client code and eliminate this.
3619          */
3620         switch (mf_mode) {
3621         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3622                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3623                 break;
3624         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3625                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3626                 break;
3627         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3628                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3629                 break;
3630         case NVM_CFG1_GLOB_MF_MODE_UFP:
3631                 p_hwfn->p_dev->mf_mode = ECORE_MF_UFP;
3632                 break;
3633         }
3634
3635         /* Read Multi-function information from shmem */
3636         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3637                    OFFSETOF(struct nvm_cfg1, glob) +
3638                    OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3639
3640         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3641         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3642                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3643                                 &p_hwfn->hw_info.device_capabilities);
3644         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3645                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3646                                 &p_hwfn->hw_info.device_capabilities);
3647         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3648                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3649                                 &p_hwfn->hw_info.device_capabilities);
3650         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3651                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3652                                 &p_hwfn->hw_info.device_capabilities);
3653         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3654                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3655                                 &p_hwfn->hw_info.device_capabilities);
3656
3657         rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3658         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3659                 rc = ECORE_SUCCESS;
3660                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3661         }
3662
3663         return rc;
3664 }
3665
3666 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3667                                 struct ecore_ptt *p_ptt)
3668 {
3669         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3670         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3671         struct ecore_dev *p_dev = p_hwfn->p_dev;
3672
3673         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3674
3675         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3676          * in the other bits are selected.
3677          * Bits 1-15 are for functions 1-15, respectively, and their value is
3678          * '0' only for enabled functions (function 0 always exists and
3679          * enabled).
3680          * In case of CMT in BB, only the "even" functions are enabled, and thus
3681          * the number of functions for both hwfns is learnt from the same bits.
3682          */
3683         if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3684                 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3685                                              MISCS_REG_FUNCTION_HIDE_BB_K2);
3686         } else { /* E5 */
3687                 reg_function_hide = 0;
3688         }
3689
3690         if (reg_function_hide & 0x1) {
3691                 if (ECORE_IS_BB(p_dev)) {
3692                         if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) {
3693                                 num_funcs = 0;
3694                                 eng_mask = 0xaaaa;
3695                         } else {
3696                                 num_funcs = 1;
3697                                 eng_mask = 0x5554;
3698                         }
3699                 } else {
3700                         num_funcs = 1;
3701                         eng_mask = 0xfffe;
3702                 }
3703
3704                 /* Get the number of the enabled functions on the engine */
3705                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3706                 while (tmp) {
3707                         if (tmp & 0x1)
3708                                 num_funcs++;
3709                         tmp >>= 0x1;
3710                 }
3711
3712                 /* Get the PF index within the enabled functions */
3713                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3714                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3715                 while (tmp) {
3716                         if (tmp & 0x1)
3717                                 enabled_func_idx--;
3718                         tmp >>= 0x1;
3719                 }
3720         }
3721
3722         p_hwfn->num_funcs_on_engine = num_funcs;
3723         p_hwfn->enabled_func_idx = enabled_func_idx;
3724
3725 #ifndef ASIC_ONLY
3726         if (CHIP_REV_IS_FPGA(p_dev)) {
3727                 DP_NOTICE(p_hwfn, false,
3728                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3729                 p_hwfn->num_funcs_on_engine = 4;
3730         }
3731 #endif
3732
3733         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3734                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3735                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3736                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3737 }
3738
3739 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3740                                       struct ecore_ptt *p_ptt)
3741 {
3742         struct ecore_dev *p_dev = p_hwfn->p_dev;
3743         u32 port_mode;
3744
3745 #ifndef ASIC_ONLY
3746         /* Read the port mode */
3747         if (CHIP_REV_IS_FPGA(p_dev))
3748                 port_mode = 4;
3749         else if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_CMT(p_dev))
3750                 /* In CMT on emulation, assume 1 port */
3751                 port_mode = 1;
3752         else
3753 #endif
3754         port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3755
3756         if (port_mode < 3) {
3757                 p_dev->num_ports_in_engine = 1;
3758         } else if (port_mode <= 5) {
3759                 p_dev->num_ports_in_engine = 2;
3760         } else {
3761                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3762                           p_dev->num_ports_in_engine);
3763
3764                 /* Default num_ports_in_engine to something */
3765                 p_dev->num_ports_in_engine = 1;
3766         }
3767 }
3768
3769 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3770                                          struct ecore_ptt *p_ptt)
3771 {
3772         struct ecore_dev *p_dev = p_hwfn->p_dev;
3773         u32 port;
3774         int i;
3775
3776         p_dev->num_ports_in_engine = 0;
3777
3778 #ifndef ASIC_ONLY
3779         if (CHIP_REV_IS_EMUL(p_dev)) {
3780                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3781                 switch ((port & 0xf000) >> 12) {
3782                 case 1:
3783                         p_dev->num_ports_in_engine = 1;
3784                         break;
3785                 case 3:
3786                         p_dev->num_ports_in_engine = 2;
3787                         break;
3788                 case 0xf:
3789                         p_dev->num_ports_in_engine = 4;
3790                         break;
3791                 default:
3792                         DP_NOTICE(p_hwfn, false,
3793                                   "Unknown port mode in ECO_RESERVED %08x\n",
3794                                   port);
3795                 }
3796         } else
3797 #endif
3798                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3799                         port = ecore_rd(p_hwfn, p_ptt,
3800                                         CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3801                                         (i * 4));
3802                         if (port & 1)
3803                                 p_dev->num_ports_in_engine++;
3804                 }
3805
3806         if (!p_dev->num_ports_in_engine) {
3807                 DP_NOTICE(p_hwfn, true, "All NIG ports are inactive\n");
3808
3809                 /* Default num_ports_in_engine to something */
3810                 p_dev->num_ports_in_engine = 1;
3811         }
3812 }
3813
3814 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3815                                    struct ecore_ptt *p_ptt)
3816 {
3817         struct ecore_dev *p_dev = p_hwfn->p_dev;
3818
3819         /* Determine the number of ports per engine */
3820         if (ECORE_IS_BB(p_dev))
3821                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3822         else
3823                 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3824
3825         /* Get the total number of ports of the device */
3826         if (ECORE_IS_CMT(p_dev)) {
3827                 /* In CMT there is always only one port */
3828                 p_dev->num_ports = 1;
3829 #ifndef ASIC_ONLY
3830         } else if (CHIP_REV_IS_EMUL(p_dev) || CHIP_REV_IS_TEDIBEAR(p_dev)) {
3831                 p_dev->num_ports = p_dev->num_ports_in_engine *
3832                                    ecore_device_num_engines(p_dev);
3833 #endif
3834         } else {
3835                 u32 addr, global_offsize, global_addr;
3836
3837                 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
3838                                             PUBLIC_GLOBAL);
3839                 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
3840                 global_addr = SECTION_ADDR(global_offsize, 0);
3841                 addr = global_addr + OFFSETOF(struct public_global, max_ports);
3842                 p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
3843         }
3844 }
3845
3846 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
3847                                    struct ecore_ptt *p_ptt)
3848 {
3849         struct ecore_mcp_link_capabilities *p_caps;
3850         u32 eee_status;
3851
3852         p_caps = &p_hwfn->mcp_info->link_capabilities;
3853         if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
3854                 return;
3855
3856         p_caps->eee_speed_caps = 0;
3857         eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
3858                               OFFSETOF(struct public_port, eee_status));
3859         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
3860                         EEE_SUPPORTED_SPEED_OFFSET;
3861         if (eee_status & EEE_1G_SUPPORTED)
3862                 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
3863         if (eee_status & EEE_10G_ADV)
3864                 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
3865 }
3866
3867 static enum _ecore_status_t
3868 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3869                   enum ecore_pci_personality personality,
3870                   struct ecore_hw_prepare_params *p_params)
3871 {
3872         bool drv_resc_alloc = p_params->drv_resc_alloc;
3873         enum _ecore_status_t rc;
3874
3875         /* Since all information is common, only first hwfns should do this */
3876         if (IS_LEAD_HWFN(p_hwfn)) {
3877                 rc = ecore_iov_hw_info(p_hwfn);
3878                 if (rc != ECORE_SUCCESS) {
3879                         if (p_params->b_relaxed_probe)
3880                                 p_params->p_relaxed_res =
3881                                                 ECORE_HW_PREPARE_BAD_IOV;
3882                         else
3883                                 return rc;
3884                 }
3885         }
3886
3887         if (IS_LEAD_HWFN(p_hwfn))
3888                 ecore_hw_info_port_num(p_hwfn, p_ptt);
3889
3890         ecore_mcp_get_capabilities(p_hwfn, p_ptt);
3891
3892 #ifndef ASIC_ONLY
3893         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3894 #endif
3895         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3896         if (rc != ECORE_SUCCESS)
3897                 return rc;
3898 #ifndef ASIC_ONLY
3899         }
3900 #endif
3901
3902         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3903         if (rc != ECORE_SUCCESS) {
3904                 if (p_params->b_relaxed_probe)
3905                         p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3906                 else
3907                         return rc;
3908         }
3909
3910 #ifndef ASIC_ONLY
3911         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3912 #endif
3913                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3914                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3915 #ifndef ASIC_ONLY
3916         } else {
3917                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3918
3919                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3920                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3921         }
3922 #endif
3923
3924         if (ecore_mcp_is_init(p_hwfn)) {
3925                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3926                         p_hwfn->hw_info.ovlan =
3927                             p_hwfn->mcp_info->func_info.ovlan;
3928
3929                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3930
3931                 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
3932
3933                 ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
3934         }
3935
3936         if (personality != ECORE_PCI_DEFAULT) {
3937                 p_hwfn->hw_info.personality = personality;
3938         } else if (ecore_mcp_is_init(p_hwfn)) {
3939                 enum ecore_pci_personality protocol;
3940
3941                 protocol = p_hwfn->mcp_info->func_info.protocol;
3942                 p_hwfn->hw_info.personality = protocol;
3943         }
3944
3945 #ifndef ASIC_ONLY
3946         /* To overcome ILT lack for emulation, until at least until we'll have
3947          * a definite answer from system about it, allow only PF0 to be RoCE.
3948          */
3949         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3950                 if (!p_hwfn->rel_pf_id)
3951                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3952                 else
3953                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3954         }
3955 #endif
3956
3957         /* although in BB some constellations may support more than 4 tcs,
3958          * that can result in performance penalty in some cases. 4
3959          * represents a good tradeoff between performance and flexibility.
3960          */
3961         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3962
3963         /* start out with a single active tc. This can be increased either
3964          * by dcbx negotiation or by upper layer driver
3965          */
3966         p_hwfn->hw_info.num_active_tc = 1;
3967
3968         ecore_get_num_funcs(p_hwfn, p_ptt);
3969
3970         if (ecore_mcp_is_init(p_hwfn))
3971                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3972
3973         /* In case of forcing the driver's default resource allocation, calling
3974          * ecore_hw_get_resc() should come after initializing the personality
3975          * and after getting the number of functions, since the calculation of
3976          * the resources/features depends on them.
3977          * This order is not harmful if not forcing.
3978          */
3979         rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
3980         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3981                 rc = ECORE_SUCCESS;
3982                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3983         }
3984
3985         return rc;
3986 }
3987
3988 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
3989                                                struct ecore_ptt *p_ptt)
3990 {
3991         struct ecore_dev *p_dev = p_hwfn->p_dev;
3992         u16 device_id_mask;
3993         u32 tmp;
3994
3995         /* Read Vendor Id / Device Id */
3996         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3997                                   &p_dev->vendor_id);
3998         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3999                                   &p_dev->device_id);
4000
4001         /* Determine type */
4002         device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
4003         switch (device_id_mask) {
4004         case ECORE_DEV_ID_MASK_BB:
4005                 p_dev->type = ECORE_DEV_TYPE_BB;
4006                 break;
4007         case ECORE_DEV_ID_MASK_AH:
4008                 p_dev->type = ECORE_DEV_TYPE_AH;
4009                 break;
4010         default:
4011                 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
4012                           p_dev->device_id);
4013                 return ECORE_ABORTED;
4014         }
4015
4016         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
4017         p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM);
4018         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
4019         p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV);
4020
4021         /* Learn number of HW-functions */
4022         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
4023
4024         if (tmp & (1 << p_hwfn->rel_pf_id)) {
4025                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
4026                 p_dev->num_hwfns = 2;
4027         } else {
4028                 p_dev->num_hwfns = 1;
4029         }
4030
4031 #ifndef ASIC_ONLY
4032         if (CHIP_REV_IS_EMUL(p_dev)) {
4033                 /* For some reason we have problems with this register
4034                  * in B0 emulation; Simply assume no CMT
4035                  */
4036                 DP_NOTICE(p_dev->hwfns, false,
4037                           "device on emul - assume no CMT\n");
4038                 p_dev->num_hwfns = 1;
4039         }
4040 #endif
4041
4042         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG);
4043         p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID);
4044         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
4045         p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL);
4046
4047         DP_INFO(p_dev->hwfns,
4048                 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n",
4049                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
4050                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
4051                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
4052                 p_dev->chip_metal);
4053
4054         if (ECORE_IS_BB_A0(p_dev)) {
4055                 DP_NOTICE(p_dev->hwfns, false,
4056                           "The chip type/rev (BB A0) is not supported!\n");
4057                 return ECORE_ABORTED;
4058         }
4059 #ifndef ASIC_ONLY
4060         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
4061                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
4062
4063         if (CHIP_REV_IS_EMUL(p_dev)) {
4064                 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
4065                 if (tmp & (1 << 29)) {
4066                         DP_NOTICE(p_hwfn, false,
4067                                   "Emulation: Running on a FULL build\n");
4068                         p_dev->b_is_emul_full = true;
4069                 } else {
4070                         DP_NOTICE(p_hwfn, false,
4071                                   "Emulation: Running on a REDUCED build\n");
4072                 }
4073         }
4074 #endif
4075
4076         return ECORE_SUCCESS;
4077 }
4078
4079 #ifndef LINUX_REMOVE
4080 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
4081 {
4082         int j;
4083
4084         if (IS_VF(p_dev))
4085                 return;
4086
4087         for_each_hwfn(p_dev, j) {
4088                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
4089
4090                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
4091                            "Mark hw/fw uninitialized\n");
4092
4093                 p_hwfn->hw_init_done = false;
4094
4095                 ecore_ptt_invalidate(p_hwfn);
4096         }
4097 }
4098 #endif
4099
4100 static enum _ecore_status_t
4101 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
4102                         void OSAL_IOMEM * p_regview,
4103                         void OSAL_IOMEM * p_doorbells,
4104                         struct ecore_hw_prepare_params *p_params)
4105 {
4106         struct ecore_mdump_retain_data mdump_retain;
4107         struct ecore_dev *p_dev = p_hwfn->p_dev;
4108         struct ecore_mdump_info mdump_info;
4109         enum _ecore_status_t rc = ECORE_SUCCESS;
4110
4111         /* Split PCI bars evenly between hwfns */
4112         p_hwfn->regview = p_regview;
4113         p_hwfn->doorbells = p_doorbells;
4114
4115         if (IS_VF(p_dev))
4116                 return ecore_vf_hw_prepare(p_hwfn);
4117
4118         /* Validate that chip access is feasible */
4119         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
4120                 DP_ERR(p_hwfn,
4121                        "Reading the ME register returns all Fs; Preventing further chip access\n");
4122                 if (p_params->b_relaxed_probe)
4123                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
4124                 return ECORE_INVAL;
4125         }
4126
4127         get_function_id(p_hwfn);
4128
4129         /* Allocate PTT pool */
4130         rc = ecore_ptt_pool_alloc(p_hwfn);
4131         if (rc) {
4132                 DP_NOTICE(p_hwfn, false, "Failed to prepare hwfn's hw\n");
4133                 if (p_params->b_relaxed_probe)
4134                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4135                 goto err0;
4136         }
4137
4138         /* Allocate the main PTT */
4139         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4140
4141         /* First hwfn learns basic information, e.g., number of hwfns */
4142         if (!p_hwfn->my_id) {
4143                 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
4144                 if (rc != ECORE_SUCCESS) {
4145                         if (p_params->b_relaxed_probe)
4146                                 p_params->p_relaxed_res =
4147                                         ECORE_HW_PREPARE_FAILED_DEV;
4148                         goto err1;
4149                 }
4150         }
4151
4152         ecore_hw_hwfn_prepare(p_hwfn);
4153
4154         /* Initialize MCP structure */
4155         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4156         if (rc) {
4157                 DP_NOTICE(p_hwfn, false, "Failed initializing mcp command\n");
4158                 if (p_params->b_relaxed_probe)
4159                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4160                 goto err1;
4161         }
4162
4163         /* Read the device configuration information from the HW and SHMEM */
4164         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
4165                                p_params->personality, p_params);
4166         if (rc) {
4167                 DP_NOTICE(p_hwfn, false, "Failed to get HW information\n");
4168                 goto err2;
4169         }
4170
4171         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
4172          * called, since among others it sets the ports number in an engine.
4173          */
4174         if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
4175             !p_dev->recov_in_prog) {
4176                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4177                 if (rc != ECORE_SUCCESS)
4178                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
4179         }
4180
4181         /* Check if mdump logs/data are present and update the epoch value */
4182         if (IS_LEAD_HWFN(p_hwfn)) {
4183 #ifndef ASIC_ONLY
4184                 if (!CHIP_REV_IS_EMUL(p_dev)) {
4185 #endif
4186                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
4187                                               &mdump_info);
4188                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
4189                         DP_NOTICE(p_hwfn, false,
4190                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
4191
4192                 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
4193                                                 &mdump_retain);
4194                 if (rc == ECORE_SUCCESS && mdump_retain.valid)
4195                         DP_NOTICE(p_hwfn, false,
4196                                   "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
4197                                   mdump_retain.epoch, mdump_retain.pf,
4198                                   mdump_retain.status);
4199
4200                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
4201                                            p_params->epoch);
4202 #ifndef ASIC_ONLY
4203                 }
4204 #endif
4205         }
4206
4207         /* Allocate the init RT array and initialize the init-ops engine */
4208         rc = ecore_init_alloc(p_hwfn);
4209         if (rc) {
4210                 DP_NOTICE(p_hwfn, false, "Failed to allocate the init array\n");
4211                 if (p_params->b_relaxed_probe)
4212                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4213                 goto err2;
4214         }
4215 #ifndef ASIC_ONLY
4216         if (CHIP_REV_IS_FPGA(p_dev)) {
4217                 DP_NOTICE(p_hwfn, false,
4218                           "FPGA: workaround; Prevent DMAE parities\n");
4219                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
4220                          7);
4221
4222                 DP_NOTICE(p_hwfn, false,
4223                           "FPGA: workaround: Set VF bar0 size\n");
4224                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4225                          PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
4226         }
4227 #endif
4228
4229         return rc;
4230 err2:
4231         if (IS_LEAD_HWFN(p_hwfn))
4232                 ecore_iov_free_hw_info(p_dev);
4233         ecore_mcp_free(p_hwfn);
4234 err1:
4235         ecore_hw_hwfn_free(p_hwfn);
4236 err0:
4237         return rc;
4238 }
4239
4240 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
4241                                       struct ecore_hw_prepare_params *p_params)
4242 {
4243         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4244         enum _ecore_status_t rc;
4245
4246         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
4247         p_dev->allow_mdump = p_params->allow_mdump;
4248
4249         if (p_params->b_relaxed_probe)
4250                 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
4251
4252         /* Store the precompiled init data ptrs */
4253         if (IS_PF(p_dev))
4254                 ecore_init_iro_array(p_dev);
4255
4256         /* Initialize the first hwfn - will learn number of hwfns */
4257         rc = ecore_hw_prepare_single(p_hwfn,
4258                                      p_dev->regview,
4259                                      p_dev->doorbells, p_params);
4260         if (rc != ECORE_SUCCESS)
4261                 return rc;
4262
4263         p_params->personality = p_hwfn->hw_info.personality;
4264
4265         /* initilalize 2nd hwfn if necessary */
4266         if (ECORE_IS_CMT(p_dev)) {
4267                 void OSAL_IOMEM *p_regview, *p_doorbell;
4268                 u8 OSAL_IOMEM *addr;
4269
4270                 /* adjust bar offset for second engine */
4271                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
4272                                         ecore_hw_bar_size(p_hwfn,
4273                                                           p_hwfn->p_main_ptt,
4274                                                           BAR_ID_0) / 2;
4275                 p_regview = (void OSAL_IOMEM *)addr;
4276
4277                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
4278                                         ecore_hw_bar_size(p_hwfn,
4279                                                           p_hwfn->p_main_ptt,
4280                                                           BAR_ID_1) / 2;
4281                 p_doorbell = (void OSAL_IOMEM *)addr;
4282
4283                 /* prepare second hw function */
4284                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
4285                                              p_doorbell, p_params);
4286
4287                 /* in case of error, need to free the previously
4288                  * initiliazed hwfn 0.
4289                  */
4290                 if (rc != ECORE_SUCCESS) {
4291                         if (p_params->b_relaxed_probe)
4292                                 p_params->p_relaxed_res =
4293                                                 ECORE_HW_PREPARE_FAILED_ENG2;
4294
4295                         if (IS_PF(p_dev)) {
4296                                 ecore_init_free(p_hwfn);
4297                                 ecore_mcp_free(p_hwfn);
4298                                 ecore_hw_hwfn_free(p_hwfn);
4299                         } else {
4300                                 DP_NOTICE(p_dev, false, "What do we need to free when VF hwfn1 init fails\n");
4301                         }
4302                         return rc;
4303                 }
4304         }
4305
4306         return rc;
4307 }
4308
4309 void ecore_hw_remove(struct ecore_dev *p_dev)
4310 {
4311         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4312         int i;
4313
4314         if (IS_PF(p_dev))
4315                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4316                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
4317
4318         for_each_hwfn(p_dev, i) {
4319                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4320
4321                 if (IS_VF(p_dev)) {
4322                         ecore_vf_pf_release(p_hwfn);
4323                         continue;
4324                 }
4325
4326                 ecore_init_free(p_hwfn);
4327                 ecore_hw_hwfn_free(p_hwfn);
4328                 ecore_mcp_free(p_hwfn);
4329
4330 #ifdef CONFIG_ECORE_LOCK_ALLOC
4331                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
4332 #endif
4333         }
4334
4335         ecore_iov_free_hw_info(p_dev);
4336 }
4337
4338 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
4339                                       struct ecore_chain *p_chain)
4340 {
4341         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
4342         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
4343         struct ecore_chain_next *p_next;
4344         u32 size, i;
4345
4346         if (!p_virt)
4347                 return;
4348
4349         size = p_chain->elem_size * p_chain->usable_per_page;
4350
4351         for (i = 0; i < p_chain->page_cnt; i++) {
4352                 if (!p_virt)
4353                         break;
4354
4355                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
4356                 p_virt_next = p_next->next_virt;
4357                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
4358
4359                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
4360                                        ECORE_CHAIN_PAGE_SIZE);
4361
4362                 p_virt = p_virt_next;
4363                 p_phys = p_phys_next;
4364         }
4365 }
4366
4367 static void ecore_chain_free_single(struct ecore_dev *p_dev,
4368                                     struct ecore_chain *p_chain)
4369 {
4370         if (!p_chain->p_virt_addr)
4371                 return;
4372
4373         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
4374                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
4375 }
4376
4377 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
4378                                  struct ecore_chain *p_chain)
4379 {
4380         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
4381         u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
4382         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
4383
4384         if (!pp_virt_addr_tbl)
4385                 return;
4386
4387         if (!p_pbl_virt)
4388                 goto out;
4389
4390         for (i = 0; i < page_cnt; i++) {
4391                 if (!pp_virt_addr_tbl[i])
4392                         break;
4393
4394                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
4395                                        *(dma_addr_t *)p_pbl_virt,
4396                                        ECORE_CHAIN_PAGE_SIZE);
4397
4398                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4399         }
4400
4401         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4402
4403         if (!p_chain->b_external_pbl)
4404                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
4405                                        p_chain->pbl_sp.p_phys_table, pbl_size);
4406 out:
4407         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
4408 }
4409
4410 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4411 {
4412         switch (p_chain->mode) {
4413         case ECORE_CHAIN_MODE_NEXT_PTR:
4414                 ecore_chain_free_next_ptr(p_dev, p_chain);
4415                 break;
4416         case ECORE_CHAIN_MODE_SINGLE:
4417                 ecore_chain_free_single(p_dev, p_chain);
4418                 break;
4419         case ECORE_CHAIN_MODE_PBL:
4420                 ecore_chain_free_pbl(p_dev, p_chain);
4421                 break;
4422         }
4423 }
4424
4425 static enum _ecore_status_t
4426 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
4427                                enum ecore_chain_cnt_type cnt_type,
4428                                osal_size_t elem_size, u32 page_cnt)
4429 {
4430         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
4431
4432         /* The actual chain size can be larger than the maximal possible value
4433          * after rounding up the requested elements number to pages, and after
4434          * taking into acount the unusuable elements (next-ptr elements).
4435          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
4436          * size/capacity fields are of a u32 type.
4437          */
4438         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
4439              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
4440             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
4441              chain_size > ECORE_U32_MAX)) {
4442                 DP_NOTICE(p_dev, true,
4443                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
4444                           (unsigned long)chain_size);
4445                 return ECORE_INVAL;
4446         }
4447
4448         return ECORE_SUCCESS;
4449 }
4450
4451 static enum _ecore_status_t
4452 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4453 {
4454         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
4455         dma_addr_t p_phys = 0;
4456         u32 i;
4457
4458         for (i = 0; i < p_chain->page_cnt; i++) {
4459                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4460                                                  ECORE_CHAIN_PAGE_SIZE);
4461                 if (!p_virt) {
4462                         DP_NOTICE(p_dev, false,
4463                                   "Failed to allocate chain memory\n");
4464                         return ECORE_NOMEM;
4465                 }
4466
4467                 if (i == 0) {
4468                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4469                         ecore_chain_reset(p_chain);
4470                 } else {
4471                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4472                                                        p_virt, p_phys);
4473                 }
4474
4475                 p_virt_prev = p_virt;
4476         }
4477         /* Last page's next element should point to the beginning of the
4478          * chain.
4479          */
4480         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4481                                        p_chain->p_virt_addr,
4482                                        p_chain->p_phys_addr);
4483
4484         return ECORE_SUCCESS;
4485 }
4486
4487 static enum _ecore_status_t
4488 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4489 {
4490         dma_addr_t p_phys = 0;
4491         void *p_virt = OSAL_NULL;
4492
4493         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
4494         if (!p_virt) {
4495                 DP_NOTICE(p_dev, false, "Failed to allocate chain memory\n");
4496                 return ECORE_NOMEM;
4497         }
4498
4499         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4500         ecore_chain_reset(p_chain);
4501
4502         return ECORE_SUCCESS;
4503 }
4504
4505 static enum _ecore_status_t
4506 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
4507                       struct ecore_chain *p_chain,
4508                       struct ecore_chain_ext_pbl *ext_pbl)
4509 {
4510         u32 page_cnt = p_chain->page_cnt, size, i;
4511         dma_addr_t p_phys = 0, p_pbl_phys = 0;
4512         void **pp_virt_addr_tbl = OSAL_NULL;
4513         u8 *p_pbl_virt = OSAL_NULL;
4514         void *p_virt = OSAL_NULL;
4515
4516         size = page_cnt * sizeof(*pp_virt_addr_tbl);
4517         pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
4518         if (!pp_virt_addr_tbl) {
4519                 DP_NOTICE(p_dev, false,
4520                           "Failed to allocate memory for the chain virtual addresses table\n");
4521                 return ECORE_NOMEM;
4522         }
4523
4524         /* The allocation of the PBL table is done with its full size, since it
4525          * is expected to be successive.
4526          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
4527          * failure, since pp_virt_addr_tbl was previously allocated, and it
4528          * should be saved to allow its freeing during the error flow.
4529          */
4530         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4531
4532         if (ext_pbl == OSAL_NULL) {
4533                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
4534         } else {
4535                 p_pbl_virt = ext_pbl->p_pbl_virt;
4536                 p_pbl_phys = ext_pbl->p_pbl_phys;
4537                 p_chain->b_external_pbl = true;
4538         }
4539
4540         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
4541                                  pp_virt_addr_tbl);
4542         if (!p_pbl_virt) {
4543                 DP_NOTICE(p_dev, false, "Failed to allocate chain pbl memory\n");
4544                 return ECORE_NOMEM;
4545         }
4546
4547         for (i = 0; i < page_cnt; i++) {
4548                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4549                                                  ECORE_CHAIN_PAGE_SIZE);
4550                 if (!p_virt) {
4551                         DP_NOTICE(p_dev, false,
4552                                   "Failed to allocate chain memory\n");
4553                         return ECORE_NOMEM;
4554                 }
4555
4556                 if (i == 0) {
4557                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4558                         ecore_chain_reset(p_chain);
4559                 }
4560
4561                 /* Fill the PBL table with the physical address of the page */
4562                 *(dma_addr_t *)p_pbl_virt = p_phys;
4563                 /* Keep the virtual address of the page */
4564                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
4565
4566                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4567         }
4568
4569         return ECORE_SUCCESS;
4570 }
4571
4572 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
4573                                        enum ecore_chain_use_mode intended_use,
4574                                        enum ecore_chain_mode mode,
4575                                        enum ecore_chain_cnt_type cnt_type,
4576                                        u32 num_elems, osal_size_t elem_size,
4577                                        struct ecore_chain *p_chain,
4578                                        struct ecore_chain_ext_pbl *ext_pbl)
4579 {
4580         u32 page_cnt;
4581         enum _ecore_status_t rc = ECORE_SUCCESS;
4582
4583         if (mode == ECORE_CHAIN_MODE_SINGLE)
4584                 page_cnt = 1;
4585         else
4586                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4587
4588         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
4589                                             page_cnt);
4590         if (rc) {
4591                 DP_NOTICE(p_dev, false,
4592                           "Cannot allocate a chain with the given arguments:\n"
4593                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4594                           intended_use, mode, cnt_type, num_elems, elem_size);
4595                 return rc;
4596         }
4597
4598         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
4599                                 mode, cnt_type, p_dev->dp_ctx);
4600
4601         switch (mode) {
4602         case ECORE_CHAIN_MODE_NEXT_PTR:
4603                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
4604                 break;
4605         case ECORE_CHAIN_MODE_SINGLE:
4606                 rc = ecore_chain_alloc_single(p_dev, p_chain);
4607                 break;
4608         case ECORE_CHAIN_MODE_PBL:
4609                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
4610                 break;
4611         }
4612         if (rc)
4613                 goto nomem;
4614
4615         return ECORE_SUCCESS;
4616
4617 nomem:
4618         ecore_chain_free(p_dev, p_chain);
4619         return rc;
4620 }
4621
4622 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
4623                                        u16 src_id, u16 *dst_id)
4624 {
4625         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
4626                 u16 min, max;
4627
4628                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
4629                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
4630                 DP_NOTICE(p_hwfn, true,
4631                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4632                           src_id, min, max);
4633
4634                 return ECORE_INVAL;
4635         }
4636
4637         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
4638
4639         return ECORE_SUCCESS;
4640 }
4641
4642 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
4643                                     u8 src_id, u8 *dst_id)
4644 {
4645         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
4646                 u8 min, max;
4647
4648                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
4649                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
4650                 DP_NOTICE(p_hwfn, true,
4651                           "vport id [%d] is not valid, available indices [%d - %d]\n",
4652                           src_id, min, max);
4653
4654                 return ECORE_INVAL;
4655         }
4656
4657         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
4658
4659         return ECORE_SUCCESS;
4660 }
4661
4662 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
4663                                       u8 src_id, u8 *dst_id)
4664 {
4665         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
4666                 u8 min, max;
4667
4668                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
4669                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
4670                 DP_NOTICE(p_hwfn, true,
4671                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4672                           src_id, min, max);
4673
4674                 return ECORE_INVAL;
4675         }
4676
4677         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
4678
4679         return ECORE_SUCCESS;
4680 }
4681
4682 static enum _ecore_status_t
4683 ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4684                                struct ecore_ptt *p_ptt, u32 high, u32 low,
4685                                u32 *p_entry_num)
4686 {
4687         u32 en;
4688         int i;
4689
4690         /* Find a free entry and utilize it */
4691         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4692                 en = ecore_rd(p_hwfn, p_ptt,
4693                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4694                               i * sizeof(u32));
4695                 if (en)
4696                         continue;
4697                 ecore_wr(p_hwfn, p_ptt,
4698                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4699                          2 * i * sizeof(u32), low);
4700                 ecore_wr(p_hwfn, p_ptt,
4701                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4702                          (2 * i + 1) * sizeof(u32), high);
4703                 ecore_wr(p_hwfn, p_ptt,
4704                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4705                          i * sizeof(u32), 0);
4706                 ecore_wr(p_hwfn, p_ptt,
4707                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4708                          i * sizeof(u32), 0);
4709                 ecore_wr(p_hwfn, p_ptt,
4710                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4711                          i * sizeof(u32), 1);
4712                 break;
4713         }
4714
4715         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4716                 return ECORE_NORESOURCES;
4717
4718         *p_entry_num = i;
4719
4720         return ECORE_SUCCESS;
4721 }
4722
4723 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4724                                           struct ecore_ptt *p_ptt, u8 *p_filter)
4725 {
4726         u32 high, low, entry_num;
4727         enum _ecore_status_t rc = ECORE_SUCCESS;
4728
4729         if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4730                            &p_hwfn->p_dev->mf_bits))
4731                 return ECORE_SUCCESS;
4732
4733         high = p_filter[1] | (p_filter[0] << 8);
4734         low = p_filter[5] | (p_filter[4] << 8) |
4735               (p_filter[3] << 16) | (p_filter[2] << 24);
4736
4737         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4738                 rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low,
4739                                                     &entry_num);
4740         if (rc != ECORE_SUCCESS) {
4741                 DP_NOTICE(p_hwfn, false,
4742                           "Failed to find an empty LLH filter to utilize\n");
4743                 return rc;
4744         }
4745
4746         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4747                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n",
4748                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4749                    p_filter[4], p_filter[5], entry_num);
4750
4751         return rc;
4752 }
4753
4754 static enum _ecore_status_t
4755 ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4756                                   struct ecore_ptt *p_ptt, u32 high, u32 low,
4757                                   u32 *p_entry_num)
4758 {
4759         int i;
4760
4761         /* Find the entry and clean it */
4762         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4763                 if (ecore_rd(p_hwfn, p_ptt,
4764                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4765                              2 * i * sizeof(u32)) != low)
4766                         continue;
4767                 if (ecore_rd(p_hwfn, p_ptt,
4768                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4769                              (2 * i + 1) * sizeof(u32)) != high)
4770                         continue;
4771
4772                 ecore_wr(p_hwfn, p_ptt,
4773                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4774                 ecore_wr(p_hwfn, p_ptt,
4775                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4776                          2 * i * sizeof(u32), 0);
4777                 ecore_wr(p_hwfn, p_ptt,
4778                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4779                          (2 * i + 1) * sizeof(u32), 0);
4780                 break;
4781         }
4782
4783         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4784                 return ECORE_INVAL;
4785
4786         *p_entry_num = i;
4787
4788         return ECORE_SUCCESS;
4789 }
4790
4791 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4792                              struct ecore_ptt *p_ptt, u8 *p_filter)
4793 {
4794         u32 high, low, entry_num;
4795         enum _ecore_status_t rc = ECORE_SUCCESS;
4796
4797         if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4798                            &p_hwfn->p_dev->mf_bits))
4799                 return;
4800
4801         high = p_filter[1] | (p_filter[0] << 8);
4802         low = p_filter[5] | (p_filter[4] << 8) |
4803               (p_filter[3] << 16) | (p_filter[2] << 24);
4804
4805         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4806                 rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high,
4807                                                        low, &entry_num);
4808         if (rc != ECORE_SUCCESS) {
4809                 DP_NOTICE(p_hwfn, false,
4810                           "Tried to remove a non-configured filter\n");
4811                 return;
4812         }
4813
4814
4815         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4816                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n",
4817                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4818                    p_filter[4], p_filter[5], entry_num);
4819 }
4820
4821 static enum _ecore_status_t
4822 ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4823                                     struct ecore_ptt *p_ptt,
4824                                     enum ecore_llh_port_filter_type_t type,
4825                                     u32 high, u32 low, u32 *p_entry_num)
4826 {
4827         u32 en;
4828         int i;
4829
4830         /* Find a free entry and utilize it */
4831         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4832                 en = ecore_rd(p_hwfn, p_ptt,
4833                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4834                               i * sizeof(u32));
4835                 if (en)
4836                         continue;
4837                 ecore_wr(p_hwfn, p_ptt,
4838                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4839                          2 * i * sizeof(u32), low);
4840                 ecore_wr(p_hwfn, p_ptt,
4841                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4842                          (2 * i + 1) * sizeof(u32), high);
4843                 ecore_wr(p_hwfn, p_ptt,
4844                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4845                          i * sizeof(u32), 1);
4846                 ecore_wr(p_hwfn, p_ptt,
4847                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4848                          i * sizeof(u32), 1 << type);
4849                 ecore_wr(p_hwfn, p_ptt,
4850                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1);
4851                 break;
4852         }
4853
4854         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4855                 return ECORE_NORESOURCES;
4856
4857         *p_entry_num = i;
4858
4859         return ECORE_SUCCESS;
4860 }
4861
4862 enum _ecore_status_t
4863 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4864                               struct ecore_ptt *p_ptt,
4865                               u16 source_port_or_eth_type,
4866                               u16 dest_port,
4867                               enum ecore_llh_port_filter_type_t type)
4868 {
4869         u32 high, low, entry_num;
4870         enum _ecore_status_t rc = ECORE_SUCCESS;
4871
4872         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
4873                            &p_hwfn->p_dev->mf_bits))
4874                 return rc;
4875
4876         high = 0;
4877         low = 0;
4878
4879         switch (type) {
4880         case ECORE_LLH_FILTER_ETHERTYPE:
4881                 high = source_port_or_eth_type;
4882                 break;
4883         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4884         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4885                 low = source_port_or_eth_type << 16;
4886                 break;
4887         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4888         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4889                 low = dest_port;
4890                 break;
4891         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4892         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4893                 low = (source_port_or_eth_type << 16) | dest_port;
4894                 break;
4895         default:
4896                 DP_NOTICE(p_hwfn, true,
4897                           "Non valid LLH protocol filter type %d\n", type);
4898                 return ECORE_INVAL;
4899         }
4900
4901         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4902                 rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4903                                                          high, low, &entry_num);
4904         if (rc != ECORE_SUCCESS) {
4905                 DP_NOTICE(p_hwfn, false,
4906                           "Failed to find an empty LLH filter to utilize\n");
4907                 return rc;
4908         }
4909         switch (type) {
4910         case ECORE_LLH_FILTER_ETHERTYPE:
4911                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4912                            "ETH type %x is added at %d\n",
4913                            source_port_or_eth_type, entry_num);
4914                 break;
4915         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4916                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4917                            "TCP src port %x is added at %d\n",
4918                            source_port_or_eth_type, entry_num);
4919                 break;
4920         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4921                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4922                            "UDP src port %x is added at %d\n",
4923                            source_port_or_eth_type, entry_num);
4924                 break;
4925         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4926                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4927                            "TCP dst port %x is added at %d\n", dest_port,
4928                            entry_num);
4929                 break;
4930         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4931                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4932                            "UDP dst port %x is added at %d\n", dest_port,
4933                            entry_num);
4934                 break;
4935         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4936                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4937                            "TCP src/dst ports %x/%x are added at %d\n",
4938                            source_port_or_eth_type, dest_port, entry_num);
4939                 break;
4940         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4941                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4942                            "UDP src/dst ports %x/%x are added at %d\n",
4943                            source_port_or_eth_type, dest_port, entry_num);
4944                 break;
4945         }
4946
4947         return rc;
4948 }
4949
4950 static enum _ecore_status_t
4951 ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4952                                        struct ecore_ptt *p_ptt,
4953                                        enum ecore_llh_port_filter_type_t type,
4954                                        u32 high, u32 low, u32 *p_entry_num)
4955 {
4956         int i;
4957
4958         /* Find the entry and clean it */
4959         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4960                 if (!ecore_rd(p_hwfn, p_ptt,
4961                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4962                               i * sizeof(u32)))
4963                         continue;
4964                 if (!ecore_rd(p_hwfn, p_ptt,
4965                               NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4966                               i * sizeof(u32)))
4967                         continue;
4968                 if (!(ecore_rd(p_hwfn, p_ptt,
4969                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4970                                i * sizeof(u32)) & (1 << type)))
4971                         continue;
4972                 if (ecore_rd(p_hwfn, p_ptt,
4973                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4974                              2 * i * sizeof(u32)) != low)
4975                         continue;
4976                 if (ecore_rd(p_hwfn, p_ptt,
4977                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4978                              (2 * i + 1) * sizeof(u32)) != high)
4979                         continue;
4980
4981                 ecore_wr(p_hwfn, p_ptt,
4982                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4983                 ecore_wr(p_hwfn, p_ptt,
4984                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4985                          i * sizeof(u32), 0);
4986                 ecore_wr(p_hwfn, p_ptt,
4987                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4988                          i * sizeof(u32), 0);
4989                 ecore_wr(p_hwfn, p_ptt,
4990                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4991                          2 * i * sizeof(u32), 0);
4992                 ecore_wr(p_hwfn, p_ptt,
4993                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4994                          (2 * i + 1) * sizeof(u32), 0);
4995                 break;
4996         }
4997
4998         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4999                 return ECORE_INVAL;
5000
5001         *p_entry_num = i;
5002
5003         return ECORE_SUCCESS;
5004 }
5005
5006 void
5007 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
5008                                  struct ecore_ptt *p_ptt,
5009                                  u16 source_port_or_eth_type,
5010                                  u16 dest_port,
5011                                  enum ecore_llh_port_filter_type_t type)
5012 {
5013         u32 high, low, entry_num;
5014         enum _ecore_status_t rc = ECORE_SUCCESS;
5015
5016         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
5017                            &p_hwfn->p_dev->mf_bits))
5018                 return;
5019
5020         high = 0;
5021         low = 0;
5022
5023         switch (type) {
5024         case ECORE_LLH_FILTER_ETHERTYPE:
5025                 high = source_port_or_eth_type;
5026                 break;
5027         case ECORE_LLH_FILTER_TCP_SRC_PORT:
5028         case ECORE_LLH_FILTER_UDP_SRC_PORT:
5029                 low = source_port_or_eth_type << 16;
5030                 break;
5031         case ECORE_LLH_FILTER_TCP_DEST_PORT:
5032         case ECORE_LLH_FILTER_UDP_DEST_PORT:
5033                 low = dest_port;
5034                 break;
5035         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
5036         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
5037                 low = (source_port_or_eth_type << 16) | dest_port;
5038                 break;
5039         default:
5040                 DP_NOTICE(p_hwfn, true,
5041                           "Non valid LLH protocol filter type %d\n", type);
5042                 return;
5043         }
5044
5045         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5046                 rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
5047                                                             high, low,
5048                                                             &entry_num);
5049         if (rc != ECORE_SUCCESS) {
5050                 DP_NOTICE(p_hwfn, false,
5051                           "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n",
5052                           type, source_port_or_eth_type, dest_port);
5053                 return;
5054         }
5055
5056         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
5057                    "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n",
5058                    type, source_port_or_eth_type, dest_port, entry_num);
5059 }
5060
5061 static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn,
5062                                               struct ecore_ptt *p_ptt)
5063 {
5064         int i;
5065
5066         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
5067                 return;
5068
5069         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
5070                 ecore_wr(p_hwfn, p_ptt,
5071                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2  +
5072                          i * sizeof(u32), 0);
5073                 ecore_wr(p_hwfn, p_ptt,
5074                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5075                          2 * i * sizeof(u32), 0);
5076                 ecore_wr(p_hwfn, p_ptt,
5077                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
5078                          (2 * i + 1) * sizeof(u32), 0);
5079         }
5080 }
5081
5082 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
5083                              struct ecore_ptt *p_ptt)
5084 {
5085         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
5086                            &p_hwfn->p_dev->mf_bits) &&
5087             !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
5088                            &p_hwfn->p_dev->mf_bits))
5089                 return;
5090
5091         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5092                 ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt);
5093 }
5094
5095 enum _ecore_status_t
5096 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
5097                                   struct ecore_ptt *p_ptt)
5098 {
5099         if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
5100                 ecore_wr(p_hwfn, p_ptt,
5101                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
5102                          1 << p_hwfn->abs_pf_id / 2);
5103                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
5104                 return ECORE_SUCCESS;
5105         }
5106
5107         DP_NOTICE(p_hwfn, false,
5108                   "This function can't be set as default\n");
5109         return ECORE_INVAL;
5110 }
5111
5112 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
5113                                                struct ecore_ptt *p_ptt,
5114                                                u32 hw_addr, void *p_eth_qzone,
5115                                                osal_size_t eth_qzone_size,
5116                                                u8 timeset)
5117 {
5118         struct coalescing_timeset *p_coal_timeset;
5119
5120         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
5121                 DP_NOTICE(p_hwfn, true,
5122                           "Coalescing configuration not enabled\n");
5123                 return ECORE_INVAL;
5124         }
5125
5126         p_coal_timeset = p_eth_qzone;
5127         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
5128         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
5129         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
5130         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
5131
5132         return ECORE_SUCCESS;
5133 }
5134
5135 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
5136                                               u16 rx_coal, u16 tx_coal,
5137                                               void *p_handle)
5138 {
5139         struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
5140         enum _ecore_status_t rc = ECORE_SUCCESS;
5141         struct ecore_ptt *p_ptt;
5142
5143         /* TODO - Configuring a single queue's coalescing but
5144          * claiming all queues are abiding same configuration
5145          * for PF and VF both.
5146          */
5147
5148         if (IS_VF(p_hwfn->p_dev))
5149                 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
5150                                                 tx_coal, p_cid);
5151
5152         p_ptt = ecore_ptt_acquire(p_hwfn);
5153         if (!p_ptt)
5154                 return ECORE_AGAIN;
5155
5156         if (rx_coal) {
5157                 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
5158                 if (rc)
5159                         goto out;
5160                 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
5161         }
5162
5163         if (tx_coal) {
5164                 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
5165                 if (rc)
5166                         goto out;
5167                 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
5168         }
5169 out:
5170         ecore_ptt_release(p_hwfn, p_ptt);
5171
5172         return rc;
5173 }
5174
5175 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
5176                                             struct ecore_ptt *p_ptt,
5177                                             u16 coalesce,
5178                                             struct ecore_queue_cid *p_cid)
5179 {
5180         struct ustorm_eth_queue_zone eth_qzone;
5181         u8 timeset, timer_res;
5182         u32 address;
5183         enum _ecore_status_t rc;
5184
5185         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5186         if (coalesce <= 0x7F) {
5187                 timer_res = 0;
5188         } else if (coalesce <= 0xFF) {
5189                 timer_res = 1;
5190         } else if (coalesce <= 0x1FF) {
5191                 timer_res = 2;
5192         } else {
5193                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5194                 return ECORE_INVAL;
5195         }
5196         timeset = (u8)(coalesce >> timer_res);
5197
5198         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5199                                      p_cid->sb_igu_id, false);
5200         if (rc != ECORE_SUCCESS)
5201                 goto out;
5202
5203         address = BAR0_MAP_REG_USDM_RAM +
5204                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5205
5206         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5207                                 sizeof(struct ustorm_eth_queue_zone), timeset);
5208         if (rc != ECORE_SUCCESS)
5209                 goto out;
5210
5211 out:
5212         return rc;
5213 }
5214
5215 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
5216                                             struct ecore_ptt *p_ptt,
5217                                             u16 coalesce,
5218                                             struct ecore_queue_cid *p_cid)
5219 {
5220         struct xstorm_eth_queue_zone eth_qzone;
5221         u8 timeset, timer_res;
5222         u32 address;
5223         enum _ecore_status_t rc;
5224
5225         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5226         if (coalesce <= 0x7F) {
5227                 timer_res = 0;
5228         } else if (coalesce <= 0xFF) {
5229                 timer_res = 1;
5230         } else if (coalesce <= 0x1FF) {
5231                 timer_res = 2;
5232         } else {
5233                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5234                 return ECORE_INVAL;
5235         }
5236
5237         timeset = (u8)(coalesce >> timer_res);
5238
5239         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5240                                      p_cid->sb_igu_id, true);
5241         if (rc != ECORE_SUCCESS)
5242                 goto out;
5243
5244         address = BAR0_MAP_REG_XSDM_RAM +
5245                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5246
5247         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5248                                 sizeof(struct xstorm_eth_queue_zone), timeset);
5249 out:
5250         return rc;
5251 }
5252
5253 /* Calculate final WFQ values for all vports and configure it.
5254  * After this configuration each vport must have
5255  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
5256  */
5257 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5258                                                struct ecore_ptt *p_ptt,
5259                                                u32 min_pf_rate)
5260 {
5261         struct init_qm_vport_params *vport_params;
5262         int i;
5263
5264         vport_params = p_hwfn->qm_info.qm_vport_params;
5265
5266         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5267                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5268
5269                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
5270                     min_pf_rate;
5271                 ecore_init_vport_wfq(p_hwfn, p_ptt,
5272                                      vport_params[i].first_tx_pq_id,
5273                                      vport_params[i].vport_wfq);
5274         }
5275 }
5276
5277 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn)
5278 {
5279         int i;
5280
5281         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5282                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
5283 }
5284
5285 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5286                                              struct ecore_ptt *p_ptt)
5287 {
5288         struct init_qm_vport_params *vport_params;
5289         int i;
5290
5291         vport_params = p_hwfn->qm_info.qm_vport_params;
5292
5293         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5294                 ecore_init_wfq_default_param(p_hwfn);
5295                 ecore_init_vport_wfq(p_hwfn, p_ptt,
5296                                      vport_params[i].first_tx_pq_id,
5297                                      vport_params[i].vport_wfq);
5298         }
5299 }
5300
5301 /* This function performs several validations for WFQ
5302  * configuration and required min rate for a given vport
5303  * 1. req_rate must be greater than one percent of min_pf_rate.
5304  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
5305  *    rates to get less than one percent of min_pf_rate.
5306  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
5307  */
5308 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
5309                                                  u16 vport_id, u32 req_rate,
5310                                                  u32 min_pf_rate)
5311 {
5312         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
5313         int non_requested_count = 0, req_count = 0, i, num_vports;
5314
5315         num_vports = p_hwfn->qm_info.num_vports;
5316
5317 /* Accounting for the vports which are configured for WFQ explicitly */
5318
5319         for (i = 0; i < num_vports; i++) {
5320                 u32 tmp_speed;
5321
5322                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
5323                         req_count++;
5324                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5325                         total_req_min_rate += tmp_speed;
5326                 }
5327         }
5328
5329         /* Include current vport data as well */
5330         req_count++;
5331         total_req_min_rate += req_rate;
5332         non_requested_count = num_vports - req_count;
5333
5334         /* validate possible error cases */
5335         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
5336                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5337                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5338                            vport_id, req_rate, min_pf_rate);
5339                 return ECORE_INVAL;
5340         }
5341
5342         /* TBD - for number of vports greater than 100 */
5343         if (num_vports > ECORE_WFQ_UNIT) {
5344                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5345                            "Number of vports is greater than %d\n",
5346                            ECORE_WFQ_UNIT);
5347                 return ECORE_INVAL;
5348         }
5349
5350         if (total_req_min_rate > min_pf_rate) {
5351                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5352                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5353                            total_req_min_rate, min_pf_rate);
5354                 return ECORE_INVAL;
5355         }
5356
5357         /* Data left for non requested vports */
5358         total_left_rate = min_pf_rate - total_req_min_rate;
5359         left_rate_per_vp = total_left_rate / non_requested_count;
5360
5361         /* validate if non requested get < 1% of min bw */
5362         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
5363                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5364                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5365                            left_rate_per_vp, min_pf_rate);
5366                 return ECORE_INVAL;
5367         }
5368
5369         /* now req_rate for given vport passes all scenarios.
5370          * assign final wfq rates to all vports.
5371          */
5372         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5373         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5374
5375         for (i = 0; i < num_vports; i++) {
5376                 if (p_hwfn->qm_info.wfq_data[i].configured)
5377                         continue;
5378
5379                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5380         }
5381
5382         return ECORE_SUCCESS;
5383 }
5384
5385 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
5386                                        struct ecore_ptt *p_ptt,
5387                                        u16 vp_id, u32 rate)
5388 {
5389         struct ecore_mcp_link_state *p_link;
5390         int rc = ECORE_SUCCESS;
5391
5392         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
5393
5394         if (!p_link->min_pf_rate) {
5395                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5396                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5397                 return rc;
5398         }
5399
5400         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5401
5402         if (rc == ECORE_SUCCESS)
5403                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5404                                                    p_link->min_pf_rate);
5405         else
5406                 DP_NOTICE(p_hwfn, false,
5407                           "Validation failed while configuring min rate\n");
5408
5409         return rc;
5410 }
5411
5412 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
5413                                                    struct ecore_ptt *p_ptt,
5414                                                    u32 min_pf_rate)
5415 {
5416         bool use_wfq = false;
5417         int rc = ECORE_SUCCESS;
5418         u16 i;
5419
5420         /* Validate all pre configured vports for wfq */
5421         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5422                 u32 rate;
5423
5424                 if (!p_hwfn->qm_info.wfq_data[i].configured)
5425                         continue;
5426
5427                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5428                 use_wfq = true;
5429
5430                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5431                 if (rc != ECORE_SUCCESS) {
5432                         DP_NOTICE(p_hwfn, false,
5433                                   "WFQ validation failed while configuring min rate\n");
5434                         break;
5435                 }
5436         }
5437
5438         if (rc == ECORE_SUCCESS && use_wfq)
5439                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5440         else
5441                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5442
5443         return rc;
5444 }
5445
5446 /* Main API for ecore clients to configure vport min rate.
5447  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5448  * rate - Speed in Mbps needs to be assigned to a given vport.
5449  */
5450 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
5451 {
5452         int i, rc = ECORE_INVAL;
5453
5454         /* TBD - for multiple hardware functions - that is 100 gig */
5455         if (ECORE_IS_CMT(p_dev)) {
5456                 DP_NOTICE(p_dev, false,
5457                           "WFQ configuration is not supported for this device\n");
5458                 return rc;
5459         }
5460
5461         for_each_hwfn(p_dev, i) {
5462                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5463                 struct ecore_ptt *p_ptt;
5464
5465                 p_ptt = ecore_ptt_acquire(p_hwfn);
5466                 if (!p_ptt)
5467                         return ECORE_TIMEOUT;
5468
5469                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5470
5471                 if (rc != ECORE_SUCCESS) {
5472                         ecore_ptt_release(p_hwfn, p_ptt);
5473                         return rc;
5474                 }
5475
5476                 ecore_ptt_release(p_hwfn, p_ptt);
5477         }
5478
5479         return rc;
5480 }
5481
5482 /* API to configure WFQ from mcp link change */
5483 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
5484                                            struct ecore_ptt *p_ptt,
5485                                            u32 min_pf_rate)
5486 {
5487         int i;
5488
5489         /* TBD - for multiple hardware functions - that is 100 gig */
5490         if (ECORE_IS_CMT(p_dev)) {
5491                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
5492                            "WFQ configuration is not supported for this device\n");
5493                 return;
5494         }
5495
5496         for_each_hwfn(p_dev, i) {
5497                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5498
5499                 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5500                                                         min_pf_rate);
5501         }
5502 }
5503
5504 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
5505                                        struct ecore_ptt *p_ptt,
5506                                        struct ecore_mcp_link_state *p_link,
5507                                        u8 max_bw)
5508 {
5509         int rc = ECORE_SUCCESS;
5510
5511         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5512
5513         if (!p_link->line_speed && (max_bw != 100))
5514                 return rc;
5515
5516         p_link->speed = (p_link->line_speed * max_bw) / 100;
5517         p_hwfn->qm_info.pf_rl = p_link->speed;
5518
5519         /* Since the limiter also affects Tx-switched traffic, we don't want it
5520          * to limit such traffic in case there's no actual limit.
5521          * In that case, set limit to imaginary high boundary.
5522          */
5523         if (max_bw == 100)
5524                 p_hwfn->qm_info.pf_rl = 100000;
5525
5526         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5527                               p_hwfn->qm_info.pf_rl);
5528
5529         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5530                    "Configured MAX bandwidth to be %08x Mb/sec\n",
5531                    p_link->speed);
5532
5533         return rc;
5534 }
5535
5536 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5537 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
5538 {
5539         int i, rc = ECORE_INVAL;
5540
5541         if (max_bw < 1 || max_bw > 100) {
5542                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
5543                 return rc;
5544         }
5545
5546         for_each_hwfn(p_dev, i) {
5547                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5548                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5549                 struct ecore_mcp_link_state *p_link;
5550                 struct ecore_ptt *p_ptt;
5551
5552                 p_link = &p_lead->mcp_info->link_output;
5553
5554                 p_ptt = ecore_ptt_acquire(p_hwfn);
5555                 if (!p_ptt)
5556                         return ECORE_TIMEOUT;
5557
5558                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5559                                                         p_link, max_bw);
5560
5561                 ecore_ptt_release(p_hwfn, p_ptt);
5562
5563                 if (rc != ECORE_SUCCESS)
5564                         break;
5565         }
5566
5567         return rc;
5568 }
5569
5570 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
5571                                        struct ecore_ptt *p_ptt,
5572                                        struct ecore_mcp_link_state *p_link,
5573                                        u8 min_bw)
5574 {
5575         int rc = ECORE_SUCCESS;
5576
5577         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5578         p_hwfn->qm_info.pf_wfq = min_bw;
5579
5580         if (!p_link->line_speed)
5581                 return rc;
5582
5583         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5584
5585         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5586
5587         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5588                    "Configured MIN bandwidth to be %d Mb/sec\n",
5589                    p_link->min_pf_rate);
5590
5591         return rc;
5592 }
5593
5594 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5595 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
5596 {
5597         int i, rc = ECORE_INVAL;
5598
5599         if (min_bw < 1 || min_bw > 100) {
5600                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
5601                 return rc;
5602         }
5603
5604         for_each_hwfn(p_dev, i) {
5605                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5606                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5607                 struct ecore_mcp_link_state *p_link;
5608                 struct ecore_ptt *p_ptt;
5609
5610                 p_link = &p_lead->mcp_info->link_output;
5611
5612                 p_ptt = ecore_ptt_acquire(p_hwfn);
5613                 if (!p_ptt)
5614                         return ECORE_TIMEOUT;
5615
5616                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5617                                                         p_link, min_bw);
5618                 if (rc != ECORE_SUCCESS) {
5619                         ecore_ptt_release(p_hwfn, p_ptt);
5620                         return rc;
5621                 }
5622
5623                 if (p_link->min_pf_rate) {
5624                         u32 min_rate = p_link->min_pf_rate;
5625
5626                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
5627                                                                      p_ptt,
5628                                                                      min_rate);
5629                 }
5630
5631                 ecore_ptt_release(p_hwfn, p_ptt);
5632         }
5633
5634         return rc;
5635 }
5636
5637 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
5638 {
5639         struct ecore_mcp_link_state *p_link;
5640
5641         p_link = &p_hwfn->mcp_info->link_output;
5642
5643         if (p_link->min_pf_rate)
5644                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5645
5646         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
5647                     sizeof(*p_hwfn->qm_info.wfq_data) *
5648                     p_hwfn->qm_info.num_vports);
5649 }
5650
5651 int ecore_device_num_engines(struct ecore_dev *p_dev)
5652 {
5653         return ECORE_IS_BB(p_dev) ? 2 : 1;
5654 }
5655
5656 int ecore_device_num_ports(struct ecore_dev *p_dev)
5657 {
5658         return p_dev->num_ports;
5659 }
5660
5661 void ecore_set_fw_mac_addr(__le16 *fw_msb,
5662                           __le16 *fw_mid,
5663                           __le16 *fw_lsb,
5664                           u8 *mac)
5665 {
5666         ((u8 *)fw_msb)[0] = mac[1];
5667         ((u8 *)fw_msb)[1] = mac[0];
5668         ((u8 *)fw_mid)[0] = mac[3];
5669         ((u8 *)fw_mid)[1] = mac[2];
5670         ((u8 *)fw_lsb)[0] = mac[5];
5671         ((u8 *)fw_lsb)[1] = mac[4];
5672 }