2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_gtt_reg_addr.h"
13 #include "ecore_chain.h"
14 #include "ecore_status.h"
16 #include "ecore_rt_defs.h"
17 #include "ecore_init_ops.h"
18 #include "ecore_int.h"
19 #include "ecore_cxt.h"
20 #include "ecore_spq.h"
21 #include "ecore_init_fw_funcs.h"
22 #include "ecore_sp_commands.h"
23 #include "ecore_dev_api.h"
24 #include "ecore_sriov.h"
26 #include "ecore_mcp.h"
27 #include "ecore_hw_defs.h"
28 #include "mcp_public.h"
29 #include "ecore_iro.h"
31 #include "ecore_dev_api.h"
32 #include "ecore_dcbx.h"
35 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
36 * registers involved are not split and thus configuration is a race where
37 * some of the PFs configuration might be lost.
38 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
39 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
40 * there's more than a single compiled ecore component in system].
42 static osal_spinlock_t qm_lock;
43 static bool qm_lock_init;
46 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to
47 * load the driver. The number was
52 #define ECORE_MIN_PWM_REGION ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
55 BAR_ID_0, /* used for GRC */
56 BAR_ID_1 /* Used for doorbells */
59 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
61 u32 bar_reg = (bar_id == BAR_ID_0 ?
62 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
65 if (IS_VF(p_hwfn->p_dev)) {
66 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
67 * read from actual register, but we're currently not using
68 * it for actual doorbelling.
73 val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
75 return 1 << (val + 15);
77 /* The above registers were updated in the past only in CMT mode. Since
78 * they were found to be useful MFW started updating them from 8.7.7.0.
79 * In older MFW versions they are set to 0 which means disabled.
81 if (p_hwfn->p_dev->num_hwfns > 1) {
82 DP_NOTICE(p_hwfn, false,
83 "BAR size not configured. Assuming BAR size of 256kB"
84 " for GRC and 512kB for DB\n");
85 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
87 DP_NOTICE(p_hwfn, false,
88 "BAR size not configured. Assuming BAR size of 512kB"
89 " for GRC and 512kB for DB\n");
96 void ecore_init_dp(struct ecore_dev *p_dev,
97 u32 dp_module, u8 dp_level, void *dp_ctx)
101 p_dev->dp_level = dp_level;
102 p_dev->dp_module = dp_module;
103 p_dev->dp_ctx = dp_ctx;
104 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
105 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
107 p_hwfn->dp_level = dp_level;
108 p_hwfn->dp_module = dp_module;
109 p_hwfn->dp_ctx = dp_ctx;
113 void ecore_init_struct(struct ecore_dev *p_dev)
117 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
118 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
120 p_hwfn->p_dev = p_dev;
122 p_hwfn->b_active = false;
124 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
125 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
128 /* hwfn 0 is always active */
129 p_dev->hwfns[0].b_active = true;
131 /* set the default cache alignment to 128 (may be overridden later) */
132 p_dev->cache_shift = 7;
135 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
137 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
139 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
140 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
141 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
142 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
145 void ecore_resc_free(struct ecore_dev *p_dev)
150 for_each_hwfn(p_dev, i)
151 ecore_l2_free(&p_dev->hwfns[i]);
155 OSAL_FREE(p_dev, p_dev->fw_data);
157 OSAL_FREE(p_dev, p_dev->reset_stats);
159 for_each_hwfn(p_dev, i) {
160 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
162 ecore_cxt_mngr_free(p_hwfn);
163 ecore_qm_info_free(p_hwfn);
164 ecore_spq_free(p_hwfn);
165 ecore_eq_free(p_hwfn);
166 ecore_consq_free(p_hwfn);
167 ecore_int_free(p_hwfn);
168 ecore_iov_free(p_hwfn);
169 ecore_l2_free(p_hwfn);
170 ecore_dmae_info_free(p_hwfn);
171 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
172 /* @@@TBD Flush work-queue ? */
176 /******************** QM initialization *******************/
178 /* bitmaps for indicating active traffic classes.
179 * Special case for Arrowhead 4 port
181 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
182 #define ACTIVE_TCS_BMAP 0x9f
183 /* 0..3 actually used, OOO and high priority stuff all use 3 */
184 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
186 /* determines the physical queue flags for a given PF. */
187 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
195 if (IS_ECORE_SRIOV(p_hwfn->p_dev))
196 flags |= PQ_FLAGS_VFS;
199 switch (p_hwfn->hw_info.personality) {
201 flags |= PQ_FLAGS_MCOS;
204 flags |= PQ_FLAGS_OFLD;
206 case ECORE_PCI_ISCSI:
207 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
209 case ECORE_PCI_ETH_ROCE:
210 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
212 case ECORE_PCI_ETH_IWARP:
213 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
217 DP_ERR(p_hwfn, "unknown personality %d\n",
218 p_hwfn->hw_info.personality);
224 /* Getters for resource amounts necessary for qm initialization */
225 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
227 return p_hwfn->hw_info.num_hw_tc;
230 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
232 return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
233 p_hwfn->p_dev->p_iov_info->total_vfs : 0;
236 #define NUM_DEFAULT_RLS 1
238 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
240 u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
243 /* num RLs can't exceed resource amount of rls or vports or the
246 num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
247 (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
249 /* make sure after we reserve the default and VF rls we'll have
252 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
253 DP_NOTICE(p_hwfn, false,
254 "no rate limiters left for PF rate limiting"
255 " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
259 /* subtract rls necessary for VFs and one default one for the PF */
260 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
265 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
267 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
269 /* all pqs share the same vport (hence the 1 below), except for vfs
272 return (!!(PQ_FLAGS_RLS & pq_flags)) *
273 ecore_init_qm_get_num_pf_rls(p_hwfn) +
274 (!!(PQ_FLAGS_VFS & pq_flags)) *
275 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
278 /* calc amount of PQs according to the requested flags */
279 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
281 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
283 return (!!(PQ_FLAGS_RLS & pq_flags)) *
284 ecore_init_qm_get_num_pf_rls(p_hwfn) +
285 (!!(PQ_FLAGS_MCOS & pq_flags)) *
286 ecore_init_qm_get_num_tcs(p_hwfn) +
287 (!!(PQ_FLAGS_LB & pq_flags)) +
288 (!!(PQ_FLAGS_OOO & pq_flags)) +
289 (!!(PQ_FLAGS_ACK & pq_flags)) +
290 (!!(PQ_FLAGS_OFLD & pq_flags)) +
291 (!!(PQ_FLAGS_VFS & pq_flags)) *
292 ecore_init_qm_get_num_vfs(p_hwfn);
295 /* initialize the top level QM params */
296 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
298 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
301 /* pq and vport bases for this PF */
302 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
303 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
305 /* rate limiting and weighted fair queueing are always enabled */
306 qm_info->vport_rl_en = 1;
307 qm_info->vport_wfq_en = 1;
309 /* TC config is different for AH 4 port */
310 four_port = p_hwfn->p_dev->num_ports_in_engines == MAX_NUM_PORTS_K2;
312 /* in AH 4 port we have fewer TCs per port */
313 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
316 /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
319 if (!qm_info->ooo_tc)
320 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
324 /* initialize qm vport params */
325 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
327 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
330 /* all vports participate in weighted fair queueing */
331 for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
332 qm_info->qm_vport_params[i].vport_wfq = 1;
335 /* initialize qm port params */
336 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
338 /* Initialize qm port parameters */
339 u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engines;
341 /* indicate how ooo and high pri traffic is dealt with */
342 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
343 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
345 for (i = 0; i < num_ports; i++) {
346 struct init_qm_port_params *p_qm_port =
347 &p_hwfn->qm_info.qm_port_params[i];
349 p_qm_port->active = 1;
350 p_qm_port->active_phys_tcs = active_phys_tcs;
351 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
352 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
356 /* Reset the params which must be reset for qm init. QM init may be called as
357 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
358 * params may be affected by the init but would simply recalculate to the same
359 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
360 * affected as these amounts stay the same.
362 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
364 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
366 qm_info->num_pqs = 0;
367 qm_info->num_vports = 0;
368 qm_info->num_pf_rls = 0;
369 qm_info->num_vf_pqs = 0;
370 qm_info->first_vf_pq = 0;
371 qm_info->first_mcos_pq = 0;
372 qm_info->first_rl_pq = 0;
375 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
377 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
379 qm_info->num_vports++;
381 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
383 "vport overflow! qm_info->num_vports %d,"
384 " qm_init_get_num_vports() %d\n",
386 ecore_init_qm_get_num_vports(p_hwfn));
389 /* initialize a single pq and manage qm_info resources accounting.
390 * The pq_init_flags param determines whether the PQ is rate limited
392 * and whether a new vport is allocated to the pq or not (i.e. vport will be
396 /* flags for pq init */
397 #define PQ_INIT_SHARE_VPORT (1 << 0)
398 #define PQ_INIT_PF_RL (1 << 1)
399 #define PQ_INIT_VF_RL (1 << 2)
401 /* defines for pq init */
402 #define PQ_INIT_DEFAULT_WRR_GROUP 1
403 #define PQ_INIT_DEFAULT_TC 0
404 #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc)
406 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
407 struct ecore_qm_info *qm_info,
408 u8 tc, u32 pq_init_flags)
410 u16 pq_idx = qm_info->num_pqs, max_pq =
411 ecore_init_qm_get_num_pqs(p_hwfn);
415 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
418 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
420 qm_info->qm_pq_params[pq_idx].tc_id = tc;
421 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
422 qm_info->qm_pq_params[pq_idx].rl_valid =
423 (pq_init_flags & PQ_INIT_PF_RL ||
424 pq_init_flags & PQ_INIT_VF_RL);
426 /* qm params accounting */
428 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
429 qm_info->num_vports++;
431 if (pq_init_flags & PQ_INIT_PF_RL)
432 qm_info->num_pf_rls++;
434 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
436 "vport overflow! qm_info->num_vports %d,"
437 " qm_init_get_num_vports() %d\n",
439 ecore_init_qm_get_num_vports(p_hwfn));
441 if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
442 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
443 " qm_init_get_num_pf_rls() %d\n",
445 ecore_init_qm_get_num_pf_rls(p_hwfn));
448 /* get pq index according to PQ_FLAGS */
449 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
452 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
454 /* Can't have multiple flags set here */
455 if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
456 sizeof(pq_flags)) > 1)
461 return &qm_info->first_rl_pq;
463 return &qm_info->first_mcos_pq;
465 return &qm_info->pure_lb_pq;
467 return &qm_info->ooo_pq;
469 return &qm_info->pure_ack_pq;
471 return &qm_info->offload_pq;
473 return &qm_info->first_vf_pq;
479 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
483 /* save pq index in qm info */
484 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
485 u32 pq_flags, u16 pq_val)
487 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
489 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
492 /* get tx pq index, with the PQ TX base already set (ready for context init) */
493 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
495 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
497 return *base_pq_idx + CM_TX_PQ_BASE;
500 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
502 u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
505 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
507 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
510 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
512 u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
515 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
517 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
520 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
522 u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
525 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
527 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
530 /* Functions for creating specific types of pqs */
531 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
533 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
535 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
538 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
539 ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
542 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
544 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
546 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
549 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
550 ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
553 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
555 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
557 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
560 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
561 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
564 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
566 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
568 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
571 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
572 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
575 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
577 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
580 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
583 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
584 for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
585 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
588 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
590 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
591 u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
593 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
596 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
598 qm_info->num_vf_pqs = num_vfs;
599 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
600 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
604 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
606 u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
607 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
609 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
612 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
613 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
614 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
618 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
620 /* rate limited pqs, must come first (FW assumption) */
621 ecore_init_qm_rl_pqs(p_hwfn);
623 /* pqs for multi cos */
624 ecore_init_qm_mcos_pqs(p_hwfn);
626 /* pure loopback pq */
627 ecore_init_qm_lb_pq(p_hwfn);
629 /* out of order pq */
630 ecore_init_qm_ooo_pq(p_hwfn);
633 ecore_init_qm_pure_ack_pq(p_hwfn);
635 /* pq for offloaded protocol */
636 ecore_init_qm_offload_pq(p_hwfn);
638 /* done sharing vports */
639 ecore_init_qm_advance_vport(p_hwfn);
642 ecore_init_qm_vf_pqs(p_hwfn);
645 /* compare values of getters against resources amounts */
646 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
648 if (ecore_init_qm_get_num_vports(p_hwfn) >
649 RESC_NUM(p_hwfn, ECORE_VPORT)) {
650 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
654 if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
655 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
659 return ECORE_SUCCESS;
663 * Function for verbose printing of the qm initialization results
665 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
667 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
668 struct init_qm_vport_params *vport;
669 struct init_qm_port_params *port;
670 struct init_qm_pq_params *pq;
673 /* top level params */
674 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
675 "qm init top level params: start_pq %d, start_vport %d,"
676 " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
677 qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
678 qm_info->offload_pq, qm_info->pure_ack_pq);
679 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
680 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
681 " num_vports %d, max_phys_tcs_per_port %d\n",
682 qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
683 qm_info->num_vf_pqs, qm_info->num_vports,
684 qm_info->max_phys_tcs_per_port);
685 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
686 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
687 " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
688 qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
689 qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
690 qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
693 for (i = 0; i < p_hwfn->p_dev->num_ports_in_engines; i++) {
694 port = &qm_info->qm_port_params[i];
695 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
696 "port idx %d, active %d, active_phys_tcs %d,"
697 " num_pbf_cmd_lines %d, num_btb_blocks %d,"
699 i, port->active, port->active_phys_tcs,
700 port->num_pbf_cmd_lines, port->num_btb_blocks,
705 for (i = 0; i < qm_info->num_vports; i++) {
706 vport = &qm_info->qm_vport_params[i];
707 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
708 "vport idx %d, vport_rl %d, wfq %d,"
709 " first_tx_pq_id [ ",
710 qm_info->start_vport + i, vport->vport_rl,
712 for (tc = 0; tc < NUM_OF_TCS; tc++)
713 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
714 vport->first_tx_pq_id[tc]);
715 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
719 for (i = 0; i < qm_info->num_pqs; i++) {
720 pq = &qm_info->qm_pq_params[i];
721 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
722 "pq idx %d, vport_id %d, tc %d, wrr_grp %d,"
724 qm_info->start_pq + i, pq->vport_id, pq->tc_id,
725 pq->wrr_group, pq->rl_valid);
729 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
731 /* reset params required for init run */
732 ecore_init_qm_reset_params(p_hwfn);
734 /* init QM top level params */
735 ecore_init_qm_params(p_hwfn);
737 /* init QM port params */
738 ecore_init_qm_port_params(p_hwfn);
740 /* init QM vport params */
741 ecore_init_qm_vport_params(p_hwfn);
743 /* init QM physical queue params */
744 ecore_init_qm_pq_params(p_hwfn);
746 /* display all that init */
747 ecore_dp_init_qm_params(p_hwfn);
750 /* This function reconfigures the QM pf on the fly.
751 * For this purpose we:
752 * 1. reconfigure the QM database
753 * 2. set new values to runtime array
754 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
755 * 4. activate init tool in QM_PF stage
756 * 5. send an sdm_qm_cmd through rbc interface to release the QM
758 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
759 struct ecore_ptt *p_ptt)
761 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
763 enum _ecore_status_t rc;
765 /* initialize ecore's qm data structure */
766 ecore_init_qm_info(p_hwfn);
768 /* stop PF's qm queues */
769 OSAL_SPIN_LOCK(&qm_lock);
770 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
771 qm_info->start_pq, qm_info->num_pqs);
772 OSAL_SPIN_UNLOCK(&qm_lock);
776 /* clear the QM_PF runtime phase leftovers from previous init */
777 ecore_init_clear_rt_data(p_hwfn);
779 /* prepare QM portion of runtime array */
780 ecore_qm_init_pf(p_hwfn);
782 /* activate init tool on runtime array */
783 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
784 p_hwfn->hw_info.hw_mode);
785 if (rc != ECORE_SUCCESS)
788 /* start PF's qm queues */
789 OSAL_SPIN_LOCK(&qm_lock);
790 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
791 qm_info->start_pq, qm_info->num_pqs);
792 OSAL_SPIN_UNLOCK(&qm_lock);
796 return ECORE_SUCCESS;
799 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
801 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
802 enum _ecore_status_t rc;
804 rc = ecore_init_qm_sanity(p_hwfn);
805 if (rc != ECORE_SUCCESS)
808 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
809 sizeof(struct init_qm_pq_params) *
810 ecore_init_qm_get_num_pqs(p_hwfn));
811 if (!qm_info->qm_pq_params)
814 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
815 sizeof(struct init_qm_vport_params) *
816 ecore_init_qm_get_num_vports(p_hwfn));
817 if (!qm_info->qm_vport_params)
820 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
821 sizeof(struct init_qm_port_params) *
822 p_hwfn->p_dev->num_ports_in_engines);
823 if (!qm_info->qm_port_params)
826 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
827 sizeof(struct ecore_wfq_data) *
828 ecore_init_qm_get_num_vports(p_hwfn));
829 if (!qm_info->wfq_data)
832 return ECORE_SUCCESS;
835 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
836 ecore_qm_info_free(p_hwfn);
839 /******************** End QM initialization ***************/
841 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
843 enum _ecore_status_t rc = ECORE_SUCCESS;
847 for_each_hwfn(p_dev, i) {
848 rc = ecore_l2_alloc(&p_dev->hwfns[i]);
849 if (rc != ECORE_SUCCESS)
855 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
856 sizeof(*p_dev->fw_data));
860 for_each_hwfn(p_dev, i) {
861 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
862 u32 n_eqes, num_cons;
864 /* First allocate the context manager structure */
865 rc = ecore_cxt_mngr_alloc(p_hwfn);
869 /* Set the HW cid/tid numbers (in the contest manager)
870 * Must be done prior to any further computations.
872 rc = ecore_cxt_set_pf_params(p_hwfn);
876 rc = ecore_alloc_qm_data(p_hwfn);
881 ecore_init_qm_info(p_hwfn);
883 /* Compute the ILT client partition */
884 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
888 /* CID map / ILT shadow table / T2
889 * The talbes sizes are determined by the computations above
891 rc = ecore_cxt_tables_alloc(p_hwfn);
895 /* SPQ, must follow ILT because initializes SPQ context */
896 rc = ecore_spq_alloc(p_hwfn);
900 /* SP status block allocation */
901 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
904 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
908 rc = ecore_iov_alloc(p_hwfn);
913 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
914 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
915 /* Calculate the EQ size
916 * ---------------------
917 * Each ICID may generate up to one event at a time i.e.
918 * the event must be handled/cleared before a new one
919 * can be generated. We calculate the sum of events per
920 * protocol and create an EQ deep enough to handle the
922 * - Core - according to SPQ.
923 * - RoCE - per QP there are a couple of ICIDs, one
924 * responder and one requester, each can
925 * generate an EQE => n_eqes_qp = 2 * n_qp.
926 * Each CQ can generate an EQE. There are 2 CQs
927 * per QP => n_eqes_cq = 2 * n_qp.
928 * Hence the RoCE total is 4 * n_qp or
930 * - ENet - There can be up to two events per VF. One
931 * for VF-PF channel and another for VF FLR
932 * initial cleanup. The number of VFs is
933 * bounded by MAX_NUM_VFS_BB, and is much
934 * smaller than RoCE's so we avoid exact
937 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
939 ecore_cxt_get_proto_cid_count(
945 num_cons = ecore_cxt_get_proto_cid_count(
950 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
951 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
953 ecore_cxt_get_proto_cid_count(p_hwfn,
956 n_eqes += 2 * num_cons;
959 if (n_eqes > 0xFFFF) {
960 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
961 "The maximum of a u16 chain is 0x%x\n",
966 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
970 rc = ecore_consq_alloc(p_hwfn);
974 rc = ecore_l2_alloc(p_hwfn);
975 if (rc != ECORE_SUCCESS)
978 /* DMA info initialization */
979 rc = ecore_dmae_info_alloc(p_hwfn);
981 DP_NOTICE(p_hwfn, true,
982 "Failed to allocate memory for dmae_info"
987 /* DCBX initialization */
988 rc = ecore_dcbx_info_alloc(p_hwfn);
990 DP_NOTICE(p_hwfn, true,
991 "Failed to allocate memory for dcbx structure\n");
996 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
997 sizeof(*p_dev->reset_stats));
998 if (!p_dev->reset_stats) {
999 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
1003 return ECORE_SUCCESS;
1008 ecore_resc_free(p_dev);
1012 void ecore_resc_setup(struct ecore_dev *p_dev)
1017 for_each_hwfn(p_dev, i)
1018 ecore_l2_setup(&p_dev->hwfns[i]);
1022 for_each_hwfn(p_dev, i) {
1023 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1025 ecore_cxt_mngr_setup(p_hwfn);
1026 ecore_spq_setup(p_hwfn);
1027 ecore_eq_setup(p_hwfn);
1028 ecore_consq_setup(p_hwfn);
1030 /* Read shadow of current MFW mailbox */
1031 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1032 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1033 p_hwfn->mcp_info->mfw_mb_cur,
1034 p_hwfn->mcp_info->mfw_mb_length);
1036 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1038 ecore_l2_setup(p_hwfn);
1039 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
1043 #define FINAL_CLEANUP_POLL_CNT (100)
1044 #define FINAL_CLEANUP_POLL_TIME (10)
1045 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1046 struct ecore_ptt *p_ptt,
1049 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1050 enum _ecore_status_t rc = ECORE_TIMEOUT;
1053 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1054 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1055 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1056 return ECORE_SUCCESS;
1060 addr = GTT_BAR0_MAP_REG_USDM_RAM +
1061 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1066 command |= X_FINAL_CLEANUP_AGG_INT <<
1067 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1068 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1069 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1070 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1072 /* Make sure notification is not set before initiating final cleanup */
1074 if (REG_RD(p_hwfn, addr)) {
1075 DP_NOTICE(p_hwfn, false,
1076 "Unexpected; Found final cleanup notification");
1077 DP_NOTICE(p_hwfn, false,
1078 " before initiating final cleanup\n");
1079 REG_WR(p_hwfn, addr, 0);
1082 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1083 "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1086 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1088 /* Poll until completion */
1089 while (!REG_RD(p_hwfn, addr) && count--)
1090 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1092 if (REG_RD(p_hwfn, addr))
1095 DP_NOTICE(p_hwfn, true,
1096 "Failed to receive FW final cleanup notification\n");
1098 /* Cleanup afterwards */
1099 REG_WR(p_hwfn, addr, 0);
1104 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1108 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1109 hw_mode |= 1 << MODE_BB;
1110 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1111 hw_mode |= 1 << MODE_K2;
1113 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1114 p_hwfn->p_dev->type);
1118 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1119 switch (p_hwfn->p_dev->num_ports_in_engines) {
1121 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1124 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1127 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1130 DP_NOTICE(p_hwfn, true,
1131 "num_ports_in_engine = %d not supported\n",
1132 p_hwfn->p_dev->num_ports_in_engines);
1136 switch (p_hwfn->p_dev->mf_mode) {
1137 case ECORE_MF_DEFAULT:
1139 hw_mode |= 1 << MODE_MF_SI;
1141 case ECORE_MF_OVLAN:
1142 hw_mode |= 1 << MODE_MF_SD;
1145 DP_NOTICE(p_hwfn, true,
1146 "Unsupported MF mode, init as DEFAULT\n");
1147 hw_mode |= 1 << MODE_MF_SI;
1151 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1152 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1153 hw_mode |= 1 << MODE_FPGA;
1155 if (p_hwfn->p_dev->b_is_emul_full)
1156 hw_mode |= 1 << MODE_EMUL_FULL;
1158 hw_mode |= 1 << MODE_EMUL_REDUCED;
1162 hw_mode |= 1 << MODE_ASIC;
1164 if (p_hwfn->p_dev->num_hwfns > 1)
1165 hw_mode |= 1 << MODE_100G;
1167 p_hwfn->hw_info.hw_mode = hw_mode;
1169 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1170 "Configuring function for hw_mode: 0x%08x\n",
1171 p_hwfn->hw_info.hw_mode);
1173 return ECORE_SUCCESS;
1177 /* MFW-replacement initializations for non-ASIC */
1178 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1179 struct ecore_ptt *p_ptt)
1181 struct ecore_dev *p_dev = p_hwfn->p_dev;
1185 if (CHIP_REV_IS_EMUL(p_dev)) {
1186 if (ECORE_IS_AH(p_dev))
1190 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1192 if (CHIP_REV_IS_EMUL(p_dev) &&
1193 (ECORE_IS_AH(p_dev)))
1194 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1197 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1198 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1199 if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1200 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1202 if (CHIP_REV_IS_EMUL(p_dev)) {
1203 if (ECORE_IS_AH(p_dev)) {
1204 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1205 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1206 (p_dev->num_ports_in_engines >> 1));
1208 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1209 p_dev->num_ports_in_engines == 4 ? 0 : 3);
1214 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1215 for (i = 0; i < 100; i++) {
1217 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1221 DP_NOTICE(p_hwfn, true,
1222 "RBC done failed to complete in PSWRQ2\n");
1224 return ECORE_SUCCESS;
1228 /* Init run time data for all PFs and their VFs on an engine.
1229 * TBD - for VFs - Once we have parent PF info for each VF in
1230 * shmem available as CAU requires knowledge of parent PF for each VF.
1232 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1234 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1237 for_each_hwfn(p_dev, i) {
1238 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1239 struct ecore_igu_info *p_igu_info;
1240 struct ecore_igu_block *p_block;
1241 struct cau_sb_entry sb_entry;
1243 p_igu_info = p_hwfn->hw_info.p_igu_info;
1246 igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1248 p_block = &p_igu_info->entry[igu_sb_id];
1250 if (!p_block->is_pf)
1253 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1254 p_block->function_id, 0, 0);
1255 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1261 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
1262 struct ecore_ptt *p_ptt)
1264 u32 val, wr_mbs, cache_line_size;
1266 val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1279 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1284 cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
1285 switch (cache_line_size) {
1300 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1304 if (wr_mbs < OSAL_CACHE_LINE_SIZE)
1306 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1307 OSAL_CACHE_LINE_SIZE, wr_mbs);
1309 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1311 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1312 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1316 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1317 struct ecore_ptt *p_ptt,
1320 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1321 struct ecore_dev *p_dev = p_hwfn->p_dev;
1322 u8 vf_id, max_num_vfs;
1325 enum _ecore_status_t rc = ECORE_SUCCESS;
1327 ecore_init_cau_rt_data(p_dev);
1329 /* Program GTT windows */
1330 ecore_gtt_init(p_hwfn);
1333 if (CHIP_REV_IS_EMUL(p_dev)) {
1334 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
1335 if (rc != ECORE_SUCCESS)
1340 if (p_hwfn->mcp_info) {
1341 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1342 qm_info->pf_rl_en = 1;
1343 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1344 qm_info->pf_wfq_en = 1;
1347 ecore_qm_common_rt_init(p_hwfn,
1348 p_dev->num_ports_in_engines,
1349 qm_info->max_phys_tcs_per_port,
1350 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1351 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1352 qm_info->qm_port_params);
1354 ecore_cxt_hw_init_common(p_hwfn);
1356 ecore_init_cache_line_size(p_hwfn, p_ptt);
1358 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1359 if (rc != ECORE_SUCCESS)
1362 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1363 * need to decide with which value, maybe runtime
1365 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1366 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1368 if (ECORE_IS_BB(p_dev)) {
1369 /* Workaround clears ROCE search for all functions to prevent
1370 * involving non initialized function in processing ROCE packet.
1372 num_pfs = NUM_OF_ENG_PFS(p_dev);
1373 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1374 ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1375 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1376 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1378 /* pretend to original PF */
1379 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1382 /* Workaround for avoiding CCFC execution error when getting packets
1383 * with CRC errors, and allowing instead the invoking of the FW error
1385 * This is not done inside the init tool since it currently can't
1386 * perform a pretending to VFs.
1388 max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1389 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1390 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1391 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1392 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1393 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1394 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1395 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1397 /* pretend to original PF */
1398 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1404 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1405 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1407 #define PMEG_IF_BYTE_COUNT 8
1409 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1410 struct ecore_ptt *p_ptt,
1411 u32 addr, u64 data, u8 reg_type, u8 port)
1413 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1414 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1415 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1416 (8 << PMEG_IF_BYTE_COUNT),
1417 (reg_type << 25) | (addr << 8) | port,
1418 (u32)((data >> 32) & 0xffffffff),
1419 (u32)(data & 0xffffffff));
1421 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1422 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1423 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1424 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1425 (reg_type << 25) | (addr << 8) | port);
1426 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1427 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1428 (data >> 32) & 0xffffffff);
1431 #define XLPORT_MODE_REG (0x20a)
1432 #define XLPORT_MAC_CONTROL (0x210)
1433 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1434 #define XLPORT_ENABLE_REG (0x20b)
1436 #define XLMAC_CTRL (0x600)
1437 #define XLMAC_MODE (0x601)
1438 #define XLMAC_RX_MAX_SIZE (0x608)
1439 #define XLMAC_TX_CTRL (0x604)
1440 #define XLMAC_PAUSE_CTRL (0x60d)
1441 #define XLMAC_PFC_CTRL (0x60e)
1443 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1444 struct ecore_ptt *p_ptt)
1446 u8 loopback = 0, port = p_hwfn->port_id * 2;
1448 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1450 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1451 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1453 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1454 /* XLMAC: SOFT RESET */
1455 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1456 /* XLMAC: Port Speed >= 10Gbps */
1457 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1458 /* XLMAC: Max Size */
1459 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1460 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1461 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1463 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1464 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1465 0x30ffffc000ULL, 0, port);
1466 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1467 port); /* XLMAC: TX_EN, RX_EN */
1468 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1469 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1470 0x1003 | (loopback << 2), 0, port);
1471 /* Enabled Parallel PFC interface */
1472 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1474 /* XLPORT port enable */
1475 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1478 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1479 struct ecore_ptt *p_ptt)
1481 u8 port = p_hwfn->port_id;
1482 u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1484 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1486 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1487 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1489 CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1490 (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1492 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1493 1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1495 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1496 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1498 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1499 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1501 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1502 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1504 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1506 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1508 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1510 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1514 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1515 struct ecore_ptt *p_ptt)
1517 if (ECORE_IS_AH(p_hwfn->p_dev))
1518 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1520 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1523 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1524 struct ecore_ptt *p_ptt, u8 port)
1526 int port_offset = port ? 0x800 : 0;
1527 u32 xmac_rxctrl = 0;
1530 /* FIXME: move to common start */
1531 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1532 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
1534 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1535 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
1537 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1539 /* Set the number of ports on the Warp Core to 10G */
1540 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1542 /* Soft reset of XMAC */
1543 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1544 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1546 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1547 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1549 /* FIXME: move to common end */
1550 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1551 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1553 /* Set Max packet size: initialize XMAC block register for port 0 */
1554 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1556 /* CRC append for Tx packets: init XMAC block register for port 1 */
1557 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1559 /* Enable TX and RX: initialize XMAC block register for port 1 */
1560 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1561 XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1562 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1563 XMAC_REG_RX_CTRL_BB + port_offset);
1564 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1565 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1569 static enum _ecore_status_t
1570 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1571 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1573 u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1574 u32 dpi_bit_shift, dpi_count;
1577 /* Calculate DPI size
1578 * ------------------
1579 * The PWM region contains Doorbell Pages. The first is reserverd for
1580 * the kernel for, e.g, L2. The others are free to be used by non-
1581 * trusted applications, typically from user space. Each page, called a
1582 * doorbell page is sectioned into windows that allow doorbells to be
1583 * issued in parallel by the kernel/application. The size of such a
1584 * window (a.k.a. WID) is 1kB.
1586 * 1kB WID x N WIDS = DPI page size
1587 * DPI page size x N DPIs = PWM region size
1589 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1590 * in order to ensure that two applications won't share the same page.
1591 * It also must contain at least one WID per CPU to allow parallelism.
1592 * It also must be a power of 2, since it is stored as a bit shift.
1594 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1595 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1596 * containing 4 WIDs.
1598 dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1599 dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1600 dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1601 dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1602 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1604 dpi_count = pwm_region_size / dpi_page_size;
1606 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1607 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1610 p_hwfn->dpi_size = dpi_page_size;
1611 p_hwfn->dpi_count = dpi_count;
1613 /* Update registers */
1614 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1616 if (dpi_count < min_dpis)
1617 return ECORE_NORESOURCES;
1619 return ECORE_SUCCESS;
1622 enum ECORE_ROCE_EDPM_MODE {
1623 ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1624 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1625 ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1628 static enum _ecore_status_t
1629 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1630 struct ecore_ptt *p_ptt)
1632 u32 pwm_regsize, norm_regsize;
1633 u32 non_pwm_conn, min_addr_reg1;
1634 u32 db_bar_size, n_cpus;
1637 enum _ecore_status_t rc = ECORE_SUCCESS;
1640 db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1641 if (p_hwfn->p_dev->num_hwfns > 1)
1644 /* Calculate doorbell regions
1645 * -----------------------------------
1646 * The doorbell BAR is made of two regions. The first is called normal
1647 * region and the second is called PWM region. In the normal region
1648 * each ICID has its own set of addresses so that writing to that
1649 * specific address identifies the ICID. In the Process Window Mode
1650 * region the ICID is given in the data written to the doorbell. The
1651 * above per PF register denotes the offset in the doorbell BAR in which
1652 * the PWM region begins.
1653 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1654 * non-PWM connection. The calculation below computes the total non-PWM
1655 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1656 * in units of 4,096 bytes.
1658 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1659 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1661 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1662 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1663 min_addr_reg1 = norm_regsize / 4096;
1664 pwm_regsize = db_bar_size - norm_regsize;
1666 /* Check that the normal and PWM sizes are valid */
1667 if (db_bar_size < norm_regsize) {
1668 DP_ERR(p_hwfn->p_dev,
1669 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1670 db_bar_size, norm_regsize);
1671 return ECORE_NORESOURCES;
1673 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1674 DP_ERR(p_hwfn->p_dev,
1675 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1676 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1678 return ECORE_NORESOURCES;
1681 /* Calculate number of DPIs */
1682 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1683 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1684 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1685 /* Either EDPM is mandatory, or we are attempting to allocate a
1688 n_cpus = OSAL_NUM_ACTIVE_CPU();
1689 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1692 cond = ((rc != ECORE_SUCCESS) &&
1693 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1694 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1695 if (cond || p_hwfn->dcbx_no_edpm) {
1696 /* Either EDPM is disabled from user configuration, or it is
1697 * disabled via DCBx, or it is not mandatory and we failed to
1698 * allocated a WID per CPU.
1701 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1703 /* If we entered this flow due to DCBX then the DPM register is
1704 * already configured.
1709 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1710 norm_regsize, pwm_regsize);
1712 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1713 p_hwfn->dpi_size, p_hwfn->dpi_count,
1714 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1715 "disabled" : "enabled");
1717 /* Check return codes from above calls */
1718 if (rc != ECORE_SUCCESS) {
1720 "Failed to allocate enough DPIs\n");
1721 return ECORE_NORESOURCES;
1725 p_hwfn->dpi_start_offset = norm_regsize;
1727 /* Update registers */
1728 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1729 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1730 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1731 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1733 return ECORE_SUCCESS;
1736 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1737 struct ecore_ptt *p_ptt,
1740 enum _ecore_status_t rc = ECORE_SUCCESS;
1742 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1744 if (rc != ECORE_SUCCESS)
1747 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
1750 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1751 return ECORE_SUCCESS;
1753 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1754 if (ECORE_IS_AH(p_hwfn->p_dev))
1755 return ECORE_SUCCESS;
1756 else if (ECORE_IS_BB(p_hwfn->p_dev))
1757 ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
1758 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1759 if (p_hwfn->p_dev->num_hwfns > 1) {
1760 /* Activate OPTE in CMT */
1763 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1765 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1766 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1767 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1768 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1769 ecore_wr(p_hwfn, p_ptt,
1770 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1771 ecore_wr(p_hwfn, p_ptt,
1772 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1773 ecore_wr(p_hwfn, p_ptt,
1774 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1778 ecore_emul_link_init(p_hwfn, p_ptt);
1780 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1787 static enum _ecore_status_t
1788 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1789 struct ecore_ptt *p_ptt,
1790 struct ecore_tunnel_info *p_tunn,
1793 enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1795 u8 rel_pf_id = p_hwfn->rel_pf_id;
1797 enum _ecore_status_t rc = ECORE_SUCCESS;
1801 if (p_hwfn->mcp_info) {
1802 struct ecore_mcp_function_info *p_info;
1804 p_info = &p_hwfn->mcp_info->func_info;
1805 if (p_info->bandwidth_min)
1806 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1808 /* Update rate limit once we'll actually have a link */
1809 p_hwfn->qm_info.pf_rl = 100000;
1811 ecore_cxt_hw_init_pf(p_hwfn);
1813 ecore_int_igu_init_rt(p_hwfn);
1815 /* Set VLAN in NIG if needed */
1816 if (hw_mode & (1 << MODE_MF_SD)) {
1817 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1818 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1819 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1820 p_hwfn->hw_info.ovlan);
1823 /* Enable classification by MAC if needed */
1824 if (hw_mode & (1 << MODE_MF_SI)) {
1825 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1826 "Configuring TAGMAC_CLS_TYPE\n");
1827 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1831 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
1832 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1833 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1834 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1835 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1836 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1838 /* perform debug configuration when chip is out of reset */
1839 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1841 /* PF Init sequence */
1842 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1846 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1847 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1851 /* Pure runtime initializations - directly to the HW */
1852 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1854 /* PCI relaxed ordering causes a decrease in the performance on some
1855 * systems. Till a root cause is found, disable this attribute in the
1859 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1861 * DP_NOTICE(p_hwfn, true,
1862 * "Failed to find the PCIe Cap\n");
1865 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1866 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1867 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1870 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1874 /* enable interrupts */
1875 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1876 if (rc != ECORE_SUCCESS)
1879 /* send function start command */
1880 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1881 allow_npar_tx_switch);
1883 DP_NOTICE(p_hwfn, true,
1884 "Function start ramrod failed\n");
1886 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1887 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1888 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1890 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1891 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1893 ecore_wr(p_hwfn, p_ptt,
1894 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1897 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1898 "PRS_REG_SEARCH registers after start PFn\n");
1899 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1900 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1901 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1902 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1903 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1904 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1905 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1906 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1907 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1908 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1909 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1910 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1911 prs_reg = ecore_rd(p_hwfn, p_ptt,
1912 PRS_REG_SEARCH_TCP_FIRST_FRAG);
1913 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1914 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1916 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1917 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1918 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1924 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
1925 struct ecore_ptt *p_ptt,
1928 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
1930 /* Configure the PF's internal FID_enable for master transactions */
1931 ecore_wr(p_hwfn, p_ptt,
1932 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1934 /* Wait until value is set - try for 1 second every 50us */
1935 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1936 val = ecore_rd(p_hwfn, p_ptt,
1937 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1944 if (val != set_val) {
1945 DP_NOTICE(p_hwfn, true,
1946 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1947 return ECORE_UNKNOWN_ERROR;
1950 return ECORE_SUCCESS;
1953 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1954 struct ecore_ptt *p_main_ptt)
1956 /* Read shadow of current MFW mailbox */
1957 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1958 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1959 p_hwfn->mcp_info->mfw_mb_cur,
1960 p_hwfn->mcp_info->mfw_mb_length);
1963 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
1964 struct ecore_hw_init_params *p_params)
1966 if (p_params->p_tunn) {
1967 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1968 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1971 p_hwfn->b_int_enabled = 1;
1973 return ECORE_SUCCESS;
1976 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
1977 struct ecore_ptt *p_ptt)
1979 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
1980 1 << p_hwfn->abs_pf_id);
1984 ecore_fill_load_req_params(struct ecore_load_req_params *p_load_req,
1985 struct ecore_drv_load_params *p_drv_load)
1987 /* Make sure that if ecore-client didn't provide inputs, all the
1988 * expected defaults are indeed zero.
1990 OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
1991 OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
1992 OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
1994 OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
1996 if (p_drv_load != OSAL_NULL) {
1997 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
1998 ECORE_DRV_ROLE_KDUMP :
2000 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2001 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2002 p_load_req->override_force_load =
2003 p_drv_load->override_force_load;
2007 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
2008 struct ecore_hw_init_params *p_params)
2010 struct ecore_load_req_params load_req_params;
2011 u32 load_code, resp, param, drv_mb_param;
2012 bool b_default_mtu = true;
2013 struct ecore_hwfn *p_hwfn;
2014 enum _ecore_status_t rc = ECORE_SUCCESS;
2017 if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
2018 (p_dev->num_hwfns > 1)) {
2019 DP_NOTICE(p_dev, false,
2020 "MSI mode is not supported for CMT devices\n");
2025 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
2026 if (rc != ECORE_SUCCESS)
2030 for_each_hwfn(p_dev, i) {
2031 p_hwfn = &p_dev->hwfns[i];
2033 /* If management didn't provide a default, set one of our own */
2034 if (!p_hwfn->hw_info.mtu) {
2035 p_hwfn->hw_info.mtu = 1500;
2036 b_default_mtu = false;
2040 ecore_vf_start(p_hwfn, p_params);
2044 rc = ecore_calc_hw_mode(p_hwfn);
2045 if (rc != ECORE_SUCCESS)
2048 ecore_fill_load_req_params(&load_req_params,
2049 p_params->p_drv_load_params);
2050 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
2052 if (rc != ECORE_SUCCESS) {
2053 DP_NOTICE(p_hwfn, true,
2054 "Failed sending a LOAD_REQ command\n");
2058 load_code = load_req_params.load_code;
2059 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2060 "Load request was sent. Load code: 0x%x\n",
2063 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
2066 * When coming back from hiberbate state, the registers from
2067 * which shadow is read initially are not initialized. It turns
2068 * out that these registers get initialized during the call to
2069 * ecore_mcp_load_req request. So we need to reread them here
2070 * to get the proper shadow register value.
2071 * Note: This is a workaround for the missing MFW
2072 * initialization. It may be removed once the implementation
2075 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2077 /* Only relevant for recovery:
2078 * Clear the indication after the LOAD_REQ command is responded
2081 p_dev->recov_in_prog = false;
2083 p_hwfn->first_on_engine = (load_code ==
2084 FW_MSG_CODE_DRV_LOAD_ENGINE);
2086 if (!qm_lock_init) {
2087 OSAL_SPIN_LOCK_INIT(&qm_lock);
2088 qm_lock_init = true;
2091 /* Clean up chip from previous driver if such remains exist.
2092 * This is not needed when the PF is the first one on the
2093 * engine, since afterwards we are going to init the FW.
2095 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2096 rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2097 p_hwfn->rel_pf_id, false);
2098 if (rc != ECORE_SUCCESS) {
2099 ecore_hw_err_notify(p_hwfn,
2100 ECORE_HW_ERR_RAMROD_FAIL);
2105 /* Log and clean previous pglue_b errors if such exist */
2106 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
2107 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2109 /* Enable the PF's internal FID_enable in the PXP */
2110 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2112 if (rc != ECORE_SUCCESS)
2115 switch (load_code) {
2116 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2117 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2118 p_hwfn->hw_info.hw_mode);
2119 if (rc != ECORE_SUCCESS)
2122 case FW_MSG_CODE_DRV_LOAD_PORT:
2123 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2124 p_hwfn->hw_info.hw_mode);
2125 if (rc != ECORE_SUCCESS)
2128 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2129 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2131 p_hwfn->hw_info.hw_mode,
2132 p_params->b_hw_start,
2134 p_params->allow_npar_tx_switch);
2137 DP_NOTICE(p_hwfn, false,
2138 "Unexpected load code [0x%08x]", load_code);
2143 if (rc != ECORE_SUCCESS) {
2144 DP_NOTICE(p_hwfn, true,
2145 "init phase failed for loadcode 0x%x (rc %d)\n",
2150 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2151 if (rc != ECORE_SUCCESS)
2154 /* send DCBX attention request command */
2155 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2156 "sending phony dcbx set command to trigger DCBx attention handling\n");
2157 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2158 DRV_MSG_CODE_SET_DCBX,
2159 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, &resp,
2161 if (rc != ECORE_SUCCESS) {
2162 DP_NOTICE(p_hwfn, true,
2163 "Failed to send DCBX attention request\n");
2167 p_hwfn->hw_init_done = true;
2171 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2172 drv_mb_param = STORM_FW_VERSION;
2173 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2174 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2175 drv_mb_param, &resp, ¶m);
2176 if (rc != ECORE_SUCCESS)
2177 DP_INFO(p_hwfn, "Failed to update firmware version\n");
2180 rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2181 p_hwfn->hw_info.mtu);
2182 if (rc != ECORE_SUCCESS)
2183 DP_INFO(p_hwfn, "Failed to update default mtu\n");
2185 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2187 ECORE_OV_DRIVER_STATE_DISABLED);
2188 if (rc != ECORE_SUCCESS)
2189 DP_INFO(p_hwfn, "Failed to update driver state\n");
2195 /* The MFW load lock should be released regardless of success or failure
2196 * of initialization.
2197 * TODO: replace this with an attempt to send cancel_load.
2199 ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2203 #define ECORE_HW_STOP_RETRY_LIMIT (10)
2204 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2205 struct ecore_hwfn *p_hwfn,
2206 struct ecore_ptt *p_ptt)
2211 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2212 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2213 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2215 if ((!ecore_rd(p_hwfn, p_ptt,
2216 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2217 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2220 /* Dependent on number of connection/tasks, possibly
2221 * 1ms sleep is required between polls
2226 if (i < ECORE_HW_STOP_RETRY_LIMIT)
2229 DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2230 " [Connection %02x Tasks %02x]\n",
2231 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2232 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2235 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2239 for_each_hwfn(p_dev, j) {
2240 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2241 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2243 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2247 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
2248 struct ecore_ptt *p_ptt,
2249 u32 addr, u32 expected_val)
2251 u32 val = ecore_rd(p_hwfn, p_ptt, addr);
2253 if (val != expected_val) {
2254 DP_NOTICE(p_hwfn, true,
2255 "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
2256 addr, val, expected_val);
2257 return ECORE_UNKNOWN_ERROR;
2260 return ECORE_SUCCESS;
2263 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2265 struct ecore_hwfn *p_hwfn;
2266 struct ecore_ptt *p_ptt;
2267 enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
2270 for_each_hwfn(p_dev, j) {
2271 p_hwfn = &p_dev->hwfns[j];
2272 p_ptt = p_hwfn->p_main_ptt;
2274 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2277 ecore_vf_pf_int_cleanup(p_hwfn);
2278 rc = ecore_vf_pf_reset(p_hwfn);
2279 if (rc != ECORE_SUCCESS) {
2280 DP_NOTICE(p_hwfn, true,
2281 "ecore_vf_pf_reset failed. rc = %d.\n",
2283 rc2 = ECORE_UNKNOWN_ERROR;
2288 /* mark the hw as uninitialized... */
2289 p_hwfn->hw_init_done = false;
2291 /* Send unload command to MCP */
2292 if (!p_dev->recov_in_prog) {
2293 rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
2294 if (rc != ECORE_SUCCESS) {
2295 DP_NOTICE(p_hwfn, true,
2296 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2298 rc2 = ECORE_UNKNOWN_ERROR;
2302 OSAL_DPC_SYNC(p_hwfn);
2304 /* After this point no MFW attentions are expected, e.g. prevent
2305 * race between pf stop and dcbx pf update.
2308 rc = ecore_sp_pf_stop(p_hwfn);
2309 if (rc != ECORE_SUCCESS) {
2310 DP_NOTICE(p_hwfn, true,
2311 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2313 rc2 = ECORE_UNKNOWN_ERROR;
2316 /* perform debug action after PF stop was sent */
2317 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
2319 /* close NIG to BRB gate */
2320 ecore_wr(p_hwfn, p_ptt,
2321 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2324 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2325 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2326 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2327 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2328 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2330 /* @@@TBD - clean transmission queues (5.b) */
2331 /* @@@TBD - clean BTB (5.c) */
2333 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2335 /* @@@TBD - verify DMAE requests are done (8) */
2337 /* Disable Attention Generation */
2338 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2339 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2340 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2341 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2342 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
2343 if (rc != ECORE_SUCCESS) {
2344 DP_NOTICE(p_hwfn, true,
2345 "Failed to return IGU CAM to default\n");
2346 rc2 = ECORE_UNKNOWN_ERROR;
2349 /* Need to wait 1ms to guarantee SBs are cleared */
2352 if (!p_dev->recov_in_prog) {
2353 ecore_verify_reg_val(p_hwfn, p_ptt,
2354 QM_REG_USG_CNT_PF_TX, 0);
2355 ecore_verify_reg_val(p_hwfn, p_ptt,
2356 QM_REG_USG_CNT_PF_OTHER, 0);
2357 /* @@@TBD - assert on incorrect xCFC values (10.b) */
2360 /* Disable PF in HW blocks */
2361 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2362 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2364 if (!p_dev->recov_in_prog) {
2365 ecore_mcp_unload_done(p_hwfn, p_ptt);
2366 if (rc != ECORE_SUCCESS) {
2367 DP_NOTICE(p_hwfn, true,
2368 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2370 rc2 = ECORE_UNKNOWN_ERROR;
2375 if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
2376 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2377 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2379 /* Clear the PF's internal FID_enable in the PXP.
2380 * In CMT this should only be done for first hw-function, and
2381 * only after all transactions have stopped for all active
2384 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2386 if (rc != ECORE_SUCCESS) {
2387 DP_NOTICE(p_hwfn, true,
2388 "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2390 rc2 = ECORE_UNKNOWN_ERROR;
2397 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2401 for_each_hwfn(p_dev, j) {
2402 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2403 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2406 ecore_vf_pf_int_cleanup(p_hwfn);
2410 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2411 "Shutting down the fastpath\n");
2413 ecore_wr(p_hwfn, p_ptt,
2414 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2416 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2417 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2418 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2419 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2420 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2422 /* @@@TBD - clean transmission queues (5.b) */
2423 /* @@@TBD - clean BTB (5.c) */
2425 /* @@@TBD - verify DMAE requests are done (8) */
2427 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2428 /* Need to wait 1ms to guarantee SBs are cleared */
2433 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2435 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2437 if (IS_VF(p_hwfn->p_dev))
2440 /* If roce info is allocated it means roce is initialized and should
2441 * be enabled in searcher.
2443 if (p_hwfn->p_rdma_info) {
2444 if (p_hwfn->b_rdma_enabled_in_prs)
2445 ecore_wr(p_hwfn, p_ptt,
2446 p_hwfn->rdma_prs_search_reg, 0x1);
2447 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2450 /* Re-open incoming traffic */
2451 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2452 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2455 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2456 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2458 ecore_ptt_pool_free(p_hwfn);
2459 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2462 /* Setup bar access */
2463 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2465 /* clear indirect access */
2466 if (ECORE_IS_AH(p_hwfn->p_dev)) {
2467 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2468 PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2469 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2470 PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2471 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2472 PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2473 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2474 PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2476 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2477 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2478 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2479 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2480 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2481 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2482 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2483 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2486 /* Clean previous pglue_b errors if such exist */
2487 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2489 /* enable internal target-read */
2490 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2491 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2494 static void get_function_id(struct ecore_hwfn *p_hwfn)
2497 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2498 PXP_PF_ME_OPAQUE_ADDR);
2500 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2502 /* Bits 16-19 from the ME registers are the pf_num */
2503 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2504 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2505 PXP_CONCRETE_FID_PFID);
2506 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2507 PXP_CONCRETE_FID_PORT);
2509 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2510 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2511 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2514 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2516 u32 *feat_num = p_hwfn->hw_info.feat_num;
2517 struct ecore_sb_cnt_info sb_cnt;
2520 OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
2521 ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
2523 /* L2 Queues require each: 1 status block. 1 L2 queue */
2524 if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
2525 /* Start by allocating VF queues, then PF's */
2526 feat_num[ECORE_VF_L2_QUE] =
2528 RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
2530 feat_num[ECORE_PF_L2_QUE] =
2532 sb_cnt.cnt - non_l2_sbs,
2533 RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2534 FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
2537 feat_num[ECORE_FCOE_CQ] = OSAL_MIN_T(u32, sb_cnt.cnt,
2540 feat_num[ECORE_ISCSI_CQ] = OSAL_MIN_T(u32, sb_cnt.cnt,
2544 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2545 "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2546 (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2547 (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2548 (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2549 (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2550 (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2554 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2557 case ECORE_L2_QUEUE:
2571 case ECORE_RDMA_CNQ_RAM:
2572 return "RDMA_CNQ_RAM";
2575 case ECORE_LL2_QUEUE:
2577 case ECORE_CMDQS_CQS:
2579 case ECORE_RDMA_STATS_QUEUE:
2580 return "RDMA_STATS_QUEUE";
2586 return "UNKNOWN_RESOURCE";
2590 static enum _ecore_status_t
2591 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2592 enum ecore_resources res_id, u32 resc_max_val,
2595 enum _ecore_status_t rc;
2597 rc = ecore_mcp_set_resc_max_val(p_hwfn, p_hwfn->p_main_ptt, res_id,
2598 resc_max_val, p_mcp_resp);
2599 if (rc != ECORE_SUCCESS) {
2600 DP_NOTICE(p_hwfn, true,
2601 "MFW response failure for a max value setting of resource %d [%s]\n",
2602 res_id, ecore_hw_get_resc_name(res_id));
2606 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2608 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2609 res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
2611 return ECORE_SUCCESS;
2614 static enum _ecore_status_t
2615 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn)
2617 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2618 u32 resc_max_val, mcp_resp;
2620 enum _ecore_status_t rc;
2622 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2625 case ECORE_LL2_QUEUE:
2626 case ECORE_RDMA_CNQ_RAM:
2627 case ECORE_RDMA_STATS_QUEUE:
2635 rc = __ecore_hw_set_soft_resc_size(p_hwfn, res_id,
2636 resc_max_val, &mcp_resp);
2637 if (rc != ECORE_SUCCESS)
2640 /* There's no point to continue to the next resource if the
2641 * command is not supported by the MFW.
2642 * We do continue if the command is supported but the resource
2643 * is unknown to the MFW. Such a resource will be later
2644 * configured with the default allocation values.
2646 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2647 return ECORE_NOTIMPL;
2650 return ECORE_SUCCESS;
2654 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
2655 enum ecore_resources res_id,
2656 u32 *p_resc_num, u32 *p_resc_start)
2658 u8 num_funcs = p_hwfn->num_funcs_on_engine;
2659 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2662 case ECORE_L2_QUEUE:
2663 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2664 MAX_NUM_L2_QUEUES_BB) / num_funcs;
2667 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2668 MAX_NUM_VPORTS_BB) / num_funcs;
2671 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2672 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2675 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2676 MAX_QM_TX_QUEUES_BB) / num_funcs;
2679 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2683 /* Each VFC resource can accommodate both a MAC and a VLAN */
2684 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2687 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2688 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2690 case ECORE_LL2_QUEUE:
2691 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2693 case ECORE_RDMA_CNQ_RAM:
2694 case ECORE_CMDQS_CQS:
2695 /* CNQ/CMDQS are the same resource */
2697 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2699 case ECORE_RDMA_STATS_QUEUE:
2701 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2702 MAX_NUM_VPORTS_BB) / num_funcs;
2719 /* Since we want its value to reflect whether MFW supports
2720 * the new scheme, have a default of 0.
2725 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2729 return ECORE_SUCCESS;
2732 static enum _ecore_status_t
2733 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
2734 bool drv_resc_alloc)
2736 u32 dflt_resc_num = 0, dflt_resc_start = 0;
2737 u32 mcp_resp, *p_resc_num, *p_resc_start;
2738 enum _ecore_status_t rc;
2740 p_resc_num = &RESC_NUM(p_hwfn, res_id);
2741 p_resc_start = &RESC_START(p_hwfn, res_id);
2743 rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2745 if (rc != ECORE_SUCCESS) {
2747 "Failed to get default amount for resource %d [%s]\n",
2748 res_id, ecore_hw_get_resc_name(res_id));
2753 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2754 *p_resc_num = dflt_resc_num;
2755 *p_resc_start = dflt_resc_start;
2760 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2761 &mcp_resp, p_resc_num, p_resc_start);
2762 if (rc != ECORE_SUCCESS) {
2763 DP_NOTICE(p_hwfn, true,
2764 "MFW response failure for an allocation request for"
2765 " resource %d [%s]\n",
2766 res_id, ecore_hw_get_resc_name(res_id));
2770 /* Default driver values are applied in the following cases:
2771 * - The resource allocation MB command is not supported by the MFW
2772 * - There is an internal error in the MFW while processing the request
2773 * - The resource ID is unknown to the MFW
2775 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2777 "Failed to receive allocation info for resource %d [%s]."
2778 " mcp_resp = 0x%x. Applying default values"
2780 res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2781 dflt_resc_num, dflt_resc_start);
2783 *p_resc_num = dflt_resc_num;
2784 *p_resc_start = dflt_resc_start;
2788 if ((*p_resc_num != dflt_resc_num ||
2789 *p_resc_start != dflt_resc_start) &&
2790 res_id != ECORE_SB) {
2792 "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
2793 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2794 *p_resc_start, dflt_resc_num, dflt_resc_start,
2795 drv_resc_alloc ? " - Applying default values" : "");
2796 if (drv_resc_alloc) {
2797 *p_resc_num = dflt_resc_num;
2798 *p_resc_start = dflt_resc_start;
2802 return ECORE_SUCCESS;
2805 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2806 bool drv_resc_alloc)
2808 enum _ecore_status_t rc;
2811 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2812 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2813 if (rc != ECORE_SUCCESS)
2817 return ECORE_SUCCESS;
2820 #define ECORE_RESC_ALLOC_LOCK_RETRY_CNT 10
2821 #define ECORE_RESC_ALLOC_LOCK_RETRY_INTVL_US 10000 /* 10 msec */
2823 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2824 bool drv_resc_alloc)
2826 struct ecore_resc_unlock_params resc_unlock_params;
2827 struct ecore_resc_lock_params resc_lock_params;
2828 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2830 enum _ecore_status_t rc;
2832 u32 *resc_start = p_hwfn->hw_info.resc_start;
2833 u32 *resc_num = p_hwfn->hw_info.resc_num;
2834 /* For AH, an equal share of the ILT lines between the maximal number of
2835 * PFs is not enough for RoCE. This would be solved by the future
2836 * resource allocation scheme, but isn't currently present for
2837 * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2838 * to work - the BB number of ILT lines divided by its max PFs number.
2840 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2843 /* Setting the max values of the soft resources and the following
2844 * resources allocation queries should be atomic. Since several PFs can
2845 * run in parallel - a resource lock is needed.
2846 * If either the resource lock or resource set value commands are not
2847 * supported - skip the the max values setting, release the lock if
2848 * needed, and proceed to the queries. Other failures, including a
2849 * failure to acquire the lock, will cause this function to fail.
2850 * Old drivers that don't acquire the lock can run in parallel, and
2851 * their allocation values won't be affected by the updated max values.
2853 OSAL_MEM_ZERO(&resc_lock_params, sizeof(resc_lock_params));
2854 resc_lock_params.resource = ECORE_RESC_LOCK_RESC_ALLOC;
2855 resc_lock_params.retry_num = ECORE_RESC_ALLOC_LOCK_RETRY_CNT;
2856 resc_lock_params.retry_interval = ECORE_RESC_ALLOC_LOCK_RETRY_INTVL_US;
2857 resc_lock_params.sleep_b4_retry = true;
2858 OSAL_MEM_ZERO(&resc_unlock_params, sizeof(resc_unlock_params));
2859 resc_unlock_params.resource = ECORE_RESC_LOCK_RESC_ALLOC;
2861 rc = ecore_mcp_resc_lock(p_hwfn, p_hwfn->p_main_ptt, &resc_lock_params);
2862 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
2864 } else if (rc == ECORE_NOTIMPL) {
2866 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2867 } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
2868 DP_NOTICE(p_hwfn, false,
2869 "Failed to acquire the resource lock for the resource allocation commands\n");
2871 goto unlock_and_exit;
2873 rc = ecore_hw_set_soft_resc_size(p_hwfn);
2874 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
2875 DP_NOTICE(p_hwfn, false,
2876 "Failed to set the max values of the soft resources\n");
2877 goto unlock_and_exit;
2878 } else if (rc == ECORE_NOTIMPL) {
2880 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2881 rc = ecore_mcp_resc_unlock(p_hwfn, p_hwfn->p_main_ptt,
2882 &resc_unlock_params);
2883 if (rc != ECORE_SUCCESS)
2885 "Failed to release the resource lock for the resource allocation commands\n");
2889 rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
2890 if (rc != ECORE_SUCCESS)
2891 goto unlock_and_exit;
2893 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2894 rc = ecore_mcp_resc_unlock(p_hwfn, p_hwfn->p_main_ptt,
2895 &resc_unlock_params);
2896 if (rc != ECORE_SUCCESS)
2898 "Failed to release the resource lock for the resource allocation commands\n");
2902 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2903 /* Reduced build contains less PQs */
2904 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2905 resc_num[ECORE_PQ] = 32;
2906 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2907 p_hwfn->enabled_func_idx;
2910 /* For AH emulation, since we have a possible maximal number of
2911 * 16 enabled PFs, in case there are not enough ILT lines -
2912 * allocate only first PF as RoCE and have all the other ETH
2913 * only with less ILT lines.
2915 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2916 resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2917 resc_num[ECORE_ILT],
2918 roce_min_ilt_lines);
2921 /* Correct the common ILT calculation if PF0 has more */
2922 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2923 p_hwfn->p_dev->b_is_emul_full &&
2924 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2925 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2926 resc_num[ECORE_ILT];
2929 /* Sanity for ILT */
2930 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2931 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2932 DP_NOTICE(p_hwfn, true,
2933 "Can't assign ILT pages [%08x,...,%08x]\n",
2934 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2940 /* This will also learn the number of SBs from MFW */
2941 if (ecore_int_igu_reset_cam(p_hwfn, p_hwfn->p_main_ptt))
2944 ecore_hw_set_feat(p_hwfn);
2946 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2947 "The numbers for each resource are:\n");
2948 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2949 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2950 ecore_hw_get_resc_name(res_id),
2951 RESC_NUM(p_hwfn, res_id),
2952 RESC_START(p_hwfn, res_id));
2954 return ECORE_SUCCESS;
2957 ecore_mcp_resc_unlock(p_hwfn, p_hwfn->p_main_ptt, &resc_unlock_params);
2961 static enum _ecore_status_t
2962 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2963 struct ecore_ptt *p_ptt,
2964 struct ecore_hw_prepare_params *p_params)
2966 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
2967 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2968 struct ecore_mcp_link_capabilities *p_caps;
2969 struct ecore_mcp_link_params *link;
2970 enum _ecore_status_t rc;
2972 /* Read global nvm_cfg address */
2973 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2975 /* Verify MCP has initialized it */
2976 if (!nvm_cfg_addr) {
2977 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2978 if (p_params->b_relaxed_probe)
2979 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
2983 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
2985 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2987 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2988 OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2991 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2993 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2994 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2995 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2996 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2998 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2999 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
3001 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
3002 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
3004 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
3005 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
3007 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
3008 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
3010 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
3011 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
3013 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
3014 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
3016 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
3017 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
3019 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
3020 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
3022 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
3023 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
3025 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3026 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
3029 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
3034 /* Read DCBX configuration */
3035 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3036 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3037 dcbx_mode = ecore_rd(p_hwfn, p_ptt,
3039 OFFSETOF(struct nvm_cfg1_port, generic_cont0));
3040 dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
3041 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
3042 switch (dcbx_mode) {
3043 case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
3044 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
3046 case NVM_CFG1_PORT_DCBX_MODE_CEE:
3047 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
3049 case NVM_CFG1_PORT_DCBX_MODE_IEEE:
3050 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
3053 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
3056 /* Read default link configuration */
3057 link = &p_hwfn->mcp_info->link_input;
3058 p_caps = &p_hwfn->mcp_info->link_capabilities;
3059 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3060 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3061 link_temp = ecore_rd(p_hwfn, p_ptt,
3063 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
3064 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
3065 link->speed.advertised_speeds = link_temp;
3066 p_caps->speed_capabilities = link->speed.advertised_speeds;
3068 link_temp = ecore_rd(p_hwfn, p_ptt,
3070 OFFSETOF(struct nvm_cfg1_port, link_settings));
3071 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
3072 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
3073 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
3074 link->speed.autoneg = true;
3076 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
3077 link->speed.forced_speed = 1000;
3079 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
3080 link->speed.forced_speed = 10000;
3082 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3083 link->speed.forced_speed = 25000;
3085 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3086 link->speed.forced_speed = 40000;
3088 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3089 link->speed.forced_speed = 50000;
3091 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3092 link->speed.forced_speed = 100000;
3095 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
3098 p_caps->default_speed = link->speed.forced_speed;
3099 p_caps->default_speed_autoneg = link->speed.autoneg;
3101 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3102 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3103 link->pause.autoneg = !!(link_temp &
3104 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3105 link->pause.forced_rx = !!(link_temp &
3106 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3107 link->pause.forced_tx = !!(link_temp &
3108 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3109 link->loopback_mode = 0;
3111 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3112 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
3113 link->speed.forced_speed, link->speed.advertised_speeds,
3114 link->speed.autoneg, link->pause.autoneg);
3116 /* Read Multi-function information from shmem */
3117 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3118 OFFSETOF(struct nvm_cfg1, glob) +
3119 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3121 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3123 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3124 NVM_CFG1_GLOB_MF_MODE_OFFSET;
3127 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3128 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3130 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3131 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3133 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3134 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3137 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
3138 p_hwfn->p_dev->mf_mode);
3140 /* Read Multi-function information from shmem */
3141 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3142 OFFSETOF(struct nvm_cfg1, glob) +
3143 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3145 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3146 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3147 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3148 &p_hwfn->hw_info.device_capabilities);
3149 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3150 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3151 &p_hwfn->hw_info.device_capabilities);
3152 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3153 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3154 &p_hwfn->hw_info.device_capabilities);
3155 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3156 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3157 &p_hwfn->hw_info.device_capabilities);
3158 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3159 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3160 &p_hwfn->hw_info.device_capabilities);
3162 rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3163 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3165 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3171 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3172 struct ecore_ptt *p_ptt)
3174 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3175 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3176 struct ecore_dev *p_dev = p_hwfn->p_dev;
3178 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3180 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3181 * in the other bits are selected.
3182 * Bits 1-15 are for functions 1-15, respectively, and their value is
3183 * '0' only for enabled functions (function 0 always exists and
3185 * In case of CMT in BB, only the "even" functions are enabled, and thus
3186 * the number of functions for both hwfns is learnt from the same bits.
3188 if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3189 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3190 MISCS_REG_FUNCTION_HIDE_BB_K2);
3192 reg_function_hide = 0;
3195 if (reg_function_hide & 0x1) {
3196 if (ECORE_IS_BB(p_dev)) {
3197 if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
3209 /* Get the number of the enabled functions on the engine */
3210 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3217 /* Get the PF index within the enabled functions */
3218 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3219 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3227 p_hwfn->num_funcs_on_engine = num_funcs;
3228 p_hwfn->enabled_func_idx = enabled_func_idx;
3231 if (CHIP_REV_IS_FPGA(p_dev)) {
3232 DP_NOTICE(p_hwfn, false,
3233 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3234 p_hwfn->num_funcs_on_engine = 4;
3238 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3239 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3240 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3241 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3244 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3245 struct ecore_ptt *p_ptt)
3250 /* Read the port mode */
3251 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
3253 else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
3254 (p_hwfn->p_dev->num_hwfns > 1))
3255 /* In CMT on emulation, assume 1 port */
3259 port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3261 if (port_mode < 3) {
3262 p_hwfn->p_dev->num_ports_in_engines = 1;
3263 } else if (port_mode <= 5) {
3264 p_hwfn->p_dev->num_ports_in_engines = 2;
3266 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3267 p_hwfn->p_dev->num_ports_in_engines);
3269 /* Default num_ports_in_engines to something */
3270 p_hwfn->p_dev->num_ports_in_engines = 1;
3274 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3275 struct ecore_ptt *p_ptt)
3280 p_hwfn->p_dev->num_ports_in_engines = 0;
3283 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
3284 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3285 switch ((port & 0xf000) >> 12) {
3287 p_hwfn->p_dev->num_ports_in_engines = 1;
3290 p_hwfn->p_dev->num_ports_in_engines = 2;
3293 p_hwfn->p_dev->num_ports_in_engines = 4;
3296 DP_NOTICE(p_hwfn, false,
3297 "Unknown port mode in ECO_RESERVED %08x\n",
3302 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3303 port = ecore_rd(p_hwfn, p_ptt,
3304 CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3307 p_hwfn->p_dev->num_ports_in_engines++;
3311 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3312 struct ecore_ptt *p_ptt)
3314 if (ECORE_IS_BB(p_hwfn->p_dev))
3315 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3317 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3320 static enum _ecore_status_t
3321 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3322 enum ecore_pci_personality personality,
3323 struct ecore_hw_prepare_params *p_params)
3325 bool drv_resc_alloc = p_params->drv_resc_alloc;
3326 enum _ecore_status_t rc;
3328 /* Since all information is common, only first hwfns should do this */
3329 if (IS_LEAD_HWFN(p_hwfn)) {
3330 rc = ecore_iov_hw_info(p_hwfn);
3331 if (rc != ECORE_SUCCESS) {
3332 if (p_params->b_relaxed_probe)
3333 p_params->p_relaxed_res =
3334 ECORE_HW_PREPARE_BAD_IOV;
3340 /* TODO In get_hw_info, amoungst others:
3341 * Get MCP FW revision and determine according to it the supported
3342 * featrues (e.g. DCB)
3344 * ecore_get_pcie_width_speed, WOL capability.
3345 * Number of global CQ-s (for storage
3347 ecore_hw_info_port_num(p_hwfn, p_ptt);
3349 ecore_mcp_get_capabilities(p_hwfn, p_ptt);
3352 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3354 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3355 if (rc != ECORE_SUCCESS)
3361 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3362 if (rc != ECORE_SUCCESS) {
3363 if (p_params->b_relaxed_probe)
3364 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3370 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3372 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3373 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3376 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3378 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3379 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3383 if (ecore_mcp_is_init(p_hwfn)) {
3384 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3385 p_hwfn->hw_info.ovlan =
3386 p_hwfn->mcp_info->func_info.ovlan;
3388 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3391 if (personality != ECORE_PCI_DEFAULT) {
3392 p_hwfn->hw_info.personality = personality;
3393 } else if (ecore_mcp_is_init(p_hwfn)) {
3394 enum ecore_pci_personality protocol;
3396 protocol = p_hwfn->mcp_info->func_info.protocol;
3397 p_hwfn->hw_info.personality = protocol;
3401 /* To overcome ILT lack for emulation, until at least until we'll have
3402 * a definite answer from system about it, allow only PF0 to be RoCE.
3404 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3405 if (!p_hwfn->rel_pf_id)
3406 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3408 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3412 /* although in BB some constellations may support more than 4 tcs,
3413 * that can result in performance penalty in some cases. 4
3414 * represents a good tradeoff between performance and flexibility.
3416 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3418 /* start out with a single active tc. This can be increased either
3419 * by dcbx negotiation or by upper layer driver
3421 p_hwfn->hw_info.num_active_tc = 1;
3423 ecore_get_num_funcs(p_hwfn, p_ptt);
3425 if (ecore_mcp_is_init(p_hwfn))
3426 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3428 /* In case of forcing the driver's default resource allocation, calling
3429 * ecore_hw_get_resc() should come after initializing the personality
3430 * and after getting the number of functions, since the calculation of
3431 * the resources/features depends on them.
3432 * This order is not harmful if not forcing.
3434 rc = ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
3435 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3437 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3443 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
3445 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3449 /* Read Vendor Id / Device Id */
3450 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3452 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3455 /* Determine type */
3456 device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
3457 switch (device_id_mask) {
3458 case ECORE_DEV_ID_MASK_BB:
3459 p_dev->type = ECORE_DEV_TYPE_BB;
3461 case ECORE_DEV_ID_MASK_AH:
3462 p_dev->type = ECORE_DEV_TYPE_AH;
3465 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
3467 return ECORE_ABORTED;
3470 p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3471 MISCS_REG_CHIP_NUM);
3472 p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3473 MISCS_REG_CHIP_REV);
3475 MASK_FIELD(CHIP_REV, p_dev->chip_rev);
3477 /* Learn number of HW-functions */
3478 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3479 MISCS_REG_CMT_ENABLED_FOR_PAIR);
3481 if (tmp & (1 << p_hwfn->rel_pf_id)) {
3482 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3483 p_dev->num_hwfns = 2;
3485 p_dev->num_hwfns = 1;
3489 if (CHIP_REV_IS_EMUL(p_dev)) {
3490 /* For some reason we have problems with this register
3491 * in B0 emulation; Simply assume no CMT
3493 DP_NOTICE(p_dev->hwfns, false,
3494 "device on emul - assume no CMT\n");
3495 p_dev->num_hwfns = 1;
3499 p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3500 MISCS_REG_CHIP_TEST_REG) >> 4;
3501 MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
3502 p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3503 MISCS_REG_CHIP_METAL);
3504 MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
3505 DP_INFO(p_dev->hwfns,
3506 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3507 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3508 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3509 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3512 if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
3513 DP_NOTICE(p_dev->hwfns, false,
3514 "The chip type/rev (BB A0) is not supported!\n");
3515 return ECORE_ABORTED;
3518 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3519 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3520 MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3522 if (CHIP_REV_IS_EMUL(p_dev)) {
3523 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3524 MISCS_REG_ECO_RESERVED);
3525 if (tmp & (1 << 29)) {
3526 DP_NOTICE(p_hwfn, false,
3527 "Emulation: Running on a FULL build\n");
3528 p_dev->b_is_emul_full = true;
3530 DP_NOTICE(p_hwfn, false,
3531 "Emulation: Running on a REDUCED build\n");
3536 return ECORE_SUCCESS;
3539 #ifndef LINUX_REMOVE
3540 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3547 for_each_hwfn(p_dev, j) {
3548 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3550 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
3551 "Mark hw/fw uninitialized\n");
3553 p_hwfn->hw_init_done = false;
3554 p_hwfn->first_on_engine = false;
3556 ecore_ptt_invalidate(p_hwfn);
3561 static enum _ecore_status_t
3562 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
3563 void OSAL_IOMEM * p_regview,
3564 void OSAL_IOMEM * p_doorbells,
3565 struct ecore_hw_prepare_params *p_params)
3567 struct ecore_dev *p_dev = p_hwfn->p_dev;
3568 struct ecore_mdump_info mdump_info;
3569 enum _ecore_status_t rc = ECORE_SUCCESS;
3571 /* Split PCI bars evenly between hwfns */
3572 p_hwfn->regview = p_regview;
3573 p_hwfn->doorbells = p_doorbells;
3576 return ecore_vf_hw_prepare(p_hwfn);
3578 /* Validate that chip access is feasible */
3579 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3581 "Reading the ME register returns all Fs; Preventing further chip access\n");
3582 if (p_params->b_relaxed_probe)
3583 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
3587 get_function_id(p_hwfn);
3589 /* Allocate PTT pool */
3590 rc = ecore_ptt_pool_alloc(p_hwfn);
3592 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
3593 if (p_params->b_relaxed_probe)
3594 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3598 /* Allocate the main PTT */
3599 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3601 /* First hwfn learns basic information, e.g., number of hwfns */
3602 if (!p_hwfn->my_id) {
3603 rc = ecore_get_dev_info(p_dev);
3604 if (rc != ECORE_SUCCESS) {
3605 if (p_params->b_relaxed_probe)
3606 p_params->p_relaxed_res =
3607 ECORE_HW_PREPARE_FAILED_DEV;
3612 ecore_hw_hwfn_prepare(p_hwfn);
3614 /* Initialize MCP structure */
3615 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3617 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3618 if (p_params->b_relaxed_probe)
3619 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3623 /* Read the device configuration information from the HW and SHMEM */
3624 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3625 p_params->personality, p_params);
3627 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3631 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3632 * called, since among others it sets the ports number in an engine.
3634 if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3635 !p_dev->recov_in_prog) {
3636 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3637 if (rc != ECORE_SUCCESS)
3638 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3641 /* Check if mdump logs are present and update the epoch value */
3642 if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) {
3643 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3645 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) {
3646 DP_NOTICE(p_hwfn, false,
3647 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3650 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3654 /* Allocate the init RT array and initialize the init-ops engine */
3655 rc = ecore_init_alloc(p_hwfn);
3657 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3658 if (p_params->b_relaxed_probe)
3659 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3663 if (CHIP_REV_IS_FPGA(p_dev)) {
3664 DP_NOTICE(p_hwfn, false,
3665 "FPGA: workaround; Prevent DMAE parities\n");
3666 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
3669 DP_NOTICE(p_hwfn, false,
3670 "FPGA: workaround: Set VF bar0 size\n");
3671 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3672 PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
3678 if (IS_LEAD_HWFN(p_hwfn))
3679 ecore_iov_free_hw_info(p_dev);
3680 ecore_mcp_free(p_hwfn);
3682 ecore_hw_hwfn_free(p_hwfn);
3687 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3688 struct ecore_hw_prepare_params *p_params)
3690 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3691 enum _ecore_status_t rc;
3693 p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3694 p_dev->allow_mdump = p_params->allow_mdump;
3696 if (p_params->b_relaxed_probe)
3697 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
3699 /* Store the precompiled init data ptrs */
3701 ecore_init_iro_array(p_dev);
3703 /* Initialize the first hwfn - will learn number of hwfns */
3704 rc = ecore_hw_prepare_single(p_hwfn,
3706 p_dev->doorbells, p_params);
3707 if (rc != ECORE_SUCCESS)
3710 p_params->personality = p_hwfn->hw_info.personality;
3712 /* initilalize 2nd hwfn if necessary */
3713 if (p_dev->num_hwfns > 1) {
3714 void OSAL_IOMEM *p_regview, *p_doorbell;
3715 u8 OSAL_IOMEM *addr;
3717 /* adjust bar offset for second engine */
3718 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3719 ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3720 p_regview = (void OSAL_IOMEM *)addr;
3722 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3723 ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3724 p_doorbell = (void OSAL_IOMEM *)addr;
3726 /* prepare second hw function */
3727 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3728 p_doorbell, p_params);
3730 /* in case of error, need to free the previously
3731 * initiliazed hwfn 0.
3733 if (rc != ECORE_SUCCESS) {
3734 if (p_params->b_relaxed_probe)
3735 p_params->p_relaxed_res =
3736 ECORE_HW_PREPARE_FAILED_ENG2;
3739 ecore_init_free(p_hwfn);
3740 ecore_mcp_free(p_hwfn);
3741 ecore_hw_hwfn_free(p_hwfn);
3743 DP_NOTICE(p_dev, true,
3744 "What do we need to free when VF hwfn1 init fails\n");
3753 void ecore_hw_remove(struct ecore_dev *p_dev)
3755 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3759 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3760 ECORE_OV_DRIVER_STATE_NOT_LOADED);
3762 for_each_hwfn(p_dev, i) {
3763 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3766 ecore_vf_pf_release(p_hwfn);
3770 ecore_init_free(p_hwfn);
3771 ecore_hw_hwfn_free(p_hwfn);
3772 ecore_mcp_free(p_hwfn);
3774 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3777 ecore_iov_free_hw_info(p_dev);
3780 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3781 struct ecore_chain *p_chain)
3783 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3784 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3785 struct ecore_chain_next *p_next;
3791 size = p_chain->elem_size * p_chain->usable_per_page;
3793 for (i = 0; i < p_chain->page_cnt; i++) {
3797 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3798 p_virt_next = p_next->next_virt;
3799 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3801 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3802 ECORE_CHAIN_PAGE_SIZE);
3804 p_virt = p_virt_next;
3805 p_phys = p_phys_next;
3809 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3810 struct ecore_chain *p_chain)
3812 if (!p_chain->p_virt_addr)
3815 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3816 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3819 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3820 struct ecore_chain *p_chain)
3822 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3823 u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
3824 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3826 if (!pp_virt_addr_tbl)
3832 for (i = 0; i < page_cnt; i++) {
3833 if (!pp_virt_addr_tbl[i])
3836 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3837 *(dma_addr_t *)p_pbl_virt,
3838 ECORE_CHAIN_PAGE_SIZE);
3840 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3843 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3845 if (!p_chain->b_external_pbl)
3846 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
3847 p_chain->pbl_sp.p_phys_table, pbl_size);
3849 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3852 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3854 switch (p_chain->mode) {
3855 case ECORE_CHAIN_MODE_NEXT_PTR:
3856 ecore_chain_free_next_ptr(p_dev, p_chain);
3858 case ECORE_CHAIN_MODE_SINGLE:
3859 ecore_chain_free_single(p_dev, p_chain);
3861 case ECORE_CHAIN_MODE_PBL:
3862 ecore_chain_free_pbl(p_dev, p_chain);
3867 static enum _ecore_status_t
3868 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3869 enum ecore_chain_cnt_type cnt_type,
3870 osal_size_t elem_size, u32 page_cnt)
3872 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3874 /* The actual chain size can be larger than the maximal possible value
3875 * after rounding up the requested elements number to pages, and after
3876 * taking into acount the unusuable elements (next-ptr elements).
3877 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3878 * size/capacity fields are of a u32 type.
3880 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3881 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3882 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3883 chain_size > ECORE_U32_MAX)) {
3884 DP_NOTICE(p_dev, true,
3885 "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3886 (unsigned long)chain_size);
3890 return ECORE_SUCCESS;
3893 static enum _ecore_status_t
3894 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3896 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3897 dma_addr_t p_phys = 0;
3900 for (i = 0; i < p_chain->page_cnt; i++) {
3901 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3902 ECORE_CHAIN_PAGE_SIZE);
3904 DP_NOTICE(p_dev, true,
3905 "Failed to allocate chain memory\n");
3910 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3911 ecore_chain_reset(p_chain);
3913 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3917 p_virt_prev = p_virt;
3919 /* Last page's next element should point to the beginning of the
3922 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3923 p_chain->p_virt_addr,
3924 p_chain->p_phys_addr);
3926 return ECORE_SUCCESS;
3929 static enum _ecore_status_t
3930 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3932 dma_addr_t p_phys = 0;
3933 void *p_virt = OSAL_NULL;
3935 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3937 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3941 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3942 ecore_chain_reset(p_chain);
3944 return ECORE_SUCCESS;
3947 static enum _ecore_status_t
3948 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3949 struct ecore_chain *p_chain,
3950 struct ecore_chain_ext_pbl *ext_pbl)
3952 void *p_virt = OSAL_NULL;
3953 u8 *p_pbl_virt = OSAL_NULL;
3954 void **pp_virt_addr_tbl = OSAL_NULL;
3955 dma_addr_t p_phys = 0, p_pbl_phys = 0;
3956 u32 page_cnt = p_chain->page_cnt, size, i;
3958 size = page_cnt * sizeof(*pp_virt_addr_tbl);
3959 pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
3960 if (!pp_virt_addr_tbl) {
3961 DP_NOTICE(p_dev, true,
3962 "Failed to allocate memory for the chain virtual addresses table\n");
3966 /* The allocation of the PBL table is done with its full size, since it
3967 * is expected to be successive.
3968 * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3969 * failure, since pp_virt_addr_tbl was previously allocated, and it
3970 * should be saved to allow its freeing during the error flow.
3972 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3974 if (ext_pbl == OSAL_NULL) {
3975 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3977 p_pbl_virt = ext_pbl->p_pbl_virt;
3978 p_pbl_phys = ext_pbl->p_pbl_phys;
3979 p_chain->b_external_pbl = true;
3982 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3985 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3989 for (i = 0; i < page_cnt; i++) {
3990 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3991 ECORE_CHAIN_PAGE_SIZE);
3993 DP_NOTICE(p_dev, true,
3994 "Failed to allocate chain memory\n");
3999 ecore_chain_init_mem(p_chain, p_virt, p_phys);
4000 ecore_chain_reset(p_chain);
4003 /* Fill the PBL table with the physical address of the page */
4004 *(dma_addr_t *)p_pbl_virt = p_phys;
4005 /* Keep the virtual address of the page */
4006 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
4008 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4011 return ECORE_SUCCESS;
4014 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
4015 enum ecore_chain_use_mode intended_use,
4016 enum ecore_chain_mode mode,
4017 enum ecore_chain_cnt_type cnt_type,
4018 u32 num_elems, osal_size_t elem_size,
4019 struct ecore_chain *p_chain,
4020 struct ecore_chain_ext_pbl *ext_pbl)
4023 enum _ecore_status_t rc = ECORE_SUCCESS;
4025 if (mode == ECORE_CHAIN_MODE_SINGLE)
4028 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4030 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
4033 DP_NOTICE(p_dev, true,
4034 "Cannot allocate a chain with the given arguments:\n"
4035 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4036 intended_use, mode, cnt_type, num_elems, elem_size);
4040 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
4041 mode, cnt_type, p_dev->dp_ctx);
4044 case ECORE_CHAIN_MODE_NEXT_PTR:
4045 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
4047 case ECORE_CHAIN_MODE_SINGLE:
4048 rc = ecore_chain_alloc_single(p_dev, p_chain);
4050 case ECORE_CHAIN_MODE_PBL:
4051 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
4057 return ECORE_SUCCESS;
4060 ecore_chain_free(p_dev, p_chain);
4064 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
4065 u16 src_id, u16 *dst_id)
4067 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
4070 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
4071 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
4072 DP_NOTICE(p_hwfn, true,
4073 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4079 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
4081 return ECORE_SUCCESS;
4084 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
4085 u8 src_id, u8 *dst_id)
4087 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
4090 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
4091 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
4092 DP_NOTICE(p_hwfn, true,
4093 "vport id [%d] is not valid, available indices [%d - %d]\n",
4099 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
4101 return ECORE_SUCCESS;
4104 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
4105 u8 src_id, u8 *dst_id)
4107 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
4110 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
4111 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
4112 DP_NOTICE(p_hwfn, true,
4113 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4119 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
4121 return ECORE_SUCCESS;
4124 static enum _ecore_status_t
4125 ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4126 struct ecore_ptt *p_ptt, u32 high, u32 low,
4132 /* Find a free entry and utilize it */
4133 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4134 en = ecore_rd(p_hwfn, p_ptt,
4135 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4139 ecore_wr(p_hwfn, p_ptt,
4140 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4141 2 * i * sizeof(u32), low);
4142 ecore_wr(p_hwfn, p_ptt,
4143 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4144 (2 * i + 1) * sizeof(u32), high);
4145 ecore_wr(p_hwfn, p_ptt,
4146 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4147 i * sizeof(u32), 0);
4148 ecore_wr(p_hwfn, p_ptt,
4149 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4150 i * sizeof(u32), 0);
4151 ecore_wr(p_hwfn, p_ptt,
4152 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4153 i * sizeof(u32), 1);
4157 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4158 return ECORE_NORESOURCES;
4162 return ECORE_SUCCESS;
4165 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4166 struct ecore_ptt *p_ptt, u8 *p_filter)
4168 u32 high, low, entry_num;
4169 enum _ecore_status_t rc;
4171 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4172 return ECORE_SUCCESS;
4174 high = p_filter[1] | (p_filter[0] << 8);
4175 low = p_filter[5] | (p_filter[4] << 8) |
4176 (p_filter[3] << 16) | (p_filter[2] << 24);
4178 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4179 rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low,
4181 if (rc != ECORE_SUCCESS) {
4182 DP_NOTICE(p_hwfn, false,
4183 "Failed to find an empty LLH filter to utilize\n");
4187 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4188 "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n",
4189 p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4190 p_filter[4], p_filter[5], entry_num);
4192 return ECORE_SUCCESS;
4195 static enum _ecore_status_t
4196 ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4197 struct ecore_ptt *p_ptt, u32 high, u32 low,
4202 /* Find the entry and clean it */
4203 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4204 if (ecore_rd(p_hwfn, p_ptt,
4205 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4206 2 * i * sizeof(u32)) != low)
4208 if (ecore_rd(p_hwfn, p_ptt,
4209 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4210 (2 * i + 1) * sizeof(u32)) != high)
4213 ecore_wr(p_hwfn, p_ptt,
4214 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4215 ecore_wr(p_hwfn, p_ptt,
4216 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4217 2 * i * sizeof(u32), 0);
4218 ecore_wr(p_hwfn, p_ptt,
4219 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4220 (2 * i + 1) * sizeof(u32), 0);
4224 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4229 return ECORE_SUCCESS;
4232 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4233 struct ecore_ptt *p_ptt, u8 *p_filter)
4235 u32 high, low, entry_num;
4236 enum _ecore_status_t rc;
4238 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4241 high = p_filter[1] | (p_filter[0] << 8);
4242 low = p_filter[5] | (p_filter[4] << 8) |
4243 (p_filter[3] << 16) | (p_filter[2] << 24);
4245 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4246 rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high,
4248 if (rc != ECORE_SUCCESS) {
4249 DP_NOTICE(p_hwfn, false,
4250 "Tried to remove a non-configured filter\n");
4255 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4256 "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n",
4257 p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4258 p_filter[4], p_filter[5], entry_num);
4261 static enum _ecore_status_t
4262 ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4263 struct ecore_ptt *p_ptt,
4264 enum ecore_llh_port_filter_type_t type,
4265 u32 high, u32 low, u32 *p_entry_num)
4270 /* Find a free entry and utilize it */
4271 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4272 en = ecore_rd(p_hwfn, p_ptt,
4273 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4277 ecore_wr(p_hwfn, p_ptt,
4278 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4279 2 * i * sizeof(u32), low);
4280 ecore_wr(p_hwfn, p_ptt,
4281 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4282 (2 * i + 1) * sizeof(u32), high);
4283 ecore_wr(p_hwfn, p_ptt,
4284 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4285 i * sizeof(u32), 1);
4286 ecore_wr(p_hwfn, p_ptt,
4287 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4288 i * sizeof(u32), 1 << type);
4289 ecore_wr(p_hwfn, p_ptt,
4290 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1);
4294 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4295 return ECORE_NORESOURCES;
4299 return ECORE_SUCCESS;
4302 enum _ecore_status_t
4303 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4304 struct ecore_ptt *p_ptt,
4305 u16 source_port_or_eth_type,
4307 enum ecore_llh_port_filter_type_t type)
4309 u32 high, low, entry_num;
4310 enum _ecore_status_t rc;
4312 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4313 return ECORE_SUCCESS;
4319 case ECORE_LLH_FILTER_ETHERTYPE:
4320 high = source_port_or_eth_type;
4322 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4323 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4324 low = source_port_or_eth_type << 16;
4326 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4327 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4330 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4331 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4332 low = (source_port_or_eth_type << 16) | dest_port;
4335 DP_NOTICE(p_hwfn, true,
4336 "Non valid LLH protocol filter type %d\n", type);
4340 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4341 rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4342 high, low, &entry_num);
4343 if (rc != ECORE_SUCCESS) {
4344 DP_NOTICE(p_hwfn, false,
4345 "Failed to find an empty LLH filter to utilize\n");
4349 case ECORE_LLH_FILTER_ETHERTYPE:
4350 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4351 "ETH type %x is added at %d\n",
4352 source_port_or_eth_type, entry_num);
4354 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4355 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4356 "TCP src port %x is added at %d\n",
4357 source_port_or_eth_type, entry_num);
4359 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4360 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4361 "UDP src port %x is added at %d\n",
4362 source_port_or_eth_type, entry_num);
4364 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4365 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4366 "TCP dst port %x is added at %d\n", dest_port,
4369 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4370 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4371 "UDP dst port %x is added at %d\n", dest_port,
4374 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4375 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4376 "TCP src/dst ports %x/%x are added at %d\n",
4377 source_port_or_eth_type, dest_port, entry_num);
4379 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4380 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4381 "UDP src/dst ports %x/%x are added at %d\n",
4382 source_port_or_eth_type, dest_port, entry_num);
4386 return ECORE_SUCCESS;
4389 static enum _ecore_status_t
4390 ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4391 struct ecore_ptt *p_ptt,
4392 enum ecore_llh_port_filter_type_t type,
4393 u32 high, u32 low, u32 *p_entry_num)
4397 /* Find the entry and clean it */
4398 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4399 if (!ecore_rd(p_hwfn, p_ptt,
4400 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4403 if (!ecore_rd(p_hwfn, p_ptt,
4404 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4407 if (!(ecore_rd(p_hwfn, p_ptt,
4408 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4409 i * sizeof(u32)) & (1 << type)))
4411 if (ecore_rd(p_hwfn, p_ptt,
4412 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4413 2 * i * sizeof(u32)) != low)
4415 if (ecore_rd(p_hwfn, p_ptt,
4416 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4417 (2 * i + 1) * sizeof(u32)) != high)
4420 ecore_wr(p_hwfn, p_ptt,
4421 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4422 ecore_wr(p_hwfn, p_ptt,
4423 NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4424 i * sizeof(u32), 0);
4425 ecore_wr(p_hwfn, p_ptt,
4426 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4427 i * sizeof(u32), 0);
4428 ecore_wr(p_hwfn, p_ptt,
4429 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4430 2 * i * sizeof(u32), 0);
4431 ecore_wr(p_hwfn, p_ptt,
4432 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4433 (2 * i + 1) * sizeof(u32), 0);
4437 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4442 return ECORE_SUCCESS;
4446 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4447 struct ecore_ptt *p_ptt,
4448 u16 source_port_or_eth_type,
4450 enum ecore_llh_port_filter_type_t type)
4452 u32 high, low, entry_num;
4453 enum _ecore_status_t rc;
4455 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4462 case ECORE_LLH_FILTER_ETHERTYPE:
4463 high = source_port_or_eth_type;
4465 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4466 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4467 low = source_port_or_eth_type << 16;
4469 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4470 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4473 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4474 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4475 low = (source_port_or_eth_type << 16) | dest_port;
4478 DP_NOTICE(p_hwfn, true,
4479 "Non valid LLH protocol filter type %d\n", type);
4483 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4484 rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4487 if (rc != ECORE_SUCCESS) {
4488 DP_NOTICE(p_hwfn, false,
4489 "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n",
4490 type, source_port_or_eth_type, dest_port);
4494 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4495 "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n",
4496 type, source_port_or_eth_type, dest_port, entry_num);
4499 static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn,
4500 struct ecore_ptt *p_ptt)
4504 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4507 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4508 ecore_wr(p_hwfn, p_ptt,
4509 NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4510 i * sizeof(u32), 0);
4511 ecore_wr(p_hwfn, p_ptt,
4512 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4513 2 * i * sizeof(u32), 0);
4514 ecore_wr(p_hwfn, p_ptt,
4515 NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4516 (2 * i + 1) * sizeof(u32), 0);
4520 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4521 struct ecore_ptt *p_ptt)
4523 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4526 if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4527 ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt);
4530 enum _ecore_status_t
4531 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
4532 struct ecore_ptt *p_ptt)
4534 if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
4535 ecore_wr(p_hwfn, p_ptt,
4536 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
4537 1 << p_hwfn->abs_pf_id / 2);
4538 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
4539 return ECORE_SUCCESS;
4542 DP_NOTICE(p_hwfn, false,
4543 "This function can't be set as default\n");
4547 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
4548 struct ecore_ptt *p_ptt,
4549 u32 hw_addr, void *p_eth_qzone,
4550 osal_size_t eth_qzone_size,
4553 struct coalescing_timeset *p_coal_timeset;
4555 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
4556 DP_NOTICE(p_hwfn, true,
4557 "Coalescing configuration not enabled\n");
4561 p_coal_timeset = p_eth_qzone;
4562 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
4563 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
4564 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
4565 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
4567 return ECORE_SUCCESS;
4570 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
4571 u16 rx_coal, u16 tx_coal,
4574 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
4575 enum _ecore_status_t rc = ECORE_SUCCESS;
4576 struct ecore_ptt *p_ptt;
4578 /* TODO - Configuring a single queue's coalescing but
4579 * claiming all queues are abiding same configuration
4580 * for PF and VF both.
4583 if (IS_VF(p_hwfn->p_dev))
4584 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
4587 p_ptt = ecore_ptt_acquire(p_hwfn);
4592 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
4595 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
4599 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
4602 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
4605 ecore_ptt_release(p_hwfn, p_ptt);
4610 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
4611 struct ecore_ptt *p_ptt,
4613 struct ecore_queue_cid *p_cid)
4615 struct ustorm_eth_queue_zone eth_qzone;
4616 u8 timeset, timer_res;
4618 enum _ecore_status_t rc;
4620 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4621 if (coalesce <= 0x7F) {
4623 } else if (coalesce <= 0xFF) {
4625 } else if (coalesce <= 0x1FF) {
4628 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4631 timeset = (u8)(coalesce >> timer_res);
4633 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4634 p_cid->sb_igu_id, false);
4635 if (rc != ECORE_SUCCESS)
4638 address = BAR0_MAP_REG_USDM_RAM +
4639 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4641 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
4642 sizeof(struct ustorm_eth_queue_zone), timeset);
4643 if (rc != ECORE_SUCCESS)
4650 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
4651 struct ecore_ptt *p_ptt,
4653 struct ecore_queue_cid *p_cid)
4655 struct xstorm_eth_queue_zone eth_qzone;
4656 u8 timeset, timer_res;
4658 enum _ecore_status_t rc;
4660 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4661 if (coalesce <= 0x7F) {
4663 } else if (coalesce <= 0xFF) {
4665 } else if (coalesce <= 0x1FF) {
4668 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4672 timeset = (u8)(coalesce >> timer_res);
4674 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4675 p_cid->sb_igu_id, true);
4676 if (rc != ECORE_SUCCESS)
4679 address = BAR0_MAP_REG_XSDM_RAM +
4680 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4682 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
4683 sizeof(struct xstorm_eth_queue_zone), timeset);
4688 /* Calculate final WFQ values for all vports and configure it.
4689 * After this configuration each vport must have
4690 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
4692 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4693 struct ecore_ptt *p_ptt,
4696 struct init_qm_vport_params *vport_params;
4699 vport_params = p_hwfn->qm_info.qm_vport_params;
4701 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4702 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4704 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
4706 ecore_init_vport_wfq(p_hwfn, p_ptt,
4707 vport_params[i].first_tx_pq_id,
4708 vport_params[i].vport_wfq);
4713 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
4717 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4718 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4721 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4722 struct ecore_ptt *p_ptt,
4725 struct init_qm_vport_params *vport_params;
4728 vport_params = p_hwfn->qm_info.qm_vport_params;
4730 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4731 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
4732 ecore_init_vport_wfq(p_hwfn, p_ptt,
4733 vport_params[i].first_tx_pq_id,
4734 vport_params[i].vport_wfq);
4738 /* This function performs several validations for WFQ
4739 * configuration and required min rate for a given vport
4740 * 1. req_rate must be greater than one percent of min_pf_rate.
4741 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4742 * rates to get less than one percent of min_pf_rate.
4743 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4745 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
4746 u16 vport_id, u32 req_rate,
4749 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4750 int non_requested_count = 0, req_count = 0, i, num_vports;
4752 num_vports = p_hwfn->qm_info.num_vports;
4754 /* Accounting for the vports which are configured for WFQ explicitly */
4756 for (i = 0; i < num_vports; i++) {
4759 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
4761 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4762 total_req_min_rate += tmp_speed;
4766 /* Include current vport data as well */
4768 total_req_min_rate += req_rate;
4769 non_requested_count = num_vports - req_count;
4771 /* validate possible error cases */
4772 if (req_rate > min_pf_rate) {
4773 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4774 "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4775 vport_id, req_rate, min_pf_rate);
4779 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
4780 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4781 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4782 vport_id, req_rate, min_pf_rate);
4786 /* TBD - for number of vports greater than 100 */
4787 if (num_vports > ECORE_WFQ_UNIT) {
4788 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4789 "Number of vports is greater than %d\n",
4794 if (total_req_min_rate > min_pf_rate) {
4795 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4796 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4797 total_req_min_rate, min_pf_rate);
4801 /* Data left for non requested vports */
4802 total_left_rate = min_pf_rate - total_req_min_rate;
4803 left_rate_per_vp = total_left_rate / non_requested_count;
4805 /* validate if non requested get < 1% of min bw */
4806 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4807 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4808 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4809 left_rate_per_vp, min_pf_rate);
4813 /* now req_rate for given vport passes all scenarios.
4814 * assign final wfq rates to all vports.
4816 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4817 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4819 for (i = 0; i < num_vports; i++) {
4820 if (p_hwfn->qm_info.wfq_data[i].configured)
4823 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4826 return ECORE_SUCCESS;
4829 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4830 struct ecore_ptt *p_ptt,
4831 u16 vp_id, u32 rate)
4833 struct ecore_mcp_link_state *p_link;
4834 int rc = ECORE_SUCCESS;
4836 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4838 if (!p_link->min_pf_rate) {
4839 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4840 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4844 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4846 if (rc == ECORE_SUCCESS)
4847 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4848 p_link->min_pf_rate);
4850 DP_NOTICE(p_hwfn, false,
4851 "Validation failed while configuring min rate\n");
4856 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4857 struct ecore_ptt *p_ptt,
4860 bool use_wfq = false;
4861 int rc = ECORE_SUCCESS;
4864 /* Validate all pre configured vports for wfq */
4865 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4868 if (!p_hwfn->qm_info.wfq_data[i].configured)
4871 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4874 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4875 if (rc != ECORE_SUCCESS) {
4876 DP_NOTICE(p_hwfn, false,
4877 "WFQ validation failed while configuring min rate\n");
4882 if (rc == ECORE_SUCCESS && use_wfq)
4883 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4885 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4890 /* Main API for ecore clients to configure vport min rate.
4891 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4892 * rate - Speed in Mbps needs to be assigned to a given vport.
4894 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4896 int i, rc = ECORE_INVAL;
4898 /* TBD - for multiple hardware functions - that is 100 gig */
4899 if (p_dev->num_hwfns > 1) {
4900 DP_NOTICE(p_dev, false,
4901 "WFQ configuration is not supported for this device\n");
4905 for_each_hwfn(p_dev, i) {
4906 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4907 struct ecore_ptt *p_ptt;
4909 p_ptt = ecore_ptt_acquire(p_hwfn);
4911 return ECORE_TIMEOUT;
4913 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4915 if (rc != ECORE_SUCCESS) {
4916 ecore_ptt_release(p_hwfn, p_ptt);
4920 ecore_ptt_release(p_hwfn, p_ptt);
4926 /* API to configure WFQ from mcp link change */
4927 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4928 struct ecore_ptt *p_ptt,
4933 /* TBD - for multiple hardware functions - that is 100 gig */
4934 if (p_dev->num_hwfns > 1) {
4935 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4936 "WFQ configuration is not supported for this device\n");
4940 for_each_hwfn(p_dev, i) {
4941 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4943 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
4948 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4949 struct ecore_ptt *p_ptt,
4950 struct ecore_mcp_link_state *p_link,
4953 int rc = ECORE_SUCCESS;
4955 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4957 if (!p_link->line_speed && (max_bw != 100))
4960 p_link->speed = (p_link->line_speed * max_bw) / 100;
4961 p_hwfn->qm_info.pf_rl = p_link->speed;
4963 /* Since the limiter also affects Tx-switched traffic, we don't want it
4964 * to limit such traffic in case there's no actual limit.
4965 * In that case, set limit to imaginary high boundary.
4968 p_hwfn->qm_info.pf_rl = 100000;
4970 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4971 p_hwfn->qm_info.pf_rl);
4973 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4974 "Configured MAX bandwidth to be %08x Mb/sec\n",
4980 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4981 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4983 int i, rc = ECORE_INVAL;
4985 if (max_bw < 1 || max_bw > 100) {
4986 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4990 for_each_hwfn(p_dev, i) {
4991 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4992 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4993 struct ecore_mcp_link_state *p_link;
4994 struct ecore_ptt *p_ptt;
4996 p_link = &p_lead->mcp_info->link_output;
4998 p_ptt = ecore_ptt_acquire(p_hwfn);
5000 return ECORE_TIMEOUT;
5002 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5005 ecore_ptt_release(p_hwfn, p_ptt);
5007 if (rc != ECORE_SUCCESS)
5014 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
5015 struct ecore_ptt *p_ptt,
5016 struct ecore_mcp_link_state *p_link,
5019 int rc = ECORE_SUCCESS;
5021 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5022 p_hwfn->qm_info.pf_wfq = min_bw;
5024 if (!p_link->line_speed)
5027 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5029 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5031 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5032 "Configured MIN bandwidth to be %d Mb/sec\n",
5033 p_link->min_pf_rate);
5038 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5039 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
5041 int i, rc = ECORE_INVAL;
5043 if (min_bw < 1 || min_bw > 100) {
5044 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
5048 for_each_hwfn(p_dev, i) {
5049 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5050 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5051 struct ecore_mcp_link_state *p_link;
5052 struct ecore_ptt *p_ptt;
5054 p_link = &p_lead->mcp_info->link_output;
5056 p_ptt = ecore_ptt_acquire(p_hwfn);
5058 return ECORE_TIMEOUT;
5060 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5062 if (rc != ECORE_SUCCESS) {
5063 ecore_ptt_release(p_hwfn, p_ptt);
5067 if (p_link->min_pf_rate) {
5068 u32 min_rate = p_link->min_pf_rate;
5070 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
5075 ecore_ptt_release(p_hwfn, p_ptt);
5081 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
5083 struct ecore_mcp_link_state *p_link;
5085 p_link = &p_hwfn->mcp_info->link_output;
5087 if (p_link->min_pf_rate)
5088 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
5089 p_link->min_pf_rate);
5091 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
5092 sizeof(*p_hwfn->qm_info.wfq_data) *
5093 p_hwfn->qm_info.num_vports);
5096 int ecore_device_num_engines(struct ecore_dev *p_dev)
5098 return ECORE_IS_BB(p_dev) ? 2 : 1;
5101 int ecore_device_num_ports(struct ecore_dev *p_dev)
5103 /* in CMT always only one port */
5104 if (p_dev->num_hwfns > 1)
5107 return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
5110 void ecore_set_fw_mac_addr(__le16 *fw_msb,
5115 ((u8 *)fw_msb)[0] = mac[1];
5116 ((u8 *)fw_msb)[1] = mac[0];
5117 ((u8 *)fw_mid)[0] = mac[3];
5118 ((u8 *)fw_mid)[1] = mac[2];
5119 ((u8 *)fw_lsb)[0] = mac[5];
5120 ((u8 *)fw_lsb)[1] = mac[4];