2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_gtt_reg_addr.h"
13 #include "ecore_chain.h"
14 #include "ecore_status.h"
16 #include "ecore_rt_defs.h"
17 #include "ecore_init_ops.h"
18 #include "ecore_int.h"
19 #include "ecore_cxt.h"
20 #include "ecore_spq.h"
21 #include "ecore_init_fw_funcs.h"
22 #include "ecore_sp_commands.h"
23 #include "ecore_dev_api.h"
24 #include "ecore_sriov.h"
26 #include "ecore_mcp.h"
27 #include "ecore_hw_defs.h"
28 #include "mcp_public.h"
29 #include "ecore_iro.h"
31 #include "ecore_dev_api.h"
32 #include "ecore_dcbx.h"
34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
35 * registers involved are not split and thus configuration is a race where
36 * some of the PFs configuration might be lost.
37 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
38 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
39 * there's more than a single compiled ecore component in system].
41 static osal_spinlock_t qm_lock;
42 static bool qm_lock_init;
45 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to
46 * load the driver. The number was
51 #define ECORE_MIN_PWM_REGION ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
54 BAR_ID_0, /* used for GRC */
55 BAR_ID_1 /* Used for doorbells */
58 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
60 u32 bar_reg = (bar_id == BAR_ID_0 ?
61 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
64 if (IS_VF(p_hwfn->p_dev)) {
65 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
66 * read from actual register, but we're currently not using
67 * it for actual doorbelling.
72 val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
74 return 1 << (val + 15);
76 /* The above registers were updated in the past only in CMT mode. Since
77 * they were found to be useful MFW started updating them from 8.7.7.0.
78 * In older MFW versions they are set to 0 which means disabled.
80 if (p_hwfn->p_dev->num_hwfns > 1) {
81 DP_NOTICE(p_hwfn, false,
82 "BAR size not configured. Assuming BAR size of 256kB"
83 " for GRC and 512kB for DB\n");
84 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
86 DP_NOTICE(p_hwfn, false,
87 "BAR size not configured. Assuming BAR size of 512kB"
88 " for GRC and 512kB for DB\n");
95 void ecore_init_dp(struct ecore_dev *p_dev,
96 u32 dp_module, u8 dp_level, void *dp_ctx)
100 p_dev->dp_level = dp_level;
101 p_dev->dp_module = dp_module;
102 p_dev->dp_ctx = dp_ctx;
103 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
104 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
106 p_hwfn->dp_level = dp_level;
107 p_hwfn->dp_module = dp_module;
108 p_hwfn->dp_ctx = dp_ctx;
112 void ecore_init_struct(struct ecore_dev *p_dev)
116 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
117 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
119 p_hwfn->p_dev = p_dev;
121 p_hwfn->b_active = false;
123 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
124 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
127 /* hwfn 0 is always active */
128 p_dev->hwfns[0].b_active = true;
130 /* set the default cache alignment to 128 (may be overridden later) */
131 p_dev->cache_shift = 7;
134 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
136 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
138 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
139 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
140 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
141 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
144 void ecore_resc_free(struct ecore_dev *p_dev)
151 OSAL_FREE(p_dev, p_dev->fw_data);
153 OSAL_FREE(p_dev, p_dev->reset_stats);
155 for_each_hwfn(p_dev, i) {
156 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
158 OSAL_FREE(p_dev, p_hwfn->p_tx_cids);
159 OSAL_FREE(p_dev, p_hwfn->p_rx_cids);
162 for_each_hwfn(p_dev, i) {
163 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
165 ecore_cxt_mngr_free(p_hwfn);
166 ecore_qm_info_free(p_hwfn);
167 ecore_spq_free(p_hwfn);
168 ecore_eq_free(p_hwfn, p_hwfn->p_eq);
169 ecore_consq_free(p_hwfn, p_hwfn->p_consq);
170 ecore_int_free(p_hwfn);
171 #ifdef CONFIG_ECORE_LL2
172 ecore_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
174 ecore_iov_free(p_hwfn);
175 ecore_dmae_info_free(p_hwfn);
176 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
177 /* @@@TBD Flush work-queue ? */
181 static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn,
184 u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue;
185 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
186 struct init_qm_port_params *p_qm_port;
187 bool init_rdma_offload_pq = false;
188 bool init_pure_ack_pq = false;
189 bool init_ooo_pq = false;
190 u16 num_pqs, protocol_pqs;
196 /* @TMP - saving the existing min/max bw config before resetting the
197 * qm_info to restore them.
199 pf_rl = qm_info->pf_rl;
200 pf_wfq = qm_info->pf_wfq;
202 #ifdef CONFIG_ECORE_SRIOV
203 if (p_hwfn->p_dev->p_iov_info)
204 num_vfs = p_hwfn->p_dev->p_iov_info->total_vfs;
206 OSAL_MEM_ZERO(qm_info, sizeof(*qm_info));
209 /* @TMP - Don't allocate QM queues for VFs on emulation */
210 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
211 DP_NOTICE(p_hwfn, false,
212 "Emulation - skip configuring QM queues for VFs\n");
217 /* ethernet PFs require a pq per tc. Even if only a subset of the TCs
218 * active, we want physical queues allocated for all of them, since we
219 * don't have a good recycle flow. Non ethernet PFs require only a
220 * single physical queue.
222 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE ||
223 p_hwfn->hw_info.personality == ECORE_PCI_IWARP ||
224 p_hwfn->hw_info.personality == ECORE_PCI_ETH)
225 protocol_pqs = p_hwfn->hw_info.num_hw_tc;
229 num_pqs = protocol_pqs + num_vfs + 1; /* The '1' is for pure-LB */
230 num_vports = (u8)RESC_NUM(p_hwfn, ECORE_VPORT);
232 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
233 num_pqs++; /* for RoCE queue */
234 init_rdma_offload_pq = true;
235 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn) {
236 /* Due to FW assumption that rl==vport, we limit the
237 * number of rate limiters by the minimum between its
238 * allocated number and the allocated number of vports.
239 * Another limitation is the number of supported qps
240 * with rate limiters in FW.
243 (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
244 RESC_NUM(p_hwfn, ECORE_VPORT));
246 /* we subtract num_vfs because each one requires a rate
247 * limiter, and one default rate limiter.
249 if (num_pf_rls < num_vfs + 1) {
250 DP_ERR(p_hwfn, "No RL for DCQCN");
251 DP_ERR(p_hwfn, "[num_pf_rls %d num_vfs %d]\n",
252 num_pf_rls, num_vfs);
255 num_pf_rls -= num_vfs + 1;
258 num_pqs += num_pf_rls;
259 qm_info->num_pf_rls = (u8)num_pf_rls;
262 if (p_hwfn->hw_info.personality == ECORE_PCI_IWARP) {
263 num_pqs += 3; /* for iwarp queue / pure-ack / ooo */
264 init_rdma_offload_pq = true;
265 init_pure_ack_pq = true;
269 if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
270 num_pqs += 2; /* for iSCSI pure-ACK / OOO queue */
271 init_pure_ack_pq = true;
275 /* Sanity checking that setup requires legal number of resources */
276 if (num_pqs > RESC_NUM(p_hwfn, ECORE_PQ)) {
278 "Need too many Physical queues - 0x%04x avail %04x",
279 num_pqs, RESC_NUM(p_hwfn, ECORE_PQ));
283 /* PQs will be arranged as follows: First per-TC PQ, then pure-LB queue,
284 * then special queues (iSCSI pure-ACK / RoCE), then per-VF PQ.
286 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev,
287 b_sleepable ? GFP_KERNEL :
289 sizeof(struct init_qm_pq_params) *
291 if (!qm_info->qm_pq_params)
294 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev,
295 b_sleepable ? GFP_KERNEL :
298 init_qm_vport_params) *
300 if (!qm_info->qm_vport_params)
303 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev,
304 b_sleepable ? GFP_KERNEL :
306 sizeof(struct init_qm_port_params)
308 if (!qm_info->qm_port_params)
311 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev,
312 b_sleepable ? GFP_KERNEL :
314 sizeof(struct ecore_wfq_data) *
317 if (!qm_info->wfq_data)
320 vport_id = (u8)RESC_START(p_hwfn, ECORE_VPORT);
322 /* First init rate limited queues ( Due to RoCE assumption of
325 for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
326 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
327 qm_info->qm_pq_params[curr_queue].tc_id =
328 p_hwfn->hw_info.offload_tc;
329 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
330 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
334 for (i = 0; i < protocol_pqs; i++) {
335 struct init_qm_pq_params *params =
336 &qm_info->qm_pq_params[curr_queue++];
338 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE ||
339 p_hwfn->hw_info.personality == ECORE_PCI_IWARP ||
340 p_hwfn->hw_info.personality == ECORE_PCI_ETH) {
341 params->vport_id = vport_id;
343 /* Note: this assumes that if we had a configuration
344 * with N tcs and subsequently another configuration
345 * With Fewer TCs, the in flight traffic (in QM queues,
346 * in FW, from driver to FW) will still trickle out and
347 * not get "stuck" in the QM. This is determined by the
348 * NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ. Unused TCs are
349 * supposed to be cleared in this map, allowing traffic
350 * to flush out. If this is not the case, we would need
351 * to set the TC of unused queues to 0, and reconfigure
352 * QM every time num of TCs changes. Unused queues in
353 * this context would mean those intended for TCs where
354 * tc_id > hw_info.num_active_tcs.
356 params->wrr_group = 1; /* @@@TBD ECORE_WRR_MEDIUM */
358 params->vport_id = vport_id;
359 params->tc_id = p_hwfn->hw_info.offload_tc;
360 params->wrr_group = 1; /* @@@TBD ECORE_WRR_MEDIUM */
364 /* Then init pure-LB PQ */
365 qm_info->pure_lb_pq = curr_queue;
366 qm_info->qm_pq_params[curr_queue].vport_id =
367 (u8)RESC_START(p_hwfn, ECORE_VPORT);
368 qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
369 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
372 qm_info->offload_pq = 0; /* Already initialized for iSCSI/FCoE */
373 if (init_rdma_offload_pq) {
374 qm_info->offload_pq = curr_queue;
375 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
376 qm_info->qm_pq_params[curr_queue].tc_id =
377 p_hwfn->hw_info.offload_tc;
378 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
382 if (init_pure_ack_pq) {
383 qm_info->pure_ack_pq = curr_queue;
384 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
385 qm_info->qm_pq_params[curr_queue].tc_id =
386 p_hwfn->hw_info.offload_tc;
387 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
392 qm_info->ooo_pq = curr_queue;
393 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
394 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
395 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
399 /* Then init per-VF PQs */
400 vf_offset = curr_queue;
401 for (i = 0; i < num_vfs; i++) {
402 /* First vport is used by the PF */
403 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
404 /* @@@TBD VF Multi-cos */
405 qm_info->qm_pq_params[curr_queue].tc_id = 0;
406 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
407 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
411 qm_info->vf_queues_offset = vf_offset;
412 qm_info->num_pqs = num_pqs;
413 qm_info->num_vports = num_vports;
415 /* Initialize qm port parameters */
416 num_ports = p_hwfn->p_dev->num_ports_in_engines;
417 for (i = 0; i < num_ports; i++) {
418 p_qm_port = &qm_info->qm_port_params[i];
419 p_qm_port->active = 1;
420 /* @@@TMP - was NUM_OF_PHYS_TCS; Changed until dcbx will
424 p_qm_port->active_phys_tcs = 0xf;
426 p_qm_port->active_phys_tcs = 0x9f;
427 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
428 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
431 if (ECORE_IS_AH(p_hwfn->p_dev) && (num_ports == 4))
432 qm_info->max_phys_tcs_per_port = NUM_PHYS_TCS_4PORT_K2;
434 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
436 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
438 qm_info->num_vf_pqs = num_vfs;
439 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
441 for (i = 0; i < qm_info->num_vports; i++)
442 qm_info->qm_vport_params[i].vport_wfq = 1;
444 qm_info->vport_rl_en = 1;
445 qm_info->vport_wfq_en = 1;
446 qm_info->pf_rl = pf_rl;
447 qm_info->pf_wfq = pf_wfq;
449 return ECORE_SUCCESS;
452 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
453 ecore_qm_info_free(p_hwfn);
457 /* This function reconfigures the QM pf on the fly.
458 * For this purpose we:
459 * 1. reconfigure the QM database
460 * 2. set new values to runtime arrat
461 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
462 * 4. activate init tool in QM_PF stage
463 * 5. send an sdm_qm_cmd through rbc interface to release the QM
465 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
466 struct ecore_ptt *p_ptt)
468 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
470 enum _ecore_status_t rc;
472 /* qm_info is allocated in ecore_init_qm_info() which is already called
473 * from ecore_resc_alloc() or previous call of ecore_qm_reconf().
474 * The allocated size may change each init, so we free it before next
477 ecore_qm_info_free(p_hwfn);
479 /* initialize ecore's qm data structure */
480 rc = ecore_init_qm_info(p_hwfn, false);
481 if (rc != ECORE_SUCCESS)
484 /* stop PF's qm queues */
485 OSAL_SPIN_LOCK(&qm_lock);
486 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
487 qm_info->start_pq, qm_info->num_pqs);
488 OSAL_SPIN_UNLOCK(&qm_lock);
492 /* clear the QM_PF runtime phase leftovers from previous init */
493 ecore_init_clear_rt_data(p_hwfn);
495 /* prepare QM portion of runtime array */
496 ecore_qm_init_pf(p_hwfn);
498 /* activate init tool on runtime array */
499 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
500 p_hwfn->hw_info.hw_mode);
501 if (rc != ECORE_SUCCESS)
504 /* start PF's qm queues */
505 OSAL_SPIN_LOCK(&qm_lock);
506 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
507 qm_info->start_pq, qm_info->num_pqs);
508 OSAL_SPIN_UNLOCK(&qm_lock);
512 return ECORE_SUCCESS;
515 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
517 struct ecore_consq *p_consq;
518 struct ecore_eq *p_eq;
519 #ifdef CONFIG_ECORE_LL2
520 struct ecore_ll2_info *p_ll2_info;
522 enum _ecore_status_t rc = ECORE_SUCCESS;
528 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
529 sizeof(*p_dev->fw_data));
533 /* Allocate Memory for the Queue->CID mapping */
534 for_each_hwfn(p_dev, i) {
535 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
536 u32 num_tx_conns = RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
537 int tx_size, rx_size;
539 /* @@@TMP - resc management, change to actual required size */
540 if (p_hwfn->pf_params.eth_pf_params.num_cons > num_tx_conns)
541 num_tx_conns = p_hwfn->pf_params.eth_pf_params.num_cons;
542 tx_size = sizeof(struct ecore_hw_cid_data) * num_tx_conns;
543 rx_size = sizeof(struct ecore_hw_cid_data) *
544 RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
546 p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
548 if (!p_hwfn->p_tx_cids) {
549 DP_NOTICE(p_hwfn, true,
550 "Failed to allocate memory for Tx Cids\n");
554 p_hwfn->p_rx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
556 if (!p_hwfn->p_rx_cids) {
557 DP_NOTICE(p_hwfn, true,
558 "Failed to allocate memory for Rx Cids\n");
563 for_each_hwfn(p_dev, i) {
564 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
565 u32 n_eqes, num_cons;
567 /* First allocate the context manager structure */
568 rc = ecore_cxt_mngr_alloc(p_hwfn);
572 /* Set the HW cid/tid numbers (in the contest manager)
573 * Must be done prior to any further computations.
575 rc = ecore_cxt_set_pf_params(p_hwfn);
579 /* Prepare and process QM requirements */
580 rc = ecore_init_qm_info(p_hwfn, true);
584 /* Compute the ILT client partition */
585 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
589 /* CID map / ILT shadow table / T2
590 * The talbes sizes are determined by the computations above
592 rc = ecore_cxt_tables_alloc(p_hwfn);
596 /* SPQ, must follow ILT because initializes SPQ context */
597 rc = ecore_spq_alloc(p_hwfn);
601 /* SP status block allocation */
602 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
605 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
609 rc = ecore_iov_alloc(p_hwfn);
614 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
615 if ((p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) ||
616 (p_hwfn->hw_info.personality == ECORE_PCI_IWARP)) {
617 /* Calculate the EQ size
618 * ---------------------
619 * Each ICID may generate up to one event at a time i.e.
620 * the event must be handled/cleared before a new one
621 * can be generated. We calculate the sum of events per
622 * protocol and create an EQ deep enough to handle the
624 * - Core - according to SPQ.
625 * - RoCE - per QP there are a couple of ICIDs, one
626 * responder and one requester, each can
627 * generate an EQE => n_eqes_qp = 2 * n_qp.
628 * Each CQ can generate an EQE. There are 2 CQs
629 * per QP => n_eqes_cq = 2 * n_qp.
630 * Hence the RoCE total is 4 * n_qp or
632 * - ENet - There can be up to two events per VF. One
633 * for VF-PF channel and another for VF FLR
634 * initial cleanup. The number of VFs is
635 * bounded by MAX_NUM_VFS_BB, and is much
636 * smaller than RoCE's so we avoid exact
639 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
641 ecore_cxt_get_proto_cid_count(
647 num_cons = ecore_cxt_get_proto_cid_count(
652 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
653 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
655 ecore_cxt_get_proto_cid_count(p_hwfn,
658 n_eqes += 2 * num_cons;
661 if (n_eqes > 0xFFFF) {
662 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
663 "The maximum of a u16 chain is 0x%x\n",
668 p_eq = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
673 p_consq = ecore_consq_alloc(p_hwfn);
676 p_hwfn->p_consq = p_consq;
678 #ifdef CONFIG_ECORE_LL2
679 if (p_hwfn->using_ll2) {
680 p_ll2_info = ecore_ll2_alloc(p_hwfn);
683 p_hwfn->p_ll2_info = p_ll2_info;
687 /* DMA info initialization */
688 rc = ecore_dmae_info_alloc(p_hwfn);
690 DP_NOTICE(p_hwfn, true,
691 "Failed to allocate memory for dmae_info structure\n");
695 /* DCBX initialization */
696 rc = ecore_dcbx_info_alloc(p_hwfn);
698 DP_NOTICE(p_hwfn, true,
699 "Failed to allocate memory for dcbx structure\n");
704 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
705 sizeof(*p_dev->reset_stats));
706 if (!p_dev->reset_stats) {
707 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
711 return ECORE_SUCCESS;
716 ecore_resc_free(p_dev);
720 void ecore_resc_setup(struct ecore_dev *p_dev)
727 for_each_hwfn(p_dev, i) {
728 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
730 ecore_cxt_mngr_setup(p_hwfn);
731 ecore_spq_setup(p_hwfn);
732 ecore_eq_setup(p_hwfn, p_hwfn->p_eq);
733 ecore_consq_setup(p_hwfn, p_hwfn->p_consq);
735 /* Read shadow of current MFW mailbox */
736 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
737 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
738 p_hwfn->mcp_info->mfw_mb_cur,
739 p_hwfn->mcp_info->mfw_mb_length);
741 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
743 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
744 #ifdef CONFIG_ECORE_LL2
745 if (p_hwfn->using_ll2)
746 ecore_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
751 #define FINAL_CLEANUP_POLL_CNT (100)
752 #define FINAL_CLEANUP_POLL_TIME (10)
753 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
754 struct ecore_ptt *p_ptt,
757 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
758 enum _ecore_status_t rc = ECORE_TIMEOUT;
761 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
762 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
763 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
764 return ECORE_SUCCESS;
768 addr = GTT_BAR0_MAP_REG_USDM_RAM +
769 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
774 command |= X_FINAL_CLEANUP_AGG_INT <<
775 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
776 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
777 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
778 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
780 /* Make sure notification is not set before initiating final cleanup */
782 if (REG_RD(p_hwfn, addr)) {
783 DP_NOTICE(p_hwfn, false,
784 "Unexpected; Found final cleanup notification");
785 DP_NOTICE(p_hwfn, false,
786 " before initiating final cleanup\n");
787 REG_WR(p_hwfn, addr, 0);
790 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
791 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
794 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
796 /* Poll until completion */
797 while (!REG_RD(p_hwfn, addr) && count--)
798 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
800 if (REG_RD(p_hwfn, addr))
803 DP_NOTICE(p_hwfn, true,
804 "Failed to receive FW final cleanup notification\n");
806 /* Cleanup afterwards */
807 REG_WR(p_hwfn, addr, 0);
812 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
816 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
817 hw_mode |= 1 << MODE_BB_B0;
818 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
819 hw_mode |= 1 << MODE_K2;
821 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
822 p_hwfn->p_dev->type);
826 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
827 switch (p_hwfn->p_dev->num_ports_in_engines) {
829 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
832 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
835 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
838 DP_NOTICE(p_hwfn, true,
839 "num_ports_in_engine = %d not supported\n",
840 p_hwfn->p_dev->num_ports_in_engines);
844 switch (p_hwfn->p_dev->mf_mode) {
845 case ECORE_MF_DEFAULT:
847 hw_mode |= 1 << MODE_MF_SI;
850 hw_mode |= 1 << MODE_MF_SD;
853 DP_NOTICE(p_hwfn, true,
854 "Unsupported MF mode, init as DEFAULT\n");
855 hw_mode |= 1 << MODE_MF_SI;
859 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
860 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
861 hw_mode |= 1 << MODE_FPGA;
863 if (p_hwfn->p_dev->b_is_emul_full)
864 hw_mode |= 1 << MODE_EMUL_FULL;
866 hw_mode |= 1 << MODE_EMUL_REDUCED;
870 hw_mode |= 1 << MODE_ASIC;
872 if (p_hwfn->p_dev->num_hwfns > 1)
873 hw_mode |= 1 << MODE_100G;
875 p_hwfn->hw_info.hw_mode = hw_mode;
877 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
878 "Configuring function for hw_mode: 0x%08x\n",
879 p_hwfn->hw_info.hw_mode);
881 return ECORE_SUCCESS;
885 /* MFW-replacement initializations for non-ASIC */
886 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
887 struct ecore_ptt *p_ptt)
892 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
895 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
897 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
898 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2, 0x3ffffff);
900 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
901 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
902 if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))
903 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0, 4);
905 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
906 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
907 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
908 (p_hwfn->p_dev->num_ports_in_engines >> 1));
910 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
911 p_hwfn->p_dev->num_ports_in_engines == 4 ? 0 : 3);
915 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
916 for (i = 0; i < 100; i++) {
918 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
922 DP_NOTICE(p_hwfn, true,
923 "RBC done failed to complete in PSWRQ2\n");
925 return ECORE_SUCCESS;
929 /* Init run time data for all PFs and their VFs on an engine.
930 * TBD - for VFs - Once we have parent PF info for each VF in
931 * shmem available as CAU requires knowledge of parent PF for each VF.
933 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
935 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
938 for_each_hwfn(p_dev, i) {
939 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
940 struct ecore_igu_info *p_igu_info;
941 struct ecore_igu_block *p_block;
942 struct cau_sb_entry sb_entry;
944 p_igu_info = p_hwfn->hw_info.p_igu_info;
946 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
948 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
953 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
954 p_block->function_id, 0, 0);
955 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
960 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
961 struct ecore_ptt *p_ptt,
964 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
965 struct ecore_dev *p_dev = p_hwfn->p_dev;
966 u8 vf_id, max_num_vfs;
969 enum _ecore_status_t rc = ECORE_SUCCESS;
971 ecore_init_cau_rt_data(p_dev);
973 /* Program GTT windows */
974 ecore_gtt_init(p_hwfn);
977 if (CHIP_REV_IS_EMUL(p_dev)) {
978 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
979 if (rc != ECORE_SUCCESS)
984 if (p_hwfn->mcp_info) {
985 if (p_hwfn->mcp_info->func_info.bandwidth_max)
986 qm_info->pf_rl_en = 1;
987 if (p_hwfn->mcp_info->func_info.bandwidth_min)
988 qm_info->pf_wfq_en = 1;
991 ecore_qm_common_rt_init(p_hwfn,
992 p_dev->num_ports_in_engines,
993 qm_info->max_phys_tcs_per_port,
994 qm_info->pf_rl_en, qm_info->pf_wfq_en,
995 qm_info->vport_rl_en, qm_info->vport_wfq_en,
996 qm_info->qm_port_params);
998 ecore_cxt_hw_init_common(p_hwfn);
1000 /* Close gate from NIG to BRB/Storm; By default they are open, but
1001 * we close them to prevent NIG from passing data to reset blocks.
1002 * Should have been done in the ENGINE phase, but init-tool lacks
1003 * proper port-pretend capabilities.
1005 ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1006 ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1007 ecore_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
1008 ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1009 ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1010 ecore_port_unpretend(p_hwfn, p_ptt);
1012 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1013 if (rc != ECORE_SUCCESS)
1016 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1017 * need to decide with which value, maybe runtime
1019 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1020 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1022 if (ECORE_IS_BB(p_dev)) {
1023 /* Workaround clears ROCE search for all functions to prevent
1024 * involving non initialized function in processing ROCE packet.
1026 num_pfs = NUM_OF_ENG_PFS(p_dev);
1027 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1028 ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1029 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1030 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1032 /* pretend to original PF */
1033 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1036 /* Workaround for avoiding CCFC execution error when getting packets
1037 * with CRC errors, and allowing instead the invoking of the FW error
1039 * This is not done inside the init tool since it currently can't
1040 * perform a pretending to VFs.
1042 max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1043 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1044 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1045 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1046 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1047 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1048 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1049 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1051 /* pretend to original PF */
1052 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1055 * CQ89456 - Mask the BRB "RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR" attention.
1057 if (ECORE_IS_AH(p_dev))
1058 ecore_wr(p_hwfn, p_ptt, BRB_REG_INT_MASK_10, 0x4000000);
1064 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1065 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1067 #define PMEG_IF_BYTE_COUNT 8
1069 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1070 struct ecore_ptt *p_ptt,
1071 u32 addr, u64 data, u8 reg_type, u8 port)
1073 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1074 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1075 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) |
1076 (8 << PMEG_IF_BYTE_COUNT),
1077 (reg_type << 25) | (addr << 8) | port,
1078 (u32)((data >> 32) & 0xffffffff),
1079 (u32)(data & 0xffffffff));
1081 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0,
1082 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) &
1083 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1084 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB_B0,
1085 (reg_type << 25) | (addr << 8) | port);
1086 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
1088 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
1089 (data >> 32) & 0xffffffff);
1092 #define XLPORT_MODE_REG (0x20a)
1093 #define XLPORT_MAC_CONTROL (0x210)
1094 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1095 #define XLPORT_ENABLE_REG (0x20b)
1097 #define XLMAC_CTRL (0x600)
1098 #define XLMAC_MODE (0x601)
1099 #define XLMAC_RX_MAX_SIZE (0x608)
1100 #define XLMAC_TX_CTRL (0x604)
1101 #define XLMAC_PAUSE_CTRL (0x60d)
1102 #define XLMAC_PFC_CTRL (0x60e)
1104 static void ecore_emul_link_init_ah(struct ecore_hwfn *p_hwfn,
1105 struct ecore_ptt *p_ptt)
1107 u8 port = p_hwfn->port_id;
1108 u32 mac_base = NWM_REG_MAC0 + (port << 2) * NWM_REG_MAC0_SIZE;
1110 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2 + (port << 2),
1111 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_SHIFT) |
1112 (port << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_SHIFT)
1113 | (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_SHIFT));
1115 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE,
1116 1 << ETH_MAC_REG_XIF_MODE_XGMII_SHIFT);
1118 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH,
1119 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_SHIFT);
1121 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH,
1122 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_SHIFT);
1124 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS,
1125 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_SHIFT);
1127 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS,
1128 (0xA << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_SHIFT) |
1129 (8 << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_SHIFT));
1131 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG, 0xa853);
1134 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1135 struct ecore_ptt *p_ptt)
1137 u8 loopback = 0, port = p_hwfn->port_id * 2;
1139 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1141 if (ECORE_IS_AH(p_hwfn->p_dev)) {
1142 ecore_emul_link_init_ah(p_hwfn, p_ptt);
1146 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1147 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1149 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1150 /* XLMAC: SOFT RESET */
1151 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1152 /* XLMAC: Port Speed >= 10Gbps */
1153 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1154 /* XLMAC: Max Size */
1155 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1156 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1157 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1159 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1160 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1161 0x30ffffc000ULL, 0, port);
1162 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1163 port); /* XLMAC: TX_EN, RX_EN */
1164 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1165 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1166 0x1003 | (loopback << 2), 0, port);
1167 /* Enabled Parallel PFC interface */
1168 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1170 /* XLPORT port enable */
1171 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1174 static void ecore_link_init(struct ecore_hwfn *p_hwfn,
1175 struct ecore_ptt *p_ptt, u8 port)
1177 int port_offset = port ? 0x800 : 0;
1178 u32 xmac_rxctrl = 0;
1181 /* FIXME: move to common start */
1182 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1183 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
1185 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1186 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
1188 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1190 /* Set the number of ports on the Warp Core to 10G */
1191 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1193 /* Soft reset of XMAC */
1194 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1195 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1197 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1198 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1200 /* FIXME: move to common end */
1201 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1202 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE + port_offset, 0x20);
1204 /* Set Max packet size: initialize XMAC block register for port 0 */
1205 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE + port_offset, 0x2710);
1207 /* CRC append for Tx packets: init XMAC block register for port 1 */
1208 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO + port_offset, 0xC800);
1210 /* Enable TX and RX: initialize XMAC block register for port 1 */
1211 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL + port_offset,
1212 XMAC_REG_CTRL_TX_EN | XMAC_REG_CTRL_RX_EN);
1213 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset);
1214 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE;
1215 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset, xmac_rxctrl);
1219 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1220 struct ecore_ptt *p_ptt,
1223 enum _ecore_status_t rc = ECORE_SUCCESS;
1225 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1227 if (rc != ECORE_SUCCESS)
1230 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1231 return ECORE_SUCCESS;
1233 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1234 if (ECORE_IS_AH(p_hwfn->p_dev))
1235 return ECORE_SUCCESS;
1236 ecore_link_init(p_hwfn, p_ptt, p_hwfn->port_id);
1237 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1238 if (p_hwfn->p_dev->num_hwfns > 1) {
1239 /* Activate OPTE in CMT */
1242 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1244 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1245 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1246 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1247 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1248 ecore_wr(p_hwfn, p_ptt,
1249 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1250 ecore_wr(p_hwfn, p_ptt,
1251 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1252 ecore_wr(p_hwfn, p_ptt,
1253 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1257 ecore_emul_link_init(p_hwfn, p_ptt);
1259 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1266 static enum _ecore_status_t
1267 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1268 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1270 u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1271 u32 dpi_bit_shift, dpi_count;
1274 /* Calculate DPI size
1275 * ------------------
1276 * The PWM region contains Doorbell Pages. The first is reserverd for
1277 * the kernel for, e.g, L2. The others are free to be used by non-
1278 * trusted applications, typically from user space. Each page, called a
1279 * doorbell page is sectioned into windows that allow doorbells to be
1280 * issued in parallel by the kernel/application. The size of such a
1281 * window (a.k.a. WID) is 1kB.
1283 * 1kB WID x N WIDS = DPI page size
1284 * DPI page size x N DPIs = PWM region size
1286 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1287 * in order to ensure that two applications won't share the same page.
1288 * It also must contain at least one WID per CPU to allow parallelism.
1289 * It also must be a power of 2, since it is stored as a bit shift.
1291 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1292 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1293 * containing 4 WIDs.
1295 dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1296 dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1297 dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1298 dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1299 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1301 dpi_count = pwm_region_size / dpi_page_size;
1303 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1304 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1307 p_hwfn->dpi_size = dpi_page_size;
1308 p_hwfn->dpi_count = dpi_count;
1310 /* Update registers */
1311 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1313 if (dpi_count < min_dpis)
1314 return ECORE_NORESOURCES;
1316 return ECORE_SUCCESS;
1319 enum ECORE_ROCE_EDPM_MODE {
1320 ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1321 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1322 ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1325 static enum _ecore_status_t
1326 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1327 struct ecore_ptt *p_ptt)
1329 u32 pwm_regsize, norm_regsize;
1330 u32 non_pwm_conn, min_addr_reg1;
1331 u32 db_bar_size, n_cpus;
1334 int rc = ECORE_SUCCESS;
1337 db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1338 if (p_hwfn->p_dev->num_hwfns > 1)
1341 /* Calculate doorbell regions
1342 * -----------------------------------
1343 * The doorbell BAR is made of two regions. The first is called normal
1344 * region and the second is called PWM region. In the normal region
1345 * each ICID has its own set of addresses so that writing to that
1346 * specific address identifies the ICID. In the Process Window Mode
1347 * region the ICID is given in the data written to the doorbell. The
1348 * above per PF register denotes the offset in the doorbell BAR in which
1349 * the PWM region begins.
1350 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1351 * non-PWM connection. The calculation below computes the total non-PWM
1352 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1353 * in units of 4,096 bytes.
1355 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1356 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1358 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1359 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1360 min_addr_reg1 = norm_regsize / 4096;
1361 pwm_regsize = db_bar_size - norm_regsize;
1363 /* Check that the normal and PWM sizes are valid */
1364 if (db_bar_size < norm_regsize) {
1365 DP_ERR(p_hwfn->p_dev,
1366 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1367 db_bar_size, norm_regsize);
1368 return ECORE_NORESOURCES;
1370 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1371 DP_ERR(p_hwfn->p_dev,
1372 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1373 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1375 return ECORE_NORESOURCES;
1378 /* Calculate number of DPIs */
1379 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1380 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1381 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1382 /* Either EDPM is mandatory, or we are attempting to allocate a
1385 n_cpus = OSAL_NUM_ACTIVE_CPU();
1386 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1389 cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1390 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1391 if (cond || p_hwfn->dcbx_no_edpm) {
1392 /* Either EDPM is disabled from user configuration, or it is
1393 * disabled via DCBx, or it is not mandatory and we failed to
1394 * allocated a WID per CPU.
1397 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1399 /* If we entered this flow due to DCBX then the DPM register is
1400 * already configured.
1405 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1406 norm_regsize, pwm_regsize);
1408 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1409 p_hwfn->dpi_size, p_hwfn->dpi_count,
1410 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1411 "disabled" : "enabled");
1413 /* Check return codes from above calls */
1416 "Failed to allocate enough DPIs\n");
1417 return ECORE_NORESOURCES;
1421 p_hwfn->dpi_start_offset = norm_regsize;
1423 /* Update registers */
1424 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1425 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1426 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1427 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1429 return ECORE_SUCCESS;
1432 static enum _ecore_status_t
1433 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1434 struct ecore_ptt *p_ptt,
1435 struct ecore_tunn_start_params *p_tunn,
1438 enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1440 u8 rel_pf_id = p_hwfn->rel_pf_id;
1442 enum _ecore_status_t rc = ECORE_SUCCESS;
1446 if (p_hwfn->mcp_info) {
1447 struct ecore_mcp_function_info *p_info;
1449 p_info = &p_hwfn->mcp_info->func_info;
1450 if (p_info->bandwidth_min)
1451 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1453 /* Update rate limit once we'll actually have a link */
1454 p_hwfn->qm_info.pf_rl = 100000;
1456 ecore_cxt_hw_init_pf(p_hwfn);
1458 ecore_int_igu_init_rt(p_hwfn);
1460 /* Set VLAN in NIG if needed */
1461 if (hw_mode & (1 << MODE_MF_SD)) {
1462 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1463 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1464 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1465 p_hwfn->hw_info.ovlan);
1468 /* Enable classification by MAC if needed */
1469 if (hw_mode & (1 << MODE_MF_SI)) {
1470 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1471 "Configuring TAGMAC_CLS_TYPE\n");
1472 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1476 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
1477 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1478 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1479 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1480 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1481 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1483 /* perform debug configuration when chip is out of reset */
1484 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1486 /* Cleanup chip from previous driver if such remains exist */
1487 rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1488 if (rc != ECORE_SUCCESS) {
1489 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1493 /* PF Init sequence */
1494 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1498 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1499 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1503 /* Pure runtime initializations - directly to the HW */
1504 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1506 /* PCI relaxed ordering causes a decrease in the performance on some
1507 * systems. Till a root cause is found, disable this attribute in the
1511 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1513 * DP_NOTICE(p_hwfn, true,
1514 * "Failed to find the PCIe Cap\n");
1517 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1518 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1519 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1522 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1526 /* enable interrupts */
1527 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1528 if (rc != ECORE_SUCCESS)
1531 /* send function start command */
1532 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1533 allow_npar_tx_switch);
1535 DP_NOTICE(p_hwfn, true,
1536 "Function start ramrod failed\n");
1538 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1539 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1540 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1542 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1543 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1545 ecore_wr(p_hwfn, p_ptt,
1546 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1549 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1550 "PRS_REG_SEARCH registers after start PFn\n");
1551 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1552 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1553 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1554 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1555 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1556 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1557 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1558 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1559 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1560 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1561 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1562 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1563 prs_reg = ecore_rd(p_hwfn, p_ptt,
1564 PRS_REG_SEARCH_TCP_FIRST_FRAG);
1565 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1566 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1568 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1569 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1570 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1576 static enum _ecore_status_t
1577 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1578 struct ecore_ptt *p_ptt, u8 enable)
1580 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1582 /* Change PF in PXP */
1583 ecore_wr(p_hwfn, p_ptt,
1584 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1586 /* wait until value is set - try for 1 second every 50us */
1587 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1588 val = ecore_rd(p_hwfn, p_ptt,
1589 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1596 if (val != set_val) {
1597 DP_NOTICE(p_hwfn, true,
1598 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1599 return ECORE_UNKNOWN_ERROR;
1602 return ECORE_SUCCESS;
1605 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1606 struct ecore_ptt *p_main_ptt)
1608 /* Read shadow of current MFW mailbox */
1609 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1610 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1611 p_hwfn->mcp_info->mfw_mb_cur,
1612 p_hwfn->mcp_info->mfw_mb_length);
1615 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1616 struct ecore_hw_init_params *p_params)
1618 enum _ecore_status_t rc = ECORE_SUCCESS, mfw_rc;
1619 u32 load_code, param, drv_mb_param;
1620 struct ecore_hwfn *p_hwfn;
1623 if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
1624 (p_dev->num_hwfns > 1)) {
1625 DP_NOTICE(p_dev, false,
1626 "MSI mode is not supported for CMT devices\n");
1631 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1632 if (rc != ECORE_SUCCESS)
1636 for_each_hwfn(p_dev, i) {
1637 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1640 p_hwfn->b_int_enabled = 1;
1644 /* Enable DMAE in PXP */
1645 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1646 if (rc != ECORE_SUCCESS)
1649 rc = ecore_calc_hw_mode(p_hwfn);
1650 if (rc != ECORE_SUCCESS)
1653 /* @@@TBD need to add here:
1654 * Check for fan failure
1657 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1659 DP_NOTICE(p_hwfn, true,
1660 "Failed sending LOAD_REQ command\n");
1665 * When coming back from hiberbate state, the registers from
1666 * which shadow is read initially are not initialized. It turns
1667 * out that these registers get initialized during the call to
1668 * ecore_mcp_load_req request. So we need to reread them here
1669 * to get the proper shadow register value.
1670 * Note: This is a workaround for the missinginig MFW
1671 * initialization. It may be removed once the implementation
1674 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1676 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1677 "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1680 /* Only relevant for recovery:
1681 * Clear the indication after the LOAD_REQ command is responded
1684 p_dev->recov_in_prog = false;
1686 p_hwfn->first_on_engine = (load_code ==
1687 FW_MSG_CODE_DRV_LOAD_ENGINE);
1689 if (!qm_lock_init) {
1690 OSAL_SPIN_LOCK_INIT(&qm_lock);
1691 qm_lock_init = true;
1694 switch (load_code) {
1695 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1696 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1697 p_hwfn->hw_info.hw_mode);
1701 case FW_MSG_CODE_DRV_LOAD_PORT:
1702 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1703 p_hwfn->hw_info.hw_mode);
1707 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1708 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1710 p_hwfn->hw_info.hw_mode,
1711 p_params->b_hw_start,
1713 p_params->allow_npar_tx_switch);
1720 if (rc != ECORE_SUCCESS)
1721 DP_NOTICE(p_hwfn, true,
1722 "init phase failed for loadcode 0x%x (rc %d)\n",
1725 /* ACK mfw regardless of success or failure of initialization */
1726 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1727 DRV_MSG_CODE_LOAD_DONE,
1728 0, &load_code, ¶m);
1729 if (rc != ECORE_SUCCESS)
1731 if (mfw_rc != ECORE_SUCCESS) {
1732 DP_NOTICE(p_hwfn, true,
1733 "Failed sending LOAD_DONE command\n");
1737 /* send DCBX attention request command */
1738 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1739 "sending phony dcbx set command to trigger DCBx attention handling\n");
1740 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1741 DRV_MSG_CODE_SET_DCBX,
1742 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1743 &load_code, ¶m);
1744 if (mfw_rc != ECORE_SUCCESS) {
1745 DP_NOTICE(p_hwfn, true,
1746 "Failed to send DCBX attention request\n");
1750 p_hwfn->hw_init_done = true;
1754 p_hwfn = ECORE_LEADING_HWFN(p_dev);
1755 drv_mb_param = (FW_MAJOR_VERSION << 24) |
1756 (FW_MINOR_VERSION << 16) |
1757 (FW_REVISION_VERSION << 8) |
1758 (FW_ENGINEERING_VERSION);
1759 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1760 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1761 drv_mb_param, &load_code, ¶m);
1762 if (rc != ECORE_SUCCESS) {
1763 DP_ERR(p_hwfn, "Failed to send firmware version\n");
1767 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
1769 ECORE_OV_DRIVER_STATE_DISABLED);
1775 #define ECORE_HW_STOP_RETRY_LIMIT (10)
1776 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
1777 struct ecore_hwfn *p_hwfn,
1778 struct ecore_ptt *p_ptt)
1783 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1784 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1785 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
1787 if ((!ecore_rd(p_hwfn, p_ptt,
1788 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1789 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1792 /* Dependent on number of connection/tasks, possibly
1793 * 1ms sleep is required between polls
1798 if (i < ECORE_HW_STOP_RETRY_LIMIT)
1801 DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
1802 " [Connection %02x Tasks %02x]\n",
1803 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1804 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1807 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
1811 for_each_hwfn(p_dev, j) {
1812 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1813 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1815 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1819 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
1821 enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
1824 for_each_hwfn(p_dev, j) {
1825 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1826 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1828 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
1831 ecore_vf_pf_int_cleanup(p_hwfn);
1835 /* mark the hw as uninitialized... */
1836 p_hwfn->hw_init_done = false;
1838 rc = ecore_sp_pf_stop(p_hwfn);
1840 DP_NOTICE(p_hwfn, true,
1841 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
1843 /* perform debug action after PF stop was sent */
1844 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
1846 /* close NIG to BRB gate */
1847 ecore_wr(p_hwfn, p_ptt,
1848 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1851 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1852 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1853 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1854 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1855 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1857 /* @@@TBD - clean transmission queues (5.b) */
1858 /* @@@TBD - clean BTB (5.c) */
1860 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1862 /* @@@TBD - verify DMAE requests are done (8) */
1864 /* Disable Attention Generation */
1865 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1866 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1867 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1868 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1869 /* Need to wait 1ms to guarantee SBs are cleared */
1874 /* Disable DMAE in PXP - in CMT, this should only be done for
1875 * first hw-function, and only after all transactions have
1876 * stopped for all active hw-functions.
1878 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
1879 p_dev->hwfns[0].p_main_ptt, false);
1880 if (t_rc != ECORE_SUCCESS)
1887 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
1891 for_each_hwfn(p_dev, j) {
1892 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1893 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1896 ecore_vf_pf_int_cleanup(p_hwfn);
1900 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1901 "Shutting down the fastpath\n");
1903 ecore_wr(p_hwfn, p_ptt,
1904 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1906 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1907 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1908 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1909 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1910 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1912 /* @@@TBD - clean transmission queues (5.b) */
1913 /* @@@TBD - clean BTB (5.c) */
1915 /* @@@TBD - verify DMAE requests are done (8) */
1917 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1918 /* Need to wait 1ms to guarantee SBs are cleared */
1923 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
1925 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1927 if (IS_VF(p_hwfn->p_dev))
1930 /* If roce info is allocated it means roce is initialized and should
1931 * be enabled in searcher.
1933 if (p_hwfn->p_rdma_info) {
1934 if (p_hwfn->b_rdma_enabled_in_prs)
1935 ecore_wr(p_hwfn, p_ptt,
1936 p_hwfn->rdma_prs_search_reg, 0x1);
1937 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
1940 /* Re-open incoming traffic */
1941 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1942 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1945 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
1946 struct ecore_ptt *p_ptt, u32 reg,
1949 u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
1951 if (assert_val != expected) {
1952 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
1954 return ECORE_UNKNOWN_ERROR;
1960 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
1962 enum _ecore_status_t rc = ECORE_SUCCESS;
1963 u32 unload_resp, unload_param;
1966 for_each_hwfn(p_dev, i) {
1967 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1970 rc = ecore_vf_pf_reset(p_hwfn);
1976 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
1978 /* Check for incorrect states */
1979 if (!p_dev->recov_in_prog) {
1980 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1981 QM_REG_USG_CNT_PF_TX, 0);
1982 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1983 QM_REG_USG_CNT_PF_OTHER, 0);
1984 /* @@@TBD - assert on incorrect xCFC values (10.b) */
1987 /* Disable PF in HW blocks */
1988 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1989 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1991 if (p_dev->recov_in_prog) {
1992 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1993 "Recovery is in progress -> skip sending unload_req/done\n");
1997 /* Send unload command to MCP */
1998 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1999 DRV_MSG_CODE_UNLOAD_REQ,
2000 DRV_MB_PARAM_UNLOAD_WOL_MCP,
2001 &unload_resp, &unload_param);
2002 if (rc != ECORE_SUCCESS) {
2003 DP_NOTICE(p_hwfn, true,
2004 "ecore_hw_reset: UNLOAD_REQ failed\n");
2005 /* @@TBD - what to do? for now, assume ENG. */
2006 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
2009 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2010 DRV_MSG_CODE_UNLOAD_DONE,
2011 0, &unload_resp, &unload_param);
2012 if (rc != ECORE_SUCCESS) {
2014 true, "ecore_hw_reset: UNLOAD_DONE failed\n");
2015 /* @@@TBD - Should it really ASSERT here ? */
2023 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2024 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2026 ecore_ptt_pool_free(p_hwfn);
2027 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2030 /* Setup bar access */
2031 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2033 /* clear indirect access */
2034 if (ECORE_IS_AH(p_hwfn->p_dev)) {
2035 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2036 PGLUE_B_REG_PGL_ADDR_E8_F0, 0);
2037 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2038 PGLUE_B_REG_PGL_ADDR_EC_F0, 0);
2039 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2040 PGLUE_B_REG_PGL_ADDR_F0_F0, 0);
2041 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2042 PGLUE_B_REG_PGL_ADDR_F4_F0, 0);
2044 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2045 PGLUE_B_REG_PGL_ADDR_88_F0, 0);
2046 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2047 PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
2048 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2049 PGLUE_B_REG_PGL_ADDR_90_F0, 0);
2050 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2051 PGLUE_B_REG_PGL_ADDR_94_F0, 0);
2054 /* Clean Previous errors if such exist */
2055 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2056 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2058 /* enable internal target-read */
2059 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2060 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2063 static void get_function_id(struct ecore_hwfn *p_hwfn)
2066 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2067 PXP_PF_ME_OPAQUE_ADDR);
2069 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2071 /* Bits 16-19 from the ME registers are the pf_num */
2072 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2073 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2074 PXP_CONCRETE_FID_PFID);
2075 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2076 PXP_CONCRETE_FID_PORT);
2078 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2079 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2080 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2083 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2085 u32 *feat_num = p_hwfn->hw_info.feat_num;
2086 struct ecore_sb_cnt_info sb_cnt_info;
2087 int num_features = 1;
2089 /* L2 Queues require each: 1 status block. 1 L2 queue */
2090 feat_num[ECORE_PF_L2_QUE] =
2092 RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2093 RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2095 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2096 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2097 feat_num[ECORE_VF_L2_QUE] =
2099 RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2100 FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2101 sb_cnt_info.sb_iov_cnt);
2103 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2104 "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d num_features=%d\n",
2105 (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2106 (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2107 (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2108 RESC_NUM(p_hwfn, ECORE_SB),
2112 static enum resource_id_enum
2113 ecore_hw_get_mfw_res_id(enum ecore_resources res_id)
2115 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2119 mfw_res_id = RESOURCE_NUM_SB_E;
2121 case ECORE_L2_QUEUE:
2122 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2125 mfw_res_id = RESOURCE_NUM_VPORT_E;
2128 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2131 mfw_res_id = RESOURCE_NUM_PQ_E;
2134 mfw_res_id = RESOURCE_NUM_RL_E;
2138 /* Each VFC resource can accommodate both a MAC and a VLAN */
2139 mfw_res_id = RESOURCE_VFC_FILTER_E;
2142 mfw_res_id = RESOURCE_ILT_E;
2144 case ECORE_LL2_QUEUE:
2145 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2147 case ECORE_RDMA_CNQ_RAM:
2148 case ECORE_CMDQS_CQS:
2149 /* CNQ/CMDQS are the same resource */
2150 mfw_res_id = RESOURCE_CQS_E;
2152 case ECORE_RDMA_STATS_QUEUE:
2153 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2162 static u32 ecore_hw_get_dflt_resc_num(struct ecore_hwfn *p_hwfn,
2163 enum ecore_resources res_id)
2165 u8 num_funcs = p_hwfn->num_funcs_on_engine;
2166 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2167 struct ecore_sb_cnt_info sb_cnt_info;
2168 u32 dflt_resc_num = 0;
2172 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2173 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2174 dflt_resc_num = sb_cnt_info.sb_cnt;
2176 case ECORE_L2_QUEUE:
2177 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2178 MAX_NUM_L2_QUEUES_BB) / num_funcs;
2181 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2182 MAX_NUM_VPORTS_BB) / num_funcs;
2185 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2186 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2189 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2190 MAX_QM_TX_QUEUES_BB) / num_funcs;
2193 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2197 /* Each VFC resource can accommodate both a MAC and a VLAN */
2198 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2201 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2202 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2204 case ECORE_LL2_QUEUE:
2205 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2207 case ECORE_RDMA_CNQ_RAM:
2208 case ECORE_CMDQS_CQS:
2209 /* CNQ/CMDQS are the same resource */
2211 dflt_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2213 case ECORE_RDMA_STATS_QUEUE:
2215 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2216 MAX_NUM_VPORTS_BB) / num_funcs;
2222 return dflt_resc_num;
2225 static const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2230 case ECORE_L2_QUEUE:
2244 case ECORE_RDMA_CNQ_RAM:
2245 return "RDMA_CNQ_RAM";
2248 case ECORE_LL2_QUEUE:
2250 case ECORE_CMDQS_CQS:
2252 case ECORE_RDMA_STATS_QUEUE:
2253 return "RDMA_STATS_QUEUE";
2255 return "UNKNOWN_RESOURCE";
2259 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2260 enum ecore_resources res_id,
2261 bool drv_resc_alloc)
2263 u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
2264 u32 *p_resc_num, *p_resc_start;
2265 struct resource_info resc_info;
2266 enum _ecore_status_t rc;
2268 p_resc_num = &RESC_NUM(p_hwfn, res_id);
2269 p_resc_start = &RESC_START(p_hwfn, res_id);
2271 dflt_resc_num = ecore_hw_get_dflt_resc_num(p_hwfn, res_id);
2272 if (!dflt_resc_num) {
2274 "Failed to get default amount for resource %d [%s]\n",
2275 res_id, ecore_hw_get_resc_name(res_id));
2278 dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
2281 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2282 *p_resc_num = dflt_resc_num;
2283 *p_resc_start = dflt_resc_start;
2288 OSAL_MEM_ZERO(&resc_info, sizeof(resc_info));
2289 resc_info.res_id = ecore_hw_get_mfw_res_id(res_id);
2290 if (resc_info.res_id == RESOURCE_NUM_INVALID) {
2292 "Failed to match resource %d with MFW resources\n",
2297 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
2298 &mcp_resp, &mcp_param);
2299 if (rc != ECORE_SUCCESS) {
2300 DP_NOTICE(p_hwfn, true,
2301 "MFW response failure for an allocation request for"
2302 " resource %d [%s]\n",
2303 res_id, ecore_hw_get_resc_name(res_id));
2307 /* Default driver values are applied in the following cases:
2308 * - The resource allocation MB command is not supported by the MFW
2309 * - There is an internal error in the MFW while processing the request
2310 * - The resource ID is unknown to the MFW
2312 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
2313 mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
2316 "Resource %d [%s]: No allocation info was received"
2317 " [mcp_resp 0x%x]. Applying default values"
2318 " [num %d, start %d].\n",
2319 res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2320 dflt_resc_num, dflt_resc_start);
2322 *p_resc_num = dflt_resc_num;
2323 *p_resc_start = dflt_resc_start;
2327 /* TBD - remove this when revising the handling of the SB resource */
2328 if (res_id == ECORE_SB) {
2329 /* Excluding the slowpath SB */
2330 resc_info.size -= 1;
2331 resc_info.offset -= p_hwfn->enabled_func_idx;
2334 *p_resc_num = resc_info.size;
2335 *p_resc_start = resc_info.offset;
2337 if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2339 "Resource %d [%s]: MFW allocation [num %d, start %d] differs from default values [num %d, start %d]%s\n",
2340 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2341 *p_resc_start, dflt_resc_num, dflt_resc_start,
2342 drv_resc_alloc ? " - Applying default values" : "");
2343 if (drv_resc_alloc) {
2344 *p_resc_num = dflt_resc_num;
2345 *p_resc_start = dflt_resc_start;
2349 return ECORE_SUCCESS;
2352 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2353 bool drv_resc_alloc)
2355 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2356 enum _ecore_status_t rc;
2359 u32 *resc_start = p_hwfn->hw_info.resc_start;
2360 u32 *resc_num = p_hwfn->hw_info.resc_num;
2361 /* For AH, an equal share of the ILT lines between the maximal number of
2362 * PFs is not enough for RoCE. This would be solved by the future
2363 * resource allocation scheme, but isn't currently present for
2364 * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2365 * to work - the BB number of ILT lines divided by its max PFs number.
2367 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2370 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2371 rc = ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2372 if (rc != ECORE_SUCCESS)
2377 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2378 /* Reduced build contains less PQs */
2379 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2380 resc_num[ECORE_PQ] = 32;
2381 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2382 p_hwfn->enabled_func_idx;
2385 /* For AH emulation, since we have a possible maximal number of
2386 * 16 enabled PFs, in case there are not enough ILT lines -
2387 * allocate only first PF as RoCE and have all the other ETH
2388 * only with less ILT lines.
2390 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2391 resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2392 resc_num[ECORE_ILT],
2393 roce_min_ilt_lines);
2396 /* Correct the common ILT calculation if PF0 has more */
2397 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2398 p_hwfn->p_dev->b_is_emul_full &&
2399 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2400 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2401 resc_num[ECORE_ILT];
2404 /* Sanity for ILT */
2405 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2406 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2407 DP_NOTICE(p_hwfn, true,
2408 "Can't assign ILT pages [%08x,...,%08x]\n",
2409 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2415 ecore_hw_set_feat(p_hwfn);
2417 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2418 "The numbers for each resource are:\n");
2419 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2420 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2421 ecore_hw_get_resc_name(res_id),
2422 RESC_NUM(p_hwfn, res_id),
2423 RESC_START(p_hwfn, res_id));
2425 return ECORE_SUCCESS;
2428 static enum _ecore_status_t ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2429 struct ecore_ptt *p_ptt)
2431 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
2432 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2433 struct ecore_mcp_link_params *link;
2435 /* Read global nvm_cfg address */
2436 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2438 /* Verify MCP has initialized it */
2439 if (!nvm_cfg_addr) {
2440 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2444 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
2446 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2448 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2449 OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2452 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2454 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2455 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2456 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2457 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2459 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2460 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2462 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2463 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2465 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2466 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2468 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2469 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2471 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2472 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2474 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2475 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2477 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2478 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2480 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2481 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
2483 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2484 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2486 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2487 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2490 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2495 /* Read DCBX configuration */
2496 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2497 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2498 dcbx_mode = ecore_rd(p_hwfn, p_ptt,
2500 OFFSETOF(struct nvm_cfg1_port, generic_cont0));
2501 dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
2502 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
2503 switch (dcbx_mode) {
2504 case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
2505 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
2507 case NVM_CFG1_PORT_DCBX_MODE_CEE:
2508 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
2510 case NVM_CFG1_PORT_DCBX_MODE_IEEE:
2511 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
2514 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
2517 /* Read default link configuration */
2518 link = &p_hwfn->mcp_info->link_input;
2519 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2520 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2521 link_temp = ecore_rd(p_hwfn, p_ptt,
2523 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2524 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2525 link->speed.advertised_speeds = link_temp;
2527 link_temp = link->speed.advertised_speeds;
2528 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2530 link_temp = ecore_rd(p_hwfn, p_ptt,
2532 OFFSETOF(struct nvm_cfg1_port, link_settings));
2533 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2534 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2535 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2536 link->speed.autoneg = true;
2538 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2539 link->speed.forced_speed = 1000;
2541 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2542 link->speed.forced_speed = 10000;
2544 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2545 link->speed.forced_speed = 25000;
2547 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2548 link->speed.forced_speed = 40000;
2550 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2551 link->speed.forced_speed = 50000;
2553 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2554 link->speed.forced_speed = 100000;
2557 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
2560 p_hwfn->mcp_info->link_capabilities.default_speed =
2561 link->speed.forced_speed;
2562 p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2563 link->speed.autoneg;
2565 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2566 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2567 link->pause.autoneg = !!(link_temp &
2568 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2569 link->pause.forced_rx = !!(link_temp &
2570 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2571 link->pause.forced_tx = !!(link_temp &
2572 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2573 link->loopback_mode = 0;
2575 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2576 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2577 link->speed.forced_speed, link->speed.advertised_speeds,
2578 link->speed.autoneg, link->pause.autoneg);
2580 /* Read Multi-function information from shmem */
2581 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2582 OFFSETOF(struct nvm_cfg1, glob) +
2583 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
2585 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
2587 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2588 NVM_CFG1_GLOB_MF_MODE_OFFSET;
2591 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2592 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
2594 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2595 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
2597 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2598 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
2601 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2602 p_hwfn->p_dev->mf_mode);
2604 /* Read Multi-function information from shmem */
2605 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2606 OFFSETOF(struct nvm_cfg1, glob) +
2607 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
2609 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
2610 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2611 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
2612 &p_hwfn->hw_info.device_capabilities);
2613 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2614 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
2615 &p_hwfn->hw_info.device_capabilities);
2616 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2617 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
2618 &p_hwfn->hw_info.device_capabilities);
2619 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2620 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
2621 &p_hwfn->hw_info.device_capabilities);
2622 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
2623 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
2624 &p_hwfn->hw_info.device_capabilities);
2626 return ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2629 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
2630 struct ecore_ptt *p_ptt)
2632 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2633 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2634 struct ecore_dev *p_dev = p_hwfn->p_dev;
2636 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2638 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2639 * in the other bits are selected.
2640 * Bits 1-15 are for functions 1-15, respectively, and their value is
2641 * '0' only for enabled functions (function 0 always exists and
2643 * In case of CMT in BB, only the "even" functions are enabled, and thus
2644 * the number of functions for both hwfns is learnt from the same bits.
2646 reg_function_hide = ecore_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2648 if (reg_function_hide & 0x1) {
2649 if (ECORE_IS_BB(p_dev)) {
2650 if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
2662 /* Get the number of the enabled functions on the engine */
2663 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2670 /* Get the PF index within the enabled functions */
2671 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2672 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2680 p_hwfn->num_funcs_on_engine = num_funcs;
2681 p_hwfn->enabled_func_idx = enabled_func_idx;
2684 if (CHIP_REV_IS_FPGA(p_dev)) {
2685 DP_NOTICE(p_hwfn, false,
2686 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
2687 p_hwfn->num_funcs_on_engine = 4;
2691 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2692 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2693 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
2694 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2697 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
2698 struct ecore_ptt *p_ptt)
2703 /* Read the port mode */
2704 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
2706 else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
2707 (p_hwfn->p_dev->num_hwfns > 1))
2708 /* In CMT on emulation, assume 1 port */
2712 port_mode = ecore_rd(p_hwfn, p_ptt,
2713 CNIG_REG_NW_PORT_MODE_BB_B0);
2715 if (port_mode < 3) {
2716 p_hwfn->p_dev->num_ports_in_engines = 1;
2717 } else if (port_mode <= 5) {
2718 p_hwfn->p_dev->num_ports_in_engines = 2;
2720 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
2721 p_hwfn->p_dev->num_ports_in_engines);
2723 /* Default num_ports_in_engines to something */
2724 p_hwfn->p_dev->num_ports_in_engines = 1;
2728 static void ecore_hw_info_port_num_ah(struct ecore_hwfn *p_hwfn,
2729 struct ecore_ptt *p_ptt)
2734 p_hwfn->p_dev->num_ports_in_engines = 0;
2737 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2738 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
2739 switch ((port & 0xf000) >> 12) {
2741 p_hwfn->p_dev->num_ports_in_engines = 1;
2744 p_hwfn->p_dev->num_ports_in_engines = 2;
2747 p_hwfn->p_dev->num_ports_in_engines = 4;
2750 DP_NOTICE(p_hwfn, false,
2751 "Unknown port mode in ECO_RESERVED %08x\n",
2756 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2757 port = ecore_rd(p_hwfn, p_ptt,
2758 CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2760 p_hwfn->p_dev->num_ports_in_engines++;
2764 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
2765 struct ecore_ptt *p_ptt)
2767 if (ECORE_IS_BB(p_hwfn->p_dev))
2768 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
2770 ecore_hw_info_port_num_ah(p_hwfn, p_ptt);
2773 static enum _ecore_status_t
2774 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2775 enum ecore_pci_personality personality, bool drv_resc_alloc)
2777 enum _ecore_status_t rc;
2779 /* Since all information is common, only first hwfns should do this */
2780 if (IS_LEAD_HWFN(p_hwfn)) {
2781 rc = ecore_iov_hw_info(p_hwfn);
2782 if (rc != ECORE_SUCCESS)
2786 /* TODO In get_hw_info, amoungst others:
2787 * Get MCP FW revision and determine according to it the supported
2788 * featrues (e.g. DCB)
2790 * ecore_get_pcie_width_speed, WOL capability.
2791 * Number of global CQ-s (for storage
2793 ecore_hw_info_port_num(p_hwfn, p_ptt);
2796 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
2798 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt);
2799 if (rc != ECORE_SUCCESS)
2805 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
2806 if (rc != ECORE_SUCCESS)
2810 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
2812 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
2813 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
2816 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
2818 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
2819 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
2823 if (ecore_mcp_is_init(p_hwfn)) {
2824 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
2825 p_hwfn->hw_info.ovlan =
2826 p_hwfn->mcp_info->func_info.ovlan;
2828 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
2831 if (personality != ECORE_PCI_DEFAULT) {
2832 p_hwfn->hw_info.personality = personality;
2833 } else if (ecore_mcp_is_init(p_hwfn)) {
2834 enum ecore_pci_personality protocol;
2836 protocol = p_hwfn->mcp_info->func_info.protocol;
2837 p_hwfn->hw_info.personality = protocol;
2841 /* To overcome ILT lack for emulation, until at least until we'll have
2842 * a definite answer from system about it, allow only PF0 to be RoCE.
2844 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
2845 if (!p_hwfn->rel_pf_id)
2846 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
2848 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
2852 /* although in BB some constellations may support more than 4 tcs,
2853 * that can result in performance penalty in some cases. 4
2854 * represents a good tradeoff between performance and flexibility.
2856 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2858 /* start out with a single active tc. This can be increased either
2859 * by dcbx negotiation or by upper layer driver
2861 p_hwfn->hw_info.num_active_tc = 1;
2863 ecore_get_num_funcs(p_hwfn, p_ptt);
2865 /* In case of forcing the driver's default resource allocation, calling
2866 * ecore_hw_get_resc() should come after initializing the personality
2867 * and after getting the number of functions, since the calculation of
2868 * the resources/features depends on them.
2869 * This order is not harmful if not forcing.
2871 return ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
2874 #define ECORE_DEV_ID_MASK 0xff00
2875 #define ECORE_DEV_ID_MASK_BB 0x1600
2876 #define ECORE_DEV_ID_MASK_AH 0x8000
2878 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
2880 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2883 /* Read Vendor Id / Device Id */
2884 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
2886 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
2889 /* Determine type */
2890 if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
2891 p_dev->type = ECORE_DEV_TYPE_AH;
2893 p_dev->type = ECORE_DEV_TYPE_BB;
2895 p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2896 MISCS_REG_CHIP_NUM);
2897 p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2898 MISCS_REG_CHIP_REV);
2900 MASK_FIELD(CHIP_REV, p_dev->chip_rev);
2902 /* Learn number of HW-functions */
2903 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2904 MISCS_REG_CMT_ENABLED_FOR_PAIR);
2906 if (tmp & (1 << p_hwfn->rel_pf_id)) {
2907 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
2908 p_dev->num_hwfns = 2;
2910 p_dev->num_hwfns = 1;
2914 if (CHIP_REV_IS_EMUL(p_dev)) {
2915 /* For some reason we have problems with this register
2916 * in B0 emulation; Simply assume no CMT
2918 DP_NOTICE(p_dev->hwfns, false,
2919 "device on emul - assume no CMT\n");
2920 p_dev->num_hwfns = 1;
2924 p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2925 MISCS_REG_CHIP_TEST_REG) >> 4;
2926 MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
2927 p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2928 MISCS_REG_CHIP_METAL);
2929 MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
2930 DP_INFO(p_dev->hwfns,
2931 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2932 ECORE_IS_BB(p_dev) ? "BB" : "AH",
2933 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
2934 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
2937 if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
2938 DP_NOTICE(p_dev->hwfns, false,
2939 "The chip type/rev (BB A0) is not supported!\n");
2940 return ECORE_ABORTED;
2943 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
2944 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2945 MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
2947 if (CHIP_REV_IS_EMUL(p_dev)) {
2948 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2949 MISCS_REG_ECO_RESERVED);
2950 if (tmp & (1 << 29)) {
2951 DP_NOTICE(p_hwfn, false,
2952 "Emulation: Running on a FULL build\n");
2953 p_dev->b_is_emul_full = true;
2955 DP_NOTICE(p_hwfn, false,
2956 "Emulation: Running on a REDUCED build\n");
2961 return ECORE_SUCCESS;
2964 #ifndef LINUX_REMOVE
2965 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
2972 for_each_hwfn(p_dev, j) {
2973 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2975 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2976 "Mark hw/fw uninitialized\n");
2978 p_hwfn->hw_init_done = false;
2979 p_hwfn->first_on_engine = false;
2981 ecore_ptt_invalidate(p_hwfn);
2986 static enum _ecore_status_t
2987 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
2988 void OSAL_IOMEM * p_regview,
2989 void OSAL_IOMEM * p_doorbells,
2990 struct ecore_hw_prepare_params *p_params)
2992 struct ecore_dev *p_dev = p_hwfn->p_dev;
2993 struct ecore_mdump_info mdump_info;
2994 enum _ecore_status_t rc = ECORE_SUCCESS;
2996 /* Split PCI bars evenly between hwfns */
2997 p_hwfn->regview = p_regview;
2998 p_hwfn->doorbells = p_doorbells;
3001 return ecore_vf_hw_prepare(p_hwfn);
3003 /* Validate that chip access is feasible */
3004 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3006 "Reading the ME register returns all Fs; Preventing further chip access\n");
3010 get_function_id(p_hwfn);
3012 /* Allocate PTT pool */
3013 rc = ecore_ptt_pool_alloc(p_hwfn);
3015 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
3019 /* Allocate the main PTT */
3020 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3022 /* First hwfn learns basic information, e.g., number of hwfns */
3023 if (!p_hwfn->my_id) {
3024 rc = ecore_get_dev_info(p_dev);
3025 if (rc != ECORE_SUCCESS)
3029 ecore_hw_hwfn_prepare(p_hwfn);
3031 /* Initialize MCP structure */
3032 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3034 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3038 /* Read the device configuration information from the HW and SHMEM */
3039 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3040 p_params->personality, p_params->drv_resc_alloc);
3042 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3046 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3047 * called, since among others it sets the ports number in an engine.
3049 if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3050 !p_dev->recov_in_prog) {
3051 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3052 if (rc != ECORE_SUCCESS)
3053 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3056 /* Check if mdump logs are present and update the epoch value */
3057 if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) {
3058 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3060 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) {
3061 DP_NOTICE(p_hwfn, false,
3062 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3065 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3069 /* Allocate the init RT array and initialize the init-ops engine */
3070 rc = ecore_init_alloc(p_hwfn);
3072 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3076 if (CHIP_REV_IS_FPGA(p_dev)) {
3077 DP_NOTICE(p_hwfn, false,
3078 "FPGA: workaround; Prevent DMAE parities\n");
3079 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK, 7);
3081 DP_NOTICE(p_hwfn, false,
3082 "FPGA: workaround: Set VF bar0 size\n");
3083 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3084 PGLUE_B_REG_VF_BAR0_SIZE, 4);
3090 if (IS_LEAD_HWFN(p_hwfn))
3091 ecore_iov_free_hw_info(p_dev);
3092 ecore_mcp_free(p_hwfn);
3094 ecore_hw_hwfn_free(p_hwfn);
3099 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3100 struct ecore_hw_prepare_params *p_params)
3102 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3103 enum _ecore_status_t rc;
3105 p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3107 /* Store the precompiled init data ptrs */
3109 ecore_init_iro_array(p_dev);
3111 /* Initialize the first hwfn - will learn number of hwfns */
3112 rc = ecore_hw_prepare_single(p_hwfn,
3114 p_dev->doorbells, p_params);
3115 if (rc != ECORE_SUCCESS)
3118 p_params->personality = p_hwfn->hw_info.personality;
3120 /* initilalize 2nd hwfn if necessary */
3121 if (p_dev->num_hwfns > 1) {
3122 void OSAL_IOMEM *p_regview, *p_doorbell;
3123 u8 OSAL_IOMEM *addr;
3125 /* adjust bar offset for second engine */
3126 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3127 ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3128 p_regview = (void OSAL_IOMEM *)addr;
3130 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3131 ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3132 p_doorbell = (void OSAL_IOMEM *)addr;
3134 /* prepare second hw function */
3135 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3136 p_doorbell, p_params);
3138 /* in case of error, need to free the previously
3139 * initiliazed hwfn 0.
3141 if (rc != ECORE_SUCCESS) {
3143 ecore_init_free(p_hwfn);
3144 ecore_mcp_free(p_hwfn);
3145 ecore_hw_hwfn_free(p_hwfn);
3147 DP_NOTICE(p_dev, true,
3148 "What do we need to free when VF hwfn1 init fails\n");
3157 void ecore_hw_remove(struct ecore_dev *p_dev)
3159 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3163 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3164 ECORE_OV_DRIVER_STATE_NOT_LOADED);
3166 for_each_hwfn(p_dev, i) {
3167 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3170 ecore_vf_pf_release(p_hwfn);
3174 ecore_init_free(p_hwfn);
3175 ecore_hw_hwfn_free(p_hwfn);
3176 ecore_mcp_free(p_hwfn);
3178 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3181 ecore_iov_free_hw_info(p_dev);
3184 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3185 struct ecore_chain *p_chain)
3187 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3188 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3189 struct ecore_chain_next *p_next;
3195 size = p_chain->elem_size * p_chain->usable_per_page;
3197 for (i = 0; i < p_chain->page_cnt; i++) {
3201 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3202 p_virt_next = p_next->next_virt;
3203 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3205 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3206 ECORE_CHAIN_PAGE_SIZE);
3208 p_virt = p_virt_next;
3209 p_phys = p_phys_next;
3213 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3214 struct ecore_chain *p_chain)
3216 if (!p_chain->p_virt_addr)
3219 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3220 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3223 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3224 struct ecore_chain *p_chain)
3226 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3227 u8 *p_pbl_virt = (u8 *)p_chain->pbl.p_virt_table;
3228 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3230 if (!pp_virt_addr_tbl)
3233 if (!p_chain->pbl.p_virt_table)
3236 for (i = 0; i < page_cnt; i++) {
3237 if (!pp_virt_addr_tbl[i])
3240 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3241 *(dma_addr_t *)p_pbl_virt,
3242 ECORE_CHAIN_PAGE_SIZE);
3244 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3247 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3249 if (!p_chain->pbl.external)
3250 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table,
3251 p_chain->pbl.p_phys_table, pbl_size);
3253 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3256 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3258 switch (p_chain->mode) {
3259 case ECORE_CHAIN_MODE_NEXT_PTR:
3260 ecore_chain_free_next_ptr(p_dev, p_chain);
3262 case ECORE_CHAIN_MODE_SINGLE:
3263 ecore_chain_free_single(p_dev, p_chain);
3265 case ECORE_CHAIN_MODE_PBL:
3266 ecore_chain_free_pbl(p_dev, p_chain);
3271 static enum _ecore_status_t
3272 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3273 enum ecore_chain_cnt_type cnt_type,
3274 osal_size_t elem_size, u32 page_cnt)
3276 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3278 /* The actual chain size can be larger than the maximal possible value
3279 * after rounding up the requested elements number to pages, and after
3280 * taking into acount the unusuable elements (next-ptr elements).
3281 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3282 * size/capacity fields are of a u32 type.
3284 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3285 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3286 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3287 chain_size > ECORE_U32_MAX)) {
3288 DP_NOTICE(p_dev, true,
3289 "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3290 (unsigned long)chain_size);
3294 return ECORE_SUCCESS;
3297 static enum _ecore_status_t
3298 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3300 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3301 dma_addr_t p_phys = 0;
3304 for (i = 0; i < p_chain->page_cnt; i++) {
3305 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3306 ECORE_CHAIN_PAGE_SIZE);
3308 DP_NOTICE(p_dev, true,
3309 "Failed to allocate chain memory\n");
3314 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3315 ecore_chain_reset(p_chain);
3317 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3321 p_virt_prev = p_virt;
3323 /* Last page's next element should point to the beginning of the
3326 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3327 p_chain->p_virt_addr,
3328 p_chain->p_phys_addr);
3330 return ECORE_SUCCESS;
3333 static enum _ecore_status_t
3334 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3336 dma_addr_t p_phys = 0;
3337 void *p_virt = OSAL_NULL;
3339 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3341 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3345 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3346 ecore_chain_reset(p_chain);
3348 return ECORE_SUCCESS;
3351 static enum _ecore_status_t
3352 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3353 struct ecore_chain *p_chain,
3354 struct ecore_chain_ext_pbl *ext_pbl)
3356 void *p_virt = OSAL_NULL;
3357 u8 *p_pbl_virt = OSAL_NULL;
3358 void **pp_virt_addr_tbl = OSAL_NULL;
3359 dma_addr_t p_phys = 0, p_pbl_phys = 0;
3360 u32 page_cnt = p_chain->page_cnt, size, i;
3362 size = page_cnt * sizeof(*pp_virt_addr_tbl);
3363 pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
3364 if (!pp_virt_addr_tbl) {
3365 DP_NOTICE(p_dev, true,
3366 "Failed to allocate memory for the chain virtual addresses table\n");
3369 OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
3371 /* The allocation of the PBL table is done with its full size, since it
3372 * is expected to be successive.
3373 * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3374 * failure, since pp_virt_addr_tbl was previously allocated, and it
3375 * should be saved to allow its freeing during the error flow.
3377 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3379 if (ext_pbl == OSAL_NULL) {
3380 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3382 p_pbl_virt = ext_pbl->p_pbl_virt;
3383 p_pbl_phys = ext_pbl->p_pbl_phys;
3384 p_chain->pbl.external = true;
3387 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3390 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3394 for (i = 0; i < page_cnt; i++) {
3395 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3396 ECORE_CHAIN_PAGE_SIZE);
3398 DP_NOTICE(p_dev, true,
3399 "Failed to allocate chain memory\n");
3404 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3405 ecore_chain_reset(p_chain);
3408 /* Fill the PBL table with the physical address of the page */
3409 *(dma_addr_t *)p_pbl_virt = p_phys;
3410 /* Keep the virtual address of the page */
3411 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3413 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3416 return ECORE_SUCCESS;
3419 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3420 enum ecore_chain_use_mode intended_use,
3421 enum ecore_chain_mode mode,
3422 enum ecore_chain_cnt_type cnt_type,
3423 u32 num_elems, osal_size_t elem_size,
3424 struct ecore_chain *p_chain,
3425 struct ecore_chain_ext_pbl *ext_pbl)
3428 enum _ecore_status_t rc = ECORE_SUCCESS;
3430 if (mode == ECORE_CHAIN_MODE_SINGLE)
3433 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3435 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3438 DP_NOTICE(p_dev, true,
3439 "Cannot allocate a chain with the given arguments:\n"
3440 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3441 intended_use, mode, cnt_type, num_elems, elem_size);
3445 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3446 mode, cnt_type, p_dev->dp_ctx);
3449 case ECORE_CHAIN_MODE_NEXT_PTR:
3450 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3452 case ECORE_CHAIN_MODE_SINGLE:
3453 rc = ecore_chain_alloc_single(p_dev, p_chain);
3455 case ECORE_CHAIN_MODE_PBL:
3456 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
3462 return ECORE_SUCCESS;
3465 ecore_chain_free(p_dev, p_chain);
3469 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3470 u16 src_id, u16 *dst_id)
3472 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3475 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3476 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3477 DP_NOTICE(p_hwfn, true,
3478 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3484 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3486 return ECORE_SUCCESS;
3489 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3490 u8 src_id, u8 *dst_id)
3492 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3495 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3496 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3497 DP_NOTICE(p_hwfn, true,
3498 "vport id [%d] is not valid, available indices [%d - %d]\n",
3504 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3506 return ECORE_SUCCESS;
3509 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
3510 u8 src_id, u8 *dst_id)
3512 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
3515 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
3516 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
3517 DP_NOTICE(p_hwfn, true,
3518 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3524 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
3526 return ECORE_SUCCESS;
3529 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
3530 struct ecore_ptt *p_ptt,
3536 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3537 return ECORE_SUCCESS;
3539 high = p_filter[1] | (p_filter[0] << 8);
3540 low = p_filter[5] | (p_filter[4] << 8) |
3541 (p_filter[3] << 16) | (p_filter[2] << 24);
3543 /* Find a free entry and utilize it */
3544 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3545 en = ecore_rd(p_hwfn, p_ptt,
3546 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3549 ecore_wr(p_hwfn, p_ptt,
3550 NIG_REG_LLH_FUNC_FILTER_VALUE +
3551 2 * i * sizeof(u32), low);
3552 ecore_wr(p_hwfn, p_ptt,
3553 NIG_REG_LLH_FUNC_FILTER_VALUE +
3554 (2 * i + 1) * sizeof(u32), high);
3555 ecore_wr(p_hwfn, p_ptt,
3556 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3557 ecore_wr(p_hwfn, p_ptt,
3558 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3559 i * sizeof(u32), 0);
3560 ecore_wr(p_hwfn, p_ptt,
3561 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3564 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3565 DP_NOTICE(p_hwfn, false,
3566 "Failed to find an empty LLH filter to utilize\n");
3570 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3571 "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
3572 p_filter[0], p_filter[1], p_filter[2],
3573 p_filter[3], p_filter[4], p_filter[5], i);
3575 return ECORE_SUCCESS;
3578 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
3579 struct ecore_ptt *p_ptt, u8 *p_filter)
3584 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3587 high = p_filter[1] | (p_filter[0] << 8);
3588 low = p_filter[5] | (p_filter[4] << 8) |
3589 (p_filter[3] << 16) | (p_filter[2] << 24);
3591 /* Find the entry and clean it */
3592 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3593 if (ecore_rd(p_hwfn, p_ptt,
3594 NIG_REG_LLH_FUNC_FILTER_VALUE +
3595 2 * i * sizeof(u32)) != low)
3597 if (ecore_rd(p_hwfn, p_ptt,
3598 NIG_REG_LLH_FUNC_FILTER_VALUE +
3599 (2 * i + 1) * sizeof(u32)) != high)
3602 ecore_wr(p_hwfn, p_ptt,
3603 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3604 ecore_wr(p_hwfn, p_ptt,
3605 NIG_REG_LLH_FUNC_FILTER_VALUE +
3606 2 * i * sizeof(u32), 0);
3607 ecore_wr(p_hwfn, p_ptt,
3608 NIG_REG_LLH_FUNC_FILTER_VALUE +
3609 (2 * i + 1) * sizeof(u32), 0);
3612 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3613 DP_NOTICE(p_hwfn, false,
3614 "Tried to remove a non-configured filter\n");
3617 enum _ecore_status_t
3618 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
3619 struct ecore_ptt *p_ptt,
3620 u16 source_port_or_eth_type,
3622 enum ecore_llh_port_filter_type_t type)
3627 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3628 return ECORE_SUCCESS;
3633 case ECORE_LLH_FILTER_ETHERTYPE:
3634 high = source_port_or_eth_type;
3636 case ECORE_LLH_FILTER_TCP_SRC_PORT:
3637 case ECORE_LLH_FILTER_UDP_SRC_PORT:
3638 low = source_port_or_eth_type << 16;
3640 case ECORE_LLH_FILTER_TCP_DEST_PORT:
3641 case ECORE_LLH_FILTER_UDP_DEST_PORT:
3644 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3645 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3646 low = (source_port_or_eth_type << 16) | dest_port;
3649 DP_NOTICE(p_hwfn, true,
3650 "Non valid LLH protocol filter type %d\n", type);
3653 /* Find a free entry and utilize it */
3654 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3655 en = ecore_rd(p_hwfn, p_ptt,
3656 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3659 ecore_wr(p_hwfn, p_ptt,
3660 NIG_REG_LLH_FUNC_FILTER_VALUE +
3661 2 * i * sizeof(u32), low);
3662 ecore_wr(p_hwfn, p_ptt,
3663 NIG_REG_LLH_FUNC_FILTER_VALUE +
3664 (2 * i + 1) * sizeof(u32), high);
3665 ecore_wr(p_hwfn, p_ptt,
3666 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3667 ecore_wr(p_hwfn, p_ptt,
3668 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3669 i * sizeof(u32), 1 << type);
3670 ecore_wr(p_hwfn, p_ptt,
3671 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3674 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3675 DP_NOTICE(p_hwfn, false,
3676 "Failed to find an empty LLH filter to utilize\n");
3677 return ECORE_NORESOURCES;
3680 case ECORE_LLH_FILTER_ETHERTYPE:
3681 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3682 "ETH type %x is added at %d\n",
3683 source_port_or_eth_type, i);
3685 case ECORE_LLH_FILTER_TCP_SRC_PORT:
3686 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3687 "TCP src port %x is added at %d\n",
3688 source_port_or_eth_type, i);
3690 case ECORE_LLH_FILTER_UDP_SRC_PORT:
3691 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3692 "UDP src port %x is added at %d\n",
3693 source_port_or_eth_type, i);
3695 case ECORE_LLH_FILTER_TCP_DEST_PORT:
3696 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3697 "TCP dst port %x is added at %d\n", dest_port, i);
3699 case ECORE_LLH_FILTER_UDP_DEST_PORT:
3700 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3701 "UDP dst port %x is added at %d\n", dest_port, i);
3703 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3704 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3705 "TCP src/dst ports %x/%x are added at %d\n",
3706 source_port_or_eth_type, dest_port, i);
3708 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3709 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3710 "UDP src/dst ports %x/%x are added at %d\n",
3711 source_port_or_eth_type, dest_port, i);
3714 return ECORE_SUCCESS;
3718 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
3719 struct ecore_ptt *p_ptt,
3720 u16 source_port_or_eth_type,
3722 enum ecore_llh_port_filter_type_t type)
3727 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3733 case ECORE_LLH_FILTER_ETHERTYPE:
3734 high = source_port_or_eth_type;
3736 case ECORE_LLH_FILTER_TCP_SRC_PORT:
3737 case ECORE_LLH_FILTER_UDP_SRC_PORT:
3738 low = source_port_or_eth_type << 16;
3740 case ECORE_LLH_FILTER_TCP_DEST_PORT:
3741 case ECORE_LLH_FILTER_UDP_DEST_PORT:
3744 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3745 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3746 low = (source_port_or_eth_type << 16) | dest_port;
3749 DP_NOTICE(p_hwfn, true,
3750 "Non valid LLH protocol filter type %d\n", type);
3754 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3755 if (!ecore_rd(p_hwfn, p_ptt,
3756 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3758 if (!ecore_rd(p_hwfn, p_ptt,
3759 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3761 if (!(ecore_rd(p_hwfn, p_ptt,
3762 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3763 i * sizeof(u32)) & (1 << type)))
3765 if (ecore_rd(p_hwfn, p_ptt,
3766 NIG_REG_LLH_FUNC_FILTER_VALUE +
3767 2 * i * sizeof(u32)) != low)
3769 if (ecore_rd(p_hwfn, p_ptt,
3770 NIG_REG_LLH_FUNC_FILTER_VALUE +
3771 (2 * i + 1) * sizeof(u32)) != high)
3774 ecore_wr(p_hwfn, p_ptt,
3775 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3776 ecore_wr(p_hwfn, p_ptt,
3777 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3778 ecore_wr(p_hwfn, p_ptt,
3779 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3780 i * sizeof(u32), 0);
3781 ecore_wr(p_hwfn, p_ptt,
3782 NIG_REG_LLH_FUNC_FILTER_VALUE +
3783 2 * i * sizeof(u32), 0);
3784 ecore_wr(p_hwfn, p_ptt,
3785 NIG_REG_LLH_FUNC_FILTER_VALUE +
3786 (2 * i + 1) * sizeof(u32), 0);
3790 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3791 DP_NOTICE(p_hwfn, false,
3792 "Tried to remove a non-configured filter\n");
3795 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
3796 struct ecore_ptt *p_ptt)
3800 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3803 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3804 ecore_wr(p_hwfn, p_ptt,
3805 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3806 ecore_wr(p_hwfn, p_ptt,
3807 NIG_REG_LLH_FUNC_FILTER_VALUE +
3808 2 * i * sizeof(u32), 0);
3809 ecore_wr(p_hwfn, p_ptt,
3810 NIG_REG_LLH_FUNC_FILTER_VALUE +
3811 (2 * i + 1) * sizeof(u32), 0);
3815 enum _ecore_status_t
3816 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
3817 struct ecore_ptt *p_ptt)
3819 if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
3820 ecore_wr(p_hwfn, p_ptt,
3821 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
3822 1 << p_hwfn->abs_pf_id / 2);
3823 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
3824 return ECORE_SUCCESS;
3827 DP_NOTICE(p_hwfn, false,
3828 "This function can't be set as default\n");
3832 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
3833 struct ecore_ptt *p_ptt,
3834 u32 hw_addr, void *p_eth_qzone,
3835 osal_size_t eth_qzone_size,
3838 struct coalescing_timeset *p_coal_timeset;
3840 if (IS_VF(p_hwfn->p_dev)) {
3841 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n");
3845 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
3846 DP_NOTICE(p_hwfn, true,
3847 "Coalescing configuration not enabled\n");
3851 p_coal_timeset = p_eth_qzone;
3852 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
3853 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3854 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3855 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3857 return ECORE_SUCCESS;
3860 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
3861 struct ecore_ptt *p_ptt,
3862 u16 coalesce, u8 qid, u16 sb_id)
3864 struct ustorm_eth_queue_zone eth_qzone;
3865 u8 timeset, timer_res;
3868 enum _ecore_status_t rc;
3870 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3871 if (coalesce <= 0x7F) {
3873 } else if (coalesce <= 0xFF) {
3875 } else if (coalesce <= 0x1FF) {
3878 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3881 timeset = (u8)(coalesce >> timer_res);
3883 rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3884 if (rc != ECORE_SUCCESS)
3887 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
3888 if (rc != ECORE_SUCCESS)
3891 address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3893 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
3894 sizeof(struct ustorm_eth_queue_zone), timeset);
3895 if (rc != ECORE_SUCCESS)
3898 p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
3903 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
3904 struct ecore_ptt *p_ptt,
3905 u16 coalesce, u8 qid, u16 sb_id)
3907 struct xstorm_eth_queue_zone eth_qzone;
3908 u8 timeset, timer_res;
3911 enum _ecore_status_t rc;
3913 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3914 if (coalesce <= 0x7F) {
3916 } else if (coalesce <= 0xFF) {
3918 } else if (coalesce <= 0x1FF) {
3921 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3925 timeset = (u8)(coalesce >> timer_res);
3927 rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3928 if (rc != ECORE_SUCCESS)
3931 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
3932 if (rc != ECORE_SUCCESS)
3935 address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3937 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
3938 sizeof(struct xstorm_eth_queue_zone), timeset);
3939 if (rc != ECORE_SUCCESS)
3942 p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
3947 /* Calculate final WFQ values for all vports and configure it.
3948 * After this configuration each vport must have
3949 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
3951 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3952 struct ecore_ptt *p_ptt,
3955 struct init_qm_vport_params *vport_params;
3958 vport_params = p_hwfn->qm_info.qm_vport_params;
3960 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3961 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3963 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
3965 ecore_init_vport_wfq(p_hwfn, p_ptt,
3966 vport_params[i].first_tx_pq_id,
3967 vport_params[i].vport_wfq);
3972 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
3976 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3977 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3980 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3981 struct ecore_ptt *p_ptt,
3984 struct init_qm_vport_params *vport_params;
3987 vport_params = p_hwfn->qm_info.qm_vport_params;
3989 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3990 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
3991 ecore_init_vport_wfq(p_hwfn, p_ptt,
3992 vport_params[i].first_tx_pq_id,
3993 vport_params[i].vport_wfq);
3997 /* This function performs several validations for WFQ
3998 * configuration and required min rate for a given vport
3999 * 1. req_rate must be greater than one percent of min_pf_rate.
4000 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4001 * rates to get less than one percent of min_pf_rate.
4002 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4004 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
4005 u16 vport_id, u32 req_rate,
4008 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4009 int non_requested_count = 0, req_count = 0, i, num_vports;
4011 num_vports = p_hwfn->qm_info.num_vports;
4013 /* Accounting for the vports which are configured for WFQ explicitly */
4015 for (i = 0; i < num_vports; i++) {
4018 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
4020 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4021 total_req_min_rate += tmp_speed;
4025 /* Include current vport data as well */
4027 total_req_min_rate += req_rate;
4028 non_requested_count = num_vports - req_count;
4030 /* validate possible error cases */
4031 if (req_rate > min_pf_rate) {
4032 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4033 "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4034 vport_id, req_rate, min_pf_rate);
4038 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
4039 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4040 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4041 vport_id, req_rate, min_pf_rate);
4045 /* TBD - for number of vports greater than 100 */
4046 if (num_vports > ECORE_WFQ_UNIT) {
4047 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4048 "Number of vports is greater than %d\n",
4053 if (total_req_min_rate > min_pf_rate) {
4054 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4055 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4056 total_req_min_rate, min_pf_rate);
4060 /* Data left for non requested vports */
4061 total_left_rate = min_pf_rate - total_req_min_rate;
4062 left_rate_per_vp = total_left_rate / non_requested_count;
4064 /* validate if non requested get < 1% of min bw */
4065 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4066 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4067 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4068 left_rate_per_vp, min_pf_rate);
4072 /* now req_rate for given vport passes all scenarios.
4073 * assign final wfq rates to all vports.
4075 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4076 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4078 for (i = 0; i < num_vports; i++) {
4079 if (p_hwfn->qm_info.wfq_data[i].configured)
4082 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4085 return ECORE_SUCCESS;
4088 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4089 struct ecore_ptt *p_ptt,
4090 u16 vp_id, u32 rate)
4092 struct ecore_mcp_link_state *p_link;
4093 int rc = ECORE_SUCCESS;
4095 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4097 if (!p_link->min_pf_rate) {
4098 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4099 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4103 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4105 if (rc == ECORE_SUCCESS)
4106 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4107 p_link->min_pf_rate);
4109 DP_NOTICE(p_hwfn, false,
4110 "Validation failed while configuring min rate\n");
4115 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4116 struct ecore_ptt *p_ptt,
4119 bool use_wfq = false;
4120 int rc = ECORE_SUCCESS;
4123 /* Validate all pre configured vports for wfq */
4124 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4127 if (!p_hwfn->qm_info.wfq_data[i].configured)
4130 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4133 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4134 if (rc != ECORE_SUCCESS) {
4135 DP_NOTICE(p_hwfn, false,
4136 "WFQ validation failed while configuring min rate\n");
4141 if (rc == ECORE_SUCCESS && use_wfq)
4142 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4144 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4149 /* Main API for ecore clients to configure vport min rate.
4150 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4151 * rate - Speed in Mbps needs to be assigned to a given vport.
4153 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4155 int i, rc = ECORE_INVAL;
4157 /* TBD - for multiple hardware functions - that is 100 gig */
4158 if (p_dev->num_hwfns > 1) {
4159 DP_NOTICE(p_dev, false,
4160 "WFQ configuration is not supported for this device\n");
4164 for_each_hwfn(p_dev, i) {
4165 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4166 struct ecore_ptt *p_ptt;
4168 p_ptt = ecore_ptt_acquire(p_hwfn);
4170 return ECORE_TIMEOUT;
4172 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4174 if (rc != ECORE_SUCCESS) {
4175 ecore_ptt_release(p_hwfn, p_ptt);
4179 ecore_ptt_release(p_hwfn, p_ptt);
4185 /* API to configure WFQ from mcp link change */
4186 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4191 /* TBD - for multiple hardware functions - that is 100 gig */
4192 if (p_dev->num_hwfns > 1) {
4193 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4194 "WFQ configuration is not supported for this device\n");
4198 for_each_hwfn(p_dev, i) {
4199 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4201 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4207 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4208 struct ecore_ptt *p_ptt,
4209 struct ecore_mcp_link_state *p_link,
4212 int rc = ECORE_SUCCESS;
4214 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4216 if (!p_link->line_speed && (max_bw != 100))
4219 p_link->speed = (p_link->line_speed * max_bw) / 100;
4220 p_hwfn->qm_info.pf_rl = p_link->speed;
4222 /* Since the limiter also affects Tx-switched traffic, we don't want it
4223 * to limit such traffic in case there's no actual limit.
4224 * In that case, set limit to imaginary high boundary.
4227 p_hwfn->qm_info.pf_rl = 100000;
4229 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4230 p_hwfn->qm_info.pf_rl);
4232 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4233 "Configured MAX bandwidth to be %08x Mb/sec\n",
4239 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4240 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4242 int i, rc = ECORE_INVAL;
4244 if (max_bw < 1 || max_bw > 100) {
4245 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4249 for_each_hwfn(p_dev, i) {
4250 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4251 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4252 struct ecore_mcp_link_state *p_link;
4253 struct ecore_ptt *p_ptt;
4255 p_link = &p_lead->mcp_info->link_output;
4257 p_ptt = ecore_ptt_acquire(p_hwfn);
4259 return ECORE_TIMEOUT;
4261 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4264 ecore_ptt_release(p_hwfn, p_ptt);
4266 if (rc != ECORE_SUCCESS)
4273 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4274 struct ecore_ptt *p_ptt,
4275 struct ecore_mcp_link_state *p_link,
4278 int rc = ECORE_SUCCESS;
4280 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4281 p_hwfn->qm_info.pf_wfq = min_bw;
4283 if (!p_link->line_speed)
4286 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4288 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4290 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4291 "Configured MIN bandwidth to be %d Mb/sec\n",
4292 p_link->min_pf_rate);
4297 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4298 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4300 int i, rc = ECORE_INVAL;
4302 if (min_bw < 1 || min_bw > 100) {
4303 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4307 for_each_hwfn(p_dev, i) {
4308 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4309 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4310 struct ecore_mcp_link_state *p_link;
4311 struct ecore_ptt *p_ptt;
4313 p_link = &p_lead->mcp_info->link_output;
4315 p_ptt = ecore_ptt_acquire(p_hwfn);
4317 return ECORE_TIMEOUT;
4319 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4321 if (rc != ECORE_SUCCESS) {
4322 ecore_ptt_release(p_hwfn, p_ptt);
4326 if (p_link->min_pf_rate) {
4327 u32 min_rate = p_link->min_pf_rate;
4329 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4334 ecore_ptt_release(p_hwfn, p_ptt);
4340 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4342 struct ecore_mcp_link_state *p_link;
4344 p_link = &p_hwfn->mcp_info->link_output;
4346 if (p_link->min_pf_rate)
4347 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4348 p_link->min_pf_rate);
4350 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4351 sizeof(*p_hwfn->qm_info.wfq_data) *
4352 p_hwfn->qm_info.num_vports);
4355 int ecore_device_num_engines(struct ecore_dev *p_dev)
4357 return ECORE_IS_BB(p_dev) ? 2 : 1;
4360 int ecore_device_num_ports(struct ecore_dev *p_dev)
4362 /* in CMT always only one port */
4363 if (p_dev->num_hwfns > 1)
4366 return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
4369 void ecore_set_fw_mac_addr(__le16 *fw_msb,
4374 ((u8 *)fw_msb)[0] = mac[1];
4375 ((u8 *)fw_msb)[1] = mac[0];
4376 ((u8 *)fw_mid)[0] = mac[3];
4377 ((u8 *)fw_mid)[1] = mac[2];
4378 ((u8 *)fw_lsb)[0] = mac[5];
4379 ((u8 *)fw_lsb)[1] = mac[4];