2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #ifndef __ECORE_HSI_COMMON__
10 #define __ECORE_HSI_COMMON__
11 /********************************/
12 /* Add include to common target */
13 /********************************/
14 #include "common_hsi.h"
18 * opcodes for the event ring
20 enum common_event_opcode {
21 COMMON_EVENT_PF_START,
23 COMMON_EVENT_VF_START,
25 COMMON_EVENT_VF_PF_CHANNEL,
27 COMMON_EVENT_PF_UPDATE,
28 COMMON_EVENT_MALICIOUS_VF,
29 COMMON_EVENT_RL_UPDATE,
31 MAX_COMMON_EVENT_OPCODE
36 * Common Ramrod Command IDs
38 enum common_ramrod_cmd_id {
40 COMMON_RAMROD_PF_START /* PF Function Start Ramrod */,
41 COMMON_RAMROD_PF_STOP /* PF Function Stop Ramrod */,
42 COMMON_RAMROD_VF_START /* VF Function Start */,
43 COMMON_RAMROD_VF_STOP /* VF Function Stop Ramrod */,
44 COMMON_RAMROD_PF_UPDATE /* PF update Ramrod */,
45 COMMON_RAMROD_RL_UPDATE /* QCN/DCQCN RL update Ramrod */,
46 COMMON_RAMROD_EMPTY /* Empty Ramrod */,
47 MAX_COMMON_RAMROD_CMD_ID
52 * The core storm context for the Ystorm
54 struct ystorm_core_conn_st_ctx {
59 * The core storm context for the Pstorm
61 struct pstorm_core_conn_st_ctx {
66 * Core Slowpath Connection storm context of Xstorm
68 struct xstorm_core_conn_st_ctx {
69 __le32 spq_base_lo /* SPQ Ring Base Address low dword */;
70 __le32 spq_base_hi /* SPQ Ring Base Address high dword */;
71 /* Consolidation Ring Base Address */
72 struct regpair consolid_base_addr;
73 __le16 spq_cons /* SPQ Ring Consumer */;
74 __le16 consolid_cons /* Consolidation Ring Consumer */;
75 __le32 reserved0[55] /* Pad to 15 cycles */;
78 struct e4_xstorm_core_conn_ag_ctx {
79 u8 reserved0 /* cdu_validation */;
80 u8 core_state /* state */;
83 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
84 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
86 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
87 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1
89 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
90 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2
92 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
93 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
95 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
96 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4
98 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
99 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5
101 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1
102 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6
104 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1
105 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7
108 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1
109 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
111 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1
112 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1
114 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1
115 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2
117 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1
118 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3
120 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1
121 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4
123 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1
124 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5
126 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
127 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
129 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
130 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
133 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
134 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
136 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
137 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2
139 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
140 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4
142 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
143 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6
145 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
146 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
147 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
148 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2
149 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
150 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4
151 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
152 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6
154 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
155 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
156 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
157 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2
159 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
160 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4
162 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3
163 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6
166 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3
167 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
169 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3
170 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2
172 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3
173 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4
175 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3
176 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6
179 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3
180 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
182 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
183 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2
185 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3
186 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4
188 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
189 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
192 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
193 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
195 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3
196 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2
198 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
199 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
201 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
202 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6
204 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
205 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7
208 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
209 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
211 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
212 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1
214 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
215 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2
217 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
218 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3
220 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
221 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4
223 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
224 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5
226 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
227 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6
229 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
230 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7
233 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
234 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
236 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1
237 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1
239 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1
240 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2
242 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1
243 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3
245 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1
246 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4
248 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1
249 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5
251 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1
252 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
254 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
255 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7
258 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
259 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
261 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
262 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
264 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
265 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
267 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1
268 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3
270 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
271 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
273 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1
274 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5
276 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1
277 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6
279 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1
280 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7
283 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1
284 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
286 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1
287 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1
289 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
290 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
292 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
293 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3
295 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
296 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4
298 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
299 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5
301 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
302 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
304 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1
305 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7
308 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1
309 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
311 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1
312 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1
314 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
315 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
317 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
318 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
320 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1
321 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4
323 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1
324 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5
326 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1
327 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6
329 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1
330 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7
333 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1
334 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
336 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1
337 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1
339 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
340 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
342 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
343 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
345 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
346 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
348 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
349 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
351 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
352 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
354 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
355 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
358 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1
359 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
361 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1
362 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1
364 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1
365 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2
367 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1
368 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3
370 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1
371 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4
373 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1
374 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5
376 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3
377 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6
378 u8 byte2 /* byte2 */;
379 __le16 physical_q0 /* physical_q0 */;
380 __le16 consolid_prod /* physical_q1 */;
381 __le16 reserved16 /* physical_q2 */;
382 __le16 tx_bd_cons /* word3 */;
383 __le16 tx_bd_or_spq_prod /* word4 */;
384 __le16 word5 /* word5 */;
385 __le16 conn_dpi /* conn_dpi */;
386 u8 byte3 /* byte3 */;
387 u8 byte4 /* byte4 */;
388 u8 byte5 /* byte5 */;
389 u8 byte6 /* byte6 */;
390 __le32 reg0 /* reg0 */;
391 __le32 reg1 /* reg1 */;
392 __le32 reg2 /* reg2 */;
393 __le32 reg3 /* reg3 */;
394 __le32 reg4 /* reg4 */;
395 __le32 reg5 /* cf_array0 */;
396 __le32 reg6 /* cf_array1 */;
397 __le16 word7 /* word7 */;
398 __le16 word8 /* word8 */;
399 __le16 word9 /* word9 */;
400 __le16 word10 /* word10 */;
401 __le32 reg7 /* reg7 */;
402 __le32 reg8 /* reg8 */;
403 __le32 reg9 /* reg9 */;
404 u8 byte7 /* byte7 */;
405 u8 byte8 /* byte8 */;
406 u8 byte9 /* byte9 */;
407 u8 byte10 /* byte10 */;
408 u8 byte11 /* byte11 */;
409 u8 byte12 /* byte12 */;
410 u8 byte13 /* byte13 */;
411 u8 byte14 /* byte14 */;
412 u8 byte15 /* byte15 */;
413 u8 e5_reserved /* e5_reserved */;
414 __le16 word11 /* word11 */;
415 __le32 reg10 /* reg10 */;
416 __le32 reg11 /* reg11 */;
417 __le32 reg12 /* reg12 */;
418 __le32 reg13 /* reg13 */;
419 __le32 reg14 /* reg14 */;
420 __le32 reg15 /* reg15 */;
421 __le32 reg16 /* reg16 */;
422 __le32 reg17 /* reg17 */;
423 __le32 reg18 /* reg18 */;
424 __le32 reg19 /* reg19 */;
425 __le16 word12 /* word12 */;
426 __le16 word13 /* word13 */;
427 __le16 word14 /* word14 */;
428 __le16 word15 /* word15 */;
431 struct e4_tstorm_core_conn_ag_ctx {
432 u8 byte0 /* cdu_validation */;
433 u8 byte1 /* state */;
435 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
436 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
437 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
438 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
439 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
440 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2
441 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
442 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3
443 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
444 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4
445 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
446 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5
447 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
448 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6
450 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
451 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
452 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
453 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2
454 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
455 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4
456 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
457 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6
459 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
460 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
461 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
462 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2
463 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
464 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4
465 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
466 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6
468 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
469 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
470 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
471 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2
472 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
473 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4
474 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
475 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5
476 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
477 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6
478 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
479 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7
481 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
482 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
483 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
484 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1
485 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
486 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2
487 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
488 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3
489 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
490 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4
491 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
492 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5
493 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
494 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6
495 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
496 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
498 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
499 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
500 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
501 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
502 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
503 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
504 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
505 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
506 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
507 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
508 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
509 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
510 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
511 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
512 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
513 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
514 __le32 reg0 /* reg0 */;
515 __le32 reg1 /* reg1 */;
516 __le32 reg2 /* reg2 */;
517 __le32 reg3 /* reg3 */;
518 __le32 reg4 /* reg4 */;
519 __le32 reg5 /* reg5 */;
520 __le32 reg6 /* reg6 */;
521 __le32 reg7 /* reg7 */;
522 __le32 reg8 /* reg8 */;
523 u8 byte2 /* byte2 */;
524 u8 byte3 /* byte3 */;
525 __le16 word0 /* word0 */;
526 u8 byte4 /* byte4 */;
527 u8 byte5 /* byte5 */;
528 __le16 word1 /* word1 */;
529 __le16 word2 /* conn_dpi */;
530 __le16 word3 /* word3 */;
531 __le32 reg9 /* reg9 */;
532 __le32 reg10 /* reg10 */;
535 struct e4_ustorm_core_conn_ag_ctx {
536 u8 reserved /* cdu_validation */;
537 u8 byte1 /* state */;
539 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
540 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
541 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
542 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
543 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
544 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
545 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
546 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
547 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
548 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
550 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
551 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
552 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
553 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2
554 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
555 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4
556 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
557 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6
559 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
560 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
561 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
562 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
563 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
564 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
565 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
566 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3
567 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
568 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4
569 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
570 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5
571 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
572 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6
573 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
574 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
576 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
577 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
578 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
579 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
580 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
581 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
582 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
583 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
584 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
585 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
586 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
587 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
588 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
589 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
590 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
591 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
592 u8 byte2 /* byte2 */;
593 u8 byte3 /* byte3 */;
594 __le16 word0 /* conn_dpi */;
595 __le16 word1 /* word1 */;
596 __le32 rx_producers /* reg0 */;
597 __le32 reg1 /* reg1 */;
598 __le32 reg2 /* reg2 */;
599 __le32 reg3 /* reg3 */;
600 __le16 word2 /* word2 */;
601 __le16 word3 /* word3 */;
605 * The core storm context for the Mstorm
607 struct mstorm_core_conn_st_ctx {
612 * The core storm context for the Ustorm
614 struct ustorm_core_conn_st_ctx {
619 * core connection context
621 struct core_conn_context {
622 /* ystorm storm context */
623 struct ystorm_core_conn_st_ctx ystorm_st_context;
624 struct regpair ystorm_st_padding[2] /* padding */;
625 /* pstorm storm context */
626 struct pstorm_core_conn_st_ctx pstorm_st_context;
627 struct regpair pstorm_st_padding[2] /* padding */;
628 /* xstorm storm context */
629 struct xstorm_core_conn_st_ctx xstorm_st_context;
630 /* xstorm aggregative context */
631 struct e4_xstorm_core_conn_ag_ctx xstorm_ag_context;
632 /* tstorm aggregative context */
633 struct e4_tstorm_core_conn_ag_ctx tstorm_ag_context;
634 /* ustorm aggregative context */
635 struct e4_ustorm_core_conn_ag_ctx ustorm_ag_context;
636 /* mstorm storm context */
637 struct mstorm_core_conn_st_ctx mstorm_st_context;
638 /* ustorm storm context */
639 struct ustorm_core_conn_st_ctx ustorm_st_context;
640 struct regpair ustorm_st_padding[2] /* padding */;
645 * How ll2 should deal with packet upon errors
647 enum core_error_handle {
648 LL2_DROP_PACKET /* If error occurs drop packet */,
649 LL2_DO_NOTHING /* If error occurs do nothing */,
650 LL2_ASSERT /* If error occurs assert */,
651 MAX_CORE_ERROR_HANDLE
656 * opcodes for the event ring
658 enum core_event_opcode {
659 CORE_EVENT_TX_QUEUE_START,
660 CORE_EVENT_TX_QUEUE_STOP,
661 CORE_EVENT_RX_QUEUE_START,
662 CORE_EVENT_RX_QUEUE_STOP,
663 CORE_EVENT_RX_QUEUE_FLUSH,
664 MAX_CORE_EVENT_OPCODE
669 * The L4 pseudo checksum mode for Core
671 enum core_l4_pseudo_checksum_mode {
672 /* Pseudo Checksum on packet is calculated with the correct packet length. */
673 CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
674 /* Pseudo Checksum on packet is calculated with zero length. */
675 CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
676 MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
681 * Light-L2 RX Producers in Tstorm RAM
683 struct core_ll2_port_stats {
684 struct regpair gsi_invalid_hdr;
685 struct regpair gsi_invalid_pkt_length;
686 struct regpair gsi_unsupported_pkt_typ;
687 struct regpair gsi_crcchksm_error;
692 * Ethernet TX Per Queue Stats
694 struct core_ll2_pstorm_per_queue_stat {
695 /* number of total bytes sent without errors */
696 struct regpair sent_ucast_bytes;
697 /* number of total bytes sent without errors */
698 struct regpair sent_mcast_bytes;
699 /* number of total bytes sent without errors */
700 struct regpair sent_bcast_bytes;
701 /* number of total packets sent without errors */
702 struct regpair sent_ucast_pkts;
703 /* number of total packets sent without errors */
704 struct regpair sent_mcast_pkts;
705 /* number of total packets sent without errors */
706 struct regpair sent_bcast_pkts;
711 * Light-L2 RX Producers in Tstorm RAM
713 struct core_ll2_rx_prod {
714 __le16 bd_prod /* BD Producer */;
715 __le16 cqe_prod /* CQE Producer */;
720 struct core_ll2_tstorm_per_queue_stat {
721 /* Number of packets discarded because they are bigger than MTU */
722 struct regpair packet_too_big_discard;
723 /* Number of packets discarded due to lack of host buffers */
724 struct regpair no_buff_discard;
728 struct core_ll2_ustorm_per_queue_stat {
729 struct regpair rcv_ucast_bytes;
730 struct regpair rcv_mcast_bytes;
731 struct regpair rcv_bcast_bytes;
732 struct regpair rcv_ucast_pkts;
733 struct regpair rcv_mcast_pkts;
734 struct regpair rcv_bcast_pkts;
739 * Core Ramrod Command IDs (light L2)
741 enum core_ramrod_cmd_id {
743 CORE_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */,
744 CORE_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */,
745 CORE_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */,
746 CORE_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */,
747 CORE_RAMROD_RX_QUEUE_FLUSH /* RX Flush queue Ramrod */,
748 MAX_CORE_RAMROD_CMD_ID
753 * Core RX CQE Type for Light L2
755 enum core_roce_flavor_type {
758 MAX_CORE_ROCE_FLAVOR_TYPE
763 * Specifies how ll2 should deal with packets errors: packet_too_big and no_buff
765 struct core_rx_action_on_error {
767 /* ll2 how to handle error packet_too_big (use enum core_error_handle) */
768 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
769 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
770 /* ll2 how to handle error with no_buff (use enum core_error_handle) */
771 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
772 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2
773 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
774 #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4
779 * Core RX BD for Light L2
788 * Core RX CM offload BD for Light L2
790 struct core_rx_bd_with_buff_len {
797 * Core RX CM offload BD for Light L2
799 union core_rx_bd_union {
800 struct core_rx_bd rx_bd /* Core Rx Bd static buffer size */;
801 /* Core Rx Bd with dynamic buffer length */
802 struct core_rx_bd_with_buff_len rx_bd_with_len;
808 * Opaque Data for Light L2 RX CQE .
810 struct core_rx_cqe_opaque_data {
811 __le32 data[2] /* Opaque CQE Data */;
816 * Core RX CQE Type for Light L2
818 enum core_rx_cqe_type {
819 CORE_RX_CQE_ILLIGAL_TYPE /* Bad RX Cqe type */,
820 CORE_RX_CQE_TYPE_REGULAR /* Regular Core RX CQE */,
821 CORE_RX_CQE_TYPE_GSI_OFFLOAD /* Fp Gsi offload RX CQE */,
822 CORE_RX_CQE_TYPE_SLOW_PATH /* Slow path Core RX CQE */,
828 * Core RX CQE for Light L2 .
830 struct core_rx_fast_path_cqe {
831 u8 type /* CQE type */;
832 /* Offset (in bytes) of the packet from start of the buffer */
834 /* Parsing and error flags from the parser */
835 struct parsing_and_err_flags parse_flags;
836 __le16 packet_length /* Total packet length (from the parser) */;
837 __le16 vlan /* 802.1q VLAN tag */;
838 struct core_rx_cqe_opaque_data opaque_data /* Opaque Data */;
839 /* bit- map: each bit represents a specific error. errors indications are
840 * provided by the cracker. see spec for detailed description
842 struct parsing_err_flags err_flags;
848 * Core Rx CM offload CQE .
850 struct core_rx_gsi_offload_cqe {
851 u8 type /* CQE type */;
852 u8 data_length_error /* set if gsi data is bigger than buff */;
853 /* Parsing and error flags from the parser */
854 struct parsing_and_err_flags parse_flags;
855 __le16 data_length /* Total packet length (from the parser) */;
856 __le16 vlan /* 802.1q VLAN tag */;
857 __le32 src_mac_addrhi /* hi 4 bytes source mac address */;
858 __le16 src_mac_addrlo /* lo 2 bytes of source mac address */;
859 /* These are the lower 16 bit of QP id in RoCE BTH header */
861 __le32 gid_dst[4] /* Gid destination address */;
865 * Core RX CQE for Light L2 .
867 struct core_rx_slow_path_cqe {
868 u8 type /* CQE type */;
871 struct core_rx_cqe_opaque_data opaque_data /* Opaque Data */;
876 * Core RX CM offload BD for Light L2
878 union core_rx_cqe_union {
879 struct core_rx_fast_path_cqe rx_cqe_fp /* Fast path CQE */;
880 struct core_rx_gsi_offload_cqe rx_cqe_gsi /* GSI offload CQE */;
881 struct core_rx_slow_path_cqe rx_cqe_sp /* Slow path CQE */;
889 * Ramrod data for rx queue start ramrod
891 struct core_rx_start_ramrod_data {
892 struct regpair bd_base /* bd address of the first bd page */;
893 struct regpair cqe_pbl_addr /* Base address on host of CQE PBL */;
894 __le16 mtu /* Maximum transmission unit */;
895 __le16 sb_id /* Status block ID */;
896 u8 sb_index /* index of the protocol index */;
897 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
898 u8 complete_event_flg /* post completion to the event ring if set */;
899 u8 drop_ttl0_flg /* drop packet with ttl0 if set */;
900 __le16 num_of_pbl_pages /* Num of pages in CQE PBL */;
901 /* if set, 802.1q tags will be removed and copied to CQE */
902 u8 inner_vlan_removal_en;
903 u8 queue_id /* Light L2 RX Queue ID */;
904 u8 main_func_queue /* Is this the main queue for the PF */;
905 /* Duplicate broadcast packets to LL2 main queue in mf_si mode. Valid if
906 * main_func_queue is set.
908 u8 mf_si_bcast_accept_all;
909 /* Duplicate multicast packets to LL2 main queue in mf_si mode. Valid if
910 * main_func_queue is set.
912 u8 mf_si_mcast_accept_all;
913 /* Specifies how ll2 should deal with packets errors: packet_too_big and
916 struct core_rx_action_on_error action_on_error;
917 /* set when in GSI offload mode on ROCE connection */
924 * Ramrod data for rx queue stop ramrod
926 struct core_rx_stop_ramrod_data {
927 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
928 u8 complete_event_flg /* post completion to the event ring if set */;
929 u8 queue_id /* Light L2 RX Queue ID */;
936 * Flags for Core TX BD
938 struct core_tx_bd_data {
940 /* Do not allow additional VLAN manipulations on this packet (DCB) */
941 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
942 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0
943 /* Insert VLAN into packet */
944 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
945 #define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1
946 /* This is the first BD of the packet (for debug) */
947 #define CORE_TX_BD_DATA_START_BD_MASK 0x1
948 #define CORE_TX_BD_DATA_START_BD_SHIFT 2
949 /* Calculate the IP checksum for the packet */
950 #define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
951 #define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3
952 /* Calculate the L4 checksum for the packet */
953 #define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
954 #define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4
955 /* Packet is IPv6 with extensions */
956 #define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
957 #define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5
958 /* If IPv6+ext, and if l4_csum is 1, than this field indicates L4 protocol:
961 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
962 #define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6
963 /* The pseudo checksum mode to place in the L4 checksum field. Required only
964 * when IPv6+ext and l4_csum is set. (use enum core_l4_pseudo_checksum_mode)
966 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1
967 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7
968 /* Number of BDs that make up one packet - width wide enough to present
969 * CORE_LL2_TX_MAX_BDS_PER_PACKET
971 #define CORE_TX_BD_DATA_NBDS_MASK 0xF
972 #define CORE_TX_BD_DATA_NBDS_SHIFT 8
973 /* Use roce_flavor enum - Differentiate between Roce flavors is valid when
974 * connType is ROCE (use enum core_roce_flavor_type)
976 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
977 #define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12
978 /* Calculate ip length */
979 #define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
980 #define CORE_TX_BD_DATA_IP_LEN_SHIFT 13
981 #define CORE_TX_BD_DATA_RESERVED0_MASK 0x3
982 #define CORE_TX_BD_DATA_RESERVED0_SHIFT 14
986 * Core TX BD for Light L2
989 struct regpair addr /* Buffer Address */;
990 __le16 nbytes /* Number of Bytes in Buffer */;
991 /* Network packets: VLAN to insert to packet (if insertion flag set) LoopBack
992 * packets: echo data to pass to Rx
994 __le16 nw_vlan_or_lb_echo;
995 struct core_tx_bd_data bd_data /* BD Flags */;
997 /* L4 Header Offset from start of packet (in Words). This is needed if both
998 * l4_csum and ipv6_ext are set
1000 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF
1001 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0
1002 /* Packet destination - Network, Loopback or Drop (use enum core_tx_dest) */
1003 #define CORE_TX_BD_TX_DST_MASK 0x3
1004 #define CORE_TX_BD_TX_DST_SHIFT 14
1010 * Light L2 TX Destination
1013 CORE_TX_DEST_NW /* TX Destination to the Network */,
1014 CORE_TX_DEST_LB /* TX Destination to the Loopback */,
1015 CORE_TX_DEST_RESERVED,
1016 CORE_TX_DEST_DROP /* TX Drop */,
1022 * Ramrod data for tx queue start ramrod
1024 struct core_tx_start_ramrod_data {
1025 struct regpair pbl_base_addr /* Address of the pbl page */;
1026 __le16 mtu /* Maximum transmission unit */;
1027 __le16 sb_id /* Status block ID */;
1028 u8 sb_index /* Status block protocol index */;
1029 u8 stats_en /* Statistics Enable */;
1030 u8 stats_id /* Statistics Counter ID */;
1031 u8 conn_type /* connection type that loaded ll2 */;
1032 __le16 pbl_size /* Number of BD pages pointed by PBL */;
1033 __le16 qm_pq_id /* QM PQ ID */;
1034 /* set when in GSI offload mode on ROCE connection */
1035 u8 gsi_offload_flag;
1041 * Ramrod data for tx queue stop ramrod
1043 struct core_tx_stop_ramrod_data {
1044 __le32 reserved0[2];
1049 * Enum flag for what type of dcb data to update
1051 enum dcb_dscp_update_mode {
1052 /* use when no change should be done to dcb data */
1053 DONT_UPDATE_DCB_DSCP,
1054 UPDATE_DCB /* use to update only l2 (vlan) priority */,
1055 UPDATE_DSCP /* use to update only l3 dscp */,
1056 UPDATE_DCB_DSCP /* update vlan pri and dscp */,
1057 MAX_DCB_DSCP_UPDATE_FLAG
1061 struct eth_mstorm_per_pf_stat {
1062 struct regpair gre_discard_pkts /* Dropped GRE RX packets */;
1063 struct regpair vxlan_discard_pkts /* Dropped VXLAN RX packets */;
1064 struct regpair geneve_discard_pkts /* Dropped GENEVE RX packets */;
1065 struct regpair lb_discard_pkts /* Dropped Tx switched packets */;
1069 struct eth_mstorm_per_queue_stat {
1070 /* Number of packets discarded because TTL=0 (in IPv4) or hopLimit=0 (IPv6) */
1071 struct regpair ttl0_discard;
1072 /* Number of packets discarded because they are bigger than MTU */
1073 struct regpair packet_too_big_discard;
1074 /* Number of packets discarded due to lack of host buffers (BDs/SGEs/CQEs) */
1075 struct regpair no_buff_discard;
1076 /* Number of packets discarded because of no active Rx connection */
1077 struct regpair not_active_discard;
1078 /* number of coalesced packets in all TPA aggregations */
1079 struct regpair tpa_coalesced_pkts;
1080 /* total number of TPA aggregations */
1081 struct regpair tpa_coalesced_events;
1082 /* number of aggregations, which abnormally ended */
1083 struct regpair tpa_aborts_num;
1084 /* total TCP payload length in all TPA aggregations */
1085 struct regpair tpa_coalesced_bytes;
1090 * Ethernet TX Per PF
1092 struct eth_pstorm_per_pf_stat {
1093 /* number of total ucast bytes sent on loopback port without errors */
1094 struct regpair sent_lb_ucast_bytes;
1095 /* number of total mcast bytes sent on loopback port without errors */
1096 struct regpair sent_lb_mcast_bytes;
1097 /* number of total bcast bytes sent on loopback port without errors */
1098 struct regpair sent_lb_bcast_bytes;
1099 /* number of total ucast packets sent on loopback port without errors */
1100 struct regpair sent_lb_ucast_pkts;
1101 /* number of total mcast packets sent on loopback port without errors */
1102 struct regpair sent_lb_mcast_pkts;
1103 /* number of total bcast packets sent on loopback port without errors */
1104 struct regpair sent_lb_bcast_pkts;
1105 struct regpair sent_gre_bytes /* Sent GRE bytes */;
1106 struct regpair sent_vxlan_bytes /* Sent VXLAN bytes */;
1107 struct regpair sent_geneve_bytes /* Sent GENEVE bytes */;
1108 struct regpair sent_gre_pkts /* Sent GRE packets */;
1109 struct regpair sent_vxlan_pkts /* Sent VXLAN packets */;
1110 struct regpair sent_geneve_pkts /* Sent GENEVE packets */;
1111 struct regpair gre_drop_pkts /* Dropped GRE TX packets */;
1112 struct regpair vxlan_drop_pkts /* Dropped VXLAN TX packets */;
1113 struct regpair geneve_drop_pkts /* Dropped GENEVE TX packets */;
1118 * Ethernet TX Per Queue Stats
1120 struct eth_pstorm_per_queue_stat {
1121 /* number of total bytes sent without errors */
1122 struct regpair sent_ucast_bytes;
1123 /* number of total bytes sent without errors */
1124 struct regpair sent_mcast_bytes;
1125 /* number of total bytes sent without errors */
1126 struct regpair sent_bcast_bytes;
1127 /* number of total packets sent without errors */
1128 struct regpair sent_ucast_pkts;
1129 /* number of total packets sent without errors */
1130 struct regpair sent_mcast_pkts;
1131 /* number of total packets sent without errors */
1132 struct regpair sent_bcast_pkts;
1133 /* number of total packets dropped due to errors */
1134 struct regpair error_drop_pkts;
1139 * ETH Rx producers data
1141 struct eth_rx_rate_limit {
1142 /* Rate Limit Multiplier - (Storm Clock (MHz) * 8 / Desired Bandwidth (MB/s)) */
1144 /* Constant term to add (or subtract from number of cycles) */
1146 u8 add_sub_cnst /* Add (1) or subtract (0) constant term */;
1152 struct eth_ustorm_per_pf_stat {
1153 /* number of total ucast bytes received on loopback port without errors */
1154 struct regpair rcv_lb_ucast_bytes;
1155 /* number of total mcast bytes received on loopback port without errors */
1156 struct regpair rcv_lb_mcast_bytes;
1157 /* number of total bcast bytes received on loopback port without errors */
1158 struct regpair rcv_lb_bcast_bytes;
1159 /* number of total ucast packets received on loopback port without errors */
1160 struct regpair rcv_lb_ucast_pkts;
1161 /* number of total mcast packets received on loopback port without errors */
1162 struct regpair rcv_lb_mcast_pkts;
1163 /* number of total bcast packets received on loopback port without errors */
1164 struct regpair rcv_lb_bcast_pkts;
1165 struct regpair rcv_gre_bytes /* Received GRE bytes */;
1166 struct regpair rcv_vxlan_bytes /* Received VXLAN bytes */;
1167 struct regpair rcv_geneve_bytes /* Received GENEVE bytes */;
1168 struct regpair rcv_gre_pkts /* Received GRE packets */;
1169 struct regpair rcv_vxlan_pkts /* Received VXLAN packets */;
1170 struct regpair rcv_geneve_pkts /* Received GENEVE packets */;
1174 struct eth_ustorm_per_queue_stat {
1175 struct regpair rcv_ucast_bytes;
1176 struct regpair rcv_mcast_bytes;
1177 struct regpair rcv_bcast_bytes;
1178 struct regpair rcv_ucast_pkts;
1179 struct regpair rcv_mcast_pkts;
1180 struct regpair rcv_bcast_pkts;
1185 * Event Ring Next Page Address
1187 struct event_ring_next_addr {
1188 struct regpair addr /* Next Page Address */;
1189 __le32 reserved[2] /* Reserved */;
1193 * Event Ring Element
1195 union event_ring_element {
1196 struct event_ring_entry entry /* Event Ring Entry */;
1197 /* Event Ring Next Page Address */
1198 struct event_ring_next_addr next_addr;
1206 enum fw_flow_ctrl_mode {
1209 MAX_FW_FLOW_CTRL_MODE
1214 * Major and Minor hsi Versions
1216 struct hsi_fp_ver_struct {
1217 u8 minor_ver_arr[2] /* Minor Version of hsi loading pf */;
1218 u8 major_ver_arr[2] /* Major Version of driver loading pf */;
1226 INTEG_PHASE_BB_A0_LATEST = 3 /* BB A0 latest integration phase */,
1227 INTEG_PHASE_BB_B0_NO_MCP = 10 /* BB B0 without MCP */,
1228 INTEG_PHASE_BB_B0_WITH_MCP = 11 /* BB B0 with MCP */,
1236 enum iwarp_ll2_tx_queues {
1237 /* LL2 queue for OOO packets sent in-order by the driver */
1238 IWARP_LL2_IN_ORDER_TX_QUEUE = 1,
1239 /* LL2 queue for unaligned packets sent aligned by the driver */
1240 IWARP_LL2_ALIGNED_TX_QUEUE,
1241 /* LL2 queue for unaligned packets sent aligned and was right-trimmed by the
1244 IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE,
1245 IWARP_LL2_ERROR /* Error indication */,
1246 MAX_IWARP_LL2_TX_QUEUES
1251 * Malicious VF error ID
1253 enum malicious_vf_error_id {
1254 MALICIOUS_VF_NO_ERROR /* Zero placeholder value */,
1255 /* Writing to VF/PF channel when it is not ready */
1256 VF_PF_CHANNEL_NOT_READY,
1257 VF_ZONE_MSG_NOT_VALID /* VF channel message is not valid */,
1258 VF_ZONE_FUNC_NOT_ENABLED /* Parent PF of VF channel is not active */,
1259 /* TX packet is shorter then reported on BDs or from minimal size */
1260 ETH_PACKET_TOO_SMALL,
1261 /* Tx packet with marked as insert VLAN when its illegal */
1262 ETH_ILLEGAL_VLAN_MODE,
1263 ETH_MTU_VIOLATION /* TX packet is greater then MTU */,
1264 /* TX packet has illegal inband tags marked */
1265 ETH_ILLEGAL_INBAND_TAGS,
1266 /* Vlan cant be added to inband tag */
1267 ETH_VLAN_INSERT_AND_INBAND_VLAN,
1268 /* indicated number of BDs for the packet is illegal */
1270 ETH_FIRST_BD_WO_SOP /* 1st BD must have start_bd flag set */,
1271 /* There are not enough BDs for transmission of even one packet */
1272 ETH_INSUFFICIENT_BDS,
1273 ETH_ILLEGAL_LSO_HDR_NBDS /* Header NBDs value is illegal */,
1274 ETH_ILLEGAL_LSO_MSS /* LSO MSS value is more than allowed */,
1275 /* empty BD (which not contains control flags) is illegal */
1277 ETH_ILLEGAL_LSO_HDR_LEN /* LSO header size is above the limit */,
1278 /* In LSO its expected that on the local BD ring there will be at least MSS
1281 ETH_INSUFFICIENT_PAYLOAD,
1282 ETH_EDPM_OUT_OF_SYNC /* Valid BDs on local ring after EDPM L2 sync */,
1283 /* Tunneled packet with IPv6+Ext without a proper number of BDs */
1284 ETH_TUNN_IPV6_EXT_NBD_ERR,
1285 ETH_CONTROL_PACKET_VIOLATION /* VF sent control frame such as PFC */,
1286 ETH_ANTI_SPOOFING_ERR /* Anti-Spoofing verification failure */,
1287 MAX_MALICIOUS_VF_ERROR_ID
1293 * Mstorm non-triggering VF zone
1295 struct mstorm_non_trigger_vf_zone {
1296 /* VF statistic bucket */
1297 struct eth_mstorm_per_queue_stat eth_queue_stat;
1298 /* VF RX queues producers */
1299 struct eth_rx_prod_data
1300 eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD];
1307 struct mstorm_vf_zone {
1308 /* non-interrupt-triggering zone */
1309 struct mstorm_non_trigger_vf_zone non_trigger;
1314 * personality per PF
1316 enum personality_type {
1317 BAD_PERSONALITY_TYP,
1318 PERSONALITY_ISCSI /* iSCSI and LL2 */,
1319 PERSONALITY_FCOE /* Fcoe and LL2 */,
1320 PERSONALITY_RDMA_AND_ETH /* Roce or Iwarp, Eth and LL2 */,
1321 PERSONALITY_RDMA /* Roce and LL2 */,
1322 PERSONALITY_CORE /* CORE(LL2) */,
1323 PERSONALITY_ETH /* Ethernet */,
1324 PERSONALITY_TOE /* Toe and LL2 */,
1325 MAX_PERSONALITY_TYPE
1330 * tunnel configuration
1332 struct pf_start_tunnel_config {
1333 /* Set VXLAN tunnel UDP destination port to vxlan_udp_port. If not set -
1334 * FW will use a default port
1336 u8 set_vxlan_udp_port_flg;
1337 /* Set GENEVE tunnel UDP destination port to geneve_udp_port. If not set -
1338 * FW will use a default port
1340 u8 set_geneve_udp_port_flg;
1341 u8 tunnel_clss_vxlan /* Rx classification scheme for VXLAN tunnel. */;
1342 /* Rx classification scheme for l2 GENEVE tunnel. */
1343 u8 tunnel_clss_l2geneve;
1344 /* Rx classification scheme for ip GENEVE tunnel. */
1345 u8 tunnel_clss_ipgeneve;
1346 u8 tunnel_clss_l2gre /* Rx classification scheme for l2 GRE tunnel. */;
1347 u8 tunnel_clss_ipgre /* Rx classification scheme for ip GRE tunnel. */;
1349 /* VXLAN tunnel UDP destination port. Valid if set_vxlan_udp_port_flg=1 */
1350 __le16 vxlan_udp_port;
1351 /* GENEVE tunnel UDP destination port. Valid if set_geneve_udp_port_flg=1 */
1352 __le16 geneve_udp_port;
1356 * Ramrod data for PF start ramrod
1358 struct pf_start_ramrod_data {
1359 struct regpair event_ring_pbl_addr /* Address of event ring PBL */;
1360 /* PBL address of consolidation queue */
1361 struct regpair consolid_q_pbl_addr;
1362 /* tunnel configuration. */
1363 struct pf_start_tunnel_config tunnel_config;
1365 __le16 event_ring_sb_id /* Status block ID */;
1366 /* All VfIds owned by Pf will be from baseVfId till baseVfId+numVfs */
1368 u8 num_vfs /* Amount of vfs owned by PF */;
1369 u8 event_ring_num_pages /* Number of PBL pages in event ring */;
1370 u8 event_ring_sb_index /* Status block index */;
1371 u8 path_id /* HW path ID (engine ID) */;
1372 u8 warning_as_error /* In FW asserts, treat warning as error */;
1373 /* If not set - throw a warning for each ramrod (for debug) */
1374 u8 dont_log_ramrods;
1375 u8 personality /* define what type of personality is new PF */;
1376 /* Log type mask. Each bit set enables a corresponding event type logging.
1377 * Event types are defined as ASSERT_LOG_TYPE_xxx
1379 __le16 log_type_mask;
1380 u8 mf_mode /* Multi function mode */;
1381 u8 integ_phase /* Integration phase */;
1382 /* If set, inter-pf tx switching is allowed in Switch Independent func mode */
1383 u8 allow_npar_tx_switching;
1384 /* Map from inner to outer priority. Set pri_map_valid when init map */
1385 u8 inner_to_outer_pri_map[8];
1386 /* If inner_to_outer_pri_map is initialize then set pri_map_valid */
1388 /* In case mf_mode is MF_OVLAN, this field specifies the outer vlan
1389 * (lower 16 bits) and ethType to use (higher 16 bits)
1392 /* FP HSI version to be used by FW */
1393 struct hsi_fp_ver_struct hsi_fp_ver;
1399 * Data for port update ramrod
1401 struct protocol_dcb_data {
1402 u8 dcb_enable_flag /* dcbEnable flag value */;
1403 u8 dscp_enable_flag /* If set use dscp value */;
1404 u8 dcb_priority /* dcbPri flag value */;
1405 u8 dcb_tc /* dcb TC value */;
1406 u8 dscp_val /* dscp value to write if dscp_enable_flag is set */;
1411 * Update tunnel configuration
1413 struct pf_update_tunnel_config {
1414 /* Update RX per PF tunnel classification scheme. */
1415 u8 update_rx_pf_clss;
1416 /* Update per PORT default tunnel RX classification scheme for traffic with
1417 * unknown unicast outer MAC in NPAR mode.
1419 u8 update_rx_def_ucast_clss;
1420 /* Update per PORT default tunnel RX classification scheme for traffic with non
1421 * unicast outer MAC in NPAR mode.
1423 u8 update_rx_def_non_ucast_clss;
1424 /* Update VXLAN tunnel UDP destination port. */
1425 u8 set_vxlan_udp_port_flg;
1426 /* Update GENEVE tunnel UDP destination port. */
1427 u8 set_geneve_udp_port_flg;
1428 u8 tunnel_clss_vxlan /* Classification scheme for VXLAN tunnel. */;
1429 /* Classification scheme for l2 GENEVE tunnel. */
1430 u8 tunnel_clss_l2geneve;
1431 /* Classification scheme for ip GENEVE tunnel. */
1432 u8 tunnel_clss_ipgeneve;
1433 u8 tunnel_clss_l2gre /* Classification scheme for l2 GRE tunnel. */;
1434 u8 tunnel_clss_ipgre /* Classification scheme for ip GRE tunnel. */;
1435 __le16 vxlan_udp_port /* VXLAN tunnel UDP destination port. */;
1436 __le16 geneve_udp_port /* GENEVE tunnel UDP destination port. */;
1441 * Data for port update ramrod
1443 struct pf_update_ramrod_data {
1445 u8 update_eth_dcb_data_mode /* Update Eth DCB data indication */;
1446 u8 update_fcoe_dcb_data_mode /* Update FCOE DCB data indication */;
1447 u8 update_iscsi_dcb_data_mode /* Update iSCSI DCB data indication */;
1448 u8 update_roce_dcb_data_mode /* Update ROCE DCB data indication */;
1449 /* Update RROCE (RoceV2) DCB data indication */
1450 u8 update_rroce_dcb_data_mode;
1451 u8 update_iwarp_dcb_data_mode /* Update IWARP DCB data indication */;
1452 u8 update_mf_vlan_flag /* Update MF outer vlan Id */;
1453 struct protocol_dcb_data eth_dcb_data /* core eth related fields */;
1454 struct protocol_dcb_data fcoe_dcb_data /* core fcoe related fields */;
1455 /* core iscsi related fields */
1456 struct protocol_dcb_data iscsi_dcb_data;
1457 struct protocol_dcb_data roce_dcb_data /* core roce related fields */;
1458 /* core roce related fields */
1459 struct protocol_dcb_data rroce_dcb_data;
1460 /* core iwarp related fields */
1461 struct protocol_dcb_data iwarp_dcb_data;
1462 __le16 mf_vlan /* new outer vlan id value */;
1464 /* tunnel configuration. */
1465 struct pf_update_tunnel_config tunnel_config;
1474 ENGX2_PORTX1 /* 2 engines x 1 port */,
1475 ENGX2_PORTX2 /* 2 engines x 2 ports */,
1476 ENGX1_PORTX1 /* 1 engine x 1 port */,
1477 ENGX1_PORTX2 /* 1 engine x 2 ports */,
1478 ENGX1_PORTX4 /* 1 engine x 4 ports */,
1485 * use to index in hsi_fp_[major|minor]_ver_arr per protocol
1487 enum protocol_version_array_key {
1490 MAX_PROTOCOL_VERSION_ARRAY_KEY
1498 struct rdma_sent_stats {
1499 struct regpair sent_bytes /* number of total RDMA bytes sent */;
1500 struct regpair sent_pkts /* number of total RDMA packets sent */;
1504 * Pstorm non-triggering VF zone
1506 struct pstorm_non_trigger_vf_zone {
1507 /* VF statistic bucket */
1508 struct eth_pstorm_per_queue_stat eth_queue_stat;
1509 struct rdma_sent_stats rdma_stats /* RoCE sent statistics */;
1516 struct pstorm_vf_zone {
1517 /* non-interrupt-triggering zone */
1518 struct pstorm_non_trigger_vf_zone non_trigger;
1519 struct regpair reserved[7] /* vf_zone size mus be power of 2 */;
1524 * Ramrod Header of SPQE
1526 struct ramrod_header {
1527 __le32 cid /* Slowpath Connection CID */;
1528 u8 cmd_id /* Ramrod Cmd (Per Protocol Type) */;
1529 u8 protocol_id /* Ramrod Protocol ID */;
1530 __le16 echo /* Ramrod echo */;
1537 struct rdma_rcv_stats {
1538 struct regpair rcv_bytes /* number of total RDMA bytes received */;
1539 struct regpair rcv_pkts /* number of total RDMA packets received */;
1545 * Data for update QCN/DCQCN RL ramrod
1547 struct rl_update_ramrod_data {
1548 u8 qcn_update_param_flg /* Update QCN global params: timeout. */;
1549 /* Update DCQCN global params: timeout, g, k. */
1550 u8 dcqcn_update_param_flg;
1551 u8 rl_init_flg /* Init RL parameters, when RL disabled. */;
1552 u8 rl_start_flg /* Start RL in IDLE state. Set rate to maximum. */;
1553 u8 rl_stop_flg /* Stop RL. */;
1554 u8 rl_id_first /* ID of first or single RL, that will be updated. */;
1555 /* ID of last RL, that will be updated. If clear, single RL will updated. */
1557 u8 rl_dc_qcn_flg /* If set, RL will used for DCQCN. */;
1558 __le32 rl_bc_rate /* Byte Counter Limit. */;
1559 __le16 rl_max_rate /* Maximum rate in 1.6 Mbps resolution. */;
1560 __le16 rl_r_ai /* Active increase rate. */;
1561 __le16 rl_r_hai /* Hyper active increase rate. */;
1562 __le16 dcqcn_g /* DCQCN Alpha update gain in 1/64K resolution . */;
1563 __le32 dcqcn_k_us /* DCQCN Alpha update interval. */;
1564 __le32 dcqcn_timeuot_us /* DCQCN timeout. */;
1565 __le32 qcn_timeuot_us /* QCN timeout. */;
1571 * Slowpath Element (SPQE)
1573 struct slow_path_element {
1574 struct ramrod_header hdr /* Ramrod Header */;
1575 struct regpair data_ptr /* Pointer to the Ramrod Data on the Host */;
1580 * Tstorm non-triggering VF zone
1582 struct tstorm_non_trigger_vf_zone {
1583 struct rdma_rcv_stats rdma_stats /* RoCE received statistics */;
1587 struct tstorm_per_port_stat {
1588 /* packet is dropped because it was truncated in NIG */
1589 struct regpair trunc_error_discard;
1590 /* packet is dropped because of Ethernet FCS error */
1591 struct regpair mac_error_discard;
1592 /* packet is dropped because classification was unsuccessful */
1593 struct regpair mftag_filter_discard;
1594 /* packet was passed to Ethernet and dropped because of no mac filter match */
1595 struct regpair eth_mac_filter_discard;
1596 /* packet passed to Light L2 and dropped because Light L2 is not configured for
1599 struct regpair ll2_mac_filter_discard;
1600 /* packet passed to Light L2 and dropped because Light L2 is not configured for
1603 struct regpair ll2_conn_disabled_discard;
1604 /* packet is an ISCSI irregular packet */
1605 struct regpair iscsi_irregular_pkt;
1606 /* packet is an FCOE irregular packet */
1607 struct regpair fcoe_irregular_pkt;
1608 /* packet is an ROCE irregular packet */
1609 struct regpair roce_irregular_pkt;
1610 /* packet is an IWARP irregular packet */
1611 struct regpair iwarp_irregular_pkt;
1612 /* packet is an ETH irregular packet */
1613 struct regpair eth_irregular_pkt;
1614 /* packet is an TOE irregular packet */
1615 struct regpair toe_irregular_pkt;
1616 /* packet is an PREROCE irregular packet */
1617 struct regpair preroce_irregular_pkt;
1618 struct regpair eth_gre_tunn_filter_discard /* GRE dropped packets */;
1619 /* VXLAN dropped packets */
1620 struct regpair eth_vxlan_tunn_filter_discard;
1621 /* GENEVE dropped packets */
1622 struct regpair eth_geneve_tunn_filter_discard;
1629 struct tstorm_vf_zone {
1630 /* non-interrupt-triggering zone */
1631 struct tstorm_non_trigger_vf_zone non_trigger;
1636 * Tunnel classification scheme
1639 /* Use MAC and VLAN from first L2 header for vport classification. */
1640 TUNNEL_CLSS_MAC_VLAN = 0,
1641 /* Use MAC from first L2 header and VNI from tunnel header for vport
1644 TUNNEL_CLSS_MAC_VNI,
1645 /* Use MAC and VLAN from last L2 header for vport classification */
1646 TUNNEL_CLSS_INNER_MAC_VLAN,
1647 /* Use MAC from last L2 header and VNI from tunnel header for vport
1650 TUNNEL_CLSS_INNER_MAC_VNI,
1651 /* Use MAC and VLAN from last L2 header for vport classification. If no exact
1652 * match, use MAC and VLAN from first L2 header for classification.
1654 TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE,
1661 * Ustorm non-triggering VF zone
1663 struct ustorm_non_trigger_vf_zone {
1664 /* VF statistic bucket */
1665 struct eth_ustorm_per_queue_stat eth_queue_stat;
1666 struct regpair vf_pf_msg_addr /* VF-PF message address */;
1671 * Ustorm triggering VF zone
1673 struct ustorm_trigger_vf_zone {
1674 u8 vf_pf_msg_valid /* VF-PF message valid flag */;
1682 struct ustorm_vf_zone {
1683 /* non-interrupt-triggering zone */
1684 struct ustorm_non_trigger_vf_zone non_trigger;
1685 struct ustorm_trigger_vf_zone trigger /* interrupt triggering zone */;
1690 * VF-PF channel data
1692 struct vf_pf_channel_data {
1693 /* 0: VF-PF Channel NOT ready. Waiting for ack from PF driver. 1: VF-PF Channel
1694 * is ready for a new transaction.
1697 /* 0: VF-PF Channel is invalid because of malicious VF. 1: VF-PF Channel is
1707 * Ramrod data for VF start ramrod
1709 struct vf_start_ramrod_data {
1710 u8 vf_id /* VF ID */;
1711 /* If set, initial cleanup ack will be sent to parent PF SP event queue */
1713 __le16 opaque_fid /* VF opaque FID */;
1714 u8 personality /* define what type of personality is new VF */;
1716 /* FP HSI version to be used by FW */
1717 struct hsi_fp_ver_struct hsi_fp_ver;
1722 * Ramrod data for VF start ramrod
1724 struct vf_stop_ramrod_data {
1725 u8 vf_id /* VF ID */;
1733 * VF zone size mode.
1735 enum vf_zone_size_mode {
1736 /* Default VF zone size. Up to 192 VF supported. */
1737 VF_ZONE_SIZE_MODE_DEFAULT,
1738 /* Doubled VF zone size. Up to 96 VF supported. */
1739 VF_ZONE_SIZE_MODE_DOUBLE,
1740 /* Quad VF zone size. Up to 48 VF supported. */
1741 VF_ZONE_SIZE_MODE_QUAD,
1742 MAX_VF_ZONE_SIZE_MODE
1749 * Attentions status block
1751 struct atten_status_block {
1755 __le16 sb_index /* status block running index */;
1761 * Igu cleanup bit values to distinguish between clean or producer consumer
1764 enum command_type_bit {
1765 IGU_COMMAND_TYPE_NOP = 0,
1766 IGU_COMMAND_TYPE_SET = 1,
1767 MAX_COMMAND_TYPE_BIT
1776 /* DMA Source. 0 - PCIe, 1 - GRC (use enum dmae_cmd_src_enum) */
1777 #define DMAE_CMD_SRC_MASK 0x1
1778 #define DMAE_CMD_SRC_SHIFT 0
1779 /* DMA destination. 0 - None, 1 - PCIe, 2 - GRC, 3 - None
1780 * (use enum dmae_cmd_dst_enum)
1782 #define DMAE_CMD_DST_MASK 0x3
1783 #define DMAE_CMD_DST_SHIFT 1
1784 /* Completion destination. 0 - PCie, 1 - GRC (use enum dmae_cmd_c_dst_enum) */
1785 #define DMAE_CMD_C_DST_MASK 0x1
1786 #define DMAE_CMD_C_DST_SHIFT 3
1787 /* Reset the CRC result (do not use the previous result as the seed) */
1788 #define DMAE_CMD_CRC_RESET_MASK 0x1
1789 #define DMAE_CMD_CRC_RESET_SHIFT 4
1790 /* Reset the source address in the next go to the same source address of the
1793 #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1
1794 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5
1795 /* Reset the destination address in the next go to the same destination address
1796 * of the previous go
1798 #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1
1799 #define DMAE_CMD_DST_ADDR_RESET_SHIFT 6
1800 /* 0 completion function is the same as src function, 1 - 0 completion
1801 * function is the same as dst function (use enum dmae_cmd_comp_func_enum)
1803 #define DMAE_CMD_COMP_FUNC_MASK 0x1
1804 #define DMAE_CMD_COMP_FUNC_SHIFT 7
1805 /* 0 - Do not write a completion word, 1 - Write a completion word
1806 * (use enum dmae_cmd_comp_word_en_enum)
1808 #define DMAE_CMD_COMP_WORD_EN_MASK 0x1
1809 #define DMAE_CMD_COMP_WORD_EN_SHIFT 8
1810 /* 0 - Do not write a CRC word, 1 - Write a CRC word
1811 * (use enum dmae_cmd_comp_crc_en_enum)
1813 #define DMAE_CMD_COMP_CRC_EN_MASK 0x1
1814 #define DMAE_CMD_COMP_CRC_EN_SHIFT 9
1815 /* The CRC word should be taken from the DMAE address space from address 9+X,
1816 * where X is the value in these bits.
1818 #define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7
1819 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
1820 #define DMAE_CMD_RESERVED1_MASK 0x1
1821 #define DMAE_CMD_RESERVED1_SHIFT 13
1822 #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3
1823 #define DMAE_CMD_ENDIANITY_MODE_SHIFT 14
1824 /* The field specifies how the completion word is affected by PCIe read error. 0
1825 * Send a regular completion, 1 - Send a completion with an error indication,
1826 * 2 do not send a completion (use enum dmae_cmd_error_handling_enum)
1828 #define DMAE_CMD_ERR_HANDLING_MASK 0x3
1829 #define DMAE_CMD_ERR_HANDLING_SHIFT 16
1830 /* The port ID to be placed on the RF FID field of the GRC bus. this field is
1831 * used both when GRC is the destination and when it is the source of the DMAE
1834 #define DMAE_CMD_PORT_ID_MASK 0x3
1835 #define DMAE_CMD_PORT_ID_SHIFT 18
1836 /* Source PCI function number [3:0] */
1837 #define DMAE_CMD_SRC_PF_ID_MASK 0xF
1838 #define DMAE_CMD_SRC_PF_ID_SHIFT 20
1839 /* Destination PCI function number [3:0] */
1840 #define DMAE_CMD_DST_PF_ID_MASK 0xF
1841 #define DMAE_CMD_DST_PF_ID_SHIFT 24
1842 #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1 /* Source VFID valid */
1843 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
1844 #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1 /* Destination VFID valid */
1845 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
1846 #define DMAE_CMD_RESERVED2_MASK 0x3
1847 #define DMAE_CMD_RESERVED2_SHIFT 30
1848 /* PCIe source address low in bytes or GRC source address in DW */
1850 /* PCIe source address high in bytes or reserved (if source is GRC) */
1852 /* PCIe destination address low in bytes or GRC destination address in DW */
1854 /* PCIe destination address high in bytes or reserved (if destination is GRC) */
1856 __le16 length_dw /* Length in DW */;
1858 #define DMAE_CMD_SRC_VF_ID_MASK 0xFF /* Source VF id */
1859 #define DMAE_CMD_SRC_VF_ID_SHIFT 0
1860 #define DMAE_CMD_DST_VF_ID_MASK 0xFF /* Destination VF id */
1861 #define DMAE_CMD_DST_VF_ID_SHIFT 8
1862 /* PCIe completion address low in bytes or GRC completion address in DW */
1863 __le32 comp_addr_lo;
1864 /* PCIe completion address high in bytes or reserved (if completion address is
1867 __le32 comp_addr_hi;
1868 __le32 comp_val /* Value to write to completion address */;
1869 __le32 crc32 /* crc16 result */;
1870 __le32 crc_32_c /* crc32_c result */;
1871 __le16 crc16 /* crc16 result */;
1872 __le16 crc16_c /* crc16_c result */;
1873 __le16 crc10 /* crc_t10 result */;
1875 __le16 xsum16 /* checksum16 result */;
1876 __le16 xsum8 /* checksum8 result */;
1880 enum dmae_cmd_comp_crc_en_enum {
1881 dmae_cmd_comp_crc_disabled /* Do not write a CRC word */,
1882 dmae_cmd_comp_crc_enabled /* Write a CRC word */,
1883 MAX_DMAE_CMD_COMP_CRC_EN_ENUM
1887 enum dmae_cmd_comp_func_enum {
1888 /* completion word and/or CRC will be sent to SRC-PCI function/SRC VFID */
1889 dmae_cmd_comp_func_to_src,
1890 /* completion word and/or CRC will be sent to DST-PCI function/DST VFID */
1891 dmae_cmd_comp_func_to_dst,
1892 MAX_DMAE_CMD_COMP_FUNC_ENUM
1896 enum dmae_cmd_comp_word_en_enum {
1897 dmae_cmd_comp_word_disabled /* Do not write a completion word */,
1898 dmae_cmd_comp_word_enabled /* Write the completion word */,
1899 MAX_DMAE_CMD_COMP_WORD_EN_ENUM
1903 enum dmae_cmd_c_dst_enum {
1904 dmae_cmd_c_dst_pcie,
1906 MAX_DMAE_CMD_C_DST_ENUM
1910 enum dmae_cmd_dst_enum {
1911 dmae_cmd_dst_none_0,
1914 dmae_cmd_dst_none_3,
1915 MAX_DMAE_CMD_DST_ENUM
1919 enum dmae_cmd_error_handling_enum {
1920 /* Send a regular completion (with no error indication) */
1921 dmae_cmd_error_handling_send_regular_comp,
1922 /* Send a completion with an error indication (i.e. set bit 31 of the completion
1925 dmae_cmd_error_handling_send_comp_with_err,
1926 dmae_cmd_error_handling_dont_send_comp /* Do not send a completion */,
1927 MAX_DMAE_CMD_ERROR_HANDLING_ENUM
1931 enum dmae_cmd_src_enum {
1932 dmae_cmd_src_pcie /* The source is the PCIe */,
1933 dmae_cmd_src_grc /* The source is the GRC */,
1934 MAX_DMAE_CMD_SRC_ENUM
1938 struct e4_mstorm_core_conn_ag_ctx {
1939 u8 byte0 /* cdu_validation */;
1940 u8 byte1 /* state */;
1942 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
1943 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1944 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1945 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
1946 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
1947 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
1948 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1949 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
1950 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
1951 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
1953 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1954 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1955 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1956 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
1957 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1958 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
1959 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1960 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
1961 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1962 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
1963 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1964 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
1965 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1966 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
1967 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1968 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
1969 __le16 word0 /* word0 */;
1970 __le16 word1 /* word1 */;
1971 __le32 reg0 /* reg0 */;
1972 __le32 reg1 /* reg1 */;
1979 struct e4_ystorm_core_conn_ag_ctx {
1980 u8 byte0 /* cdu_validation */;
1981 u8 byte1 /* state */;
1983 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
1984 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1985 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1986 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
1987 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
1988 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
1989 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1990 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
1991 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
1992 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
1994 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1995 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1996 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1997 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
1998 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1999 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
2000 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2001 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
2002 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2003 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
2004 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2005 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
2006 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2007 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
2008 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2009 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
2010 u8 byte2 /* byte2 */;
2011 u8 byte3 /* byte3 */;
2012 __le16 word0 /* word0 */;
2013 __le32 reg0 /* reg0 */;
2014 __le32 reg1 /* reg1 */;
2015 __le16 word1 /* word1 */;
2016 __le16 word2 /* word2 */;
2017 __le16 word3 /* word3 */;
2018 __le16 word4 /* word4 */;
2019 __le32 reg2 /* reg2 */;
2020 __le32 reg3 /* reg3 */;
2025 * IGU cleanup command
2027 struct igu_cleanup {
2028 __le32 sb_id_and_flags;
2029 #define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF
2030 #define IGU_CLEANUP_RESERVED0_SHIFT 0
2031 /* cleanup clear - 0, set - 1 */
2032 #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1
2033 #define IGU_CLEANUP_CLEANUP_SET_SHIFT 27
2034 #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7
2035 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28
2036 /* must always be set (use enum command_type_bit) */
2037 #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1
2038 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31
2044 * IGU firmware driver command
2047 struct igu_prod_cons_update prod_cons_update;
2048 struct igu_cleanup cleanup;
2053 * IGU firmware driver command
2055 struct igu_command_reg_ctrl {
2057 __le16 igu_command_reg_ctrl_fields;
2058 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF
2059 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
2060 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7
2061 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12
2062 /* command typ: 0 - read, 1 - write */
2063 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1
2064 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
2069 * IGU mapping line structure
2071 struct igu_mapping_line {
2072 __le32 igu_mapping_line_fields;
2073 #define IGU_MAPPING_LINE_VALID_MASK 0x1
2074 #define IGU_MAPPING_LINE_VALID_SHIFT 0
2075 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF
2076 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1
2077 /* In BB: VF-0-120, PF-0-7; In K2: VF-0-191, PF-0-15 */
2078 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF
2079 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9
2080 #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1 /* PF-1, VF-0 */
2081 #define IGU_MAPPING_LINE_PF_VALID_SHIFT 17
2082 #define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F
2083 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18
2084 #define IGU_MAPPING_LINE_RESERVED_MASK 0xFF
2085 #define IGU_MAPPING_LINE_RESERVED_SHIFT 24
2090 * IGU MSIX line structure
2092 struct igu_msix_vector {
2093 struct regpair address;
2095 __le32 msix_vector_fields;
2096 #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1
2097 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0
2098 #define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF
2099 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1
2100 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF
2101 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16
2102 #define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF
2103 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24
2108 * per encapsulation type enabling flags
2110 struct prs_reg_encapsulation_type_en {
2112 /* Enable bit for Ethernet-over-GRE (L2 GRE) encapsulation. */
2113 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1
2114 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0
2115 /* Enable bit for IP-over-GRE (IP GRE) encapsulation. */
2116 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1
2117 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1
2118 /* Enable bit for VXLAN encapsulation. */
2119 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1
2120 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2
2121 /* Enable bit for T-Tag encapsulation. */
2122 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1
2123 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3
2124 /* Enable bit for Ethernet-over-GENEVE (L2 GENEVE) encapsulation. */
2125 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1
2126 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4
2127 /* Enable bit for IP-over-GENEVE (IP GENEVE) encapsulation. */
2128 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1
2129 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5
2130 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3
2131 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6
2135 enum pxp_tph_st_hint {
2136 TPH_ST_HINT_BIDIR /* Read/Write access by Host and Device */,
2137 TPH_ST_HINT_REQUESTER /* Read/Write access by Device */,
2138 /* Device Write and Host Read, or Host Write and Device Read */
2140 /* Device Write and Host Read, or Host Write and Device Read - with temporal
2143 TPH_ST_HINT_TARGET_PRIO,
2149 * QM hardware structure of enable bypass credit mask
2151 struct qm_rf_bypass_mask {
2153 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1
2154 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0
2155 #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1
2156 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1
2157 #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1
2158 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2
2159 #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1
2160 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3
2161 #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1
2162 #define QM_RF_BYPASS_MASK_PFRL_SHIFT 4
2163 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1
2164 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5
2165 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1
2166 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6
2167 #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1
2168 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7
2173 * QM hardware structure of opportunistic credit mask
2175 struct qm_rf_opportunistic_mask {
2177 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1
2178 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0
2179 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1
2180 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1
2181 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1
2182 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2
2183 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1
2184 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3
2185 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1
2186 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4
2187 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1
2188 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5
2189 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1
2190 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6
2191 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1
2192 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7
2193 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1
2194 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8
2195 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F
2196 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9
2201 * QM hardware structure of QM map memory
2203 struct qm_rf_pq_map {
2205 #define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1 /* PQ active */
2206 #define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0
2207 #define QM_RF_PQ_MAP_RL_ID_MASK 0xFF /* RL ID */
2208 #define QM_RF_PQ_MAP_RL_ID_SHIFT 1
2209 /* the first PQ associated with the VPORT and VOQ of this PQ */
2210 #define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF
2211 #define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT 9
2212 #define QM_RF_PQ_MAP_VOQ_MASK 0x1F /* VOQ */
2213 #define QM_RF_PQ_MAP_VOQ_SHIFT 18
2214 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3 /* WRR weight */
2215 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23
2216 #define QM_RF_PQ_MAP_RL_VALID_MASK 0x1 /* RL active */
2217 #define QM_RF_PQ_MAP_RL_VALID_SHIFT 25
2218 #define QM_RF_PQ_MAP_RESERVED_MASK 0x3F
2219 #define QM_RF_PQ_MAP_RESERVED_SHIFT 26
2224 * Completion params for aggregated interrupt completion
2226 struct sdm_agg_int_comp_params {
2228 /* the number of aggregated interrupt, 0-31 */
2229 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F
2230 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0
2231 /* 1 - set a bit in aggregated vector, 0 - dont set */
2232 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1
2233 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
2234 /* Number of bit in the aggregated vector, 0-279 (TBD) */
2235 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF
2236 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7
2241 * SDM operation gen command (generate aggregative interrupt)
2245 /* completion parameters 0-15 */
2246 #define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF
2247 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
2248 #define SDM_OP_GEN_COMP_TYPE_MASK 0xF /* completion type 16-19 */
2249 #define SDM_OP_GEN_COMP_TYPE_SHIFT 16
2250 #define SDM_OP_GEN_RESERVED_MASK 0xFFF /* reserved 20-31 */
2251 #define SDM_OP_GEN_RESERVED_SHIFT 20
2254 struct ystorm_core_conn_ag_ctx {
2255 u8 byte0 /* cdu_validation */;
2256 u8 byte1 /* state */;
2258 #define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2259 #define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
2260 #define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2261 #define YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
2262 #define YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
2263 #define YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
2264 #define YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
2265 #define YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
2266 #define YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
2267 #define YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
2269 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2270 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
2271 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2272 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
2273 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2274 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
2275 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2276 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
2277 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2278 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
2279 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2280 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
2281 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2282 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
2283 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2284 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
2285 u8 byte2 /* byte2 */;
2286 u8 byte3 /* byte3 */;
2287 __le16 word0 /* word0 */;
2288 __le32 reg0 /* reg0 */;
2289 __le32 reg1 /* reg1 */;
2290 __le16 word1 /* word1 */;
2291 __le16 word2 /* word2 */;
2292 __le16 word3 /* word3 */;
2293 __le16 word4 /* word4 */;
2294 __le32 reg2 /* reg2 */;
2295 __le32 reg3 /* reg3 */;
2298 #endif /* __ECORE_HSI_COMMON__ */