1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
7 #ifndef __ECORE_HSI_COMMON__
8 #define __ECORE_HSI_COMMON__
9 /********************************/
10 /* Add include to common target */
11 /********************************/
12 #include "common_hsi.h"
16 * opcodes for the event ring
18 enum common_event_opcode {
19 COMMON_EVENT_PF_START,
21 COMMON_EVENT_VF_START,
23 COMMON_EVENT_VF_PF_CHANNEL,
25 COMMON_EVENT_PF_UPDATE,
26 COMMON_EVENT_MALICIOUS_VF,
27 COMMON_EVENT_RL_UPDATE,
29 MAX_COMMON_EVENT_OPCODE
34 * Common Ramrod Command IDs
36 enum common_ramrod_cmd_id {
38 COMMON_RAMROD_PF_START /* PF Function Start Ramrod */,
39 COMMON_RAMROD_PF_STOP /* PF Function Stop Ramrod */,
40 COMMON_RAMROD_VF_START /* VF Function Start */,
41 COMMON_RAMROD_VF_STOP /* VF Function Stop Ramrod */,
42 COMMON_RAMROD_PF_UPDATE /* PF update Ramrod */,
43 COMMON_RAMROD_RL_UPDATE /* QCN/DCQCN RL update Ramrod */,
44 COMMON_RAMROD_EMPTY /* Empty Ramrod */,
45 MAX_COMMON_RAMROD_CMD_ID
50 * The core storm context for the Ystorm
52 struct ystorm_core_conn_st_ctx {
57 * The core storm context for the Pstorm
59 struct pstorm_core_conn_st_ctx {
64 * Core Slowpath Connection storm context of Xstorm
66 struct xstorm_core_conn_st_ctx {
67 __le32 spq_base_lo /* SPQ Ring Base Address low dword */;
68 __le32 spq_base_hi /* SPQ Ring Base Address high dword */;
69 /* Consolidation Ring Base Address */
70 struct regpair consolid_base_addr;
71 __le16 spq_cons /* SPQ Ring Consumer */;
72 __le16 consolid_cons /* Consolidation Ring Consumer */;
73 __le32 reserved0[55] /* Pad to 15 cycles */;
76 struct e4_xstorm_core_conn_ag_ctx {
77 u8 reserved0 /* cdu_validation */;
78 u8 core_state /* state */;
81 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
82 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
84 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
85 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1
87 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
88 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2
90 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
91 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
93 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
94 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4
96 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
97 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5
99 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1
100 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6
102 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1
103 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7
106 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1
107 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
109 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1
110 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1
112 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1
113 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2
115 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1
116 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3
118 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1
119 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4
121 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1
122 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5
124 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
125 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
127 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
128 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
131 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
132 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
134 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
135 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2
137 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
138 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4
140 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
141 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6
143 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
144 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
145 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
146 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2
147 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
148 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4
149 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
150 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6
152 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
153 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
154 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
155 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2
157 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
158 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4
160 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3
161 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6
164 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3
165 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
167 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3
168 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2
170 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3
171 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4
173 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3
174 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6
177 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3
178 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
180 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
181 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2
183 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3
184 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4
186 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
187 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
190 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
191 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
193 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3
194 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2
196 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
197 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
199 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
200 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6
202 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
203 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7
206 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
207 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
209 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
210 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1
212 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
213 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2
215 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
216 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3
218 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
219 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4
221 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
222 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5
224 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
225 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6
227 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
228 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7
231 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
232 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
234 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1
235 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1
237 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1
238 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2
240 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1
241 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3
243 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1
244 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4
246 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1
247 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5
249 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1
250 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
252 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
253 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7
256 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
257 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
259 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
260 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
262 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
263 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
265 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1
266 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3
268 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
269 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
271 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1
272 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5
274 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1
275 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6
277 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1
278 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7
281 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1
282 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
284 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1
285 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1
287 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
288 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
290 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
291 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3
293 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
294 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4
296 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
297 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5
299 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
300 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
302 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1
303 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7
306 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1
307 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
309 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1
310 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1
312 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
313 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
315 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
316 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
318 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1
319 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4
321 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1
322 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5
324 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1
325 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6
327 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1
328 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7
331 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1
332 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
334 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1
335 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1
337 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
338 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
340 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
341 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
343 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
344 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
346 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
347 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
349 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
350 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
352 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
353 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
356 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1
357 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
359 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1
360 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1
362 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1
363 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2
365 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1
366 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3
368 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1
369 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4
371 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1
372 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5
374 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3
375 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6
376 u8 byte2 /* byte2 */;
377 __le16 physical_q0 /* physical_q0 */;
378 __le16 consolid_prod /* physical_q1 */;
379 __le16 reserved16 /* physical_q2 */;
380 __le16 tx_bd_cons /* word3 */;
381 __le16 tx_bd_or_spq_prod /* word4 */;
382 __le16 updated_qm_pq_id /* word5 */;
383 __le16 conn_dpi /* conn_dpi */;
384 u8 byte3 /* byte3 */;
385 u8 byte4 /* byte4 */;
386 u8 byte5 /* byte5 */;
387 u8 byte6 /* byte6 */;
388 __le32 reg0 /* reg0 */;
389 __le32 reg1 /* reg1 */;
390 __le32 reg2 /* reg2 */;
391 __le32 reg3 /* reg3 */;
392 __le32 reg4 /* reg4 */;
393 __le32 reg5 /* cf_array0 */;
394 __le32 reg6 /* cf_array1 */;
395 __le16 word7 /* word7 */;
396 __le16 word8 /* word8 */;
397 __le16 word9 /* word9 */;
398 __le16 word10 /* word10 */;
399 __le32 reg7 /* reg7 */;
400 __le32 reg8 /* reg8 */;
401 __le32 reg9 /* reg9 */;
402 u8 byte7 /* byte7 */;
403 u8 byte8 /* byte8 */;
404 u8 byte9 /* byte9 */;
405 u8 byte10 /* byte10 */;
406 u8 byte11 /* byte11 */;
407 u8 byte12 /* byte12 */;
408 u8 byte13 /* byte13 */;
409 u8 byte14 /* byte14 */;
410 u8 byte15 /* byte15 */;
411 u8 e5_reserved /* e5_reserved */;
412 __le16 word11 /* word11 */;
413 __le32 reg10 /* reg10 */;
414 __le32 reg11 /* reg11 */;
415 __le32 reg12 /* reg12 */;
416 __le32 reg13 /* reg13 */;
417 __le32 reg14 /* reg14 */;
418 __le32 reg15 /* reg15 */;
419 __le32 reg16 /* reg16 */;
420 __le32 reg17 /* reg17 */;
421 __le32 reg18 /* reg18 */;
422 __le32 reg19 /* reg19 */;
423 __le16 word12 /* word12 */;
424 __le16 word13 /* word13 */;
425 __le16 word14 /* word14 */;
426 __le16 word15 /* word15 */;
429 struct e4_tstorm_core_conn_ag_ctx {
430 u8 byte0 /* cdu_validation */;
431 u8 byte1 /* state */;
433 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
434 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
435 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
436 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
437 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
438 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2
439 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
440 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3
441 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
442 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4
443 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
444 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5
445 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
446 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6
448 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
449 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
450 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
451 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2
452 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
453 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4
454 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
455 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6
457 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
458 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
459 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
460 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2
461 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
462 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4
463 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
464 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6
466 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
467 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
468 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
469 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2
470 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
471 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4
472 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
473 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5
474 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
475 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6
476 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
477 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7
479 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
480 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
481 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
482 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1
483 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
484 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2
485 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
486 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3
487 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
488 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4
489 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
490 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5
491 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
492 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6
493 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
494 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
496 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
497 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
498 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
499 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
500 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
501 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
502 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
503 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
504 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
505 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
506 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
507 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
508 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
509 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
510 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
511 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
512 __le32 reg0 /* reg0 */;
513 __le32 reg1 /* reg1 */;
514 __le32 reg2 /* reg2 */;
515 __le32 reg3 /* reg3 */;
516 __le32 reg4 /* reg4 */;
517 __le32 reg5 /* reg5 */;
518 __le32 reg6 /* reg6 */;
519 __le32 reg7 /* reg7 */;
520 __le32 reg8 /* reg8 */;
521 u8 byte2 /* byte2 */;
522 u8 byte3 /* byte3 */;
523 __le16 word0 /* word0 */;
524 u8 byte4 /* byte4 */;
525 u8 byte5 /* byte5 */;
526 __le16 word1 /* word1 */;
527 __le16 word2 /* conn_dpi */;
528 __le16 word3 /* word3 */;
529 __le32 reg9 /* reg9 */;
530 __le32 reg10 /* reg10 */;
533 struct e4_ustorm_core_conn_ag_ctx {
534 u8 reserved /* cdu_validation */;
535 u8 byte1 /* state */;
537 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
538 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
539 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
540 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
541 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
542 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
543 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
544 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
545 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
546 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
548 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
549 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
550 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
551 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2
552 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
553 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4
554 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
555 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6
557 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
558 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
559 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
560 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
561 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
562 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
563 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
564 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3
565 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
566 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4
567 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
568 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5
569 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
570 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6
571 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
572 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
574 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
575 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
576 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
577 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
578 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
579 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
580 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
581 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
582 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
583 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
584 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
585 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
586 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
587 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
588 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
589 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
590 u8 byte2 /* byte2 */;
591 u8 byte3 /* byte3 */;
592 __le16 word0 /* conn_dpi */;
593 __le16 word1 /* word1 */;
594 __le32 rx_producers /* reg0 */;
595 __le32 reg1 /* reg1 */;
596 __le32 reg2 /* reg2 */;
597 __le32 reg3 /* reg3 */;
598 __le16 word2 /* word2 */;
599 __le16 word3 /* word3 */;
603 * The core storm context for the Mstorm
605 struct mstorm_core_conn_st_ctx {
610 * The core storm context for the Ustorm
612 struct ustorm_core_conn_st_ctx {
617 * core connection context
619 struct e4_core_conn_context {
620 /* ystorm storm context */
621 struct ystorm_core_conn_st_ctx ystorm_st_context;
622 struct regpair ystorm_st_padding[2] /* padding */;
623 /* pstorm storm context */
624 struct pstorm_core_conn_st_ctx pstorm_st_context;
625 struct regpair pstorm_st_padding[2] /* padding */;
626 /* xstorm storm context */
627 struct xstorm_core_conn_st_ctx xstorm_st_context;
628 /* xstorm aggregative context */
629 struct e4_xstorm_core_conn_ag_ctx xstorm_ag_context;
630 /* tstorm aggregative context */
631 struct e4_tstorm_core_conn_ag_ctx tstorm_ag_context;
632 /* ustorm aggregative context */
633 struct e4_ustorm_core_conn_ag_ctx ustorm_ag_context;
634 /* mstorm storm context */
635 struct mstorm_core_conn_st_ctx mstorm_st_context;
636 /* ustorm storm context */
637 struct ustorm_core_conn_st_ctx ustorm_st_context;
638 struct regpair ustorm_st_padding[2] /* padding */;
643 * How ll2 should deal with packet upon errors
645 enum core_error_handle {
646 LL2_DROP_PACKET /* If error occurs drop packet */,
647 LL2_DO_NOTHING /* If error occurs do nothing */,
648 LL2_ASSERT /* If error occurs assert */,
649 MAX_CORE_ERROR_HANDLE
654 * opcodes for the event ring
656 enum core_event_opcode {
657 CORE_EVENT_TX_QUEUE_START,
658 CORE_EVENT_TX_QUEUE_STOP,
659 CORE_EVENT_RX_QUEUE_START,
660 CORE_EVENT_RX_QUEUE_STOP,
661 CORE_EVENT_RX_QUEUE_FLUSH,
662 CORE_EVENT_TX_QUEUE_UPDATE,
663 MAX_CORE_EVENT_OPCODE
668 * The L4 pseudo checksum mode for Core
670 enum core_l4_pseudo_checksum_mode {
671 /* Pseudo Checksum on packet is calculated with the correct packet length. */
672 CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
673 /* Pseudo Checksum on packet is calculated with zero length. */
674 CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
675 MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
680 * Light-L2 RX Producers in Tstorm RAM
682 struct core_ll2_port_stats {
683 struct regpair gsi_invalid_hdr;
684 struct regpair gsi_invalid_pkt_length;
685 struct regpair gsi_unsupported_pkt_typ;
686 struct regpair gsi_crcchksm_error;
691 * Ethernet TX Per Queue Stats
693 struct core_ll2_pstorm_per_queue_stat {
694 /* number of total bytes sent without errors */
695 struct regpair sent_ucast_bytes;
696 /* number of total bytes sent without errors */
697 struct regpair sent_mcast_bytes;
698 /* number of total bytes sent without errors */
699 struct regpair sent_bcast_bytes;
700 /* number of total packets sent without errors */
701 struct regpair sent_ucast_pkts;
702 /* number of total packets sent without errors */
703 struct regpair sent_mcast_pkts;
704 /* number of total packets sent without errors */
705 struct regpair sent_bcast_pkts;
710 * Light-L2 RX Producers in Tstorm RAM
712 struct core_ll2_rx_prod {
713 __le16 bd_prod /* BD Producer */;
714 __le16 cqe_prod /* CQE Producer */;
719 struct core_ll2_tstorm_per_queue_stat {
720 /* Number of packets discarded because they are bigger than MTU */
721 struct regpair packet_too_big_discard;
722 /* Number of packets discarded due to lack of host buffers */
723 struct regpair no_buff_discard;
727 struct core_ll2_ustorm_per_queue_stat {
728 struct regpair rcv_ucast_bytes;
729 struct regpair rcv_mcast_bytes;
730 struct regpair rcv_bcast_bytes;
731 struct regpair rcv_ucast_pkts;
732 struct regpair rcv_mcast_pkts;
733 struct regpair rcv_bcast_pkts;
738 * Core Ramrod Command IDs (light L2)
740 enum core_ramrod_cmd_id {
742 CORE_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */,
743 CORE_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */,
744 CORE_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */,
745 CORE_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */,
746 CORE_RAMROD_RX_QUEUE_FLUSH /* RX Flush queue Ramrod */,
747 CORE_RAMROD_TX_QUEUE_UPDATE /* TX Queue Update Ramrod */,
748 MAX_CORE_RAMROD_CMD_ID
753 * Core RX CQE Type for Light L2
755 enum core_roce_flavor_type {
758 MAX_CORE_ROCE_FLAVOR_TYPE
763 * Specifies how ll2 should deal with packets errors: packet_too_big and no_buff
765 struct core_rx_action_on_error {
767 /* ll2 how to handle error packet_too_big (use enum core_error_handle) */
768 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
769 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
770 /* ll2 how to handle error with no_buff (use enum core_error_handle) */
771 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
772 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2
773 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
774 #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4
779 * Core RX BD for Light L2
788 * Core RX CM offload BD for Light L2
790 struct core_rx_bd_with_buff_len {
797 * Core RX CM offload BD for Light L2
799 union core_rx_bd_union {
800 struct core_rx_bd rx_bd /* Core Rx Bd static buffer size */;
801 /* Core Rx Bd with dynamic buffer length */
802 struct core_rx_bd_with_buff_len rx_bd_with_len;
808 * Opaque Data for Light L2 RX CQE .
810 struct core_rx_cqe_opaque_data {
811 __le32 data[2] /* Opaque CQE Data */;
816 * Core RX CQE Type for Light L2
818 enum core_rx_cqe_type {
819 CORE_RX_CQE_ILLIGAL_TYPE /* Bad RX Cqe type */,
820 CORE_RX_CQE_TYPE_REGULAR /* Regular Core RX CQE */,
821 CORE_RX_CQE_TYPE_GSI_OFFLOAD /* Fp Gsi offload RX CQE */,
822 CORE_RX_CQE_TYPE_SLOW_PATH /* Slow path Core RX CQE */,
828 * Core RX CQE for Light L2 .
830 struct core_rx_fast_path_cqe {
831 u8 type /* CQE type */;
832 /* Offset (in bytes) of the packet from start of the buffer */
834 /* Parsing and error flags from the parser */
835 struct parsing_and_err_flags parse_flags;
836 __le16 packet_length /* Total packet length (from the parser) */;
837 __le16 vlan /* 802.1q VLAN tag */;
838 struct core_rx_cqe_opaque_data opaque_data /* Opaque Data */;
839 /* bit- map: each bit represents a specific error. errors indications are
840 * provided by the cracker. see spec for detailed description
842 struct parsing_err_flags err_flags;
848 * Core Rx CM offload CQE .
850 struct core_rx_gsi_offload_cqe {
851 u8 type /* CQE type */;
852 u8 data_length_error /* set if gsi data is bigger than buff */;
853 /* Parsing and error flags from the parser */
854 struct parsing_and_err_flags parse_flags;
855 __le16 data_length /* Total packet length (from the parser) */;
856 __le16 vlan /* 802.1q VLAN tag */;
857 __le32 src_mac_addrhi /* hi 4 bytes source mac address */;
858 __le16 src_mac_addrlo /* lo 2 bytes of source mac address */;
859 /* These are the lower 16 bit of QP id in RoCE BTH header */
861 __le32 src_qp /* Source QP from DETH header */;
866 * Core RX CQE for Light L2 .
868 struct core_rx_slow_path_cqe {
869 u8 type /* CQE type */;
872 struct core_rx_cqe_opaque_data opaque_data /* Opaque Data */;
877 * Core RX CM offload BD for Light L2
879 union core_rx_cqe_union {
880 struct core_rx_fast_path_cqe rx_cqe_fp /* Fast path CQE */;
881 struct core_rx_gsi_offload_cqe rx_cqe_gsi /* GSI offload CQE */;
882 struct core_rx_slow_path_cqe rx_cqe_sp /* Slow path CQE */;
890 * Ramrod data for rx queue start ramrod
892 struct core_rx_start_ramrod_data {
893 struct regpair bd_base /* bd address of the first bd page */;
894 struct regpair cqe_pbl_addr /* Base address on host of CQE PBL */;
895 __le16 mtu /* Maximum transmission unit */;
896 __le16 sb_id /* Status block ID */;
897 u8 sb_index /* index of the protocol index */;
898 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
899 u8 complete_event_flg /* post completion to the event ring if set */;
900 u8 drop_ttl0_flg /* drop packet with ttl0 if set */;
901 __le16 num_of_pbl_pages /* Num of pages in CQE PBL */;
902 /* if set, 802.1q tags will be removed and copied to CQE */
903 /* if set, 802.1q tags will be removed and copied to CQE */
904 u8 inner_vlan_stripping_en;
905 /* if set and inner vlan does not exist, the outer vlan will copied to CQE as
906 * inner vlan. should be used in MF_OVLAN mode only.
908 u8 report_outer_vlan;
909 u8 queue_id /* Light L2 RX Queue ID */;
910 u8 main_func_queue /* Is this the main queue for the PF */;
911 /* Duplicate broadcast packets to LL2 main queue in mf_si mode. Valid if
912 * main_func_queue is set.
914 u8 mf_si_bcast_accept_all;
915 /* Duplicate multicast packets to LL2 main queue in mf_si mode. Valid if
916 * main_func_queue is set.
918 u8 mf_si_mcast_accept_all;
919 /* Specifies how ll2 should deal with packets errors: packet_too_big and
922 struct core_rx_action_on_error action_on_error;
923 /* set when in GSI offload mode on ROCE connection */
925 /* If set, the inner vlan (802.1q tag) priority that is written to cqe will be
926 * zero out, used for TenantDcb
928 u8 wipe_inner_vlan_pri_en;
934 * Ramrod data for rx queue stop ramrod
936 struct core_rx_stop_ramrod_data {
937 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
938 u8 complete_event_flg /* post completion to the event ring if set */;
939 u8 queue_id /* Light L2 RX Queue ID */;
946 * Flags for Core TX BD
948 struct core_tx_bd_data {
950 /* Do not allow additional VLAN manipulations on this packet (DCB) */
951 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
952 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0
953 /* Insert VLAN into packet. Cannot be set for LB packets
954 * (tx_dst == CORE_TX_DEST_LB)
956 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
957 #define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1
958 /* This is the first BD of the packet (for debug) */
959 #define CORE_TX_BD_DATA_START_BD_MASK 0x1
960 #define CORE_TX_BD_DATA_START_BD_SHIFT 2
961 /* Calculate the IP checksum for the packet */
962 #define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
963 #define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3
964 /* Calculate the L4 checksum for the packet */
965 #define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
966 #define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4
967 /* Packet is IPv6 with extensions */
968 #define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
969 #define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5
970 /* If IPv6+ext, and if l4_csum is 1, than this field indicates L4 protocol:
973 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
974 #define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6
975 /* The pseudo checksum mode to place in the L4 checksum field. Required only
976 * when IPv6+ext and l4_csum is set. (use enum core_l4_pseudo_checksum_mode)
978 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1
979 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7
980 /* Number of BDs that make up one packet - width wide enough to present
981 * CORE_LL2_TX_MAX_BDS_PER_PACKET
983 #define CORE_TX_BD_DATA_NBDS_MASK 0xF
984 #define CORE_TX_BD_DATA_NBDS_SHIFT 8
985 /* Use roce_flavor enum - Differentiate between Roce flavors is valid when
986 * connType is ROCE (use enum core_roce_flavor_type)
988 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
989 #define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12
990 /* Calculate ip length */
991 #define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
992 #define CORE_TX_BD_DATA_IP_LEN_SHIFT 13
993 /* disables the STAG insertion, relevant only in MF OVLAN mode. */
994 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK 0x1
995 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_SHIFT 14
996 #define CORE_TX_BD_DATA_RESERVED0_MASK 0x1
997 #define CORE_TX_BD_DATA_RESERVED0_SHIFT 15
1001 * Core TX BD for Light L2
1004 struct regpair addr /* Buffer Address */;
1005 __le16 nbytes /* Number of Bytes in Buffer */;
1006 /* Network packets: VLAN to insert to packet (if insertion flag set) LoopBack
1007 * packets: echo data to pass to Rx
1009 __le16 nw_vlan_or_lb_echo;
1010 struct core_tx_bd_data bd_data /* BD Flags */;
1012 /* L4 Header Offset from start of packet (in Words). This is needed if both
1013 * l4_csum and ipv6_ext are set
1015 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF
1016 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0
1017 /* Packet destination - Network, Loopback or Drop (use enum core_tx_dest) */
1018 #define CORE_TX_BD_TX_DST_MASK 0x3
1019 #define CORE_TX_BD_TX_DST_SHIFT 14
1025 * Light L2 TX Destination
1028 CORE_TX_DEST_NW /* TX Destination to the Network */,
1029 CORE_TX_DEST_LB /* TX Destination to the Loopback */,
1030 CORE_TX_DEST_RESERVED,
1031 CORE_TX_DEST_DROP /* TX Drop */,
1037 * Ramrod data for tx queue start ramrod
1039 struct core_tx_start_ramrod_data {
1040 struct regpair pbl_base_addr /* Address of the pbl page */;
1041 __le16 mtu /* Maximum transmission unit */;
1042 __le16 sb_id /* Status block ID */;
1043 u8 sb_index /* Status block protocol index */;
1044 u8 stats_en /* Statistics Enable */;
1045 u8 stats_id /* Statistics Counter ID */;
1046 u8 conn_type /* connection type that loaded ll2 */;
1047 __le16 pbl_size /* Number of BD pages pointed by PBL */;
1048 __le16 qm_pq_id /* QM PQ ID */;
1049 /* set when in GSI offload mode on ROCE connection */
1050 u8 gsi_offload_flag;
1051 /* vport id of the current connection, used to access non_rdma_in_to_in_pri_map
1052 * which is per vport
1060 * Ramrod data for tx queue stop ramrod
1062 struct core_tx_stop_ramrod_data {
1063 __le32 reserved0[2];
1068 * Ramrod data for tx queue update ramrod
1070 struct core_tx_update_ramrod_data {
1071 u8 update_qm_pq_id_flg /* Flag to Update QM PQ ID */;
1073 __le16 qm_pq_id /* Updated QM PQ ID */;
1074 __le32 reserved1[1];
1079 * Enum flag for what type of dcb data to update
1081 enum dcb_dscp_update_mode {
1082 /* use when no change should be done to DCB data */
1083 DONT_UPDATE_DCB_DSCP,
1084 UPDATE_DCB /* use to update only L2 (vlan) priority */,
1085 UPDATE_DSCP /* use to update only IP DSCP */,
1086 UPDATE_DCB_DSCP /* update vlan pri and DSCP */,
1087 MAX_DCB_DSCP_UPDATE_FLAG
1091 struct eth_mstorm_per_pf_stat {
1092 struct regpair gre_discard_pkts /* Dropped GRE RX packets */;
1093 struct regpair vxlan_discard_pkts /* Dropped VXLAN RX packets */;
1094 struct regpair geneve_discard_pkts /* Dropped GENEVE RX packets */;
1095 struct regpair lb_discard_pkts /* Dropped Tx switched packets */;
1099 struct eth_mstorm_per_queue_stat {
1100 /* Number of packets discarded because TTL=0 (in IPv4) or hopLimit=0 (IPv6) */
1101 struct regpair ttl0_discard;
1102 /* Number of packets discarded because they are bigger than MTU */
1103 struct regpair packet_too_big_discard;
1104 /* Number of packets discarded due to lack of host buffers (BDs/SGEs/CQEs) */
1105 struct regpair no_buff_discard;
1106 /* Number of packets discarded because of no active Rx connection */
1107 struct regpair not_active_discard;
1108 /* number of coalesced packets in all TPA aggregations */
1109 struct regpair tpa_coalesced_pkts;
1110 /* total number of TPA aggregations */
1111 struct regpair tpa_coalesced_events;
1112 /* number of aggregations, which abnormally ended */
1113 struct regpair tpa_aborts_num;
1114 /* total TCP payload length in all TPA aggregations */
1115 struct regpair tpa_coalesced_bytes;
1120 * Ethernet TX Per PF
1122 struct eth_pstorm_per_pf_stat {
1123 /* number of total ucast bytes sent on loopback port without errors */
1124 struct regpair sent_lb_ucast_bytes;
1125 /* number of total mcast bytes sent on loopback port without errors */
1126 struct regpair sent_lb_mcast_bytes;
1127 /* number of total bcast bytes sent on loopback port without errors */
1128 struct regpair sent_lb_bcast_bytes;
1129 /* number of total ucast packets sent on loopback port without errors */
1130 struct regpair sent_lb_ucast_pkts;
1131 /* number of total mcast packets sent on loopback port without errors */
1132 struct regpair sent_lb_mcast_pkts;
1133 /* number of total bcast packets sent on loopback port without errors */
1134 struct regpair sent_lb_bcast_pkts;
1135 struct regpair sent_gre_bytes /* Sent GRE bytes */;
1136 struct regpair sent_vxlan_bytes /* Sent VXLAN bytes */;
1137 struct regpair sent_geneve_bytes /* Sent GENEVE bytes */;
1138 struct regpair sent_gre_pkts /* Sent GRE packets */;
1139 struct regpair sent_vxlan_pkts /* Sent VXLAN packets */;
1140 struct regpair sent_geneve_pkts /* Sent GENEVE packets */;
1141 struct regpair gre_drop_pkts /* Dropped GRE TX packets */;
1142 struct regpair vxlan_drop_pkts /* Dropped VXLAN TX packets */;
1143 struct regpair geneve_drop_pkts /* Dropped GENEVE TX packets */;
1148 * Ethernet TX Per Queue Stats
1150 struct eth_pstorm_per_queue_stat {
1151 /* number of total bytes sent without errors */
1152 struct regpair sent_ucast_bytes;
1153 /* number of total bytes sent without errors */
1154 struct regpair sent_mcast_bytes;
1155 /* number of total bytes sent without errors */
1156 struct regpair sent_bcast_bytes;
1157 /* number of total packets sent without errors */
1158 struct regpair sent_ucast_pkts;
1159 /* number of total packets sent without errors */
1160 struct regpair sent_mcast_pkts;
1161 /* number of total packets sent without errors */
1162 struct regpair sent_bcast_pkts;
1163 /* number of total packets dropped due to errors */
1164 struct regpair error_drop_pkts;
1169 * ETH Rx producers data
1171 struct eth_rx_rate_limit {
1172 /* Rate Limit Multiplier - (Storm Clock (MHz) * 8 / Desired Bandwidth (MB/s)) */
1174 /* Constant term to add (or subtract from number of cycles) */
1176 u8 add_sub_cnst /* Add (1) or subtract (0) constant term */;
1182 /* Update RSS indirection table entry command. One outstanding command supported
1185 struct eth_tstorm_rss_update_data {
1186 /* Valid flag. Driver must set this flag, FW clear valid flag when ready for new
1187 * RSS update command.
1190 /* Global VPORT ID. If RSS is disable for VPORT, RSS update command will be
1194 u8 ind_table_index /* RSS indirect table index that will be updated. */;
1196 __le16 ind_table_value /* RSS indirect table new value. */;
1197 __le16 reserved1 /* reserved. */;
1201 struct eth_ustorm_per_pf_stat {
1202 /* number of total ucast bytes received on loopback port without errors */
1203 struct regpair rcv_lb_ucast_bytes;
1204 /* number of total mcast bytes received on loopback port without errors */
1205 struct regpair rcv_lb_mcast_bytes;
1206 /* number of total bcast bytes received on loopback port without errors */
1207 struct regpair rcv_lb_bcast_bytes;
1208 /* number of total ucast packets received on loopback port without errors */
1209 struct regpair rcv_lb_ucast_pkts;
1210 /* number of total mcast packets received on loopback port without errors */
1211 struct regpair rcv_lb_mcast_pkts;
1212 /* number of total bcast packets received on loopback port without errors */
1213 struct regpair rcv_lb_bcast_pkts;
1214 struct regpair rcv_gre_bytes /* Received GRE bytes */;
1215 struct regpair rcv_vxlan_bytes /* Received VXLAN bytes */;
1216 struct regpair rcv_geneve_bytes /* Received GENEVE bytes */;
1217 struct regpair rcv_gre_pkts /* Received GRE packets */;
1218 struct regpair rcv_vxlan_pkts /* Received VXLAN packets */;
1219 struct regpair rcv_geneve_pkts /* Received GENEVE packets */;
1223 struct eth_ustorm_per_queue_stat {
1224 struct regpair rcv_ucast_bytes;
1225 struct regpair rcv_mcast_bytes;
1226 struct regpair rcv_bcast_bytes;
1227 struct regpair rcv_ucast_pkts;
1228 struct regpair rcv_mcast_pkts;
1229 struct regpair rcv_bcast_pkts;
1234 * Event Ring VF-PF Channel data
1236 struct vf_pf_channel_eqe_data {
1237 struct regpair msg_addr /* VF-PF message address */;
1241 * Event Ring malicious VF data
1243 struct malicious_vf_eqe_data {
1244 u8 vf_id /* Malicious VF ID */;
1245 u8 err_id /* Malicious VF error (use enum malicious_vf_error_id) */;
1250 * Event Ring initial cleanup data
1252 struct initial_cleanup_eqe_data {
1253 u8 vf_id /* VF ID */;
1260 union event_ring_data {
1261 u8 bytes[8] /* Byte Array */;
1262 struct vf_pf_channel_eqe_data vf_pf_channel /* VF-PF Channel data */;
1263 struct iscsi_eqe_data iscsi_info /* Dedicated fields to iscsi data */;
1264 /* Dedicated fields to iscsi connect done results */
1265 struct iscsi_connect_done_results iscsi_conn_done_info;
1266 struct malicious_vf_eqe_data malicious_vf /* Malicious VF data */;
1267 /* VF Initial Cleanup data */
1268 struct initial_cleanup_eqe_data vf_init_cleanup;
1275 struct event_ring_entry {
1276 u8 protocol_id /* Event Protocol ID (use enum protocol_type) */;
1277 u8 opcode /* Event Opcode */;
1278 __le16 reserved0 /* Reserved */;
1279 __le16 echo /* Echo value from ramrod data on the host */;
1280 u8 fw_return_code /* FW return code for SP ramrods */;
1282 /* 0: synchronous EQE - a completion of SP message. 1: asynchronous EQE */
1283 #define EVENT_RING_ENTRY_ASYNC_MASK 0x1
1284 #define EVENT_RING_ENTRY_ASYNC_SHIFT 0
1285 #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
1286 #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
1287 union event_ring_data data;
1291 * Event Ring Next Page Address
1293 struct event_ring_next_addr {
1294 struct regpair addr /* Next Page Address */;
1295 __le32 reserved[2] /* Reserved */;
1299 * Event Ring Element
1301 union event_ring_element {
1302 struct event_ring_entry entry /* Event Ring Entry */;
1303 /* Event Ring Next Page Address */
1304 struct event_ring_next_addr next_addr;
1312 enum fw_flow_ctrl_mode {
1315 MAX_FW_FLOW_CTRL_MODE
1322 enum gft_profile_type {
1323 /* tunnel type, inner 4 tuple, IP type and L4 type match. */
1324 GFT_PROFILE_TYPE_4_TUPLE,
1325 /* tunnel type, inner L4 destination port, IP type and L4 type match. */
1326 GFT_PROFILE_TYPE_L4_DST_PORT,
1327 /* tunnel type, inner IP destination address and IP type match. */
1328 GFT_PROFILE_TYPE_IP_DST_ADDR,
1329 /* tunnel type, inner IP source address and IP type match. */
1330 GFT_PROFILE_TYPE_IP_SRC_ADDR,
1331 GFT_PROFILE_TYPE_TUNNEL_TYPE /* tunnel type and outer IP type match. */,
1332 MAX_GFT_PROFILE_TYPE
1337 * Major and Minor hsi Versions
1339 struct hsi_fp_ver_struct {
1340 u8 minor_ver_arr[2] /* Minor Version of hsi loading pf */;
1341 u8 major_ver_arr[2] /* Major Version of driver loading pf */;
1349 INTEG_PHASE_BB_A0_LATEST = 3 /* BB A0 latest integration phase */,
1350 INTEG_PHASE_BB_B0_NO_MCP = 10 /* BB B0 without MCP */,
1351 INTEG_PHASE_BB_B0_WITH_MCP = 11 /* BB B0 with MCP */,
1359 enum iwarp_ll2_tx_queues {
1360 /* LL2 queue for OOO packets sent in-order by the driver */
1361 IWARP_LL2_IN_ORDER_TX_QUEUE = 1,
1362 /* LL2 queue for unaligned packets sent aligned by the driver */
1363 IWARP_LL2_ALIGNED_TX_QUEUE,
1364 /* LL2 queue for unaligned packets sent aligned and was right-trimmed by the
1367 IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE,
1368 IWARP_LL2_ERROR /* Error indication */,
1369 MAX_IWARP_LL2_TX_QUEUES
1374 * Malicious VF error ID
1376 enum malicious_vf_error_id {
1377 MALICIOUS_VF_NO_ERROR /* Zero placeholder value */,
1378 /* Writing to VF/PF channel when it is not ready */
1379 VF_PF_CHANNEL_NOT_READY,
1380 VF_ZONE_MSG_NOT_VALID /* VF channel message is not valid */,
1381 VF_ZONE_FUNC_NOT_ENABLED /* Parent PF of VF channel is not active */,
1382 /* TX packet is shorter then reported on BDs or from minimal size */
1383 ETH_PACKET_TOO_SMALL,
1384 /* Tx packet with marked as insert VLAN when its illegal */
1385 ETH_ILLEGAL_VLAN_MODE,
1386 ETH_MTU_VIOLATION /* TX packet is greater then MTU */,
1387 /* TX packet has illegal inband tags marked */
1388 ETH_ILLEGAL_INBAND_TAGS,
1389 /* Vlan cant be added to inband tag */
1390 ETH_VLAN_INSERT_AND_INBAND_VLAN,
1391 /* indicated number of BDs for the packet is illegal */
1393 ETH_FIRST_BD_WO_SOP /* 1st BD must have start_bd flag set */,
1394 /* There are not enough BDs for transmission of even one packet */
1395 ETH_INSUFFICIENT_BDS,
1396 ETH_ILLEGAL_LSO_HDR_NBDS /* Header NBDs value is illegal */,
1397 ETH_ILLEGAL_LSO_MSS /* LSO MSS value is more than allowed */,
1398 /* empty BD (which not contains control flags) is illegal */
1400 ETH_ILLEGAL_LSO_HDR_LEN /* LSO header size is above the limit */,
1401 /* In LSO its expected that on the local BD ring there will be at least MSS
1404 ETH_INSUFFICIENT_PAYLOAD,
1405 ETH_EDPM_OUT_OF_SYNC /* Valid BDs on local ring after EDPM L2 sync */,
1406 /* Tunneled packet with IPv6+Ext without a proper number of BDs */
1407 ETH_TUNN_IPV6_EXT_NBD_ERR,
1408 ETH_CONTROL_PACKET_VIOLATION /* VF sent control frame such as PFC */,
1409 ETH_ANTI_SPOOFING_ERR /* Anti-Spoofing verification failure */,
1410 MAX_MALICIOUS_VF_ERROR_ID
1416 * Mstorm non-triggering VF zone
1418 struct mstorm_non_trigger_vf_zone {
1419 /* VF statistic bucket */
1420 struct eth_mstorm_per_queue_stat eth_queue_stat;
1421 /* VF RX queues producers */
1422 struct eth_rx_prod_data
1423 eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD];
1430 struct mstorm_vf_zone {
1431 /* non-interrupt-triggering zone */
1432 struct mstorm_non_trigger_vf_zone non_trigger;
1437 * vlan header including TPID and TCI fields
1439 struct vlan_header {
1440 __le16 tpid /* Tag Protocol Identifier */;
1441 __le16 tci /* Tag Control Information */;
1445 * outer tag configurations
1447 struct outer_tag_config_struct {
1448 /* Enables updating S-tag priority from inner tag or DCB. Should be 1 for Bette
1449 * Davis, UFP with Host Control mode, and UFP with DCB over base interface.
1452 u8 enable_stag_pri_change;
1453 /* If inner_to_outer_pri_map is initialize then set pri_map_valid */
1456 /* In case mf_mode is MF_OVLAN, this field specifies the outer tag protocol
1457 * identifier and outer tag control information
1459 struct vlan_header outer_tag;
1460 /* Map from inner to outer priority. Set pri_map_valid when init map */
1461 u8 inner_to_outer_pri_map[8];
1466 * personality per PF
1468 enum personality_type {
1469 BAD_PERSONALITY_TYP,
1470 PERSONALITY_ISCSI /* iSCSI and LL2 */,
1471 PERSONALITY_FCOE /* Fcoe and LL2 */,
1472 PERSONALITY_RDMA_AND_ETH /* Roce or Iwarp, Eth and LL2 */,
1473 PERSONALITY_RDMA /* Roce and LL2 */,
1474 PERSONALITY_CORE /* CORE(LL2) */,
1475 PERSONALITY_ETH /* Ethernet */,
1476 PERSONALITY_TOE /* Toe and LL2 */,
1477 MAX_PERSONALITY_TYPE
1482 * tunnel configuration
1484 struct pf_start_tunnel_config {
1485 /* Set VXLAN tunnel UDP destination port to vxlan_udp_port. If not set -
1486 * FW will use a default port
1488 u8 set_vxlan_udp_port_flg;
1489 /* Set GENEVE tunnel UDP destination port to geneve_udp_port. If not set -
1490 * FW will use a default port
1492 u8 set_geneve_udp_port_flg;
1493 /* Set no-innet-L2 VXLAN tunnel UDP destination port to
1494 * no_inner_l2_vxlan_udp_port. If not set - FW will use a default port
1496 u8 set_no_inner_l2_vxlan_udp_port_flg;
1497 u8 tunnel_clss_vxlan /* Rx classification scheme for VXLAN tunnel. */;
1498 /* Rx classification scheme for l2 GENEVE tunnel. */
1499 u8 tunnel_clss_l2geneve;
1500 /* Rx classification scheme for ip GENEVE tunnel. */
1501 u8 tunnel_clss_ipgeneve;
1502 u8 tunnel_clss_l2gre /* Rx classification scheme for l2 GRE tunnel. */;
1503 u8 tunnel_clss_ipgre /* Rx classification scheme for ip GRE tunnel. */;
1504 /* VXLAN tunnel UDP destination port. Valid if set_vxlan_udp_port_flg=1 */
1505 __le16 vxlan_udp_port;
1506 /* GENEVE tunnel UDP destination port. Valid if set_geneve_udp_port_flg=1 */
1507 __le16 geneve_udp_port;
1508 /* no-innet-L2 VXLAN tunnel UDP destination port. Valid if
1509 * set_no_inner_l2_vxlan_udp_port_flg=1
1511 __le16 no_inner_l2_vxlan_udp_port;
1516 * Ramrod data for PF start ramrod
1518 struct pf_start_ramrod_data {
1519 struct regpair event_ring_pbl_addr /* Address of event ring PBL */;
1520 /* PBL address of consolidation queue */
1521 struct regpair consolid_q_pbl_addr;
1522 /* tunnel configuration. */
1523 struct pf_start_tunnel_config tunnel_config;
1524 __le16 event_ring_sb_id /* Status block ID */;
1525 /* All VfIds owned by Pf will be from baseVfId till baseVfId+numVfs */
1527 u8 num_vfs /* Amount of vfs owned by PF */;
1528 u8 event_ring_num_pages /* Number of PBL pages in event ring */;
1529 u8 event_ring_sb_index /* Status block index */;
1530 u8 path_id /* HW path ID (engine ID) */;
1531 u8 warning_as_error /* In FW asserts, treat warning as error */;
1532 /* If not set - throw a warning for each ramrod (for debug) */
1533 u8 dont_log_ramrods;
1534 u8 personality /* define what type of personality is new PF */;
1535 /* Log type mask. Each bit set enables a corresponding event type logging.
1536 * Event types are defined as ASSERT_LOG_TYPE_xxx
1538 __le16 log_type_mask;
1539 u8 mf_mode /* Multi function mode */;
1540 u8 integ_phase /* Integration phase */;
1541 /* If set, inter-pf tx switching is allowed in Switch Independent func mode */
1542 u8 allow_npar_tx_switching;
1544 /* FP HSI version to be used by FW */
1545 struct hsi_fp_ver_struct hsi_fp_ver;
1546 /* Outer tag configurations */
1547 struct outer_tag_config_struct outer_tag_config;
1553 * Per protocol DCB data
1555 struct protocol_dcb_data {
1556 u8 dcb_enable_flag /* Enable DCB */;
1557 u8 dscp_enable_flag /* Enable updating DSCP value */;
1558 u8 dcb_priority /* DCB priority */;
1559 u8 dcb_tc /* DCB TC */;
1560 u8 dscp_val /* DSCP value to write if dscp_enable_flag is set */;
1561 /* When DCB is enabled - if this flag is set, dont add VLAN 0 tag to untagged
1564 u8 dcb_dont_add_vlan0;
1568 * Update tunnel configuration
1570 struct pf_update_tunnel_config {
1571 /* Update RX per PF tunnel classification scheme. */
1572 u8 update_rx_pf_clss;
1573 /* Update per PORT default tunnel RX classification scheme for traffic with
1574 * unknown unicast outer MAC in NPAR mode.
1576 u8 update_rx_def_ucast_clss;
1577 /* Update per PORT default tunnel RX classification scheme for traffic with non
1578 * unicast outer MAC in NPAR mode.
1580 u8 update_rx_def_non_ucast_clss;
1581 /* Update VXLAN tunnel UDP destination port. */
1582 u8 set_vxlan_udp_port_flg;
1583 /* Update GENEVE tunnel UDP destination port. */
1584 u8 set_geneve_udp_port_flg;
1585 /* Update no-innet-L2 VXLAN tunnel UDP destination port. */
1586 u8 set_no_inner_l2_vxlan_udp_port_flg;
1587 u8 tunnel_clss_vxlan /* Classification scheme for VXLAN tunnel. */;
1588 /* Classification scheme for l2 GENEVE tunnel. */
1589 u8 tunnel_clss_l2geneve;
1590 /* Classification scheme for ip GENEVE tunnel. */
1591 u8 tunnel_clss_ipgeneve;
1592 u8 tunnel_clss_l2gre /* Classification scheme for l2 GRE tunnel. */;
1593 u8 tunnel_clss_ipgre /* Classification scheme for ip GRE tunnel. */;
1595 __le16 vxlan_udp_port /* VXLAN tunnel UDP destination port. */;
1596 __le16 geneve_udp_port /* GENEVE tunnel UDP destination port. */;
1597 /* no-innet-L2 VXLAN tunnel UDP destination port. */
1598 __le16 no_inner_l2_vxlan_udp_port;
1599 __le16 reserved1[3];
1603 * Data for port update ramrod
1605 struct pf_update_ramrod_data {
1606 /* Update Eth DCB data indication (use enum dcb_dscp_update_mode) */
1607 u8 update_eth_dcb_data_mode;
1608 /* Update FCOE DCB data indication (use enum dcb_dscp_update_mode) */
1609 u8 update_fcoe_dcb_data_mode;
1610 /* Update iSCSI DCB data indication (use enum dcb_dscp_update_mode) */
1611 u8 update_iscsi_dcb_data_mode;
1612 u8 update_roce_dcb_data_mode /* Update ROCE DCB data indication */;
1613 /* Update RROCE (RoceV2) DCB data indication */
1614 u8 update_rroce_dcb_data_mode;
1615 u8 update_iwarp_dcb_data_mode /* Update IWARP DCB data indication */;
1616 u8 update_mf_vlan_flag /* Update MF outer vlan Id */;
1617 /* Update Enable STAG Priority Change indication */
1618 u8 update_enable_stag_pri_change;
1619 struct protocol_dcb_data eth_dcb_data /* core eth related fields */;
1620 struct protocol_dcb_data fcoe_dcb_data /* core fcoe related fields */;
1621 /* core iscsi related fields */
1622 struct protocol_dcb_data iscsi_dcb_data;
1623 struct protocol_dcb_data roce_dcb_data /* core roce related fields */;
1624 /* core roce related fields */
1625 struct protocol_dcb_data rroce_dcb_data;
1626 /* core iwarp related fields */
1627 struct protocol_dcb_data iwarp_dcb_data;
1628 __le16 mf_vlan /* new outer vlan id value */;
1629 /* enables updating S-tag priority from inner tag or DCB. Should be 1 for Bette
1630 * Davis, UFP with Host Control mode, and UFP with DCB over base interface.
1633 u8 enable_stag_pri_change;
1635 /* tunnel configuration. */
1636 struct pf_update_tunnel_config tunnel_config;
1645 ENGX2_PORTX1 /* 2 engines x 1 port */,
1646 ENGX2_PORTX2 /* 2 engines x 2 ports */,
1647 ENGX1_PORTX1 /* 1 engine x 1 port */,
1648 ENGX1_PORTX2 /* 1 engine x 2 ports */,
1649 ENGX1_PORTX4 /* 1 engine x 4 ports */,
1656 * use to index in hsi_fp_[major|minor]_ver_arr per protocol
1658 enum protocol_version_array_key {
1661 MAX_PROTOCOL_VERSION_ARRAY_KEY
1669 struct rdma_sent_stats {
1670 struct regpair sent_bytes /* number of total RDMA bytes sent */;
1671 struct regpair sent_pkts /* number of total RDMA packets sent */;
1675 * Pstorm non-triggering VF zone
1677 struct pstorm_non_trigger_vf_zone {
1678 /* VF statistic bucket */
1679 struct eth_pstorm_per_queue_stat eth_queue_stat;
1680 struct rdma_sent_stats rdma_stats /* RoCE sent statistics */;
1687 struct pstorm_vf_zone {
1688 /* non-interrupt-triggering zone */
1689 struct pstorm_non_trigger_vf_zone non_trigger;
1690 struct regpair reserved[7] /* vf_zone size mus be power of 2 */;
1695 * Ramrod Header of SPQE
1697 struct ramrod_header {
1698 __le32 cid /* Slowpath Connection CID */;
1699 u8 cmd_id /* Ramrod Cmd (Per Protocol Type) */;
1700 u8 protocol_id /* Ramrod Protocol ID */;
1701 __le16 echo /* Ramrod echo */;
1708 struct rdma_rcv_stats {
1709 struct regpair rcv_bytes /* number of total RDMA bytes received */;
1710 struct regpair rcv_pkts /* number of total RDMA packets received */;
1716 * Data for update QCN/DCQCN RL ramrod
1718 struct rl_update_ramrod_data {
1719 u8 qcn_update_param_flg /* Update QCN global params: timeout. */;
1720 /* Update DCQCN global params: timeout, g, k. */
1721 u8 dcqcn_update_param_flg;
1722 u8 rl_init_flg /* Init RL parameters, when RL disabled. */;
1723 u8 rl_start_flg /* Start RL in IDLE state. Set rate to maximum. */;
1724 u8 rl_stop_flg /* Stop RL. */;
1725 u8 rl_id_first /* ID of first or single RL, that will be updated. */;
1726 /* ID of last RL, that will be updated. If clear, single RL will updated. */
1728 u8 rl_dc_qcn_flg /* If set, RL will used for DCQCN. */;
1729 /* If set, alpha will be reset to 1 when the state machine is idle. */
1730 u8 dcqcn_reset_alpha_on_idle;
1731 /* Byte counter threshold to change rate increase stage. */
1733 /* Timer threshold to change rate increase stage. */
1734 u8 rl_timer_stage_th;
1736 __le32 rl_bc_rate /* Byte Counter Limit. */;
1737 __le16 rl_max_rate /* Maximum rate in 1.6 Mbps resolution. */;
1738 __le16 rl_r_ai /* Active increase rate. */;
1739 __le16 rl_r_hai /* Hyper active increase rate. */;
1740 __le16 dcqcn_g /* DCQCN Alpha update gain in 1/64K resolution . */;
1741 __le32 dcqcn_k_us /* DCQCN Alpha update interval. */;
1742 __le32 dcqcn_timeuot_us /* DCQCN timeout. */;
1743 __le32 qcn_timeuot_us /* QCN timeout. */;
1749 * Slowpath Element (SPQE)
1751 struct slow_path_element {
1752 struct ramrod_header hdr /* Ramrod Header */;
1753 struct regpair data_ptr /* Pointer to the Ramrod Data on the Host */;
1758 * Tstorm non-triggering VF zone
1760 struct tstorm_non_trigger_vf_zone {
1761 struct rdma_rcv_stats rdma_stats /* RoCE received statistics */;
1765 struct tstorm_per_port_stat {
1766 /* packet is dropped because it was truncated in NIG */
1767 struct regpair trunc_error_discard;
1768 /* packet is dropped because of Ethernet FCS error */
1769 struct regpair mac_error_discard;
1770 /* packet is dropped because classification was unsuccessful */
1771 struct regpair mftag_filter_discard;
1772 /* packet was passed to Ethernet and dropped because of no mac filter match */
1773 struct regpair eth_mac_filter_discard;
1774 /* packet passed to Light L2 and dropped because Light L2 is not configured for
1777 struct regpair ll2_mac_filter_discard;
1778 /* packet passed to Light L2 and dropped because Light L2 is not configured for
1781 struct regpair ll2_conn_disabled_discard;
1782 /* packet is an ISCSI irregular packet */
1783 struct regpair iscsi_irregular_pkt;
1784 /* packet is an FCOE irregular packet */
1785 struct regpair fcoe_irregular_pkt;
1786 /* packet is an ROCE irregular packet */
1787 struct regpair roce_irregular_pkt;
1788 /* packet is an IWARP irregular packet */
1789 struct regpair iwarp_irregular_pkt;
1790 /* packet is an ETH irregular packet */
1791 struct regpair eth_irregular_pkt;
1792 /* packet is an TOE irregular packet */
1793 struct regpair toe_irregular_pkt;
1794 /* packet is an PREROCE irregular packet */
1795 struct regpair preroce_irregular_pkt;
1796 struct regpair eth_gre_tunn_filter_discard /* GRE dropped packets */;
1797 /* VXLAN dropped packets */
1798 struct regpair eth_vxlan_tunn_filter_discard;
1799 /* GENEVE dropped packets */
1800 struct regpair eth_geneve_tunn_filter_discard;
1801 struct regpair eth_gft_drop_pkt /* GFT dropped packets */;
1808 struct tstorm_vf_zone {
1809 /* non-interrupt-triggering zone */
1810 struct tstorm_non_trigger_vf_zone non_trigger;
1815 * Tunnel classification scheme
1818 /* Use MAC and VLAN from first L2 header for vport classification. */
1819 TUNNEL_CLSS_MAC_VLAN = 0,
1820 /* Use MAC from first L2 header and VNI from tunnel header for vport
1823 TUNNEL_CLSS_MAC_VNI,
1824 /* Use MAC and VLAN from last L2 header for vport classification */
1825 TUNNEL_CLSS_INNER_MAC_VLAN,
1826 /* Use MAC from last L2 header and VNI from tunnel header for vport
1829 TUNNEL_CLSS_INNER_MAC_VNI,
1830 /* Use MAC and VLAN from last L2 header for vport classification. If no exact
1831 * match, use MAC and VLAN from first L2 header for classification.
1833 TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE,
1840 * Ustorm non-triggering VF zone
1842 struct ustorm_non_trigger_vf_zone {
1843 /* VF statistic bucket */
1844 struct eth_ustorm_per_queue_stat eth_queue_stat;
1845 struct regpair vf_pf_msg_addr /* VF-PF message address */;
1850 * Ustorm triggering VF zone
1852 struct ustorm_trigger_vf_zone {
1853 u8 vf_pf_msg_valid /* VF-PF message valid flag */;
1861 struct ustorm_vf_zone {
1862 /* non-interrupt-triggering zone */
1863 struct ustorm_non_trigger_vf_zone non_trigger;
1864 struct ustorm_trigger_vf_zone trigger /* interrupt triggering zone */;
1869 * VF-PF channel data
1871 struct vf_pf_channel_data {
1872 /* 0: VF-PF Channel NOT ready. Waiting for ack from PF driver. 1: VF-PF Channel
1873 * is ready for a new transaction.
1876 /* 0: VF-PF Channel is invalid because of malicious VF. 1: VF-PF Channel is
1886 * Ramrod data for VF start ramrod
1888 struct vf_start_ramrod_data {
1889 u8 vf_id /* VF ID */;
1890 /* If set, initial cleanup ack will be sent to parent PF SP event queue */
1892 __le16 opaque_fid /* VF opaque FID */;
1893 u8 personality /* define what type of personality is new VF */;
1895 /* FP HSI version to be used by FW */
1896 struct hsi_fp_ver_struct hsi_fp_ver;
1901 * Ramrod data for VF start ramrod
1903 struct vf_stop_ramrod_data {
1904 u8 vf_id /* VF ID */;
1912 * VF zone size mode.
1914 enum vf_zone_size_mode {
1915 /* Default VF zone size. Up to 192 VF supported. */
1916 VF_ZONE_SIZE_MODE_DEFAULT,
1917 /* Doubled VF zone size. Up to 96 VF supported. */
1918 VF_ZONE_SIZE_MODE_DOUBLE,
1919 /* Quad VF zone size. Up to 48 VF supported. */
1920 VF_ZONE_SIZE_MODE_QUAD,
1921 MAX_VF_ZONE_SIZE_MODE
1929 * Attentions status block
1931 struct atten_status_block {
1935 __le16 sb_index /* status block running index */;
1945 /* DMA Source. 0 - PCIe, 1 - GRC (use enum dmae_cmd_src_enum) */
1946 #define DMAE_CMD_SRC_MASK 0x1
1947 #define DMAE_CMD_SRC_SHIFT 0
1948 /* DMA destination. 0 - None, 1 - PCIe, 2 - GRC, 3 - None
1949 * (use enum dmae_cmd_dst_enum)
1951 #define DMAE_CMD_DST_MASK 0x3
1952 #define DMAE_CMD_DST_SHIFT 1
1953 /* Completion destination. 0 - PCie, 1 - GRC (use enum dmae_cmd_c_dst_enum) */
1954 #define DMAE_CMD_C_DST_MASK 0x1
1955 #define DMAE_CMD_C_DST_SHIFT 3
1956 /* Reset the CRC result (do not use the previous result as the seed) */
1957 #define DMAE_CMD_CRC_RESET_MASK 0x1
1958 #define DMAE_CMD_CRC_RESET_SHIFT 4
1959 /* Reset the source address in the next go to the same source address of the
1962 #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1
1963 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5
1964 /* Reset the destination address in the next go to the same destination address
1965 * of the previous go
1967 #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1
1968 #define DMAE_CMD_DST_ADDR_RESET_SHIFT 6
1969 /* 0 completion function is the same as src function, 1 - 0 completion
1970 * function is the same as dst function (use enum dmae_cmd_comp_func_enum)
1972 #define DMAE_CMD_COMP_FUNC_MASK 0x1
1973 #define DMAE_CMD_COMP_FUNC_SHIFT 7
1974 /* 0 - Do not write a completion word, 1 - Write a completion word
1975 * (use enum dmae_cmd_comp_word_en_enum)
1977 #define DMAE_CMD_COMP_WORD_EN_MASK 0x1
1978 #define DMAE_CMD_COMP_WORD_EN_SHIFT 8
1979 /* 0 - Do not write a CRC word, 1 - Write a CRC word
1980 * (use enum dmae_cmd_comp_crc_en_enum)
1982 #define DMAE_CMD_COMP_CRC_EN_MASK 0x1
1983 #define DMAE_CMD_COMP_CRC_EN_SHIFT 9
1984 /* The CRC word should be taken from the DMAE address space from address 9+X,
1985 * where X is the value in these bits.
1987 #define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7
1988 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
1989 #define DMAE_CMD_RESERVED1_MASK 0x1
1990 #define DMAE_CMD_RESERVED1_SHIFT 13
1991 #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3
1992 #define DMAE_CMD_ENDIANITY_MODE_SHIFT 14
1993 /* The field specifies how the completion word is affected by PCIe read error. 0
1994 * Send a regular completion, 1 - Send a completion with an error indication,
1995 * 2 do not send a completion (use enum dmae_cmd_error_handling_enum)
1997 #define DMAE_CMD_ERR_HANDLING_MASK 0x3
1998 #define DMAE_CMD_ERR_HANDLING_SHIFT 16
1999 /* The port ID to be placed on the RF FID field of the GRC bus. this field is
2000 * used both when GRC is the destination and when it is the source of the DMAE
2003 #define DMAE_CMD_PORT_ID_MASK 0x3
2004 #define DMAE_CMD_PORT_ID_SHIFT 18
2005 /* Source PCI function number [3:0] */
2006 #define DMAE_CMD_SRC_PF_ID_MASK 0xF
2007 #define DMAE_CMD_SRC_PF_ID_SHIFT 20
2008 /* Destination PCI function number [3:0] */
2009 #define DMAE_CMD_DST_PF_ID_MASK 0xF
2010 #define DMAE_CMD_DST_PF_ID_SHIFT 24
2011 #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1 /* Source VFID valid */
2012 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
2013 #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1 /* Destination VFID valid */
2014 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
2015 #define DMAE_CMD_RESERVED2_MASK 0x3
2016 #define DMAE_CMD_RESERVED2_SHIFT 30
2017 /* PCIe source address low in bytes or GRC source address in DW */
2019 /* PCIe source address high in bytes or reserved (if source is GRC) */
2021 /* PCIe destination address low in bytes or GRC destination address in DW */
2023 /* PCIe destination address high in bytes or reserved (if destination is GRC) */
2025 __le16 length_dw /* Length in DW */;
2027 #define DMAE_CMD_SRC_VF_ID_MASK 0xFF /* Source VF id */
2028 #define DMAE_CMD_SRC_VF_ID_SHIFT 0
2029 #define DMAE_CMD_DST_VF_ID_MASK 0xFF /* Destination VF id */
2030 #define DMAE_CMD_DST_VF_ID_SHIFT 8
2031 /* PCIe completion address low in bytes or GRC completion address in DW */
2032 __le32 comp_addr_lo;
2033 /* PCIe completion address high in bytes or reserved (if completion address is
2036 __le32 comp_addr_hi;
2037 __le32 comp_val /* Value to write to completion address */;
2038 __le32 crc32 /* crc16 result */;
2039 __le32 crc_32_c /* crc32_c result */;
2040 __le16 crc16 /* crc16 result */;
2041 __le16 crc16_c /* crc16_c result */;
2042 __le16 crc10 /* crc_t10 result */;
2044 __le16 xsum16 /* checksum16 result */;
2045 __le16 xsum8 /* checksum8 result */;
2049 enum dmae_cmd_comp_crc_en_enum {
2050 dmae_cmd_comp_crc_disabled /* Do not write a CRC word */,
2051 dmae_cmd_comp_crc_enabled /* Write a CRC word */,
2052 MAX_DMAE_CMD_COMP_CRC_EN_ENUM
2056 enum dmae_cmd_comp_func_enum {
2057 /* completion word and/or CRC will be sent to SRC-PCI function/SRC VFID */
2058 dmae_cmd_comp_func_to_src,
2059 /* completion word and/or CRC will be sent to DST-PCI function/DST VFID */
2060 dmae_cmd_comp_func_to_dst,
2061 MAX_DMAE_CMD_COMP_FUNC_ENUM
2065 enum dmae_cmd_comp_word_en_enum {
2066 dmae_cmd_comp_word_disabled /* Do not write a completion word */,
2067 dmae_cmd_comp_word_enabled /* Write the completion word */,
2068 MAX_DMAE_CMD_COMP_WORD_EN_ENUM
2072 enum dmae_cmd_c_dst_enum {
2073 dmae_cmd_c_dst_pcie,
2075 MAX_DMAE_CMD_C_DST_ENUM
2079 enum dmae_cmd_dst_enum {
2080 dmae_cmd_dst_none_0,
2083 dmae_cmd_dst_none_3,
2084 MAX_DMAE_CMD_DST_ENUM
2088 enum dmae_cmd_error_handling_enum {
2089 /* Send a regular completion (with no error indication) */
2090 dmae_cmd_error_handling_send_regular_comp,
2091 /* Send a completion with an error indication (i.e. set bit 31 of the completion
2094 dmae_cmd_error_handling_send_comp_with_err,
2095 dmae_cmd_error_handling_dont_send_comp /* Do not send a completion */,
2096 MAX_DMAE_CMD_ERROR_HANDLING_ENUM
2100 enum dmae_cmd_src_enum {
2101 dmae_cmd_src_pcie /* The source is the PCIe */,
2102 dmae_cmd_src_grc /* The source is the GRC */,
2103 MAX_DMAE_CMD_SRC_ENUM
2107 struct e4_mstorm_core_conn_ag_ctx {
2108 u8 byte0 /* cdu_validation */;
2109 u8 byte1 /* state */;
2111 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2112 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
2113 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2114 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
2115 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
2116 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
2117 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
2118 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
2119 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
2120 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
2122 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2123 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
2124 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2125 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
2126 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2127 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
2128 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2129 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
2130 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2131 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
2132 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2133 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
2134 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2135 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
2136 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2137 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
2138 __le16 word0 /* word0 */;
2139 __le16 word1 /* word1 */;
2140 __le32 reg0 /* reg0 */;
2141 __le32 reg1 /* reg1 */;
2148 struct e4_ystorm_core_conn_ag_ctx {
2149 u8 byte0 /* cdu_validation */;
2150 u8 byte1 /* state */;
2152 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2153 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
2154 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2155 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
2156 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
2157 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
2158 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
2159 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
2160 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
2161 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
2163 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2164 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
2165 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2166 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
2167 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2168 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
2169 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2170 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
2171 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2172 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
2173 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2174 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
2175 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2176 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
2177 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2178 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
2179 u8 byte2 /* byte2 */;
2180 u8 byte3 /* byte3 */;
2181 __le16 word0 /* word0 */;
2182 __le32 reg0 /* reg0 */;
2183 __le32 reg1 /* reg1 */;
2184 __le16 word1 /* word1 */;
2185 __le16 word2 /* word2 */;
2186 __le16 word3 /* word3 */;
2187 __le16 word4 /* word4 */;
2188 __le32 reg2 /* reg2 */;
2189 __le32 reg3 /* reg3 */;
2193 struct fw_asserts_ram_section {
2194 /* The offset of the section in the RAM in RAM lines (64-bit units) */
2195 __le16 section_ram_line_offset;
2196 /* The size of the section in RAM lines (64-bit units) */
2197 __le16 section_ram_line_size;
2198 /* The offset of the asserts list within the section in dwords */
2199 u8 list_dword_offset;
2200 /* The size of an assert list element in dwords */
2201 u8 list_element_dword_size;
2202 u8 list_num_elements /* The number of elements in the asserts list */;
2203 /* The offset of the next list index field within the section in dwords */
2204 u8 list_next_index_dword_offset;
2209 u8 major /* Firmware major version number */;
2210 u8 minor /* Firmware minor version number */;
2211 u8 rev /* Firmware revision version number */;
2212 u8 eng /* Firmware engineering version number (for bootleg versions) */;
2215 struct fw_ver_info {
2216 __le16 tools_ver /* Tools version number */;
2217 u8 image_id /* FW image ID (e.g. main, l2b, kuku) */;
2219 struct fw_ver_num num /* FW version number */;
2220 __le32 timestamp /* FW Timestamp in unix time (sec. since 1970) */;
2225 struct fw_ver_info ver /* FW version information */;
2226 /* Info regarding the FW asserts section in the Storm RAM */
2227 struct fw_asserts_ram_section fw_asserts_section;
2231 struct fw_info_location {
2232 __le32 grc_addr /* GRC address where the fw_info struct is located. */;
2233 /* Size of the fw_info structure (thats located at the grc_addr). */
2241 * IGU cleanup command
2243 struct igu_cleanup {
2244 __le32 sb_id_and_flags;
2245 #define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF
2246 #define IGU_CLEANUP_RESERVED0_SHIFT 0
2247 /* cleanup clear - 0, set - 1 */
2248 #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1
2249 #define IGU_CLEANUP_CLEANUP_SET_SHIFT 27
2250 #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7
2251 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28
2252 /* must always be set (use enum command_type_bit) */
2253 #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1U
2254 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31
2260 * IGU firmware driver command
2263 struct igu_prod_cons_update prod_cons_update;
2264 struct igu_cleanup cleanup;
2269 * IGU firmware driver command
2271 struct igu_command_reg_ctrl {
2273 __le16 igu_command_reg_ctrl_fields;
2274 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF
2275 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
2276 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7
2277 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12
2278 /* command typ: 0 - read, 1 - write */
2279 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1
2280 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
2285 * IGU mapping line structure
2287 struct igu_mapping_line {
2288 __le32 igu_mapping_line_fields;
2289 #define IGU_MAPPING_LINE_VALID_MASK 0x1
2290 #define IGU_MAPPING_LINE_VALID_SHIFT 0
2291 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF
2292 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1
2293 /* In BB: VF-0-120, PF-0-7; In K2: VF-0-191, PF-0-15 */
2294 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF
2295 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9
2296 #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1 /* PF-1, VF-0 */
2297 #define IGU_MAPPING_LINE_PF_VALID_SHIFT 17
2298 #define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F
2299 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18
2300 #define IGU_MAPPING_LINE_RESERVED_MASK 0xFF
2301 #define IGU_MAPPING_LINE_RESERVED_SHIFT 24
2306 * IGU MSIX line structure
2308 struct igu_msix_vector {
2309 struct regpair address;
2311 __le32 msix_vector_fields;
2312 #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1
2313 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0
2314 #define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF
2315 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1
2316 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF
2317 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16
2318 #define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF
2319 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24
2324 * per encapsulation type enabling flags
2326 struct prs_reg_encapsulation_type_en {
2328 /* Enable bit for Ethernet-over-GRE (L2 GRE) encapsulation. */
2329 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1
2330 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0
2331 /* Enable bit for IP-over-GRE (IP GRE) encapsulation. */
2332 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1
2333 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1
2334 /* Enable bit for VXLAN encapsulation. */
2335 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1
2336 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2
2337 /* Enable bit for T-Tag encapsulation. */
2338 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1
2339 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3
2340 /* Enable bit for Ethernet-over-GENEVE (L2 GENEVE) encapsulation. */
2341 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1
2342 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4
2343 /* Enable bit for IP-over-GENEVE (IP GENEVE) encapsulation. */
2344 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1
2345 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5
2346 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3
2347 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6
2351 enum pxp_tph_st_hint {
2352 TPH_ST_HINT_BIDIR /* Read/Write access by Host and Device */,
2353 TPH_ST_HINT_REQUESTER /* Read/Write access by Device */,
2354 /* Device Write and Host Read, or Host Write and Device Read */
2356 /* Device Write and Host Read, or Host Write and Device Read - with temporal
2359 TPH_ST_HINT_TARGET_PRIO,
2365 * QM hardware structure of enable bypass credit mask
2367 struct qm_rf_bypass_mask {
2369 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1
2370 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0
2371 #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1
2372 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1
2373 #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1
2374 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2
2375 #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1
2376 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3
2377 #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1
2378 #define QM_RF_BYPASS_MASK_PFRL_SHIFT 4
2379 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1
2380 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5
2381 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1
2382 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6
2383 #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1
2384 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7
2389 * QM hardware structure of opportunistic credit mask
2391 struct qm_rf_opportunistic_mask {
2393 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1
2394 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0
2395 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1
2396 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1
2397 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1
2398 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2
2399 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1
2400 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3
2401 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1
2402 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4
2403 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1
2404 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5
2405 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1
2406 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6
2407 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1
2408 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7
2409 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1
2410 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8
2411 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F
2412 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9
2417 * QM hardware structure of QM map memory
2419 struct qm_rf_pq_map_e4 {
2421 #define QM_RF_PQ_MAP_E4_PQ_VALID_MASK 0x1 /* PQ active */
2422 #define QM_RF_PQ_MAP_E4_PQ_VALID_SHIFT 0
2423 #define QM_RF_PQ_MAP_E4_RL_ID_MASK 0xFF /* RL ID */
2424 #define QM_RF_PQ_MAP_E4_RL_ID_SHIFT 1
2425 /* the first PQ associated with the VPORT and VOQ of this PQ */
2426 #define QM_RF_PQ_MAP_E4_VP_PQ_ID_MASK 0x1FF
2427 #define QM_RF_PQ_MAP_E4_VP_PQ_ID_SHIFT 9
2428 #define QM_RF_PQ_MAP_E4_VOQ_MASK 0x1F /* VOQ */
2429 #define QM_RF_PQ_MAP_E4_VOQ_SHIFT 18
2430 #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_MASK 0x3 /* WRR weight */
2431 #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_SHIFT 23
2432 #define QM_RF_PQ_MAP_E4_RL_VALID_MASK 0x1 /* RL active */
2433 #define QM_RF_PQ_MAP_E4_RL_VALID_SHIFT 25
2434 #define QM_RF_PQ_MAP_E4_RESERVED_MASK 0x3F
2435 #define QM_RF_PQ_MAP_E4_RESERVED_SHIFT 26
2440 * Completion params for aggregated interrupt completion
2442 struct sdm_agg_int_comp_params {
2444 /* the number of aggregated interrupt, 0-31 */
2445 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F
2446 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0
2447 /* 1 - set a bit in aggregated vector, 0 - dont set */
2448 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1
2449 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
2450 /* Number of bit in the aggregated vector, 0-279 (TBD) */
2451 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF
2452 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7
2457 * SDM operation gen command (generate aggregative interrupt)
2461 /* completion parameters 0-15 */
2462 #define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF
2463 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
2464 #define SDM_OP_GEN_COMP_TYPE_MASK 0xF /* completion type 16-19 */
2465 #define SDM_OP_GEN_COMP_TYPE_SHIFT 16
2466 #define SDM_OP_GEN_RESERVED_MASK 0xFFF /* reserved 20-31 */
2467 #define SDM_OP_GEN_RESERVED_SHIFT 20
2470 struct ystorm_core_conn_ag_ctx {
2471 u8 byte0 /* cdu_validation */;
2472 u8 byte1 /* state */;
2474 #define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2475 #define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
2476 #define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2477 #define YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
2478 #define YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
2479 #define YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
2480 #define YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
2481 #define YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
2482 #define YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
2483 #define YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
2485 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2486 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
2487 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2488 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
2489 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2490 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
2491 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2492 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
2493 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2494 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
2495 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2496 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
2497 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2498 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
2499 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2500 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
2501 u8 byte2 /* byte2 */;
2502 u8 byte3 /* byte3 */;
2503 __le16 word0 /* word0 */;
2504 __le32 reg0 /* reg0 */;
2505 __le32 reg1 /* reg1 */;
2506 __le16 word1 /* word1 */;
2507 __le16 word2 /* word2 */;
2508 __le16 word3 /* word3 */;
2509 __le16 word4 /* word4 */;
2510 __le32 reg2 /* reg2 */;
2511 __le32 reg3 /* reg3 */;
2514 #endif /* __ECORE_HSI_COMMON__ */