2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #ifndef __ECORE_HSI_COMMON__
10 #define __ECORE_HSI_COMMON__
11 /********************************/
12 /* Add include to common target */
13 /********************************/
14 #include "common_hsi.h"
18 * opcodes for the event ring
20 enum common_event_opcode {
21 COMMON_EVENT_PF_START,
23 COMMON_EVENT_VF_START,
25 COMMON_EVENT_VF_PF_CHANNEL,
27 COMMON_EVENT_PF_UPDATE,
28 COMMON_EVENT_MALICIOUS_VF,
29 COMMON_EVENT_RL_UPDATE,
31 MAX_COMMON_EVENT_OPCODE
36 * Common Ramrod Command IDs
38 enum common_ramrod_cmd_id {
40 COMMON_RAMROD_PF_START /* PF Function Start Ramrod */,
41 COMMON_RAMROD_PF_STOP /* PF Function Stop Ramrod */,
42 COMMON_RAMROD_VF_START /* VF Function Start */,
43 COMMON_RAMROD_VF_STOP /* VF Function Stop Ramrod */,
44 COMMON_RAMROD_PF_UPDATE /* PF update Ramrod */,
45 COMMON_RAMROD_RL_UPDATE /* QCN/DCQCN RL update Ramrod */,
46 COMMON_RAMROD_EMPTY /* Empty Ramrod */,
47 MAX_COMMON_RAMROD_CMD_ID
52 * The core storm context for the Ystorm
54 struct ystorm_core_conn_st_ctx {
59 * The core storm context for the Pstorm
61 struct pstorm_core_conn_st_ctx {
66 * Core Slowpath Connection storm context of Xstorm
68 struct xstorm_core_conn_st_ctx {
69 __le32 spq_base_lo /* SPQ Ring Base Address low dword */;
70 __le32 spq_base_hi /* SPQ Ring Base Address high dword */;
71 /* Consolidation Ring Base Address */
72 struct regpair consolid_base_addr;
73 __le16 spq_cons /* SPQ Ring Consumer */;
74 __le16 consolid_cons /* Consolidation Ring Consumer */;
75 __le32 reserved0[55] /* Pad to 15 cycles */;
78 struct e4_xstorm_core_conn_ag_ctx {
79 u8 reserved0 /* cdu_validation */;
80 u8 core_state /* state */;
83 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
84 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
86 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
87 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1
89 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
90 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2
92 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
93 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
95 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
96 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4
98 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
99 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5
101 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1
102 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6
104 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1
105 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7
108 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1
109 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
111 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1
112 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1
114 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1
115 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2
117 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1
118 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3
120 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1
121 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4
123 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1
124 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5
126 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
127 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
129 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
130 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
133 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
134 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
136 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
137 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2
139 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
140 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4
142 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
143 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6
145 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
146 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
147 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
148 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2
149 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
150 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4
151 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
152 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6
154 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
155 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
156 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
157 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2
159 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
160 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4
162 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3
163 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6
166 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3
167 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
169 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3
170 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2
172 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3
173 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4
175 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3
176 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6
179 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3
180 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
182 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
183 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2
185 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3
186 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4
188 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
189 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
192 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
193 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
195 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3
196 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2
198 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
199 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
201 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
202 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6
204 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
205 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7
208 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
209 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
211 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
212 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1
214 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
215 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2
217 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
218 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3
220 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
221 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4
223 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
224 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5
226 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
227 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6
229 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
230 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7
233 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
234 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
236 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1
237 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1
239 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1
240 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2
242 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1
243 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3
245 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1
246 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4
248 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1
249 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5
251 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1
252 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
254 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
255 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7
258 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
259 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
261 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
262 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
264 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
265 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
267 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1
268 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3
270 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
271 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
273 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1
274 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5
276 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1
277 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6
279 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1
280 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7
283 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1
284 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
286 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1
287 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1
289 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
290 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
292 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
293 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3
295 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
296 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4
298 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
299 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5
301 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
302 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
304 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1
305 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7
308 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1
309 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
311 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1
312 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1
314 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
315 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
317 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
318 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
320 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1
321 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4
323 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1
324 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5
326 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1
327 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6
329 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1
330 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7
333 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1
334 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
336 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1
337 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1
339 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
340 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
342 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
343 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
345 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
346 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
348 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
349 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
351 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
352 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
354 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
355 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
358 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1
359 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
361 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1
362 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1
364 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1
365 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2
367 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1
368 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3
370 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1
371 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4
373 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1
374 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5
376 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3
377 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6
378 u8 byte2 /* byte2 */;
379 __le16 physical_q0 /* physical_q0 */;
380 __le16 consolid_prod /* physical_q1 */;
381 __le16 reserved16 /* physical_q2 */;
382 __le16 tx_bd_cons /* word3 */;
383 __le16 tx_bd_or_spq_prod /* word4 */;
384 __le16 updated_qm_pq_id /* word5 */;
385 __le16 conn_dpi /* conn_dpi */;
386 u8 byte3 /* byte3 */;
387 u8 byte4 /* byte4 */;
388 u8 byte5 /* byte5 */;
389 u8 byte6 /* byte6 */;
390 __le32 reg0 /* reg0 */;
391 __le32 reg1 /* reg1 */;
392 __le32 reg2 /* reg2 */;
393 __le32 reg3 /* reg3 */;
394 __le32 reg4 /* reg4 */;
395 __le32 reg5 /* cf_array0 */;
396 __le32 reg6 /* cf_array1 */;
397 __le16 word7 /* word7 */;
398 __le16 word8 /* word8 */;
399 __le16 word9 /* word9 */;
400 __le16 word10 /* word10 */;
401 __le32 reg7 /* reg7 */;
402 __le32 reg8 /* reg8 */;
403 __le32 reg9 /* reg9 */;
404 u8 byte7 /* byte7 */;
405 u8 byte8 /* byte8 */;
406 u8 byte9 /* byte9 */;
407 u8 byte10 /* byte10 */;
408 u8 byte11 /* byte11 */;
409 u8 byte12 /* byte12 */;
410 u8 byte13 /* byte13 */;
411 u8 byte14 /* byte14 */;
412 u8 byte15 /* byte15 */;
413 u8 e5_reserved /* e5_reserved */;
414 __le16 word11 /* word11 */;
415 __le32 reg10 /* reg10 */;
416 __le32 reg11 /* reg11 */;
417 __le32 reg12 /* reg12 */;
418 __le32 reg13 /* reg13 */;
419 __le32 reg14 /* reg14 */;
420 __le32 reg15 /* reg15 */;
421 __le32 reg16 /* reg16 */;
422 __le32 reg17 /* reg17 */;
423 __le32 reg18 /* reg18 */;
424 __le32 reg19 /* reg19 */;
425 __le16 word12 /* word12 */;
426 __le16 word13 /* word13 */;
427 __le16 word14 /* word14 */;
428 __le16 word15 /* word15 */;
431 struct e4_tstorm_core_conn_ag_ctx {
432 u8 byte0 /* cdu_validation */;
433 u8 byte1 /* state */;
435 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
436 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
437 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
438 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
439 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
440 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2
441 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
442 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3
443 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
444 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4
445 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
446 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5
447 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
448 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6
450 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
451 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
452 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
453 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2
454 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
455 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4
456 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
457 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6
459 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
460 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
461 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
462 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2
463 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
464 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4
465 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
466 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6
468 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
469 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
470 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
471 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2
472 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
473 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4
474 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
475 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5
476 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
477 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6
478 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
479 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7
481 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
482 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
483 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
484 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1
485 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
486 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2
487 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
488 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3
489 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
490 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4
491 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
492 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5
493 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
494 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6
495 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
496 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
498 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
499 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
500 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
501 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
502 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
503 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
504 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
505 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
506 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
507 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
508 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
509 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
510 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
511 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
512 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
513 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
514 __le32 reg0 /* reg0 */;
515 __le32 reg1 /* reg1 */;
516 __le32 reg2 /* reg2 */;
517 __le32 reg3 /* reg3 */;
518 __le32 reg4 /* reg4 */;
519 __le32 reg5 /* reg5 */;
520 __le32 reg6 /* reg6 */;
521 __le32 reg7 /* reg7 */;
522 __le32 reg8 /* reg8 */;
523 u8 byte2 /* byte2 */;
524 u8 byte3 /* byte3 */;
525 __le16 word0 /* word0 */;
526 u8 byte4 /* byte4 */;
527 u8 byte5 /* byte5 */;
528 __le16 word1 /* word1 */;
529 __le16 word2 /* conn_dpi */;
530 __le16 word3 /* word3 */;
531 __le32 reg9 /* reg9 */;
532 __le32 reg10 /* reg10 */;
535 struct e4_ustorm_core_conn_ag_ctx {
536 u8 reserved /* cdu_validation */;
537 u8 byte1 /* state */;
539 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
540 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
541 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
542 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
543 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
544 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
545 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
546 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
547 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
548 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
550 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
551 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
552 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
553 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2
554 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
555 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4
556 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
557 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6
559 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
560 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
561 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
562 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
563 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
564 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
565 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
566 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3
567 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
568 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4
569 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
570 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5
571 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
572 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6
573 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
574 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
576 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
577 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
578 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
579 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
580 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
581 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
582 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
583 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
584 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
585 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
586 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
587 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
588 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
589 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
590 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
591 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
592 u8 byte2 /* byte2 */;
593 u8 byte3 /* byte3 */;
594 __le16 word0 /* conn_dpi */;
595 __le16 word1 /* word1 */;
596 __le32 rx_producers /* reg0 */;
597 __le32 reg1 /* reg1 */;
598 __le32 reg2 /* reg2 */;
599 __le32 reg3 /* reg3 */;
600 __le16 word2 /* word2 */;
601 __le16 word3 /* word3 */;
605 * The core storm context for the Mstorm
607 struct mstorm_core_conn_st_ctx {
612 * The core storm context for the Ustorm
614 struct ustorm_core_conn_st_ctx {
619 * core connection context
621 struct e4_core_conn_context {
622 /* ystorm storm context */
623 struct ystorm_core_conn_st_ctx ystorm_st_context;
624 struct regpair ystorm_st_padding[2] /* padding */;
625 /* pstorm storm context */
626 struct pstorm_core_conn_st_ctx pstorm_st_context;
627 struct regpair pstorm_st_padding[2] /* padding */;
628 /* xstorm storm context */
629 struct xstorm_core_conn_st_ctx xstorm_st_context;
630 /* xstorm aggregative context */
631 struct e4_xstorm_core_conn_ag_ctx xstorm_ag_context;
632 /* tstorm aggregative context */
633 struct e4_tstorm_core_conn_ag_ctx tstorm_ag_context;
634 /* ustorm aggregative context */
635 struct e4_ustorm_core_conn_ag_ctx ustorm_ag_context;
636 /* mstorm storm context */
637 struct mstorm_core_conn_st_ctx mstorm_st_context;
638 /* ustorm storm context */
639 struct ustorm_core_conn_st_ctx ustorm_st_context;
640 struct regpair ustorm_st_padding[2] /* padding */;
645 * How ll2 should deal with packet upon errors
647 enum core_error_handle {
648 LL2_DROP_PACKET /* If error occurs drop packet */,
649 LL2_DO_NOTHING /* If error occurs do nothing */,
650 LL2_ASSERT /* If error occurs assert */,
651 MAX_CORE_ERROR_HANDLE
656 * opcodes for the event ring
658 enum core_event_opcode {
659 CORE_EVENT_TX_QUEUE_START,
660 CORE_EVENT_TX_QUEUE_STOP,
661 CORE_EVENT_RX_QUEUE_START,
662 CORE_EVENT_RX_QUEUE_STOP,
663 CORE_EVENT_RX_QUEUE_FLUSH,
664 CORE_EVENT_TX_QUEUE_UPDATE,
665 MAX_CORE_EVENT_OPCODE
670 * The L4 pseudo checksum mode for Core
672 enum core_l4_pseudo_checksum_mode {
673 /* Pseudo Checksum on packet is calculated with the correct packet length. */
674 CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
675 /* Pseudo Checksum on packet is calculated with zero length. */
676 CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
677 MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
682 * Light-L2 RX Producers in Tstorm RAM
684 struct core_ll2_port_stats {
685 struct regpair gsi_invalid_hdr;
686 struct regpair gsi_invalid_pkt_length;
687 struct regpair gsi_unsupported_pkt_typ;
688 struct regpair gsi_crcchksm_error;
693 * Ethernet TX Per Queue Stats
695 struct core_ll2_pstorm_per_queue_stat {
696 /* number of total bytes sent without errors */
697 struct regpair sent_ucast_bytes;
698 /* number of total bytes sent without errors */
699 struct regpair sent_mcast_bytes;
700 /* number of total bytes sent without errors */
701 struct regpair sent_bcast_bytes;
702 /* number of total packets sent without errors */
703 struct regpair sent_ucast_pkts;
704 /* number of total packets sent without errors */
705 struct regpair sent_mcast_pkts;
706 /* number of total packets sent without errors */
707 struct regpair sent_bcast_pkts;
712 * Light-L2 RX Producers in Tstorm RAM
714 struct core_ll2_rx_prod {
715 __le16 bd_prod /* BD Producer */;
716 __le16 cqe_prod /* CQE Producer */;
721 struct core_ll2_tstorm_per_queue_stat {
722 /* Number of packets discarded because they are bigger than MTU */
723 struct regpair packet_too_big_discard;
724 /* Number of packets discarded due to lack of host buffers */
725 struct regpair no_buff_discard;
729 struct core_ll2_ustorm_per_queue_stat {
730 struct regpair rcv_ucast_bytes;
731 struct regpair rcv_mcast_bytes;
732 struct regpair rcv_bcast_bytes;
733 struct regpair rcv_ucast_pkts;
734 struct regpair rcv_mcast_pkts;
735 struct regpair rcv_bcast_pkts;
740 * Core Ramrod Command IDs (light L2)
742 enum core_ramrod_cmd_id {
744 CORE_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */,
745 CORE_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */,
746 CORE_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */,
747 CORE_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */,
748 CORE_RAMROD_RX_QUEUE_FLUSH /* RX Flush queue Ramrod */,
749 CORE_RAMROD_TX_QUEUE_UPDATE /* TX Queue Update Ramrod */,
750 MAX_CORE_RAMROD_CMD_ID
755 * Core RX CQE Type for Light L2
757 enum core_roce_flavor_type {
760 MAX_CORE_ROCE_FLAVOR_TYPE
765 * Specifies how ll2 should deal with packets errors: packet_too_big and no_buff
767 struct core_rx_action_on_error {
769 /* ll2 how to handle error packet_too_big (use enum core_error_handle) */
770 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
771 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
772 /* ll2 how to handle error with no_buff (use enum core_error_handle) */
773 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
774 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2
775 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
776 #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4
781 * Core RX BD for Light L2
790 * Core RX CM offload BD for Light L2
792 struct core_rx_bd_with_buff_len {
799 * Core RX CM offload BD for Light L2
801 union core_rx_bd_union {
802 struct core_rx_bd rx_bd /* Core Rx Bd static buffer size */;
803 /* Core Rx Bd with dynamic buffer length */
804 struct core_rx_bd_with_buff_len rx_bd_with_len;
810 * Opaque Data for Light L2 RX CQE .
812 struct core_rx_cqe_opaque_data {
813 __le32 data[2] /* Opaque CQE Data */;
818 * Core RX CQE Type for Light L2
820 enum core_rx_cqe_type {
821 CORE_RX_CQE_ILLIGAL_TYPE /* Bad RX Cqe type */,
822 CORE_RX_CQE_TYPE_REGULAR /* Regular Core RX CQE */,
823 CORE_RX_CQE_TYPE_GSI_OFFLOAD /* Fp Gsi offload RX CQE */,
824 CORE_RX_CQE_TYPE_SLOW_PATH /* Slow path Core RX CQE */,
830 * Core RX CQE for Light L2 .
832 struct core_rx_fast_path_cqe {
833 u8 type /* CQE type */;
834 /* Offset (in bytes) of the packet from start of the buffer */
836 /* Parsing and error flags from the parser */
837 struct parsing_and_err_flags parse_flags;
838 __le16 packet_length /* Total packet length (from the parser) */;
839 __le16 vlan /* 802.1q VLAN tag */;
840 struct core_rx_cqe_opaque_data opaque_data /* Opaque Data */;
841 /* bit- map: each bit represents a specific error. errors indications are
842 * provided by the cracker. see spec for detailed description
844 struct parsing_err_flags err_flags;
850 * Core Rx CM offload CQE .
852 struct core_rx_gsi_offload_cqe {
853 u8 type /* CQE type */;
854 u8 data_length_error /* set if gsi data is bigger than buff */;
855 /* Parsing and error flags from the parser */
856 struct parsing_and_err_flags parse_flags;
857 __le16 data_length /* Total packet length (from the parser) */;
858 __le16 vlan /* 802.1q VLAN tag */;
859 __le32 src_mac_addrhi /* hi 4 bytes source mac address */;
860 __le16 src_mac_addrlo /* lo 2 bytes of source mac address */;
861 /* These are the lower 16 bit of QP id in RoCE BTH header */
863 __le32 src_qp /* Source QP from DETH header */;
868 * Core RX CQE for Light L2 .
870 struct core_rx_slow_path_cqe {
871 u8 type /* CQE type */;
874 struct core_rx_cqe_opaque_data opaque_data /* Opaque Data */;
879 * Core RX CM offload BD for Light L2
881 union core_rx_cqe_union {
882 struct core_rx_fast_path_cqe rx_cqe_fp /* Fast path CQE */;
883 struct core_rx_gsi_offload_cqe rx_cqe_gsi /* GSI offload CQE */;
884 struct core_rx_slow_path_cqe rx_cqe_sp /* Slow path CQE */;
892 * Ramrod data for rx queue start ramrod
894 struct core_rx_start_ramrod_data {
895 struct regpair bd_base /* bd address of the first bd page */;
896 struct regpair cqe_pbl_addr /* Base address on host of CQE PBL */;
897 __le16 mtu /* Maximum transmission unit */;
898 __le16 sb_id /* Status block ID */;
899 u8 sb_index /* index of the protocol index */;
900 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
901 u8 complete_event_flg /* post completion to the event ring if set */;
902 u8 drop_ttl0_flg /* drop packet with ttl0 if set */;
903 __le16 num_of_pbl_pages /* Num of pages in CQE PBL */;
904 /* if set, 802.1q tags will be removed and copied to CQE */
905 /* if set, 802.1q tags will be removed and copied to CQE */
906 u8 inner_vlan_stripping_en;
907 /* if set and inner vlan does not exist, the outer vlan will copied to CQE as
908 * inner vlan. should be used in MF_OVLAN mode only.
910 u8 report_outer_vlan;
911 u8 queue_id /* Light L2 RX Queue ID */;
912 u8 main_func_queue /* Is this the main queue for the PF */;
913 /* Duplicate broadcast packets to LL2 main queue in mf_si mode. Valid if
914 * main_func_queue is set.
916 u8 mf_si_bcast_accept_all;
917 /* Duplicate multicast packets to LL2 main queue in mf_si mode. Valid if
918 * main_func_queue is set.
920 u8 mf_si_mcast_accept_all;
921 /* Specifies how ll2 should deal with packets errors: packet_too_big and
924 struct core_rx_action_on_error action_on_error;
925 /* set when in GSI offload mode on ROCE connection */
932 * Ramrod data for rx queue stop ramrod
934 struct core_rx_stop_ramrod_data {
935 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
936 u8 complete_event_flg /* post completion to the event ring if set */;
937 u8 queue_id /* Light L2 RX Queue ID */;
944 * Flags for Core TX BD
946 struct core_tx_bd_data {
948 /* Do not allow additional VLAN manipulations on this packet (DCB) */
949 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
950 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0
951 /* Insert VLAN into packet */
952 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
953 #define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1
954 /* This is the first BD of the packet (for debug) */
955 #define CORE_TX_BD_DATA_START_BD_MASK 0x1
956 #define CORE_TX_BD_DATA_START_BD_SHIFT 2
957 /* Calculate the IP checksum for the packet */
958 #define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
959 #define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3
960 /* Calculate the L4 checksum for the packet */
961 #define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
962 #define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4
963 /* Packet is IPv6 with extensions */
964 #define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
965 #define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5
966 /* If IPv6+ext, and if l4_csum is 1, than this field indicates L4 protocol:
969 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
970 #define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6
971 /* The pseudo checksum mode to place in the L4 checksum field. Required only
972 * when IPv6+ext and l4_csum is set. (use enum core_l4_pseudo_checksum_mode)
974 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1
975 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7
976 /* Number of BDs that make up one packet - width wide enough to present
977 * CORE_LL2_TX_MAX_BDS_PER_PACKET
979 #define CORE_TX_BD_DATA_NBDS_MASK 0xF
980 #define CORE_TX_BD_DATA_NBDS_SHIFT 8
981 /* Use roce_flavor enum - Differentiate between Roce flavors is valid when
982 * connType is ROCE (use enum core_roce_flavor_type)
984 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
985 #define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12
986 /* Calculate ip length */
987 #define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
988 #define CORE_TX_BD_DATA_IP_LEN_SHIFT 13
989 /* disables the STAG insertion, relevant only in MF OVLAN mode. */
990 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK 0x1
991 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_SHIFT 14
992 #define CORE_TX_BD_DATA_RESERVED0_MASK 0x1
993 #define CORE_TX_BD_DATA_RESERVED0_SHIFT 15
997 * Core TX BD for Light L2
1000 struct regpair addr /* Buffer Address */;
1001 __le16 nbytes /* Number of Bytes in Buffer */;
1002 /* Network packets: VLAN to insert to packet (if insertion flag set) LoopBack
1003 * packets: echo data to pass to Rx
1005 __le16 nw_vlan_or_lb_echo;
1006 struct core_tx_bd_data bd_data /* BD Flags */;
1008 /* L4 Header Offset from start of packet (in Words). This is needed if both
1009 * l4_csum and ipv6_ext are set
1011 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF
1012 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0
1013 /* Packet destination - Network, Loopback or Drop (use enum core_tx_dest) */
1014 #define CORE_TX_BD_TX_DST_MASK 0x3
1015 #define CORE_TX_BD_TX_DST_SHIFT 14
1021 * Light L2 TX Destination
1024 CORE_TX_DEST_NW /* TX Destination to the Network */,
1025 CORE_TX_DEST_LB /* TX Destination to the Loopback */,
1026 CORE_TX_DEST_RESERVED,
1027 CORE_TX_DEST_DROP /* TX Drop */,
1033 * Ramrod data for tx queue start ramrod
1035 struct core_tx_start_ramrod_data {
1036 struct regpair pbl_base_addr /* Address of the pbl page */;
1037 __le16 mtu /* Maximum transmission unit */;
1038 __le16 sb_id /* Status block ID */;
1039 u8 sb_index /* Status block protocol index */;
1040 u8 stats_en /* Statistics Enable */;
1041 u8 stats_id /* Statistics Counter ID */;
1042 u8 conn_type /* connection type that loaded ll2 */;
1043 __le16 pbl_size /* Number of BD pages pointed by PBL */;
1044 __le16 qm_pq_id /* QM PQ ID */;
1045 /* set when in GSI offload mode on ROCE connection */
1046 u8 gsi_offload_flag;
1052 * Ramrod data for tx queue stop ramrod
1054 struct core_tx_stop_ramrod_data {
1055 __le32 reserved0[2];
1060 * Ramrod data for tx queue update ramrod
1062 struct core_tx_update_ramrod_data {
1063 u8 update_qm_pq_id_flg /* Flag to Update QM PQ ID */;
1065 __le16 qm_pq_id /* Updated QM PQ ID */;
1066 __le32 reserved1[1];
1071 * Enum flag for what type of dcb data to update
1073 enum dcb_dscp_update_mode {
1074 /* use when no change should be done to dcb data */
1075 DONT_UPDATE_DCB_DSCP,
1076 UPDATE_DCB /* use to update only l2 (vlan) priority */,
1077 UPDATE_DSCP /* use to update only l3 dscp */,
1078 UPDATE_DCB_DSCP /* update vlan pri and dscp */,
1079 MAX_DCB_DSCP_UPDATE_FLAG
1083 struct eth_mstorm_per_pf_stat {
1084 struct regpair gre_discard_pkts /* Dropped GRE RX packets */;
1085 struct regpair vxlan_discard_pkts /* Dropped VXLAN RX packets */;
1086 struct regpair geneve_discard_pkts /* Dropped GENEVE RX packets */;
1087 struct regpair lb_discard_pkts /* Dropped Tx switched packets */;
1091 struct eth_mstorm_per_queue_stat {
1092 /* Number of packets discarded because TTL=0 (in IPv4) or hopLimit=0 (IPv6) */
1093 struct regpair ttl0_discard;
1094 /* Number of packets discarded because they are bigger than MTU */
1095 struct regpair packet_too_big_discard;
1096 /* Number of packets discarded due to lack of host buffers (BDs/SGEs/CQEs) */
1097 struct regpair no_buff_discard;
1098 /* Number of packets discarded because of no active Rx connection */
1099 struct regpair not_active_discard;
1100 /* number of coalesced packets in all TPA aggregations */
1101 struct regpair tpa_coalesced_pkts;
1102 /* total number of TPA aggregations */
1103 struct regpair tpa_coalesced_events;
1104 /* number of aggregations, which abnormally ended */
1105 struct regpair tpa_aborts_num;
1106 /* total TCP payload length in all TPA aggregations */
1107 struct regpair tpa_coalesced_bytes;
1112 * Ethernet TX Per PF
1114 struct eth_pstorm_per_pf_stat {
1115 /* number of total ucast bytes sent on loopback port without errors */
1116 struct regpair sent_lb_ucast_bytes;
1117 /* number of total mcast bytes sent on loopback port without errors */
1118 struct regpair sent_lb_mcast_bytes;
1119 /* number of total bcast bytes sent on loopback port without errors */
1120 struct regpair sent_lb_bcast_bytes;
1121 /* number of total ucast packets sent on loopback port without errors */
1122 struct regpair sent_lb_ucast_pkts;
1123 /* number of total mcast packets sent on loopback port without errors */
1124 struct regpair sent_lb_mcast_pkts;
1125 /* number of total bcast packets sent on loopback port without errors */
1126 struct regpair sent_lb_bcast_pkts;
1127 struct regpair sent_gre_bytes /* Sent GRE bytes */;
1128 struct regpair sent_vxlan_bytes /* Sent VXLAN bytes */;
1129 struct regpair sent_geneve_bytes /* Sent GENEVE bytes */;
1130 struct regpair sent_gre_pkts /* Sent GRE packets */;
1131 struct regpair sent_vxlan_pkts /* Sent VXLAN packets */;
1132 struct regpair sent_geneve_pkts /* Sent GENEVE packets */;
1133 struct regpair gre_drop_pkts /* Dropped GRE TX packets */;
1134 struct regpair vxlan_drop_pkts /* Dropped VXLAN TX packets */;
1135 struct regpair geneve_drop_pkts /* Dropped GENEVE TX packets */;
1140 * Ethernet TX Per Queue Stats
1142 struct eth_pstorm_per_queue_stat {
1143 /* number of total bytes sent without errors */
1144 struct regpair sent_ucast_bytes;
1145 /* number of total bytes sent without errors */
1146 struct regpair sent_mcast_bytes;
1147 /* number of total bytes sent without errors */
1148 struct regpair sent_bcast_bytes;
1149 /* number of total packets sent without errors */
1150 struct regpair sent_ucast_pkts;
1151 /* number of total packets sent without errors */
1152 struct regpair sent_mcast_pkts;
1153 /* number of total packets sent without errors */
1154 struct regpair sent_bcast_pkts;
1155 /* number of total packets dropped due to errors */
1156 struct regpair error_drop_pkts;
1161 * ETH Rx producers data
1163 struct eth_rx_rate_limit {
1164 /* Rate Limit Multiplier - (Storm Clock (MHz) * 8 / Desired Bandwidth (MB/s)) */
1166 /* Constant term to add (or subtract from number of cycles) */
1168 u8 add_sub_cnst /* Add (1) or subtract (0) constant term */;
1174 struct eth_ustorm_per_pf_stat {
1175 /* number of total ucast bytes received on loopback port without errors */
1176 struct regpair rcv_lb_ucast_bytes;
1177 /* number of total mcast bytes received on loopback port without errors */
1178 struct regpair rcv_lb_mcast_bytes;
1179 /* number of total bcast bytes received on loopback port without errors */
1180 struct regpair rcv_lb_bcast_bytes;
1181 /* number of total ucast packets received on loopback port without errors */
1182 struct regpair rcv_lb_ucast_pkts;
1183 /* number of total mcast packets received on loopback port without errors */
1184 struct regpair rcv_lb_mcast_pkts;
1185 /* number of total bcast packets received on loopback port without errors */
1186 struct regpair rcv_lb_bcast_pkts;
1187 struct regpair rcv_gre_bytes /* Received GRE bytes */;
1188 struct regpair rcv_vxlan_bytes /* Received VXLAN bytes */;
1189 struct regpair rcv_geneve_bytes /* Received GENEVE bytes */;
1190 struct regpair rcv_gre_pkts /* Received GRE packets */;
1191 struct regpair rcv_vxlan_pkts /* Received VXLAN packets */;
1192 struct regpair rcv_geneve_pkts /* Received GENEVE packets */;
1196 struct eth_ustorm_per_queue_stat {
1197 struct regpair rcv_ucast_bytes;
1198 struct regpair rcv_mcast_bytes;
1199 struct regpair rcv_bcast_bytes;
1200 struct regpair rcv_ucast_pkts;
1201 struct regpair rcv_mcast_pkts;
1202 struct regpair rcv_bcast_pkts;
1207 * Event Ring VF-PF Channel data
1209 struct vf_pf_channel_eqe_data {
1210 struct regpair msg_addr /* VF-PF message address */;
1214 * Event Ring malicious VF data
1216 struct malicious_vf_eqe_data {
1217 u8 vf_id /* Malicious VF ID */;
1218 u8 err_id /* Malicious VF error (use enum malicious_vf_error_id) */;
1223 * Event Ring initial cleanup data
1225 struct initial_cleanup_eqe_data {
1226 u8 vf_id /* VF ID */;
1233 union event_ring_data {
1234 u8 bytes[8] /* Byte Array */;
1235 struct vf_pf_channel_eqe_data vf_pf_channel /* VF-PF Channel data */;
1236 struct iscsi_eqe_data iscsi_info /* Dedicated fields to iscsi data */;
1237 /* Dedicated fields to iscsi connect done results */
1238 struct iscsi_connect_done_results iscsi_conn_done_info;
1239 struct malicious_vf_eqe_data malicious_vf /* Malicious VF data */;
1240 /* VF Initial Cleanup data */
1241 struct initial_cleanup_eqe_data vf_init_cleanup;
1248 struct event_ring_entry {
1249 u8 protocol_id /* Event Protocol ID (use enum protocol_type) */;
1250 u8 opcode /* Event Opcode */;
1251 __le16 reserved0 /* Reserved */;
1252 __le16 echo /* Echo value from ramrod data on the host */;
1253 u8 fw_return_code /* FW return code for SP ramrods */;
1255 /* 0: synchronous EQE - a completion of SP message. 1: asynchronous EQE */
1256 #define EVENT_RING_ENTRY_ASYNC_MASK 0x1
1257 #define EVENT_RING_ENTRY_ASYNC_SHIFT 0
1258 #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
1259 #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
1260 union event_ring_data data;
1264 * Event Ring Next Page Address
1266 struct event_ring_next_addr {
1267 struct regpair addr /* Next Page Address */;
1268 __le32 reserved[2] /* Reserved */;
1272 * Event Ring Element
1274 union event_ring_element {
1275 struct event_ring_entry entry /* Event Ring Entry */;
1276 /* Event Ring Next Page Address */
1277 struct event_ring_next_addr next_addr;
1285 enum fw_flow_ctrl_mode {
1288 MAX_FW_FLOW_CTRL_MODE
1295 enum gft_profile_type {
1296 GFT_PROFILE_TYPE_4_TUPLE /* 4 tuple, IP type and L4 type match. */,
1297 /* L4 destination port, IP type and L4 type match. */
1298 GFT_PROFILE_TYPE_L4_DST_PORT,
1299 GFT_PROFILE_TYPE_IP_DST_ADDR /* IP destination port and IP type. */,
1300 /* tunnel type, inner IP source address and IP type match. */
1301 GFT_PROFILE_TYPE_IP_SRC_ADDR,
1302 GFT_PROFILE_TYPE_TUNNEL_TYPE /* tunnel type and outer IP type match. */,
1303 MAX_GFT_PROFILE_TYPE
1308 * Major and Minor hsi Versions
1310 struct hsi_fp_ver_struct {
1311 u8 minor_ver_arr[2] /* Minor Version of hsi loading pf */;
1312 u8 major_ver_arr[2] /* Major Version of driver loading pf */;
1320 INTEG_PHASE_BB_A0_LATEST = 3 /* BB A0 latest integration phase */,
1321 INTEG_PHASE_BB_B0_NO_MCP = 10 /* BB B0 without MCP */,
1322 INTEG_PHASE_BB_B0_WITH_MCP = 11 /* BB B0 with MCP */,
1330 enum iwarp_ll2_tx_queues {
1331 /* LL2 queue for OOO packets sent in-order by the driver */
1332 IWARP_LL2_IN_ORDER_TX_QUEUE = 1,
1333 /* LL2 queue for unaligned packets sent aligned by the driver */
1334 IWARP_LL2_ALIGNED_TX_QUEUE,
1335 /* LL2 queue for unaligned packets sent aligned and was right-trimmed by the
1338 IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE,
1339 IWARP_LL2_ERROR /* Error indication */,
1340 MAX_IWARP_LL2_TX_QUEUES
1345 * Malicious VF error ID
1347 enum malicious_vf_error_id {
1348 MALICIOUS_VF_NO_ERROR /* Zero placeholder value */,
1349 /* Writing to VF/PF channel when it is not ready */
1350 VF_PF_CHANNEL_NOT_READY,
1351 VF_ZONE_MSG_NOT_VALID /* VF channel message is not valid */,
1352 VF_ZONE_FUNC_NOT_ENABLED /* Parent PF of VF channel is not active */,
1353 /* TX packet is shorter then reported on BDs or from minimal size */
1354 ETH_PACKET_TOO_SMALL,
1355 /* Tx packet with marked as insert VLAN when its illegal */
1356 ETH_ILLEGAL_VLAN_MODE,
1357 ETH_MTU_VIOLATION /* TX packet is greater then MTU */,
1358 /* TX packet has illegal inband tags marked */
1359 ETH_ILLEGAL_INBAND_TAGS,
1360 /* Vlan cant be added to inband tag */
1361 ETH_VLAN_INSERT_AND_INBAND_VLAN,
1362 /* indicated number of BDs for the packet is illegal */
1364 ETH_FIRST_BD_WO_SOP /* 1st BD must have start_bd flag set */,
1365 /* There are not enough BDs for transmission of even one packet */
1366 ETH_INSUFFICIENT_BDS,
1367 ETH_ILLEGAL_LSO_HDR_NBDS /* Header NBDs value is illegal */,
1368 ETH_ILLEGAL_LSO_MSS /* LSO MSS value is more than allowed */,
1369 /* empty BD (which not contains control flags) is illegal */
1371 ETH_ILLEGAL_LSO_HDR_LEN /* LSO header size is above the limit */,
1372 /* In LSO its expected that on the local BD ring there will be at least MSS
1375 ETH_INSUFFICIENT_PAYLOAD,
1376 ETH_EDPM_OUT_OF_SYNC /* Valid BDs on local ring after EDPM L2 sync */,
1377 /* Tunneled packet with IPv6+Ext without a proper number of BDs */
1378 ETH_TUNN_IPV6_EXT_NBD_ERR,
1379 ETH_CONTROL_PACKET_VIOLATION /* VF sent control frame such as PFC */,
1380 ETH_ANTI_SPOOFING_ERR /* Anti-Spoofing verification failure */,
1381 MAX_MALICIOUS_VF_ERROR_ID
1387 * Mstorm non-triggering VF zone
1389 struct mstorm_non_trigger_vf_zone {
1390 /* VF statistic bucket */
1391 struct eth_mstorm_per_queue_stat eth_queue_stat;
1392 /* VF RX queues producers */
1393 struct eth_rx_prod_data
1394 eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD];
1401 struct mstorm_vf_zone {
1402 /* non-interrupt-triggering zone */
1403 struct mstorm_non_trigger_vf_zone non_trigger;
1408 * vlan header including TPID and TCI fields
1410 struct vlan_header {
1411 __le16 tpid /* Tag Protocol Identifier */;
1412 __le16 tci /* Tag Control Information */;
1416 * outer tag configurations
1418 struct outer_tag_config_struct {
1419 /* Enables the STAG Priority Change , Should be 1 for Bette Davis and UFP with
1420 * Host Control mode. Else - 0
1422 u8 enable_stag_pri_change;
1423 /* If inner_to_outer_pri_map is initialize then set pri_map_valid */
1426 /* In case mf_mode is MF_OVLAN, this field specifies the outer tag protocol
1427 * identifier and outer tag control information
1429 struct vlan_header outer_tag;
1430 /* Map from inner to outer priority. Set pri_map_valid when init map */
1431 u8 inner_to_outer_pri_map[8];
1436 * personality per PF
1438 enum personality_type {
1439 BAD_PERSONALITY_TYP,
1440 PERSONALITY_ISCSI /* iSCSI and LL2 */,
1441 PERSONALITY_FCOE /* Fcoe and LL2 */,
1442 PERSONALITY_RDMA_AND_ETH /* Roce or Iwarp, Eth and LL2 */,
1443 PERSONALITY_RDMA /* Roce and LL2 */,
1444 PERSONALITY_CORE /* CORE(LL2) */,
1445 PERSONALITY_ETH /* Ethernet */,
1446 PERSONALITY_TOE /* Toe and LL2 */,
1447 MAX_PERSONALITY_TYPE
1452 * tunnel configuration
1454 struct pf_start_tunnel_config {
1455 /* Set VXLAN tunnel UDP destination port to vxlan_udp_port. If not set -
1456 * FW will use a default port
1458 u8 set_vxlan_udp_port_flg;
1459 /* Set GENEVE tunnel UDP destination port to geneve_udp_port. If not set -
1460 * FW will use a default port
1462 u8 set_geneve_udp_port_flg;
1463 u8 tunnel_clss_vxlan /* Rx classification scheme for VXLAN tunnel. */;
1464 /* Rx classification scheme for l2 GENEVE tunnel. */
1465 u8 tunnel_clss_l2geneve;
1466 /* Rx classification scheme for ip GENEVE tunnel. */
1467 u8 tunnel_clss_ipgeneve;
1468 u8 tunnel_clss_l2gre /* Rx classification scheme for l2 GRE tunnel. */;
1469 u8 tunnel_clss_ipgre /* Rx classification scheme for ip GRE tunnel. */;
1471 /* VXLAN tunnel UDP destination port. Valid if set_vxlan_udp_port_flg=1 */
1472 __le16 vxlan_udp_port;
1473 /* GENEVE tunnel UDP destination port. Valid if set_geneve_udp_port_flg=1 */
1474 __le16 geneve_udp_port;
1478 * Ramrod data for PF start ramrod
1480 struct pf_start_ramrod_data {
1481 struct regpair event_ring_pbl_addr /* Address of event ring PBL */;
1482 /* PBL address of consolidation queue */
1483 struct regpair consolid_q_pbl_addr;
1484 /* tunnel configuration. */
1485 struct pf_start_tunnel_config tunnel_config;
1486 __le16 event_ring_sb_id /* Status block ID */;
1487 /* All VfIds owned by Pf will be from baseVfId till baseVfId+numVfs */
1489 u8 num_vfs /* Amount of vfs owned by PF */;
1490 u8 event_ring_num_pages /* Number of PBL pages in event ring */;
1491 u8 event_ring_sb_index /* Status block index */;
1492 u8 path_id /* HW path ID (engine ID) */;
1493 u8 warning_as_error /* In FW asserts, treat warning as error */;
1494 /* If not set - throw a warning for each ramrod (for debug) */
1495 u8 dont_log_ramrods;
1496 u8 personality /* define what type of personality is new PF */;
1497 /* Log type mask. Each bit set enables a corresponding event type logging.
1498 * Event types are defined as ASSERT_LOG_TYPE_xxx
1500 __le16 log_type_mask;
1501 u8 mf_mode /* Multi function mode */;
1502 u8 integ_phase /* Integration phase */;
1503 /* If set, inter-pf tx switching is allowed in Switch Independent func mode */
1504 u8 allow_npar_tx_switching;
1506 /* FP HSI version to be used by FW */
1507 struct hsi_fp_ver_struct hsi_fp_ver;
1508 /* Outer tag configurations */
1509 struct outer_tag_config_struct outer_tag_config;
1515 * Data for port update ramrod
1517 struct protocol_dcb_data {
1518 u8 dcb_enable_flag /* dcbEnable flag value */;
1519 u8 dscp_enable_flag /* If set use dscp value */;
1520 u8 dcb_priority /* dcbPri flag value */;
1521 u8 dcb_tc /* dcb TC value */;
1522 u8 dscp_val /* dscp value to write if dscp_enable_flag is set */;
1523 /* When DCB is enabled - if this flag is set, dont add VLAN 0 tag to untagged
1526 u8 dcb_dont_add_vlan0;
1530 * Update tunnel configuration
1532 struct pf_update_tunnel_config {
1533 /* Update RX per PF tunnel classification scheme. */
1534 u8 update_rx_pf_clss;
1535 /* Update per PORT default tunnel RX classification scheme for traffic with
1536 * unknown unicast outer MAC in NPAR mode.
1538 u8 update_rx_def_ucast_clss;
1539 /* Update per PORT default tunnel RX classification scheme for traffic with non
1540 * unicast outer MAC in NPAR mode.
1542 u8 update_rx_def_non_ucast_clss;
1543 /* Update VXLAN tunnel UDP destination port. */
1544 u8 set_vxlan_udp_port_flg;
1545 /* Update GENEVE tunnel UDP destination port. */
1546 u8 set_geneve_udp_port_flg;
1547 u8 tunnel_clss_vxlan /* Classification scheme for VXLAN tunnel. */;
1548 /* Classification scheme for l2 GENEVE tunnel. */
1549 u8 tunnel_clss_l2geneve;
1550 /* Classification scheme for ip GENEVE tunnel. */
1551 u8 tunnel_clss_ipgeneve;
1552 u8 tunnel_clss_l2gre /* Classification scheme for l2 GRE tunnel. */;
1553 u8 tunnel_clss_ipgre /* Classification scheme for ip GRE tunnel. */;
1554 __le16 vxlan_udp_port /* VXLAN tunnel UDP destination port. */;
1555 __le16 geneve_udp_port /* GENEVE tunnel UDP destination port. */;
1560 * Data for port update ramrod
1562 struct pf_update_ramrod_data {
1563 /* Update Eth DCB data indication (use enum dcb_dscp_update_mode) */
1564 u8 update_eth_dcb_data_mode;
1565 /* Update FCOE DCB data indication (use enum dcb_dscp_update_mode) */
1566 u8 update_fcoe_dcb_data_mode;
1567 /* Update iSCSI DCB data indication (use enum dcb_dscp_update_mode) */
1568 u8 update_iscsi_dcb_data_mode;
1569 u8 update_roce_dcb_data_mode /* Update ROCE DCB data indication */;
1570 /* Update RROCE (RoceV2) DCB data indication */
1571 u8 update_rroce_dcb_data_mode;
1572 u8 update_iwarp_dcb_data_mode /* Update IWARP DCB data indication */;
1573 u8 update_mf_vlan_flag /* Update MF outer vlan Id */;
1574 /* Update Enable STAG Priority Change indication */
1575 u8 update_enable_stag_pri_change;
1576 struct protocol_dcb_data eth_dcb_data /* core eth related fields */;
1577 struct protocol_dcb_data fcoe_dcb_data /* core fcoe related fields */;
1578 /* core iscsi related fields */
1579 struct protocol_dcb_data iscsi_dcb_data;
1580 struct protocol_dcb_data roce_dcb_data /* core roce related fields */;
1581 /* core roce related fields */
1582 struct protocol_dcb_data rroce_dcb_data;
1583 /* core iwarp related fields */
1584 struct protocol_dcb_data iwarp_dcb_data;
1585 __le16 mf_vlan /* new outer vlan id value */;
1586 /* enables the inner to outer TAG priority mapping. Should be 1 for Bette Davis
1587 * and UFP with Host Control mode, else - 0.
1589 u8 enable_stag_pri_change;
1591 /* tunnel configuration. */
1592 struct pf_update_tunnel_config tunnel_config;
1601 ENGX2_PORTX1 /* 2 engines x 1 port */,
1602 ENGX2_PORTX2 /* 2 engines x 2 ports */,
1603 ENGX1_PORTX1 /* 1 engine x 1 port */,
1604 ENGX1_PORTX2 /* 1 engine x 2 ports */,
1605 ENGX1_PORTX4 /* 1 engine x 4 ports */,
1612 * use to index in hsi_fp_[major|minor]_ver_arr per protocol
1614 enum protocol_version_array_key {
1617 MAX_PROTOCOL_VERSION_ARRAY_KEY
1625 struct rdma_sent_stats {
1626 struct regpair sent_bytes /* number of total RDMA bytes sent */;
1627 struct regpair sent_pkts /* number of total RDMA packets sent */;
1631 * Pstorm non-triggering VF zone
1633 struct pstorm_non_trigger_vf_zone {
1634 /* VF statistic bucket */
1635 struct eth_pstorm_per_queue_stat eth_queue_stat;
1636 struct rdma_sent_stats rdma_stats /* RoCE sent statistics */;
1643 struct pstorm_vf_zone {
1644 /* non-interrupt-triggering zone */
1645 struct pstorm_non_trigger_vf_zone non_trigger;
1646 struct regpair reserved[7] /* vf_zone size mus be power of 2 */;
1651 * Ramrod Header of SPQE
1653 struct ramrod_header {
1654 __le32 cid /* Slowpath Connection CID */;
1655 u8 cmd_id /* Ramrod Cmd (Per Protocol Type) */;
1656 u8 protocol_id /* Ramrod Protocol ID */;
1657 __le16 echo /* Ramrod echo */;
1664 struct rdma_rcv_stats {
1665 struct regpair rcv_bytes /* number of total RDMA bytes received */;
1666 struct regpair rcv_pkts /* number of total RDMA packets received */;
1672 * Data for update QCN/DCQCN RL ramrod
1674 struct rl_update_ramrod_data {
1675 u8 qcn_update_param_flg /* Update QCN global params: timeout. */;
1676 /* Update DCQCN global params: timeout, g, k. */
1677 u8 dcqcn_update_param_flg;
1678 u8 rl_init_flg /* Init RL parameters, when RL disabled. */;
1679 u8 rl_start_flg /* Start RL in IDLE state. Set rate to maximum. */;
1680 u8 rl_stop_flg /* Stop RL. */;
1681 u8 rl_id_first /* ID of first or single RL, that will be updated. */;
1682 /* ID of last RL, that will be updated. If clear, single RL will updated. */
1684 u8 rl_dc_qcn_flg /* If set, RL will used for DCQCN. */;
1685 __le32 rl_bc_rate /* Byte Counter Limit. */;
1686 __le16 rl_max_rate /* Maximum rate in 1.6 Mbps resolution. */;
1687 __le16 rl_r_ai /* Active increase rate. */;
1688 __le16 rl_r_hai /* Hyper active increase rate. */;
1689 __le16 dcqcn_g /* DCQCN Alpha update gain in 1/64K resolution . */;
1690 __le32 dcqcn_k_us /* DCQCN Alpha update interval. */;
1691 __le32 dcqcn_timeuot_us /* DCQCN timeout. */;
1692 __le32 qcn_timeuot_us /* QCN timeout. */;
1698 * Slowpath Element (SPQE)
1700 struct slow_path_element {
1701 struct ramrod_header hdr /* Ramrod Header */;
1702 struct regpair data_ptr /* Pointer to the Ramrod Data on the Host */;
1707 * Tstorm non-triggering VF zone
1709 struct tstorm_non_trigger_vf_zone {
1710 struct rdma_rcv_stats rdma_stats /* RoCE received statistics */;
1714 struct tstorm_per_port_stat {
1715 /* packet is dropped because it was truncated in NIG */
1716 struct regpair trunc_error_discard;
1717 /* packet is dropped because of Ethernet FCS error */
1718 struct regpair mac_error_discard;
1719 /* packet is dropped because classification was unsuccessful */
1720 struct regpair mftag_filter_discard;
1721 /* packet was passed to Ethernet and dropped because of no mac filter match */
1722 struct regpair eth_mac_filter_discard;
1723 /* packet passed to Light L2 and dropped because Light L2 is not configured for
1726 struct regpair ll2_mac_filter_discard;
1727 /* packet passed to Light L2 and dropped because Light L2 is not configured for
1730 struct regpair ll2_conn_disabled_discard;
1731 /* packet is an ISCSI irregular packet */
1732 struct regpair iscsi_irregular_pkt;
1733 /* packet is an FCOE irregular packet */
1734 struct regpair fcoe_irregular_pkt;
1735 /* packet is an ROCE irregular packet */
1736 struct regpair roce_irregular_pkt;
1737 /* packet is an IWARP irregular packet */
1738 struct regpair iwarp_irregular_pkt;
1739 /* packet is an ETH irregular packet */
1740 struct regpair eth_irregular_pkt;
1741 /* packet is an TOE irregular packet */
1742 struct regpair toe_irregular_pkt;
1743 /* packet is an PREROCE irregular packet */
1744 struct regpair preroce_irregular_pkt;
1745 struct regpair eth_gre_tunn_filter_discard /* GRE dropped packets */;
1746 /* VXLAN dropped packets */
1747 struct regpair eth_vxlan_tunn_filter_discard;
1748 /* GENEVE dropped packets */
1749 struct regpair eth_geneve_tunn_filter_discard;
1750 struct regpair eth_gft_drop_pkt /* GFT dropped packets */;
1757 struct tstorm_vf_zone {
1758 /* non-interrupt-triggering zone */
1759 struct tstorm_non_trigger_vf_zone non_trigger;
1764 * Tunnel classification scheme
1767 /* Use MAC and VLAN from first L2 header for vport classification. */
1768 TUNNEL_CLSS_MAC_VLAN = 0,
1769 /* Use MAC from first L2 header and VNI from tunnel header for vport
1772 TUNNEL_CLSS_MAC_VNI,
1773 /* Use MAC and VLAN from last L2 header for vport classification */
1774 TUNNEL_CLSS_INNER_MAC_VLAN,
1775 /* Use MAC from last L2 header and VNI from tunnel header for vport
1778 TUNNEL_CLSS_INNER_MAC_VNI,
1779 /* Use MAC and VLAN from last L2 header for vport classification. If no exact
1780 * match, use MAC and VLAN from first L2 header for classification.
1782 TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE,
1789 * Ustorm non-triggering VF zone
1791 struct ustorm_non_trigger_vf_zone {
1792 /* VF statistic bucket */
1793 struct eth_ustorm_per_queue_stat eth_queue_stat;
1794 struct regpair vf_pf_msg_addr /* VF-PF message address */;
1799 * Ustorm triggering VF zone
1801 struct ustorm_trigger_vf_zone {
1802 u8 vf_pf_msg_valid /* VF-PF message valid flag */;
1810 struct ustorm_vf_zone {
1811 /* non-interrupt-triggering zone */
1812 struct ustorm_non_trigger_vf_zone non_trigger;
1813 struct ustorm_trigger_vf_zone trigger /* interrupt triggering zone */;
1818 * VF-PF channel data
1820 struct vf_pf_channel_data {
1821 /* 0: VF-PF Channel NOT ready. Waiting for ack from PF driver. 1: VF-PF Channel
1822 * is ready for a new transaction.
1825 /* 0: VF-PF Channel is invalid because of malicious VF. 1: VF-PF Channel is
1835 * Ramrod data for VF start ramrod
1837 struct vf_start_ramrod_data {
1838 u8 vf_id /* VF ID */;
1839 /* If set, initial cleanup ack will be sent to parent PF SP event queue */
1841 __le16 opaque_fid /* VF opaque FID */;
1842 u8 personality /* define what type of personality is new VF */;
1844 /* FP HSI version to be used by FW */
1845 struct hsi_fp_ver_struct hsi_fp_ver;
1850 * Ramrod data for VF start ramrod
1852 struct vf_stop_ramrod_data {
1853 u8 vf_id /* VF ID */;
1861 * VF zone size mode.
1863 enum vf_zone_size_mode {
1864 /* Default VF zone size. Up to 192 VF supported. */
1865 VF_ZONE_SIZE_MODE_DEFAULT,
1866 /* Doubled VF zone size. Up to 96 VF supported. */
1867 VF_ZONE_SIZE_MODE_DOUBLE,
1868 /* Quad VF zone size. Up to 48 VF supported. */
1869 VF_ZONE_SIZE_MODE_QUAD,
1870 MAX_VF_ZONE_SIZE_MODE
1878 * Attentions status block
1880 struct atten_status_block {
1884 __le16 sb_index /* status block running index */;
1894 /* DMA Source. 0 - PCIe, 1 - GRC (use enum dmae_cmd_src_enum) */
1895 #define DMAE_CMD_SRC_MASK 0x1
1896 #define DMAE_CMD_SRC_SHIFT 0
1897 /* DMA destination. 0 - None, 1 - PCIe, 2 - GRC, 3 - None
1898 * (use enum dmae_cmd_dst_enum)
1900 #define DMAE_CMD_DST_MASK 0x3
1901 #define DMAE_CMD_DST_SHIFT 1
1902 /* Completion destination. 0 - PCie, 1 - GRC (use enum dmae_cmd_c_dst_enum) */
1903 #define DMAE_CMD_C_DST_MASK 0x1
1904 #define DMAE_CMD_C_DST_SHIFT 3
1905 /* Reset the CRC result (do not use the previous result as the seed) */
1906 #define DMAE_CMD_CRC_RESET_MASK 0x1
1907 #define DMAE_CMD_CRC_RESET_SHIFT 4
1908 /* Reset the source address in the next go to the same source address of the
1911 #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1
1912 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5
1913 /* Reset the destination address in the next go to the same destination address
1914 * of the previous go
1916 #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1
1917 #define DMAE_CMD_DST_ADDR_RESET_SHIFT 6
1918 /* 0 completion function is the same as src function, 1 - 0 completion
1919 * function is the same as dst function (use enum dmae_cmd_comp_func_enum)
1921 #define DMAE_CMD_COMP_FUNC_MASK 0x1
1922 #define DMAE_CMD_COMP_FUNC_SHIFT 7
1923 /* 0 - Do not write a completion word, 1 - Write a completion word
1924 * (use enum dmae_cmd_comp_word_en_enum)
1926 #define DMAE_CMD_COMP_WORD_EN_MASK 0x1
1927 #define DMAE_CMD_COMP_WORD_EN_SHIFT 8
1928 /* 0 - Do not write a CRC word, 1 - Write a CRC word
1929 * (use enum dmae_cmd_comp_crc_en_enum)
1931 #define DMAE_CMD_COMP_CRC_EN_MASK 0x1
1932 #define DMAE_CMD_COMP_CRC_EN_SHIFT 9
1933 /* The CRC word should be taken from the DMAE address space from address 9+X,
1934 * where X is the value in these bits.
1936 #define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7
1937 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
1938 #define DMAE_CMD_RESERVED1_MASK 0x1
1939 #define DMAE_CMD_RESERVED1_SHIFT 13
1940 #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3
1941 #define DMAE_CMD_ENDIANITY_MODE_SHIFT 14
1942 /* The field specifies how the completion word is affected by PCIe read error. 0
1943 * Send a regular completion, 1 - Send a completion with an error indication,
1944 * 2 do not send a completion (use enum dmae_cmd_error_handling_enum)
1946 #define DMAE_CMD_ERR_HANDLING_MASK 0x3
1947 #define DMAE_CMD_ERR_HANDLING_SHIFT 16
1948 /* The port ID to be placed on the RF FID field of the GRC bus. this field is
1949 * used both when GRC is the destination and when it is the source of the DMAE
1952 #define DMAE_CMD_PORT_ID_MASK 0x3
1953 #define DMAE_CMD_PORT_ID_SHIFT 18
1954 /* Source PCI function number [3:0] */
1955 #define DMAE_CMD_SRC_PF_ID_MASK 0xF
1956 #define DMAE_CMD_SRC_PF_ID_SHIFT 20
1957 /* Destination PCI function number [3:0] */
1958 #define DMAE_CMD_DST_PF_ID_MASK 0xF
1959 #define DMAE_CMD_DST_PF_ID_SHIFT 24
1960 #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1 /* Source VFID valid */
1961 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
1962 #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1 /* Destination VFID valid */
1963 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
1964 #define DMAE_CMD_RESERVED2_MASK 0x3
1965 #define DMAE_CMD_RESERVED2_SHIFT 30
1966 /* PCIe source address low in bytes or GRC source address in DW */
1968 /* PCIe source address high in bytes or reserved (if source is GRC) */
1970 /* PCIe destination address low in bytes or GRC destination address in DW */
1972 /* PCIe destination address high in bytes or reserved (if destination is GRC) */
1974 __le16 length_dw /* Length in DW */;
1976 #define DMAE_CMD_SRC_VF_ID_MASK 0xFF /* Source VF id */
1977 #define DMAE_CMD_SRC_VF_ID_SHIFT 0
1978 #define DMAE_CMD_DST_VF_ID_MASK 0xFF /* Destination VF id */
1979 #define DMAE_CMD_DST_VF_ID_SHIFT 8
1980 /* PCIe completion address low in bytes or GRC completion address in DW */
1981 __le32 comp_addr_lo;
1982 /* PCIe completion address high in bytes or reserved (if completion address is
1985 __le32 comp_addr_hi;
1986 __le32 comp_val /* Value to write to completion address */;
1987 __le32 crc32 /* crc16 result */;
1988 __le32 crc_32_c /* crc32_c result */;
1989 __le16 crc16 /* crc16 result */;
1990 __le16 crc16_c /* crc16_c result */;
1991 __le16 crc10 /* crc_t10 result */;
1993 __le16 xsum16 /* checksum16 result */;
1994 __le16 xsum8 /* checksum8 result */;
1998 enum dmae_cmd_comp_crc_en_enum {
1999 dmae_cmd_comp_crc_disabled /* Do not write a CRC word */,
2000 dmae_cmd_comp_crc_enabled /* Write a CRC word */,
2001 MAX_DMAE_CMD_COMP_CRC_EN_ENUM
2005 enum dmae_cmd_comp_func_enum {
2006 /* completion word and/or CRC will be sent to SRC-PCI function/SRC VFID */
2007 dmae_cmd_comp_func_to_src,
2008 /* completion word and/or CRC will be sent to DST-PCI function/DST VFID */
2009 dmae_cmd_comp_func_to_dst,
2010 MAX_DMAE_CMD_COMP_FUNC_ENUM
2014 enum dmae_cmd_comp_word_en_enum {
2015 dmae_cmd_comp_word_disabled /* Do not write a completion word */,
2016 dmae_cmd_comp_word_enabled /* Write the completion word */,
2017 MAX_DMAE_CMD_COMP_WORD_EN_ENUM
2021 enum dmae_cmd_c_dst_enum {
2022 dmae_cmd_c_dst_pcie,
2024 MAX_DMAE_CMD_C_DST_ENUM
2028 enum dmae_cmd_dst_enum {
2029 dmae_cmd_dst_none_0,
2032 dmae_cmd_dst_none_3,
2033 MAX_DMAE_CMD_DST_ENUM
2037 enum dmae_cmd_error_handling_enum {
2038 /* Send a regular completion (with no error indication) */
2039 dmae_cmd_error_handling_send_regular_comp,
2040 /* Send a completion with an error indication (i.e. set bit 31 of the completion
2043 dmae_cmd_error_handling_send_comp_with_err,
2044 dmae_cmd_error_handling_dont_send_comp /* Do not send a completion */,
2045 MAX_DMAE_CMD_ERROR_HANDLING_ENUM
2049 enum dmae_cmd_src_enum {
2050 dmae_cmd_src_pcie /* The source is the PCIe */,
2051 dmae_cmd_src_grc /* The source is the GRC */,
2052 MAX_DMAE_CMD_SRC_ENUM
2056 struct e4_mstorm_core_conn_ag_ctx {
2057 u8 byte0 /* cdu_validation */;
2058 u8 byte1 /* state */;
2060 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2061 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
2062 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2063 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
2064 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
2065 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
2066 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
2067 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
2068 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
2069 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
2071 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2072 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
2073 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2074 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
2075 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2076 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
2077 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2078 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
2079 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2080 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
2081 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2082 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
2083 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2084 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
2085 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2086 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
2087 __le16 word0 /* word0 */;
2088 __le16 word1 /* word1 */;
2089 __le32 reg0 /* reg0 */;
2090 __le32 reg1 /* reg1 */;
2097 struct e4_ystorm_core_conn_ag_ctx {
2098 u8 byte0 /* cdu_validation */;
2099 u8 byte1 /* state */;
2101 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2102 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
2103 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2104 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
2105 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
2106 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
2107 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
2108 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
2109 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
2110 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
2112 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2113 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
2114 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2115 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
2116 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2117 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
2118 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2119 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
2120 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2121 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
2122 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2123 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
2124 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2125 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
2126 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2127 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
2128 u8 byte2 /* byte2 */;
2129 u8 byte3 /* byte3 */;
2130 __le16 word0 /* word0 */;
2131 __le32 reg0 /* reg0 */;
2132 __le32 reg1 /* reg1 */;
2133 __le16 word1 /* word1 */;
2134 __le16 word2 /* word2 */;
2135 __le16 word3 /* word3 */;
2136 __le16 word4 /* word4 */;
2137 __le32 reg2 /* reg2 */;
2138 __le32 reg3 /* reg3 */;
2143 * IGU cleanup command
2145 struct igu_cleanup {
2146 __le32 sb_id_and_flags;
2147 #define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF
2148 #define IGU_CLEANUP_RESERVED0_SHIFT 0
2149 /* cleanup clear - 0, set - 1 */
2150 #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1
2151 #define IGU_CLEANUP_CLEANUP_SET_SHIFT 27
2152 #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7
2153 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28
2154 /* must always be set (use enum command_type_bit) */
2155 #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1
2156 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31
2162 * IGU firmware driver command
2165 struct igu_prod_cons_update prod_cons_update;
2166 struct igu_cleanup cleanup;
2171 * IGU firmware driver command
2173 struct igu_command_reg_ctrl {
2175 __le16 igu_command_reg_ctrl_fields;
2176 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF
2177 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
2178 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7
2179 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12
2180 /* command typ: 0 - read, 1 - write */
2181 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1
2182 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
2187 * IGU mapping line structure
2189 struct igu_mapping_line {
2190 __le32 igu_mapping_line_fields;
2191 #define IGU_MAPPING_LINE_VALID_MASK 0x1
2192 #define IGU_MAPPING_LINE_VALID_SHIFT 0
2193 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF
2194 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1
2195 /* In BB: VF-0-120, PF-0-7; In K2: VF-0-191, PF-0-15 */
2196 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF
2197 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9
2198 #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1 /* PF-1, VF-0 */
2199 #define IGU_MAPPING_LINE_PF_VALID_SHIFT 17
2200 #define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F
2201 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18
2202 #define IGU_MAPPING_LINE_RESERVED_MASK 0xFF
2203 #define IGU_MAPPING_LINE_RESERVED_SHIFT 24
2208 * IGU MSIX line structure
2210 struct igu_msix_vector {
2211 struct regpair address;
2213 __le32 msix_vector_fields;
2214 #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1
2215 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0
2216 #define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF
2217 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1
2218 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF
2219 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16
2220 #define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF
2221 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24
2226 * per encapsulation type enabling flags
2228 struct prs_reg_encapsulation_type_en {
2230 /* Enable bit for Ethernet-over-GRE (L2 GRE) encapsulation. */
2231 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1
2232 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0
2233 /* Enable bit for IP-over-GRE (IP GRE) encapsulation. */
2234 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1
2235 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1
2236 /* Enable bit for VXLAN encapsulation. */
2237 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1
2238 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2
2239 /* Enable bit for T-Tag encapsulation. */
2240 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1
2241 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3
2242 /* Enable bit for Ethernet-over-GENEVE (L2 GENEVE) encapsulation. */
2243 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1
2244 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4
2245 /* Enable bit for IP-over-GENEVE (IP GENEVE) encapsulation. */
2246 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1
2247 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5
2248 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3
2249 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6
2253 enum pxp_tph_st_hint {
2254 TPH_ST_HINT_BIDIR /* Read/Write access by Host and Device */,
2255 TPH_ST_HINT_REQUESTER /* Read/Write access by Device */,
2256 /* Device Write and Host Read, or Host Write and Device Read */
2258 /* Device Write and Host Read, or Host Write and Device Read - with temporal
2261 TPH_ST_HINT_TARGET_PRIO,
2267 * QM hardware structure of enable bypass credit mask
2269 struct qm_rf_bypass_mask {
2271 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1
2272 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0
2273 #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1
2274 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1
2275 #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1
2276 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2
2277 #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1
2278 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3
2279 #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1
2280 #define QM_RF_BYPASS_MASK_PFRL_SHIFT 4
2281 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1
2282 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5
2283 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1
2284 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6
2285 #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1
2286 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7
2291 * QM hardware structure of opportunistic credit mask
2293 struct qm_rf_opportunistic_mask {
2295 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1
2296 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0
2297 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1
2298 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1
2299 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1
2300 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2
2301 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1
2302 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3
2303 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1
2304 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4
2305 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1
2306 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5
2307 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1
2308 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6
2309 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1
2310 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7
2311 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1
2312 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8
2313 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F
2314 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9
2319 * QM hardware structure of QM map memory
2321 struct qm_rf_pq_map_e4 {
2323 #define QM_RF_PQ_MAP_E4_PQ_VALID_MASK 0x1 /* PQ active */
2324 #define QM_RF_PQ_MAP_E4_PQ_VALID_SHIFT 0
2325 #define QM_RF_PQ_MAP_E4_RL_ID_MASK 0xFF /* RL ID */
2326 #define QM_RF_PQ_MAP_E4_RL_ID_SHIFT 1
2327 /* the first PQ associated with the VPORT and VOQ of this PQ */
2328 #define QM_RF_PQ_MAP_E4_VP_PQ_ID_MASK 0x1FF
2329 #define QM_RF_PQ_MAP_E4_VP_PQ_ID_SHIFT 9
2330 #define QM_RF_PQ_MAP_E4_VOQ_MASK 0x1F /* VOQ */
2331 #define QM_RF_PQ_MAP_E4_VOQ_SHIFT 18
2332 #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_MASK 0x3 /* WRR weight */
2333 #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_SHIFT 23
2334 #define QM_RF_PQ_MAP_E4_RL_VALID_MASK 0x1 /* RL active */
2335 #define QM_RF_PQ_MAP_E4_RL_VALID_SHIFT 25
2336 #define QM_RF_PQ_MAP_E4_RESERVED_MASK 0x3F
2337 #define QM_RF_PQ_MAP_E4_RESERVED_SHIFT 26
2342 * Completion params for aggregated interrupt completion
2344 struct sdm_agg_int_comp_params {
2346 /* the number of aggregated interrupt, 0-31 */
2347 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F
2348 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0
2349 /* 1 - set a bit in aggregated vector, 0 - dont set */
2350 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1
2351 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
2352 /* Number of bit in the aggregated vector, 0-279 (TBD) */
2353 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF
2354 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7
2359 * SDM operation gen command (generate aggregative interrupt)
2363 /* completion parameters 0-15 */
2364 #define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF
2365 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
2366 #define SDM_OP_GEN_COMP_TYPE_MASK 0xF /* completion type 16-19 */
2367 #define SDM_OP_GEN_COMP_TYPE_SHIFT 16
2368 #define SDM_OP_GEN_RESERVED_MASK 0xFFF /* reserved 20-31 */
2369 #define SDM_OP_GEN_RESERVED_SHIFT 20
2372 struct ystorm_core_conn_ag_ctx {
2373 u8 byte0 /* cdu_validation */;
2374 u8 byte1 /* state */;
2376 #define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2377 #define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
2378 #define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2379 #define YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
2380 #define YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
2381 #define YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
2382 #define YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
2383 #define YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
2384 #define YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
2385 #define YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
2387 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2388 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
2389 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2390 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
2391 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2392 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
2393 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2394 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
2395 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2396 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
2397 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2398 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
2399 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2400 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
2401 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2402 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
2403 u8 byte2 /* byte2 */;
2404 u8 byte3 /* byte3 */;
2405 __le16 word0 /* word0 */;
2406 __le32 reg0 /* reg0 */;
2407 __le32 reg1 /* reg1 */;
2408 __le16 word1 /* word1 */;
2409 __le16 word2 /* word2 */;
2410 __le16 word3 /* word3 */;
2411 __le16 word4 /* word4 */;
2412 __le32 reg2 /* reg2 */;
2413 __le32 reg3 /* reg3 */;
2416 #endif /* __ECORE_HSI_COMMON__ */