2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #ifndef __ECORE_HSI_DEBUG_TOOLS__
10 #define __ECORE_HSI_DEBUG_TOOLS__
11 /****************************************/
12 /* Debug Tools HSI constants and macros */
13 /****************************************/
17 GRCBASE_GRC = 0x50000,
18 GRCBASE_MISCS = 0x9000,
19 GRCBASE_MISC = 0x8000,
21 GRCBASE_PGLUE_B = 0x2a8000,
22 GRCBASE_CNIG = 0x218000,
23 GRCBASE_CPMU = 0x30000,
24 GRCBASE_NCSI = 0x40000,
25 GRCBASE_OPTE = 0x53000,
26 GRCBASE_BMB = 0x540000,
27 GRCBASE_PCIE = 0x54000,
28 GRCBASE_MCP = 0xe00000,
29 GRCBASE_MCP2 = 0x52000,
30 GRCBASE_PSWHST = 0x2a0000,
31 GRCBASE_PSWHST2 = 0x29e000,
32 GRCBASE_PSWRD = 0x29c000,
33 GRCBASE_PSWRD2 = 0x29d000,
34 GRCBASE_PSWWR = 0x29a000,
35 GRCBASE_PSWWR2 = 0x29b000,
36 GRCBASE_PSWRQ = 0x280000,
37 GRCBASE_PSWRQ2 = 0x240000,
39 GRCBASE_DMAE = 0xc000,
40 GRCBASE_PTU = 0x560000,
41 GRCBASE_TCM = 0x1180000,
42 GRCBASE_MCM = 0x1200000,
43 GRCBASE_UCM = 0x1280000,
44 GRCBASE_XCM = 0x1000000,
45 GRCBASE_YCM = 0x1080000,
46 GRCBASE_PCM = 0x1100000,
47 GRCBASE_QM = 0x2f0000,
48 GRCBASE_TM = 0x2c0000,
49 GRCBASE_DORQ = 0x100000,
50 GRCBASE_BRB = 0x340000,
51 GRCBASE_SRC = 0x238000,
52 GRCBASE_PRS = 0x1f0000,
53 GRCBASE_TSDM = 0xfb0000,
54 GRCBASE_MSDM = 0xfc0000,
55 GRCBASE_USDM = 0xfd0000,
56 GRCBASE_XSDM = 0xf80000,
57 GRCBASE_YSDM = 0xf90000,
58 GRCBASE_PSDM = 0xfa0000,
59 GRCBASE_TSEM = 0x1700000,
60 GRCBASE_MSEM = 0x1800000,
61 GRCBASE_USEM = 0x1900000,
62 GRCBASE_XSEM = 0x1400000,
63 GRCBASE_YSEM = 0x1500000,
64 GRCBASE_PSEM = 0x1600000,
65 GRCBASE_RSS = 0x238800,
66 GRCBASE_TMLD = 0x4d0000,
67 GRCBASE_MULD = 0x4e0000,
68 GRCBASE_YULD = 0x4c8000,
69 GRCBASE_XYLD = 0x4c0000,
70 GRCBASE_PRM = 0x230000,
71 GRCBASE_PBF_PB1 = 0xda0000,
72 GRCBASE_PBF_PB2 = 0xda4000,
73 GRCBASE_RPB = 0x23c000,
74 GRCBASE_BTB = 0xdb0000,
75 GRCBASE_PBF = 0xd80000,
76 GRCBASE_RDIF = 0x300000,
77 GRCBASE_TDIF = 0x310000,
78 GRCBASE_CDU = 0x580000,
79 GRCBASE_CCFC = 0x2e0000,
80 GRCBASE_TCFC = 0x2d0000,
81 GRCBASE_IGU = 0x180000,
82 GRCBASE_CAU = 0x1c0000,
83 GRCBASE_UMAC = 0x51000,
84 GRCBASE_XMAC = 0x210000,
85 GRCBASE_DBG = 0x10000,
86 GRCBASE_NIG = 0x500000,
87 GRCBASE_WOL = 0x600000,
88 GRCBASE_BMBN = 0x610000,
89 GRCBASE_IPC = 0x20000,
90 GRCBASE_NWM = 0x800000,
91 GRCBASE_NWS = 0x700000,
92 GRCBASE_MS = 0x6a0000,
93 GRCBASE_PHY_PCIE = 0x620000,
94 GRCBASE_LED = 0x6b8000,
95 GRCBASE_AVS_WRAP = 0x6b0000,
96 GRCBASE_RGFS = 0x19d0000,
97 GRCBASE_TGFS = 0x19e0000,
98 GRCBASE_PTLD = 0x19f0000,
99 GRCBASE_YPLD = 0x1a10000,
100 GRCBASE_MISC_AEU = 0x8000,
101 GRCBASE_BAR0_MAP = 0x1c00000,
197 * binary debug buffer types
199 enum bin_dbg_buffer_type {
200 BIN_BUF_DBG_MODE_TREE /* init modes tree */,
201 BIN_BUF_DBG_DUMP_REG /* GRC Dump registers */,
202 BIN_BUF_DBG_DUMP_MEM /* GRC Dump memories */,
203 BIN_BUF_DBG_IDLE_CHK_REGS /* Idle Check registers */,
204 BIN_BUF_DBG_IDLE_CHK_IMMS /* Idle Check immediates */,
205 BIN_BUF_DBG_IDLE_CHK_RULES /* Idle Check rules */,
206 BIN_BUF_DBG_IDLE_CHK_PARSING_DATA /* Idle Check parsing data */,
207 BIN_BUF_DBG_ATTN_BLOCKS /* Attention blocks */,
208 BIN_BUF_DBG_ATTN_REGS /* Attention registers */,
209 BIN_BUF_DBG_ATTN_INDEXES /* Attention indexes */,
210 BIN_BUF_DBG_ATTN_NAME_OFFSETS /* Attention name offsets */,
211 BIN_BUF_DBG_PARSING_STRINGS /* Debug Tools parsing strings */,
212 MAX_BIN_DBG_BUFFER_TYPE
217 * Attention bit mapping
219 struct dbg_attn_bit_mapping {
221 /* The index of an attention in the blocks attentions list
222 * (if is_unused_idx_cnt=0), or a number of consecutive unused attention bits
223 * (if is_unused_idx_cnt=1)
225 #define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF
226 #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0
227 /* if set, the val field indicates the number of consecutive unused attention
230 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1
231 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15
236 * Attention block per-type data
238 struct dbg_attn_block_type_data {
239 /* Offset of this block attention names in the debug attention name offsets
244 u8 num_regs /* Number of attention registers in this block */;
246 /* Offset of this blocks attention registers in the attention registers array
247 * (in dbg_attn_reg units)
255 struct dbg_attn_block {
256 /* attention block per-type data. Count must match the number of elements in
259 struct dbg_attn_block_type_data per_type_data[2];
264 * Attention register result
266 struct dbg_attn_reg_result {
268 /* STS attention register GRC address (in dwords) */
269 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF
270 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0
271 /* Number of attention indexes in this register */
272 #define DBG_ATTN_REG_RESULT_NUM_ATTN_IDX_MASK 0xFF
273 #define DBG_ATTN_REG_RESULT_NUM_ATTN_IDX_SHIFT 24
274 /* Offset of this registers block attention indexes (values in the range
275 * 0..number of block attentions)
277 __le16 attn_idx_offset;
279 __le32 sts_val /* Value read from the STS attention register */;
280 __le32 mask_val /* Value read from the MASK attention register */;
284 * Attention block result
286 struct dbg_attn_block_result {
287 u8 block_id /* Registers block ID */;
289 /* Value from dbg_attn_type enum */
290 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3
291 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0
292 /* Number of registers in the blok in which at least one attention bit is set */
293 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F
294 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2
295 /* Offset of this registers block attention names in the attention name offsets
299 /* result data for each register in the block in which at least one attention
302 struct dbg_attn_reg_result reg_results[15];
310 struct dbg_mode_hdr {
312 /* indicates if a mode expression should be evaluated (0/1) */
313 #define DBG_MODE_HDR_EVAL_MODE_MASK 0x1
314 #define DBG_MODE_HDR_EVAL_MODE_SHIFT 0
315 /* offset (in bytes) in modes expression buffer. valid only if eval_mode is
318 #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF
319 #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1
325 struct dbg_attn_reg {
326 struct dbg_mode_hdr mode /* Mode header */;
327 /* Offset of this registers block attention indexes (values in the range
328 * 0..number of block attentions)
330 __le16 attn_idx_offset;
332 /* STS attention register GRC address (in dwords) */
333 #define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF
334 #define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0
335 /* Number of attention indexes in this register */
336 #define DBG_ATTN_REG_NUM_ATTN_IDX_MASK 0xFF
337 #define DBG_ATTN_REG_NUM_ATTN_IDX_SHIFT 24
338 /* STS_CLR attention register GRC address (in dwords) */
339 __le32 sts_clr_address;
340 /* MASK attention register GRC address (in dwords) */
357 * condition header for registers dump
359 struct dbg_dump_cond_hdr {
360 struct dbg_mode_hdr mode /* Mode header */;
361 u8 block_id /* block ID */;
362 u8 data_size /* size in dwords of the data following this header */;
367 * memory data for registers dump
369 struct dbg_dump_mem {
371 /* register address (in dwords) */
372 #define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF
373 #define DBG_DUMP_MEM_ADDRESS_SHIFT 0
374 #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF /* memory group ID */
375 #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24
377 /* register size (in dwords) */
378 #define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF
379 #define DBG_DUMP_MEM_LENGTH_SHIFT 0
380 #define DBG_DUMP_MEM_RESERVED_MASK 0xFF
381 #define DBG_DUMP_MEM_RESERVED_SHIFT 24
386 * register data for registers dump
388 struct dbg_dump_reg {
390 /* register address (in dwords) */
391 #define DBG_DUMP_REG_ADDRESS_MASK 0xFFFFFF
392 #define DBG_DUMP_REG_ADDRESS_SHIFT 0
393 #define DBG_DUMP_REG_LENGTH_MASK 0xFF /* register size (in dwords) */
394 #define DBG_DUMP_REG_LENGTH_SHIFT 24
399 * split header for registers dump
401 struct dbg_dump_split_hdr {
403 /* size in dwords of the data following this header */
404 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF
405 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0
406 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF /* split type ID */
407 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24
412 * condition header for idle check
414 struct dbg_idle_chk_cond_hdr {
415 struct dbg_mode_hdr mode /* Mode header */;
416 /* size in dwords of the data following this header */
422 * Idle Check condition register
424 struct dbg_idle_chk_cond_reg {
426 /* Register GRC address (in dwords) */
427 #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0xFFFFFF
428 #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0
429 /* value from block_id enum */
430 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF
431 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24
432 __le16 num_entries /* number of registers entries to check */;
433 u8 entry_size /* size of registers entry (in dwords) */;
434 u8 start_entry /* index of the first entry to check */;
439 * Idle Check info register
441 struct dbg_idle_chk_info_reg {
443 /* Register GRC address (in dwords) */
444 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0xFFFFFF
445 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0
446 /* value from block_id enum */
447 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF
448 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24
449 __le16 size /* register size in dwords */;
450 struct dbg_mode_hdr mode /* Mode header */;
455 * Idle Check register
457 union dbg_idle_chk_reg {
458 struct dbg_idle_chk_cond_reg cond_reg /* condition register */;
459 struct dbg_idle_chk_info_reg info_reg /* info register */;
464 * Idle Check result header
466 struct dbg_idle_chk_result_hdr {
467 __le16 rule_id /* Failing rule index */;
468 __le16 mem_entry_id /* Failing memory entry index */;
469 u8 num_dumped_cond_regs /* number of dumped condition registers */;
470 u8 num_dumped_info_regs /* number of dumped condition registers */;
471 u8 severity /* from dbg_idle_chk_severity_types enum */;
477 * Idle Check result register header
479 struct dbg_idle_chk_result_reg_hdr {
481 /* indicates if this register is a memory */
482 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1
483 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0
484 /* register index within the failing rule */
485 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F
486 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1
487 u8 start_entry /* index of the first checked entry */;
488 __le16 size /* register size in dwords */;
495 struct dbg_idle_chk_rule {
496 __le16 rule_id /* Idle Check rule ID */;
497 u8 severity /* value from dbg_idle_chk_severity_types enum */;
498 u8 cond_id /* Condition ID */;
499 u8 num_cond_regs /* number of condition registers */;
500 u8 num_info_regs /* number of info registers */;
501 u8 num_imms /* number of immediates in the condition */;
503 /* offset of this rules registers in the idle check register array
504 * (in dbg_idle_chk_reg units)
507 /* offset of this rules immediate values in the immediate values array
515 * Idle Check rule parsing data
517 struct dbg_idle_chk_rule_parsing_data {
519 /* indicates if this register has a FW message */
520 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1
521 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0
522 /* Offset of this rules strings in the debug strings array (in bytes) */
523 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF
524 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1
529 * idle check severity types
531 enum dbg_idle_chk_severity_types {
532 /* idle check failure should cause an error */
533 IDLE_CHK_SEVERITY_ERROR,
534 /* idle check failure should cause an error only if theres no traffic */
535 IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC,
536 /* idle check failure should cause a warning */
537 IDLE_CHK_SEVERITY_WARNING,
538 MAX_DBG_IDLE_CHK_SEVERITY_TYPES
544 * Debug Bus block data
546 struct dbg_bus_block_data {
547 /* Indicates if the block is enabled for recording (0/1) */
549 u8 hw_id /* HW ID associated with the block */;
550 u8 line_num /* Debug line number to select */;
551 u8 right_shift /* Number of units to right the debug data (0-3) */;
552 u8 cycle_en /* 4-bit value: bit i set -> unit i is enabled. */;
553 /* 4-bit value: bit i set -> unit i is forced valid. */
555 /* 4-bit value: bit i set -> unit i frame bit is forced. */
564 enum dbg_bus_clients {
575 DBG_BUS_CLIENT_OTHER_ENGINE,
576 DBG_BUS_CLIENT_TIMESTAMP,
589 * Debug Bus constraint operation types
591 enum dbg_bus_constraint_ops {
592 DBG_BUS_CONSTRAINT_OP_EQ /* equal */,
593 DBG_BUS_CONSTRAINT_OP_NE /* not equal */,
594 DBG_BUS_CONSTRAINT_OP_LT /* less than */,
595 DBG_BUS_CONSTRAINT_OP_LTC /* less than (cyclic) */,
596 DBG_BUS_CONSTRAINT_OP_LE /* less than or equal */,
597 DBG_BUS_CONSTRAINT_OP_LEC /* less than or equal (cyclic) */,
598 DBG_BUS_CONSTRAINT_OP_GT /* greater than */,
599 DBG_BUS_CONSTRAINT_OP_GTC /* greater than (cyclic) */,
600 DBG_BUS_CONSTRAINT_OP_GE /* greater than or equal */,
601 DBG_BUS_CONSTRAINT_OP_GEC /* greater than or equal (cyclic) */,
602 MAX_DBG_BUS_CONSTRAINT_OPS
607 * Debug Bus memory address
609 struct dbg_bus_mem_addr {
615 * Debug Bus PCI buffer data
617 struct dbg_bus_pci_buf_data {
618 struct dbg_bus_mem_addr phys_addr /* PCI buffer physical address */;
619 struct dbg_bus_mem_addr virt_addr /* PCI buffer virtual address */;
620 __le32 size /* PCI buffer size in bytes */;
624 * Debug Bus Storm EID range filter params
626 struct dbg_bus_storm_eid_range_params {
627 u8 min /* Minimal event ID to filter on */;
628 u8 max /* Maximal event ID to filter on */;
632 * Debug Bus Storm EID mask filter params
634 struct dbg_bus_storm_eid_mask_params {
635 u8 val /* Event ID value */;
636 u8 mask /* Event ID mask. 1s in the mask = dont care bits. */;
640 * Debug Bus Storm EID filter params
642 union dbg_bus_storm_eid_params {
643 /* EID range filter params */
644 struct dbg_bus_storm_eid_range_params range;
645 /* EID mask filter params */
646 struct dbg_bus_storm_eid_mask_params mask;
650 * Debug Bus Storm data
652 struct dbg_bus_storm_data {
653 /* Indicates if the Storm is enabled for fast debug recording (0/1) */
655 /* Fast debug Storm mode, valid only if fast_enabled is set */
657 /* Indicates if the Storm is enabled for slow debug recording (0/1) */
659 /* Slow debug Storm mode, valid only if slow_enabled is set */
661 u8 hw_id /* HW ID associated with the Storm */;
662 u8 eid_filter_en /* Indicates if EID filtering is performed (0/1) */;
663 /* 1 = EID range filter, 0 = EID mask filter. Valid only if eid_filter_en is
666 u8 eid_range_not_mask;
667 u8 cid_filter_en /* Indicates if CID filtering is performed (0/1) */;
668 /* EID filter params to filter on. Valid only if eid_filter_en is set. */
669 union dbg_bus_storm_eid_params eid_filter_params;
671 /* CID to filter on. Valid only if cid_filter_en is set. */
678 struct dbg_bus_data {
679 __le32 app_version /* The tools version number of the application */;
680 u8 state /* The current debug bus state */;
681 u8 hw_dwords /* HW dwords per cycle */;
682 u8 next_hw_id /* Next HW ID to be associated with an input */;
683 u8 num_enabled_blocks /* Number of blocks enabled for recording */;
684 u8 num_enabled_storms /* Number of Storms enabled for recording */;
685 u8 target /* Output target */;
686 u8 next_trigger_state /* ID of next trigger state to be added */;
687 /* ID of next filter/trigger constraint to be added */
688 u8 next_constraint_id;
689 u8 one_shot_en /* Indicates if one-shot mode is enabled (0/1) */;
690 u8 grc_input_en /* Indicates if GRC recording is enabled (0/1) */;
691 /* Indicates if timestamp recording is enabled (0/1) */
692 u8 timestamp_input_en;
693 u8 filter_en /* Indicates if the recording filter is enabled (0/1) */;
694 /* Indicates if the recording trigger is enabled (0/1) */
696 /* If true, the next added constraint belong to the filter. Otherwise,
697 * it belongs to the last added trigger state. Valid only if either filter or
698 * triggers are enabled.
701 /* Indicates if the recording filter should be applied before the trigger.
702 * Valid only if both filter and trigger are enabled (0/1)
704 u8 filter_pre_trigger;
705 /* Indicates if the recording filter should be applied after the trigger.
706 * Valid only if both filter and trigger are enabled (0/1)
708 u8 filter_post_trigger;
709 /* If true, all inputs are associated with HW ID 0. Otherwise, each input is
710 * assigned a different HW ID (0/1)
713 /* Indicates if the other engine sends it NW recording to this engine (0/1) */
714 u8 rcv_from_other_engine;
715 /* Debug Bus PCI buffer data. Valid only when the target is
716 * DBG_BUS_TARGET_ID_PCI.
718 struct dbg_bus_pci_buf_data pci_buf;
720 /* Debug Bus data for each block */
721 struct dbg_bus_block_data blocks[88];
722 /* Debug Bus data for each block */
723 struct dbg_bus_storm_data storms[6];
728 * Debug bus filter types
730 enum dbg_bus_filter_types {
731 DBG_BUS_FILTER_TYPE_OFF /* filter always off */,
732 DBG_BUS_FILTER_TYPE_PRE /* filter before trigger only */,
733 DBG_BUS_FILTER_TYPE_POST /* filter after trigger only */,
734 DBG_BUS_FILTER_TYPE_ON /* filter always on */,
735 MAX_DBG_BUS_FILTER_TYPES
740 * Debug bus frame modes
742 enum dbg_bus_frame_modes {
743 DBG_BUS_FRAME_MODE_0HW_4ST = 0 /* 0 HW dwords, 4 Storm dwords */,
744 DBG_BUS_FRAME_MODE_4HW_0ST = 3 /* 4 HW dwords, 0 Storm dwords */,
745 DBG_BUS_FRAME_MODE_8HW_0ST = 4 /* 8 HW dwords, 0 Storm dwords */,
746 MAX_DBG_BUS_FRAME_MODES
751 * Debug bus input types
753 enum dbg_bus_input_types {
754 DBG_BUS_INPUT_TYPE_STORM,
755 DBG_BUS_INPUT_TYPE_BLOCK,
756 MAX_DBG_BUS_INPUT_TYPES
762 * Debug bus other engine mode
764 enum dbg_bus_other_engine_modes {
765 DBG_BUS_OTHER_ENGINE_MODE_NONE,
766 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX,
767 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX,
768 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX,
769 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX,
770 MAX_DBG_BUS_OTHER_ENGINE_MODES
776 * Debug bus post-trigger recording types
778 enum dbg_bus_post_trigger_types {
779 DBG_BUS_POST_TRIGGER_RECORD /* start recording after trigger */,
780 DBG_BUS_POST_TRIGGER_DROP /* drop data after trigger */,
781 MAX_DBG_BUS_POST_TRIGGER_TYPES
786 * Debug bus pre-trigger recording types
788 enum dbg_bus_pre_trigger_types {
789 DBG_BUS_PRE_TRIGGER_START_FROM_ZERO /* start recording from time 0 */,
790 /* start recording some chunks before trigger */
791 DBG_BUS_PRE_TRIGGER_NUM_CHUNKS,
792 DBG_BUS_PRE_TRIGGER_DROP /* drop data before trigger */,
793 MAX_DBG_BUS_PRE_TRIGGER_TYPES
798 * Debug bus SEMI frame modes
800 enum dbg_bus_semi_frame_modes {
801 /* 0 slow dwords, 4 fast dwords */
802 DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST = 0,
803 /* 4 slow dwords, 0 fast dwords */
804 DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST = 3,
805 MAX_DBG_BUS_SEMI_FRAME_MODES
812 enum dbg_bus_states {
813 DBG_BUS_STATE_IDLE /* debug bus idle state (not recording) */,
814 /* debug bus is ready for configuration and recording */
816 DBG_BUS_STATE_RECORDING /* debug bus is currently recording */,
817 DBG_BUS_STATE_STOPPED /* debug bus recording has stopped */,
827 * Debug Bus Storm modes
829 enum dbg_bus_storm_modes {
830 DBG_BUS_STORM_MODE_PRINTF /* store data (fast debug) */,
831 DBG_BUS_STORM_MODE_PRAM_ADDR /* pram address (fast debug) */,
832 DBG_BUS_STORM_MODE_DRA_RW /* DRA read/write data (fast debug) */,
833 DBG_BUS_STORM_MODE_DRA_W /* DRA write data (fast debug) */,
834 DBG_BUS_STORM_MODE_LD_ST_ADDR /* load/store address (fast debug) */,
835 DBG_BUS_STORM_MODE_DRA_FSM /* DRA state machines (fast debug) */,
836 DBG_BUS_STORM_MODE_RH /* recording handlers (fast debug) */,
837 DBG_BUS_STORM_MODE_FOC /* FOC: FIN + DRA Rd (slow debug) */,
838 DBG_BUS_STORM_MODE_EXT_STORE /* FOC: External Store (slow) */,
839 MAX_DBG_BUS_STORM_MODES
844 * Debug bus target IDs
846 enum dbg_bus_targets {
847 /* records debug bus to DBG block internal buffer */
848 DBG_BUS_TARGET_ID_INT_BUF,
849 DBG_BUS_TARGET_ID_NIG /* records debug bus to the NW */,
850 DBG_BUS_TARGET_ID_PCI /* records debug bus to a PCI buffer */,
858 struct dbg_grc_data {
859 /* Indicates if the GRC parameters were initialized */
860 u8 params_initialized;
863 /* Value of each GRC parameter. Array size must match enum dbg_grc_params. */
864 __le32 param_val[48];
871 enum dbg_grc_params {
872 DBG_GRC_PARAM_DUMP_TSTORM /* dump Tstorm memories (0/1) */,
873 DBG_GRC_PARAM_DUMP_MSTORM /* dump Mstorm memories (0/1) */,
874 DBG_GRC_PARAM_DUMP_USTORM /* dump Ustorm memories (0/1) */,
875 DBG_GRC_PARAM_DUMP_XSTORM /* dump Xstorm memories (0/1) */,
876 DBG_GRC_PARAM_DUMP_YSTORM /* dump Ystorm memories (0/1) */,
877 DBG_GRC_PARAM_DUMP_PSTORM /* dump Pstorm memories (0/1) */,
878 DBG_GRC_PARAM_DUMP_REGS /* dump non-memory registers (0/1) */,
879 DBG_GRC_PARAM_DUMP_RAM /* dump Storm internal RAMs (0/1) */,
880 DBG_GRC_PARAM_DUMP_PBUF /* dump Storm passive buffer (0/1) */,
881 DBG_GRC_PARAM_DUMP_IOR /* dump Storm IORs (0/1) */,
882 DBG_GRC_PARAM_DUMP_VFC /* dump VFC memories (0/1) */,
883 DBG_GRC_PARAM_DUMP_CM_CTX /* dump CM contexts (0/1) */,
884 DBG_GRC_PARAM_DUMP_PXP /* dump PXP memories (0/1) */,
885 DBG_GRC_PARAM_DUMP_RSS /* dump RSS memories (0/1) */,
886 DBG_GRC_PARAM_DUMP_CAU /* dump CAU memories (0/1) */,
887 DBG_GRC_PARAM_DUMP_QM /* dump QM memories (0/1) */,
888 DBG_GRC_PARAM_DUMP_MCP /* dump MCP memories (0/1) */,
889 DBG_GRC_PARAM_RESERVED /* reserved */,
890 DBG_GRC_PARAM_DUMP_CFC /* dump CFC memories (0/1) */,
891 DBG_GRC_PARAM_DUMP_IGU /* dump IGU memories (0/1) */,
892 DBG_GRC_PARAM_DUMP_BRB /* dump BRB memories (0/1) */,
893 DBG_GRC_PARAM_DUMP_BTB /* dump BTB memories (0/1) */,
894 DBG_GRC_PARAM_DUMP_BMB /* dump BMB memories (0/1) */,
895 DBG_GRC_PARAM_DUMP_NIG /* dump NIG memories (0/1) */,
896 DBG_GRC_PARAM_DUMP_MULD /* dump MULD memories (0/1) */,
897 DBG_GRC_PARAM_DUMP_PRS /* dump PRS memories (0/1) */,
898 DBG_GRC_PARAM_DUMP_DMAE /* dump PRS memories (0/1) */,
899 DBG_GRC_PARAM_DUMP_TM /* dump TM (timers) memories (0/1) */,
900 DBG_GRC_PARAM_DUMP_SDM /* dump SDM memories (0/1) */,
901 DBG_GRC_PARAM_DUMP_DIF /* dump DIF memories (0/1) */,
902 DBG_GRC_PARAM_DUMP_STATIC /* dump static debug data (0/1) */,
903 DBG_GRC_PARAM_UNSTALL /* un-stall Storms after dump (0/1) */,
904 DBG_GRC_PARAM_NUM_LCIDS /* number of LCIDs (0..320) */,
905 DBG_GRC_PARAM_NUM_LTIDS /* number of LTIDs (0..320) */,
906 /* preset: exclude all memories from dump (1 only) */
907 DBG_GRC_PARAM_EXCLUDE_ALL,
908 /* preset: include memories for crash dump (1 only) */
910 /* perform dump only if MFW is responding (0/1) */
911 DBG_GRC_PARAM_PARITY_SAFE,
912 DBG_GRC_PARAM_DUMP_CM /* dump CM memories (0/1) */,
913 DBG_GRC_PARAM_DUMP_PHY /* dump PHY memories (0/1) */,
914 DBG_GRC_PARAM_NO_MCP /* dont perform MCP commands (0/1) */,
915 DBG_GRC_PARAM_NO_FW_VER /* dont read FW/MFW version (0/1) */,
921 * Debug reset registers
923 enum dbg_reset_regs {
924 DBG_RESET_REG_MISCS_PL_UA,
925 DBG_RESET_REG_MISCS_PL_HV,
926 DBG_RESET_REG_MISCS_PL_HV_2,
927 DBG_RESET_REG_MISC_PL_UA,
928 DBG_RESET_REG_MISC_PL_HV,
929 DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
930 DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
931 DBG_RESET_REG_MISC_PL_PDA_VAUX,
941 DBG_STATUS_APP_VERSION_NOT_SET,
942 DBG_STATUS_UNSUPPORTED_APP_VERSION,
943 DBG_STATUS_DBG_BLOCK_NOT_RESET,
944 DBG_STATUS_INVALID_ARGS,
945 DBG_STATUS_OUTPUT_ALREADY_SET,
946 DBG_STATUS_INVALID_PCI_BUF_SIZE,
947 DBG_STATUS_PCI_BUF_ALLOC_FAILED,
948 DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
949 DBG_STATUS_TOO_MANY_INPUTS,
950 DBG_STATUS_INPUT_OVERLAP,
951 DBG_STATUS_HW_ONLY_RECORDING,
952 DBG_STATUS_STORM_ALREADY_ENABLED,
953 DBG_STATUS_STORM_NOT_ENABLED,
954 DBG_STATUS_BLOCK_ALREADY_ENABLED,
955 DBG_STATUS_BLOCK_NOT_ENABLED,
956 DBG_STATUS_NO_INPUT_ENABLED,
957 DBG_STATUS_NO_FILTER_TRIGGER_64B,
958 DBG_STATUS_FILTER_ALREADY_ENABLED,
959 DBG_STATUS_TRIGGER_ALREADY_ENABLED,
960 DBG_STATUS_TRIGGER_NOT_ENABLED,
961 DBG_STATUS_CANT_ADD_CONSTRAINT,
962 DBG_STATUS_TOO_MANY_TRIGGER_STATES,
963 DBG_STATUS_TOO_MANY_CONSTRAINTS,
964 DBG_STATUS_RECORDING_NOT_STARTED,
965 DBG_STATUS_DATA_DIDNT_TRIGGER,
966 DBG_STATUS_NO_DATA_RECORDED,
967 DBG_STATUS_DUMP_BUF_TOO_SMALL,
968 DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,
969 DBG_STATUS_UNKNOWN_CHIP,
970 DBG_STATUS_VIRT_MEM_ALLOC_FAILED,
971 DBG_STATUS_BLOCK_IN_RESET,
972 DBG_STATUS_INVALID_TRACE_SIGNATURE,
973 DBG_STATUS_INVALID_NVRAM_BUNDLE,
974 DBG_STATUS_NVRAM_GET_IMAGE_FAILED,
975 DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,
976 DBG_STATUS_NVRAM_READ_FAILED,
977 DBG_STATUS_IDLE_CHK_PARSE_FAILED,
978 DBG_STATUS_MCP_TRACE_BAD_DATA,
979 DBG_STATUS_MCP_TRACE_NO_META,
980 DBG_STATUS_MCP_COULD_NOT_HALT,
981 DBG_STATUS_MCP_COULD_NOT_RESUME,
982 DBG_STATUS_DMAE_FAILED,
983 DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
984 DBG_STATUS_IGU_FIFO_BAD_DATA,
985 DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
986 DBG_STATUS_FW_ASSERTS_PARSE_FAILED,
987 DBG_STATUS_REG_FIFO_BAD_DATA,
988 DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
989 DBG_STATUS_DBG_ARRAY_NOT_SET,
990 DBG_STATUS_MULTI_BLOCKS_WITH_FILTER,
1012 struct idle_chk_data {
1013 __le32 buf_size /* Idle check buffer size in dwords */;
1014 /* Indicates if the idle check buffer size was set (0/1) */
1021 * Debug Tools data (per HW function)
1023 struct dbg_tools_data {
1024 struct dbg_grc_data grc /* GRC Dump data */;
1025 struct dbg_bus_data bus /* Debug Bus data */;
1026 struct idle_chk_data idle_chk /* Idle Check data */;
1027 u8 mode_enable[40] /* Indicates if a mode is enabled (0/1) */;
1028 /* Indicates if a block is in reset state (0/1) */
1029 u8 block_in_reset[88];
1030 u8 chip_id /* Chip ID (from enum chip_ids) */;
1031 u8 platform_id /* Platform ID (from enum platform_ids) */;
1032 u8 initialized /* Indicates if the data was initialized */;
1037 #endif /* __ECORE_HSI_DEBUG_TOOLS__ */