2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #ifndef __ECORE_HSI_DEBUG_TOOLS__
10 #define __ECORE_HSI_DEBUG_TOOLS__
11 /****************************************/
12 /* Debug Tools HSI constants and macros */
13 /****************************************/
17 GRCBASE_GRC = 0x50000,
18 GRCBASE_MISCS = 0x9000,
19 GRCBASE_MISC = 0x8000,
21 GRCBASE_PGLUE_B = 0x2a8000,
22 GRCBASE_CNIG = 0x218000,
23 GRCBASE_CPMU = 0x30000,
24 GRCBASE_NCSI = 0x40000,
25 GRCBASE_OPTE = 0x53000,
26 GRCBASE_BMB = 0x540000,
27 GRCBASE_PCIE = 0x54000,
28 GRCBASE_MCP = 0xe00000,
29 GRCBASE_MCP2 = 0x52000,
30 GRCBASE_PSWHST = 0x2a0000,
31 GRCBASE_PSWHST2 = 0x29e000,
32 GRCBASE_PSWRD = 0x29c000,
33 GRCBASE_PSWRD2 = 0x29d000,
34 GRCBASE_PSWWR = 0x29a000,
35 GRCBASE_PSWWR2 = 0x29b000,
36 GRCBASE_PSWRQ = 0x280000,
37 GRCBASE_PSWRQ2 = 0x240000,
39 GRCBASE_DMAE = 0xc000,
40 GRCBASE_PTU = 0x560000,
41 GRCBASE_TCM = 0x1180000,
42 GRCBASE_MCM = 0x1200000,
43 GRCBASE_UCM = 0x1280000,
44 GRCBASE_XCM = 0x1000000,
45 GRCBASE_YCM = 0x1080000,
46 GRCBASE_PCM = 0x1100000,
47 GRCBASE_QM = 0x2f0000,
48 GRCBASE_TM = 0x2c0000,
49 GRCBASE_DORQ = 0x100000,
50 GRCBASE_BRB = 0x340000,
51 GRCBASE_SRC = 0x238000,
52 GRCBASE_PRS = 0x1f0000,
53 GRCBASE_TSDM = 0xfb0000,
54 GRCBASE_MSDM = 0xfc0000,
55 GRCBASE_USDM = 0xfd0000,
56 GRCBASE_XSDM = 0xf80000,
57 GRCBASE_YSDM = 0xf90000,
58 GRCBASE_PSDM = 0xfa0000,
59 GRCBASE_TSEM = 0x1700000,
60 GRCBASE_MSEM = 0x1800000,
61 GRCBASE_USEM = 0x1900000,
62 GRCBASE_XSEM = 0x1400000,
63 GRCBASE_YSEM = 0x1500000,
64 GRCBASE_PSEM = 0x1600000,
65 GRCBASE_RSS = 0x238800,
66 GRCBASE_TMLD = 0x4d0000,
67 GRCBASE_MULD = 0x4e0000,
68 GRCBASE_YULD = 0x4c8000,
69 GRCBASE_XYLD = 0x4c0000,
70 GRCBASE_PRM = 0x230000,
71 GRCBASE_PBF_PB1 = 0xda0000,
72 GRCBASE_PBF_PB2 = 0xda4000,
73 GRCBASE_RPB = 0x23c000,
74 GRCBASE_BTB = 0xdb0000,
75 GRCBASE_PBF = 0xd80000,
76 GRCBASE_RDIF = 0x300000,
77 GRCBASE_TDIF = 0x310000,
78 GRCBASE_CDU = 0x580000,
79 GRCBASE_CCFC = 0x2e0000,
80 GRCBASE_TCFC = 0x2d0000,
81 GRCBASE_IGU = 0x180000,
82 GRCBASE_CAU = 0x1c0000,
83 GRCBASE_UMAC = 0x51000,
84 GRCBASE_XMAC = 0x210000,
85 GRCBASE_DBG = 0x10000,
86 GRCBASE_NIG = 0x500000,
87 GRCBASE_WOL = 0x600000,
88 GRCBASE_BMBN = 0x610000,
89 GRCBASE_IPC = 0x20000,
90 GRCBASE_NWM = 0x800000,
91 GRCBASE_NWS = 0x700000,
92 GRCBASE_MS = 0x6a0000,
93 GRCBASE_PHY_PCIE = 0x620000,
94 GRCBASE_LED = 0x6b8000,
95 GRCBASE_MISC_AEU = 0x8000,
96 GRCBASE_BAR0_MAP = 0x1c00000,
187 * binary debug buffer types
189 enum bin_dbg_buffer_type {
190 BIN_BUF_DBG_MODE_TREE /* init modes tree */,
191 BIN_BUF_DBG_DUMP_REG /* GRC Dump registers */,
192 BIN_BUF_DBG_DUMP_MEM /* GRC Dump memories */,
193 BIN_BUF_DBG_IDLE_CHK_REGS /* Idle Check registers */,
194 BIN_BUF_DBG_IDLE_CHK_IMMS /* Idle Check immediates */,
195 BIN_BUF_DBG_IDLE_CHK_RULES /* Idle Check rules */,
196 BIN_BUF_DBG_IDLE_CHK_PARSING_DATA /* Idle Check parsing data */,
197 BIN_BUF_DBG_ATTN_BLOCKS /* Attention blocks */,
198 BIN_BUF_DBG_ATTN_REGS /* Attention registers */,
199 BIN_BUF_DBG_ATTN_INDEXES /* Attention indexes */,
200 BIN_BUF_DBG_ATTN_NAME_OFFSETS /* Attention name offsets */,
201 BIN_BUF_DBG_PARSING_STRINGS /* Debug Tools parsing strings */,
202 MAX_BIN_DBG_BUFFER_TYPE
207 * Attention bit mapping
209 struct dbg_attn_bit_mapping {
211 /* The index of an attention in the blocks attentions list
212 * (if is_unused_idx_cnt=0), or a number of consecutive unused attention bits
213 * (if is_unused_idx_cnt=1)
215 #define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF
216 #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0
217 /* if set, the val field indicates the number of consecutive unused attention
220 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1
221 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15
226 * Attention block per-type data
228 struct dbg_attn_block_type_data {
229 /* Offset of this block attention names in the debug attention name offsets
234 u8 num_regs /* Number of attention registers in this block */;
236 /* Offset of this blocks attention registers in the attention registers array
237 * (in dbg_attn_reg units)
245 struct dbg_attn_block {
246 /* attention block per-type data. Count must match the number of elements in
249 struct dbg_attn_block_type_data per_type_data[2];
254 * Attention register result
256 struct dbg_attn_reg_result {
258 /* STS attention register GRC address (in dwords) */
259 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF
260 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0
261 /* Number of attention indexes in this register */
262 #define DBG_ATTN_REG_RESULT_NUM_ATTN_IDX_MASK 0xFF
263 #define DBG_ATTN_REG_RESULT_NUM_ATTN_IDX_SHIFT 24
264 /* Offset of this registers block attention indexes (values in the range
265 * 0..number of block attentions)
267 __le16 attn_idx_offset;
269 __le32 sts_val /* Value read from the STS attention register */;
270 __le32 mask_val /* Value read from the MASK attention register */;
274 * Attention block result
276 struct dbg_attn_block_result {
277 u8 block_id /* Registers block ID */;
279 /* Value from dbg_attn_type enum */
280 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3
281 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0
282 /* Number of registers in the blok in which at least one attention bit is set */
283 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F
284 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2
285 /* Offset of this registers block attention names in the attention name offsets
289 /* result data for each register in the block in which at least one attention
292 struct dbg_attn_reg_result reg_results[15];
300 struct dbg_mode_hdr {
302 /* indicates if a mode expression should be evaluated (0/1) */
303 #define DBG_MODE_HDR_EVAL_MODE_MASK 0x1
304 #define DBG_MODE_HDR_EVAL_MODE_SHIFT 0
305 /* offset (in bytes) in modes expression buffer. valid only if eval_mode is
308 #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF
309 #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1
315 struct dbg_attn_reg {
316 struct dbg_mode_hdr mode /* Mode header */;
317 /* Offset of this registers block attention indexes (values in the range
318 * 0..number of block attentions)
320 __le16 attn_idx_offset;
322 /* STS attention register GRC address (in dwords) */
323 #define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF
324 #define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0
325 /* Number of attention indexes in this register */
326 #define DBG_ATTN_REG_NUM_ATTN_IDX_MASK 0xFF
327 #define DBG_ATTN_REG_NUM_ATTN_IDX_SHIFT 24
328 /* STS_CLR attention register GRC address (in dwords) */
329 __le32 sts_clr_address;
330 /* MASK attention register GRC address (in dwords) */
347 * condition header for registers dump
349 struct dbg_dump_cond_hdr {
350 struct dbg_mode_hdr mode /* Mode header */;
351 u8 block_id /* block ID */;
352 u8 data_size /* size in dwords of the data following this header */;
357 * memory data for registers dump
359 struct dbg_dump_mem {
361 /* register address (in dwords) */
362 #define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF
363 #define DBG_DUMP_MEM_ADDRESS_SHIFT 0
364 #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF /* memory group ID */
365 #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24
367 /* register size (in dwords) */
368 #define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF
369 #define DBG_DUMP_MEM_LENGTH_SHIFT 0
370 #define DBG_DUMP_MEM_RESERVED_MASK 0xFF
371 #define DBG_DUMP_MEM_RESERVED_SHIFT 24
376 * register data for registers dump
378 struct dbg_dump_reg {
380 /* register address (in dwords) */
381 #define DBG_DUMP_REG_ADDRESS_MASK 0xFFFFFF
382 #define DBG_DUMP_REG_ADDRESS_SHIFT 0
383 #define DBG_DUMP_REG_LENGTH_MASK 0xFF /* register size (in dwords) */
384 #define DBG_DUMP_REG_LENGTH_SHIFT 24
389 * split header for registers dump
391 struct dbg_dump_split_hdr {
393 /* size in dwords of the data following this header */
394 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF
395 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0
396 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF /* split type ID */
397 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24
402 * condition header for idle check
404 struct dbg_idle_chk_cond_hdr {
405 struct dbg_mode_hdr mode /* Mode header */;
406 /* size in dwords of the data following this header */
412 * Idle Check condition register
414 struct dbg_idle_chk_cond_reg {
416 /* Register GRC address (in dwords) */
417 #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0xFFFFFF
418 #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0
419 /* value from block_id enum */
420 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF
421 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24
422 __le16 num_entries /* number of registers entries to check */;
423 u8 entry_size /* size of registers entry (in dwords) */;
424 u8 start_entry /* index of the first entry to check */;
429 * Idle Check info register
431 struct dbg_idle_chk_info_reg {
433 /* Register GRC address (in dwords) */
434 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0xFFFFFF
435 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0
436 /* value from block_id enum */
437 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF
438 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24
439 __le16 size /* register size in dwords */;
440 struct dbg_mode_hdr mode /* Mode header */;
445 * Idle Check register
447 union dbg_idle_chk_reg {
448 struct dbg_idle_chk_cond_reg cond_reg /* condition register */;
449 struct dbg_idle_chk_info_reg info_reg /* info register */;
454 * Idle Check result header
456 struct dbg_idle_chk_result_hdr {
457 __le16 rule_id /* Failing rule index */;
458 __le16 mem_entry_id /* Failing memory entry index */;
459 u8 num_dumped_cond_regs /* number of dumped condition registers */;
460 u8 num_dumped_info_regs /* number of dumped condition registers */;
461 u8 severity /* from dbg_idle_chk_severity_types enum */;
467 * Idle Check result register header
469 struct dbg_idle_chk_result_reg_hdr {
471 /* indicates if this register is a memory */
472 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1
473 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0
474 /* register index within the failing rule */
475 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F
476 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1
477 u8 start_entry /* index of the first checked entry */;
478 __le16 size /* register size in dwords */;
485 struct dbg_idle_chk_rule {
486 __le16 rule_id /* Idle Check rule ID */;
487 u8 severity /* value from dbg_idle_chk_severity_types enum */;
488 u8 cond_id /* Condition ID */;
489 u8 num_cond_regs /* number of condition registers */;
490 u8 num_info_regs /* number of info registers */;
491 u8 num_imms /* number of immediates in the condition */;
493 /* offset of this rules registers in the idle check register array
494 * (in dbg_idle_chk_reg units)
497 /* offset of this rules immediate values in the immediate values array
505 * Idle Check rule parsing data
507 struct dbg_idle_chk_rule_parsing_data {
509 /* indicates if this register has a FW message */
510 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1
511 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0
512 /* Offset of this rules strings in the debug strings array (in bytes) */
513 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF
514 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1
519 * idle check severity types
521 enum dbg_idle_chk_severity_types {
522 /* idle check failure should cause an error */
523 IDLE_CHK_SEVERITY_ERROR,
524 /* idle check failure should cause an error only if theres no traffic */
525 IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC,
526 /* idle check failure should cause a warning */
527 IDLE_CHK_SEVERITY_WARNING,
528 MAX_DBG_IDLE_CHK_SEVERITY_TYPES
534 * Debug Bus block data
536 struct dbg_bus_block_data {
537 /* Indicates if the block is enabled for recording (0/1) */
539 u8 hw_id /* HW ID associated with the block */;
540 u8 line_num /* Debug line number to select */;
541 u8 right_shift /* Number of units to right the debug data (0-3) */;
542 u8 cycle_en /* 4-bit value: bit i set -> unit i is enabled. */;
543 /* 4-bit value: bit i set -> unit i is forced valid. */
545 /* 4-bit value: bit i set -> unit i frame bit is forced. */
554 enum dbg_bus_clients {
565 DBG_BUS_CLIENT_OTHER_ENGINE,
566 DBG_BUS_CLIENT_TIMESTAMP,
579 * Debug Bus constraint operation types
581 enum dbg_bus_constraint_ops {
582 DBG_BUS_CONSTRAINT_OP_EQ /* equal */,
583 DBG_BUS_CONSTRAINT_OP_NE /* not equal */,
584 DBG_BUS_CONSTRAINT_OP_LT /* less than */,
585 DBG_BUS_CONSTRAINT_OP_LTC /* less than (cyclic) */,
586 DBG_BUS_CONSTRAINT_OP_LE /* less than or equal */,
587 DBG_BUS_CONSTRAINT_OP_LEC /* less than or equal (cyclic) */,
588 DBG_BUS_CONSTRAINT_OP_GT /* greater than */,
589 DBG_BUS_CONSTRAINT_OP_GTC /* greater than (cyclic) */,
590 DBG_BUS_CONSTRAINT_OP_GE /* greater than or equal */,
591 DBG_BUS_CONSTRAINT_OP_GEC /* greater than or equal (cyclic) */,
592 MAX_DBG_BUS_CONSTRAINT_OPS
597 * Debug Bus memory address
599 struct dbg_bus_mem_addr {
605 * Debug Bus PCI buffer data
607 struct dbg_bus_pci_buf_data {
608 struct dbg_bus_mem_addr phys_addr /* PCI buffer physical address */;
609 struct dbg_bus_mem_addr virt_addr /* PCI buffer virtual address */;
610 __le32 size /* PCI buffer size in bytes */;
614 * Debug Bus Storm EID range filter params
616 struct dbg_bus_storm_eid_range_params {
617 u8 min /* Minimal event ID to filter on */;
618 u8 max /* Maximal event ID to filter on */;
622 * Debug Bus Storm EID mask filter params
624 struct dbg_bus_storm_eid_mask_params {
625 u8 val /* Event ID value */;
626 u8 mask /* Event ID mask. 1s in the mask = dont care bits. */;
630 * Debug Bus Storm EID filter params
632 union dbg_bus_storm_eid_params {
633 /* EID range filter params */
634 struct dbg_bus_storm_eid_range_params range;
635 /* EID mask filter params */
636 struct dbg_bus_storm_eid_mask_params mask;
640 * Debug Bus Storm data
642 struct dbg_bus_storm_data {
643 /* Indicates if the Storm is enabled for fast debug recording (0/1) */
645 /* Fast debug Storm mode, valid only if fast_enabled is set */
647 /* Indicates if the Storm is enabled for slow debug recording (0/1) */
649 /* Slow debug Storm mode, valid only if slow_enabled is set */
651 u8 hw_id /* HW ID associated with the Storm */;
652 u8 eid_filter_en /* Indicates if EID filtering is performed (0/1) */;
653 /* 1 = EID range filter, 0 = EID mask filter. Valid only if eid_filter_en is
656 u8 eid_range_not_mask;
657 u8 cid_filter_en /* Indicates if CID filtering is performed (0/1) */;
658 /* EID filter params to filter on. Valid only if eid_filter_en is set. */
659 union dbg_bus_storm_eid_params eid_filter_params;
661 /* CID to filter on. Valid only if cid_filter_en is set. */
668 struct dbg_bus_data {
669 __le32 app_version /* The tools version number of the application */;
670 u8 state /* The current debug bus state */;
671 u8 hw_dwords /* HW dwords per cycle */;
672 u8 next_hw_id /* Next HW ID to be associated with an input */;
673 u8 num_enabled_blocks /* Number of blocks enabled for recording */;
674 u8 num_enabled_storms /* Number of Storms enabled for recording */;
675 u8 target /* Output target */;
676 u8 next_trigger_state /* ID of next trigger state to be added */;
677 /* ID of next filter/trigger constraint to be added */
678 u8 next_constraint_id;
679 u8 one_shot_en /* Indicates if one-shot mode is enabled (0/1) */;
680 u8 grc_input_en /* Indicates if GRC recording is enabled (0/1) */;
681 /* Indicates if timestamp recording is enabled (0/1) */
682 u8 timestamp_input_en;
683 u8 filter_en /* Indicates if the recording filter is enabled (0/1) */;
684 /* Indicates if the recording trigger is enabled (0/1) */
686 /* If true, the next added constraint belong to the filter. Otherwise,
687 * it belongs to the last added trigger state. Valid only if either filter or
688 * triggers are enabled.
691 /* Indicates if the recording filter should be applied before the trigger.
692 * Valid only if both filter and trigger are enabled (0/1)
694 u8 filter_pre_trigger;
695 /* Indicates if the recording filter should be applied after the trigger.
696 * Valid only if both filter and trigger are enabled (0/1)
698 u8 filter_post_trigger;
699 /* If true, all inputs are associated with HW ID 0. Otherwise, each input is
700 * assigned a different HW ID (0/1)
703 /* Indicates if the other engine sends it NW recording to this engine (0/1) */
704 u8 rcv_from_other_engine;
705 /* Debug Bus PCI buffer data. Valid only when the target is
706 * DBG_BUS_TARGET_ID_PCI.
708 struct dbg_bus_pci_buf_data pci_buf;
710 /* Debug Bus data for each block */
711 struct dbg_bus_block_data blocks[80];
712 /* Debug Bus data for each block */
713 struct dbg_bus_storm_data storms[6];
718 * Debug bus filter types
720 enum dbg_bus_filter_types {
721 DBG_BUS_FILTER_TYPE_OFF /* filter always off */,
722 DBG_BUS_FILTER_TYPE_PRE /* filter before trigger only */,
723 DBG_BUS_FILTER_TYPE_POST /* filter after trigger only */,
724 DBG_BUS_FILTER_TYPE_ON /* filter always on */,
725 MAX_DBG_BUS_FILTER_TYPES
730 * Debug bus frame modes
732 enum dbg_bus_frame_modes {
733 DBG_BUS_FRAME_MODE_0HW_4ST = 0 /* 0 HW dwords, 4 Storm dwords */,
734 DBG_BUS_FRAME_MODE_4HW_0ST = 3 /* 4 HW dwords, 0 Storm dwords */,
735 DBG_BUS_FRAME_MODE_8HW_0ST = 4 /* 8 HW dwords, 0 Storm dwords */,
736 MAX_DBG_BUS_FRAME_MODES
741 * Debug bus input types
743 enum dbg_bus_input_types {
744 DBG_BUS_INPUT_TYPE_STORM,
745 DBG_BUS_INPUT_TYPE_BLOCK,
746 MAX_DBG_BUS_INPUT_TYPES
752 * Debug bus other engine mode
754 enum dbg_bus_other_engine_modes {
755 DBG_BUS_OTHER_ENGINE_MODE_NONE,
756 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX,
757 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX,
758 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX,
759 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX,
760 MAX_DBG_BUS_OTHER_ENGINE_MODES
766 * Debug bus post-trigger recording types
768 enum dbg_bus_post_trigger_types {
769 DBG_BUS_POST_TRIGGER_RECORD /* start recording after trigger */,
770 DBG_BUS_POST_TRIGGER_DROP /* drop data after trigger */,
771 MAX_DBG_BUS_POST_TRIGGER_TYPES
776 * Debug bus pre-trigger recording types
778 enum dbg_bus_pre_trigger_types {
779 DBG_BUS_PRE_TRIGGER_START_FROM_ZERO /* start recording from time 0 */,
780 /* start recording some chunks before trigger */
781 DBG_BUS_PRE_TRIGGER_NUM_CHUNKS,
782 DBG_BUS_PRE_TRIGGER_DROP /* drop data before trigger */,
783 MAX_DBG_BUS_PRE_TRIGGER_TYPES
788 * Debug bus SEMI frame modes
790 enum dbg_bus_semi_frame_modes {
791 /* 0 slow dwords, 4 fast dwords */
792 DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST = 0,
793 /* 4 slow dwords, 0 fast dwords */
794 DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST = 3,
795 MAX_DBG_BUS_SEMI_FRAME_MODES
802 enum dbg_bus_states {
803 DBG_BUS_STATE_IDLE /* debug bus idle state (not recording) */,
804 /* debug bus is ready for configuration and recording */
806 DBG_BUS_STATE_RECORDING /* debug bus is currently recording */,
807 DBG_BUS_STATE_STOPPED /* debug bus recording has stopped */,
817 * Debug Bus Storm modes
819 enum dbg_bus_storm_modes {
820 DBG_BUS_STORM_MODE_PRINTF /* store data (fast debug) */,
821 DBG_BUS_STORM_MODE_PRAM_ADDR /* pram address (fast debug) */,
822 DBG_BUS_STORM_MODE_DRA_RW /* DRA read/write data (fast debug) */,
823 DBG_BUS_STORM_MODE_DRA_W /* DRA write data (fast debug) */,
824 DBG_BUS_STORM_MODE_LD_ST_ADDR /* load/store address (fast debug) */,
825 DBG_BUS_STORM_MODE_DRA_FSM /* DRA state machines (fast debug) */,
826 DBG_BUS_STORM_MODE_RH /* recording handlers (fast debug) */,
827 DBG_BUS_STORM_MODE_FOC /* FOC: FIN + DRA Rd (slow debug) */,
828 DBG_BUS_STORM_MODE_EXT_STORE /* FOC: External Store (slow) */,
829 MAX_DBG_BUS_STORM_MODES
834 * Debug bus target IDs
836 enum dbg_bus_targets {
837 /* records debug bus to DBG block internal buffer */
838 DBG_BUS_TARGET_ID_INT_BUF,
839 DBG_BUS_TARGET_ID_NIG /* records debug bus to the NW */,
840 DBG_BUS_TARGET_ID_PCI /* records debug bus to a PCI buffer */,
848 struct dbg_grc_data {
849 /* Value of each GRC parameter. Array size must match enum dbg_grc_params. */
850 __le32 param_val[40];
851 /* Indicates for each GRC parameter if it was set by the user (0/1).
852 * Array size must match the enum dbg_grc_params.
854 u8 param_set_by_user[40];
861 enum dbg_grc_params {
862 DBG_GRC_PARAM_DUMP_TSTORM /* dump Tstorm memories (0/1) */,
863 DBG_GRC_PARAM_DUMP_MSTORM /* dump Mstorm memories (0/1) */,
864 DBG_GRC_PARAM_DUMP_USTORM /* dump Ustorm memories (0/1) */,
865 DBG_GRC_PARAM_DUMP_XSTORM /* dump Xstorm memories (0/1) */,
866 DBG_GRC_PARAM_DUMP_YSTORM /* dump Ystorm memories (0/1) */,
867 DBG_GRC_PARAM_DUMP_PSTORM /* dump Pstorm memories (0/1) */,
868 DBG_GRC_PARAM_DUMP_REGS /* dump non-memory registers (0/1) */,
869 DBG_GRC_PARAM_DUMP_RAM /* dump Storm internal RAMs (0/1) */,
870 DBG_GRC_PARAM_DUMP_PBUF /* dump Storm passive buffer (0/1) */,
871 DBG_GRC_PARAM_DUMP_IOR /* dump Storm IORs (0/1) */,
872 DBG_GRC_PARAM_DUMP_VFC /* dump VFC memories (0/1) */,
873 DBG_GRC_PARAM_DUMP_CM_CTX /* dump CM contexts (0/1) */,
874 DBG_GRC_PARAM_DUMP_PXP /* dump PXP memories (0/1) */,
875 DBG_GRC_PARAM_DUMP_RSS /* dump RSS memories (0/1) */,
876 DBG_GRC_PARAM_DUMP_CAU /* dump CAU memories (0/1) */,
877 DBG_GRC_PARAM_DUMP_QM /* dump QM memories (0/1) */,
878 DBG_GRC_PARAM_DUMP_MCP /* dump MCP memories (0/1) */,
879 DBG_GRC_PARAM_RESERVED /* reserved */,
880 DBG_GRC_PARAM_DUMP_CFC /* dump CFC memories (0/1) */,
881 DBG_GRC_PARAM_DUMP_IGU /* dump IGU memories (0/1) */,
882 DBG_GRC_PARAM_DUMP_BRB /* dump BRB memories (0/1) */,
883 DBG_GRC_PARAM_DUMP_BTB /* dump BTB memories (0/1) */,
884 DBG_GRC_PARAM_DUMP_BMB /* dump BMB memories (0/1) */,
885 DBG_GRC_PARAM_DUMP_NIG /* dump NIG memories (0/1) */,
886 DBG_GRC_PARAM_DUMP_MULD /* dump MULD memories (0/1) */,
887 DBG_GRC_PARAM_DUMP_PRS /* dump PRS memories (0/1) */,
888 DBG_GRC_PARAM_DUMP_DMAE /* dump PRS memories (0/1) */,
889 DBG_GRC_PARAM_DUMP_TM /* dump TM (timers) memories (0/1) */,
890 DBG_GRC_PARAM_DUMP_SDM /* dump SDM memories (0/1) */,
891 DBG_GRC_PARAM_DUMP_DIF /* dump DIF memories (0/1) */,
892 DBG_GRC_PARAM_DUMP_STATIC /* dump static debug data (0/1) */,
893 DBG_GRC_PARAM_UNSTALL /* un-stall Storms after dump (0/1) */,
894 DBG_GRC_PARAM_NUM_LCIDS /* number of LCIDs (0..320) */,
895 DBG_GRC_PARAM_NUM_LTIDS /* number of LTIDs (0..320) */,
896 /* preset: exclude all memories from dump (1 only) */
897 DBG_GRC_PARAM_EXCLUDE_ALL,
898 /* preset: include memories for crash dump (1 only) */
900 /* perform dump only if MFW is responding (0/1) */
901 DBG_GRC_PARAM_PARITY_SAFE,
902 DBG_GRC_PARAM_DUMP_CM /* dump CM memories (0/1) */,
903 DBG_GRC_PARAM_DUMP_PHY /* dump PHY memories (0/1) */,
909 * Debug reset registers
911 enum dbg_reset_regs {
912 DBG_RESET_REG_MISCS_PL_UA,
913 DBG_RESET_REG_MISCS_PL_HV,
914 DBG_RESET_REG_MISCS_PL_HV_2,
915 DBG_RESET_REG_MISC_PL_UA,
916 DBG_RESET_REG_MISC_PL_HV,
917 DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
918 DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
919 DBG_RESET_REG_MISC_PL_PDA_VAUX,
929 DBG_STATUS_APP_VERSION_NOT_SET,
930 DBG_STATUS_UNSUPPORTED_APP_VERSION,
931 DBG_STATUS_DBG_BLOCK_NOT_RESET,
932 DBG_STATUS_INVALID_ARGS,
933 DBG_STATUS_OUTPUT_ALREADY_SET,
934 DBG_STATUS_INVALID_PCI_BUF_SIZE,
935 DBG_STATUS_PCI_BUF_ALLOC_FAILED,
936 DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
937 DBG_STATUS_TOO_MANY_INPUTS,
938 DBG_STATUS_INPUT_OVERLAP,
939 DBG_STATUS_HW_ONLY_RECORDING,
940 DBG_STATUS_STORM_ALREADY_ENABLED,
941 DBG_STATUS_STORM_NOT_ENABLED,
942 DBG_STATUS_BLOCK_ALREADY_ENABLED,
943 DBG_STATUS_BLOCK_NOT_ENABLED,
944 DBG_STATUS_NO_INPUT_ENABLED,
945 DBG_STATUS_NO_FILTER_TRIGGER_64B,
946 DBG_STATUS_FILTER_ALREADY_ENABLED,
947 DBG_STATUS_TRIGGER_ALREADY_ENABLED,
948 DBG_STATUS_TRIGGER_NOT_ENABLED,
949 DBG_STATUS_CANT_ADD_CONSTRAINT,
950 DBG_STATUS_TOO_MANY_TRIGGER_STATES,
951 DBG_STATUS_TOO_MANY_CONSTRAINTS,
952 DBG_STATUS_RECORDING_NOT_STARTED,
953 DBG_STATUS_DATA_DIDNT_TRIGGER,
954 DBG_STATUS_NO_DATA_RECORDED,
955 DBG_STATUS_DUMP_BUF_TOO_SMALL,
956 DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,
957 DBG_STATUS_UNKNOWN_CHIP,
958 DBG_STATUS_VIRT_MEM_ALLOC_FAILED,
959 DBG_STATUS_BLOCK_IN_RESET,
960 DBG_STATUS_INVALID_TRACE_SIGNATURE,
961 DBG_STATUS_INVALID_NVRAM_BUNDLE,
962 DBG_STATUS_NVRAM_GET_IMAGE_FAILED,
963 DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,
964 DBG_STATUS_NVRAM_READ_FAILED,
965 DBG_STATUS_IDLE_CHK_PARSE_FAILED,
966 DBG_STATUS_MCP_TRACE_BAD_DATA,
967 DBG_STATUS_MCP_TRACE_NO_META,
968 DBG_STATUS_MCP_COULD_NOT_HALT,
969 DBG_STATUS_MCP_COULD_NOT_RESUME,
970 DBG_STATUS_DMAE_FAILED,
971 DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
972 DBG_STATUS_IGU_FIFO_BAD_DATA,
973 DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
974 DBG_STATUS_FW_ASSERTS_PARSE_FAILED,
975 DBG_STATUS_REG_FIFO_BAD_DATA,
976 DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
977 DBG_STATUS_DBG_ARRAY_NOT_SET,
978 DBG_STATUS_MULTI_BLOCKS_WITH_FILTER,
1000 struct idle_chk_data {
1001 __le32 buf_size /* Idle check buffer size in dwords */;
1002 /* Indicates if the idle check buffer size was set (0/1) */
1009 * Debug Tools data (per HW function)
1011 struct dbg_tools_data {
1012 struct dbg_grc_data grc /* GRC Dump data */;
1013 struct dbg_bus_data bus /* Debug Bus data */;
1014 struct idle_chk_data idle_chk /* Idle Check data */;
1015 u8 mode_enable[40] /* Indicates if a mode is enabled (0/1) */;
1016 /* Indicates if a block is in reset state (0/1) */
1017 u8 block_in_reset[80];
1018 u8 chip_id /* Chip ID (from enum chip_ids) */;
1019 u8 platform_id /* Platform ID (from enum platform_ids) */;
1020 u8 initialized /* Indicates if the data was initialized */;
1025 #endif /* __ECORE_HSI_DEBUG_TOOLS__ */