2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #ifndef __ECORE_HSI_ETH__
10 #define __ECORE_HSI_ETH__
11 /************************************************************************/
12 /* Add include to common eth target for both eCore and protocol driver */
13 /************************************************************************/
14 #include "eth_common.h"
17 * The eth storm context for the Tstorm
19 struct tstorm_eth_conn_st_ctx {
24 * The eth storm context for the Pstorm
26 struct pstorm_eth_conn_st_ctx {
31 * The eth storm context for the Xstorm
33 struct xstorm_eth_conn_st_ctx {
37 struct e4_xstorm_eth_conn_ag_ctx {
38 u8 reserved0 /* cdu_validation */;
39 u8 eth_state /* state */;
42 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
43 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
45 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
46 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
48 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
49 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
51 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
52 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
54 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
55 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
57 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
58 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
60 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
61 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
63 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
64 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
67 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
68 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
70 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
71 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
73 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
74 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
76 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
77 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
79 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1
80 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4
82 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1
83 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5
85 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
86 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
88 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
89 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
92 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
93 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
95 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
96 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
98 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
99 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
101 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
102 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
105 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
106 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
108 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
109 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
111 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
112 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
114 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
115 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
118 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
119 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
121 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
122 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
124 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
125 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
127 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
128 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
131 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
132 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
134 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
135 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
137 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
138 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
140 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
141 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
144 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
145 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
147 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
148 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
150 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
151 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
153 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
154 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
157 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
158 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
160 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
161 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
163 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
164 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
166 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
167 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
169 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
170 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
173 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
174 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
176 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
177 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
179 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
180 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
182 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
183 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
185 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
186 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
188 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
189 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
191 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
192 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
194 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
195 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
198 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
199 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
201 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
202 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
204 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
205 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
207 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
208 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
210 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
211 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
213 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
214 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
216 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
217 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
219 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
220 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
223 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
224 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
226 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
227 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
229 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
230 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
232 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
233 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
235 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
236 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
238 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
239 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
241 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
242 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
244 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
245 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
248 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
249 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
251 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
252 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
254 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
255 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
257 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
258 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
260 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
261 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
263 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
264 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
266 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
267 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
269 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
270 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
273 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
274 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
276 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
277 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
279 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
280 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
282 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
283 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
285 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
286 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
288 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
289 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
291 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
292 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
294 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
295 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
298 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
299 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
301 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
302 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
304 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
305 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
307 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
308 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
310 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
311 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
313 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
314 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
316 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
317 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
319 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
320 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
323 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
324 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
326 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
327 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
329 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
330 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
332 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
333 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
335 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
336 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
338 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
339 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
341 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
342 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
343 u8 edpm_event_id /* byte2 */;
344 __le16 physical_q0 /* physical_q0 */;
345 __le16 e5_reserved1 /* physical_q1 */;
346 __le16 edpm_num_bds /* physical_q2 */;
347 __le16 tx_bd_cons /* word3 */;
348 __le16 tx_bd_prod /* word4 */;
349 __le16 tx_class /* word5 */;
350 __le16 conn_dpi /* conn_dpi */;
351 u8 byte3 /* byte3 */;
352 u8 byte4 /* byte4 */;
353 u8 byte5 /* byte5 */;
354 u8 byte6 /* byte6 */;
355 __le32 reg0 /* reg0 */;
356 __le32 reg1 /* reg1 */;
357 __le32 reg2 /* reg2 */;
358 __le32 reg3 /* reg3 */;
359 __le32 reg4 /* reg4 */;
360 __le32 reg5 /* cf_array0 */;
361 __le32 reg6 /* cf_array1 */;
362 __le16 word7 /* word7 */;
363 __le16 word8 /* word8 */;
364 __le16 word9 /* word9 */;
365 __le16 word10 /* word10 */;
366 __le32 reg7 /* reg7 */;
367 __le32 reg8 /* reg8 */;
368 __le32 reg9 /* reg9 */;
369 u8 byte7 /* byte7 */;
370 u8 byte8 /* byte8 */;
371 u8 byte9 /* byte9 */;
372 u8 byte10 /* byte10 */;
373 u8 byte11 /* byte11 */;
374 u8 byte12 /* byte12 */;
375 u8 byte13 /* byte13 */;
376 u8 byte14 /* byte14 */;
377 u8 byte15 /* byte15 */;
378 u8 e5_reserved /* e5_reserved */;
379 __le16 word11 /* word11 */;
380 __le32 reg10 /* reg10 */;
381 __le32 reg11 /* reg11 */;
382 __le32 reg12 /* reg12 */;
383 __le32 reg13 /* reg13 */;
384 __le32 reg14 /* reg14 */;
385 __le32 reg15 /* reg15 */;
386 __le32 reg16 /* reg16 */;
387 __le32 reg17 /* reg17 */;
388 __le32 reg18 /* reg18 */;
389 __le32 reg19 /* reg19 */;
390 __le16 word12 /* word12 */;
391 __le16 word13 /* word13 */;
392 __le16 word14 /* word14 */;
393 __le16 word15 /* word15 */;
397 * The eth storm context for the Ystorm
399 struct ystorm_eth_conn_st_ctx {
403 struct e4_ystorm_eth_conn_ag_ctx {
404 u8 byte0 /* cdu_validation */;
405 u8 state /* state */;
408 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
409 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
411 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
412 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
413 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf0 */
414 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2
415 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 /* cf1 */
416 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4
417 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
418 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
421 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
422 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
424 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
425 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1
427 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
428 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
430 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
431 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
433 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
434 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
436 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
437 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
439 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
440 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
442 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
443 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
444 u8 tx_q0_int_coallecing_timeset /* byte2 */;
445 u8 byte3 /* byte3 */;
446 __le16 word0 /* word0 */;
447 __le32 terminate_spqe /* reg0 */;
448 __le32 reg1 /* reg1 */;
449 __le16 tx_bd_cons_upd /* word1 */;
450 __le16 word2 /* word2 */;
451 __le16 word3 /* word3 */;
452 __le16 word4 /* word4 */;
453 __le32 reg2 /* reg2 */;
454 __le32 reg3 /* reg3 */;
457 struct e4_tstorm_eth_conn_ag_ctx {
458 u8 byte0 /* cdu_validation */;
459 u8 byte1 /* state */;
461 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
462 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
463 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
464 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
465 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
466 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
467 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
468 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
469 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
470 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
471 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
472 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
473 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
474 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
476 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
477 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
478 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
479 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
480 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
481 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
482 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
483 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
485 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
486 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
487 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
488 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
489 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
490 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
491 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
492 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
494 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
495 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
496 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
497 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
498 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
499 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
500 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
501 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
502 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
503 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
504 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
505 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
507 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
508 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
509 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
510 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
511 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
512 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
513 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
514 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
515 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
516 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
517 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
518 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
519 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
520 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
521 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
522 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
524 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
525 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
526 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
527 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
528 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
529 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
530 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
531 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
532 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
533 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
534 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 /* rule6en */
535 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
536 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
537 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
538 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
539 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
540 __le32 reg0 /* reg0 */;
541 __le32 reg1 /* reg1 */;
542 __le32 reg2 /* reg2 */;
543 __le32 reg3 /* reg3 */;
544 __le32 reg4 /* reg4 */;
545 __le32 reg5 /* reg5 */;
546 __le32 reg6 /* reg6 */;
547 __le32 reg7 /* reg7 */;
548 __le32 reg8 /* reg8 */;
549 u8 byte2 /* byte2 */;
550 u8 byte3 /* byte3 */;
551 __le16 rx_bd_cons /* word0 */;
552 u8 byte4 /* byte4 */;
553 u8 byte5 /* byte5 */;
554 __le16 rx_bd_prod /* word1 */;
555 __le16 word2 /* conn_dpi */;
556 __le16 word3 /* word3 */;
557 __le32 reg9 /* reg9 */;
558 __le32 reg10 /* reg10 */;
561 struct e4_ustorm_eth_conn_ag_ctx {
562 u8 byte0 /* cdu_validation */;
563 u8 byte1 /* state */;
566 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
567 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
569 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
570 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
572 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
573 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2
575 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
576 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4
578 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
579 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
582 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
583 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
585 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
586 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
588 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
589 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
591 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
592 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
595 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
596 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
598 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
599 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
601 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
602 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
604 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
605 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
607 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
608 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
610 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
611 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
613 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
614 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
616 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
617 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
620 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
621 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
623 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
624 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
626 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
627 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
629 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
630 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
632 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
633 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
635 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
636 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
638 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
639 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
641 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
642 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
643 u8 byte2 /* byte2 */;
644 u8 byte3 /* byte3 */;
645 __le16 word0 /* conn_dpi */;
646 __le16 tx_bd_cons /* word1 */;
647 __le32 reg0 /* reg0 */;
648 __le32 reg1 /* reg1 */;
649 __le32 reg2 /* reg2 */;
650 __le32 tx_int_coallecing_timeset /* reg3 */;
651 __le16 tx_drv_bd_cons /* word2 */;
652 __le16 rx_drv_cqe_cons /* word3 */;
656 * The eth storm context for the Ustorm
658 struct ustorm_eth_conn_st_ctx {
663 * The eth storm context for the Mstorm
665 struct mstorm_eth_conn_st_ctx {
670 * eth connection context
672 struct eth_conn_context {
673 /* tstorm storm context */
674 struct tstorm_eth_conn_st_ctx tstorm_st_context;
675 struct regpair tstorm_st_padding[2] /* padding */;
676 /* pstorm storm context */
677 struct pstorm_eth_conn_st_ctx pstorm_st_context;
678 /* xstorm storm context */
679 struct xstorm_eth_conn_st_ctx xstorm_st_context;
680 /* xstorm aggregative context */
681 struct e4_xstorm_eth_conn_ag_ctx xstorm_ag_context;
682 /* ystorm storm context */
683 struct ystorm_eth_conn_st_ctx ystorm_st_context;
684 /* ystorm aggregative context */
685 struct e4_ystorm_eth_conn_ag_ctx ystorm_ag_context;
686 /* tstorm aggregative context */
687 struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context;
688 /* ustorm aggregative context */
689 struct e4_ustorm_eth_conn_ag_ctx ustorm_ag_context;
690 /* ustorm storm context */
691 struct ustorm_eth_conn_st_ctx ustorm_st_context;
692 /* mstorm storm context */
693 struct mstorm_eth_conn_st_ctx mstorm_st_context;
698 * Ethernet filter types: mac/vlan/pair
700 enum eth_error_code {
701 ETH_OK = 0x00 /* command succeeded */,
702 /* mac add filters command failed due to cam full state */
703 ETH_FILTERS_MAC_ADD_FAIL_FULL,
704 /* mac add filters command failed due to mtt2 full state */
705 ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2,
706 /* mac add filters command failed due to duplicate mac address */
707 ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2,
708 /* mac add filters command failed due to duplicate mac address */
709 ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2,
710 /* mac delete filters command failed due to not found state */
711 ETH_FILTERS_MAC_DEL_FAIL_NOF,
712 /* mac delete filters command failed due to not found state */
713 ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2,
714 /* mac delete filters command failed due to not found state */
715 ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2,
716 /* mac add filters command failed due to MAC Address of 00:00:00:00:00:00 */
717 ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC,
718 /* vlan add filters command failed due to cam full state */
719 ETH_FILTERS_VLAN_ADD_FAIL_FULL,
720 /* vlan add filters command failed due to duplicate VLAN filter */
721 ETH_FILTERS_VLAN_ADD_FAIL_DUP,
722 /* vlan delete filters command failed due to not found state */
723 ETH_FILTERS_VLAN_DEL_FAIL_NOF,
724 /* vlan delete filters command failed due to not found state */
725 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1,
726 /* pair add filters command failed due to duplicate request */
727 ETH_FILTERS_PAIR_ADD_FAIL_DUP,
728 /* pair add filters command failed due to full state */
729 ETH_FILTERS_PAIR_ADD_FAIL_FULL,
730 /* pair add filters command failed due to full state */
731 ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC,
732 /* pair add filters command failed due not found state */
733 ETH_FILTERS_PAIR_DEL_FAIL_NOF,
734 /* pair add filters command failed due not found state */
735 ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1,
736 /* pair add filters command failed due to MAC Address of 00:00:00:00:00:00 */
737 ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC,
738 /* vni add filters command failed due to cam full state */
739 ETH_FILTERS_VNI_ADD_FAIL_FULL,
740 /* vni add filters command failed due to duplicate VNI filter */
741 ETH_FILTERS_VNI_ADD_FAIL_DUP,
742 ETH_FILTERS_GFT_UPDATE_FAIL /* Fail update GFT filter. */,
748 * opcodes for the event ring
750 enum eth_event_opcode {
752 ETH_EVENT_VPORT_START,
753 ETH_EVENT_VPORT_UPDATE,
754 ETH_EVENT_VPORT_STOP,
755 ETH_EVENT_TX_QUEUE_START,
756 ETH_EVENT_TX_QUEUE_STOP,
757 ETH_EVENT_RX_QUEUE_START,
758 ETH_EVENT_RX_QUEUE_UPDATE,
759 ETH_EVENT_RX_QUEUE_STOP,
760 ETH_EVENT_FILTERS_UPDATE,
761 ETH_EVENT_RX_ADD_OPENFLOW_FILTER,
762 ETH_EVENT_RX_DELETE_OPENFLOW_FILTER,
763 ETH_EVENT_RX_CREATE_OPENFLOW_ACTION,
764 ETH_EVENT_RX_ADD_UDP_FILTER,
765 ETH_EVENT_RX_DELETE_UDP_FILTER,
766 ETH_EVENT_RX_CREATE_GFT_ACTION,
767 ETH_EVENT_RX_GFT_UPDATE_FILTER,
773 * Classify rule types in E2/E3
775 enum eth_filter_action {
776 ETH_FILTER_ACTION_UNUSED,
777 ETH_FILTER_ACTION_REMOVE,
778 ETH_FILTER_ACTION_ADD,
779 /* Remove all filters of given type and vport ID. */
780 ETH_FILTER_ACTION_REMOVE_ALL,
781 MAX_ETH_FILTER_ACTION
786 * Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$
788 struct eth_filter_cmd {
789 u8 type /* Filter Type (MAC/VLAN/Pair/VNI) */;
790 u8 vport_id /* the vport id */;
791 u8 action /* filter command action: add/remove/replace */;
802 * $$KEEP_ENDIANNESS$$
804 struct eth_filter_cmd_header {
805 u8 rx /* If set, apply these commands to the RX path */;
806 u8 tx /* If set, apply these commands to the TX path */;
807 u8 cmd_cnt /* Number of filter commands */;
808 /* 0 - dont assert in case of filter configuration error. Just return an error
809 * code. 1 - assert in case of filter configuration error.
817 * Ethernet filter types: mac/vlan/pair
819 enum eth_filter_type {
820 ETH_FILTER_TYPE_UNUSED,
821 ETH_FILTER_TYPE_MAC /* Add/remove a MAC address */,
822 ETH_FILTER_TYPE_VLAN /* Add/remove a VLAN */,
823 ETH_FILTER_TYPE_PAIR /* Add/remove a MAC-VLAN pair */,
824 ETH_FILTER_TYPE_INNER_MAC /* Add/remove a inner MAC address */,
825 ETH_FILTER_TYPE_INNER_VLAN /* Add/remove a inner VLAN */,
826 ETH_FILTER_TYPE_INNER_PAIR /* Add/remove a inner MAC-VLAN pair */,
827 /* Add/remove a inner MAC-VNI pair */
828 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
829 ETH_FILTER_TYPE_MAC_VNI_PAIR /* Add/remove a MAC-VNI pair */,
830 ETH_FILTER_TYPE_VNI /* Add/remove a VNI */,
836 * eth IPv4 Fragment Type
838 enum eth_ipv4_frag_type {
839 ETH_IPV4_NOT_FRAG /* IPV4 Packet Not Fragmented */,
840 /* First Fragment of IPv4 Packet (contains headers) */
842 /* Non-First Fragment of IPv4 Packet (does not contain headers) */
843 ETH_IPV4_NON_FIRST_FRAG,
844 MAX_ETH_IPV4_FRAG_TYPE
849 * eth IPv4 Fragment Type
859 * Ethernet Ramrod Command IDs
861 enum eth_ramrod_cmd_id {
863 ETH_RAMROD_VPORT_START /* VPort Start Ramrod */,
864 ETH_RAMROD_VPORT_UPDATE /* VPort Update Ramrod */,
865 ETH_RAMROD_VPORT_STOP /* VPort Stop Ramrod */,
866 ETH_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */,
867 ETH_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */,
868 ETH_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */,
869 ETH_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */,
870 ETH_RAMROD_FILTERS_UPDATE /* Add or Remove Mac/Vlan/Pair filters */,
871 ETH_RAMROD_RX_QUEUE_UPDATE /* RX Queue Update Ramrod */,
872 /* RX - Create an Openflow Action */
873 ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION,
874 /* RX - Add an Openflow Filter to the Searcher */
875 ETH_RAMROD_RX_ADD_OPENFLOW_FILTER,
876 /* RX - Delete an Openflow Filter to the Searcher */
877 ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER,
878 /* RX - Add a UDP Filter to the Searcher */
879 ETH_RAMROD_RX_ADD_UDP_FILTER,
880 /* RX - Delete a UDP Filter to the Searcher */
881 ETH_RAMROD_RX_DELETE_UDP_FILTER,
882 ETH_RAMROD_RX_CREATE_GFT_ACTION /* RX - Create a Gft Action */,
883 /* RX - Add/Delete a GFT Filter to the Searcher */
884 ETH_RAMROD_GFT_UPDATE_FILTER,
885 MAX_ETH_RAMROD_CMD_ID
890 * return code from eth sp ramrods
892 struct eth_return_code {
894 /* error code (use enum eth_error_code) */
895 #define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F
896 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
897 #define ETH_RETURN_CODE_RESERVED_MASK 0x3
898 #define ETH_RETURN_CODE_RESERVED_SHIFT 5
899 /* rx path - 0, tx path - 1 */
900 #define ETH_RETURN_CODE_RX_TX_MASK 0x1
901 #define ETH_RETURN_CODE_RX_TX_SHIFT 7
906 * What to do in case an error occurs
909 ETH_TX_ERR_DROP /* Drop erroneous packet. */,
910 /* Assert an interrupt for PF, declare as malicious for VF */
911 ETH_TX_ERR_ASSERT_MALICIOUS,
917 * Array of the different error type behaviors
919 struct eth_tx_err_vals {
921 /* Wrong VLAN insertion mode (use enum eth_tx_err) */
922 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1
923 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0
924 /* Packet is below minimal size (use enum eth_tx_err) */
925 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1
926 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1
927 /* Vport has sent spoofed packet (use enum eth_tx_err) */
928 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1
929 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2
930 /* Packet with illegal type of inband tag (use enum eth_tx_err) */
931 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1
932 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3
933 /* Packet marked for VLAN insertion when inband tag is present
934 * (use enum eth_tx_err)
936 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1
937 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4
938 /* Non LSO packet larger than MTU (use enum eth_tx_err) */
939 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1
940 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5
941 /* VF/PF has sent LLDP/PFC or any other type of control packet which is not
942 * allowed to (use enum eth_tx_err)
944 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
945 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6
946 #define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF
947 #define ETH_TX_ERR_VALS_RESERVED_SHIFT 7
952 * vport rss configuration data
954 struct eth_vport_rss_config {
956 /* configuration of the IpV4 2-tuple capability */
957 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
958 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0
959 /* configuration of the IpV6 2-tuple capability */
960 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
961 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1
962 /* configuration of the IpV4 4-tuple capability for TCP */
963 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
964 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2
965 /* configuration of the IpV6 4-tuple capability for TCP */
966 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
967 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3
968 /* configuration of the IpV4 4-tuple capability for UDP */
969 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
970 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4
971 /* configuration of the IpV6 4-tuple capability for UDP */
972 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
973 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5
974 /* configuration of the 5-tuple capability */
975 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
976 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
977 /* if set update the rss keys */
978 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF
979 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7
980 /* The RSS engine ID. Must be allocated to each vport with RSS enabled.
981 * Total number of RSS engines is ETH_RSS_ENGINE_NUM_ , according to chip type.
984 u8 rss_mode /* The RSS mode for this function */;
985 u8 update_rss_key /* if set update the rss key */;
986 /* if set update the indirection table values */
987 u8 update_rss_ind_table;
988 /* if set update the capabilities and indirection table size. */
989 u8 update_rss_capabilities;
990 u8 tbl_size /* rss mask (Tbl size) */;
992 /* RSS indirection table */
993 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
994 /* RSS key supplied to us by OS */
995 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
1001 * eth vport RSS mode
1003 enum eth_vport_rss_mode {
1004 ETH_VPORT_RSS_MODE_DISABLED /* RSS Disabled */,
1005 ETH_VPORT_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */,
1006 MAX_ETH_VPORT_RSS_MODE
1011 * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$
1013 struct eth_vport_rx_mode {
1015 /* drop all unicast packets */
1016 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
1017 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0
1018 /* accept all unicast packets (subject to vlan) */
1019 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
1020 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
1021 /* accept all unmatched unicast packets */
1022 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
1023 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
1024 /* drop all multicast packets */
1025 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
1026 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3
1027 /* accept all multicast packets (subject to vlan) */
1028 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
1029 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4
1030 /* accept all broadcast packets (subject to vlan) */
1031 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
1032 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5
1033 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF
1034 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6
1035 __le16 reserved2[3];
1040 * Command for setting tpa parameters
1042 struct eth_vport_tpa_param {
1043 u8 tpa_ipv4_en_flg /* Enable TPA for IPv4 packets */;
1044 u8 tpa_ipv6_en_flg /* Enable TPA for IPv6 packets */;
1045 u8 tpa_ipv4_tunn_en_flg /* Enable TPA for IPv4 over tunnel */;
1046 u8 tpa_ipv6_tunn_en_flg /* Enable TPA for IPv6 over tunnel */;
1047 /* If set, start each tpa segment on new SGE (GRO mode). One SGE per segment
1050 u8 tpa_pkt_split_flg;
1051 /* If set, put header of first TPA segment on bd and data on SGE */
1052 u8 tpa_hdr_data_split_flg;
1053 /* If set, GRO data consistent will checked for TPA continue */
1054 u8 tpa_gro_consistent_flg;
1055 /* maximum number of opened aggregations per v-port */
1056 u8 tpa_max_aggs_num;
1057 __le16 tpa_max_size /* maximal size for the aggregated TPA packets */;
1058 /* minimum TCP payload size for a packet to start aggregation */
1059 __le16 tpa_min_size_to_start;
1060 /* minimum TCP payload size for a packet to continue aggregation */
1061 __le16 tpa_min_size_to_cont;
1062 /* maximal number of buffers that can be used for one aggregation */
1069 * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$
1071 struct eth_vport_tx_mode {
1073 /* drop all unicast packets */
1074 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
1075 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0
1076 /* accept all unicast packets (subject to vlan) */
1077 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
1078 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
1079 /* drop all multicast packets */
1080 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
1081 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2
1082 /* accept all multicast packets (subject to vlan) */
1083 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
1084 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
1085 /* accept all broadcast packets (subject to vlan) */
1086 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
1087 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
1088 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF
1089 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5
1090 __le16 reserved2[3];
1095 * Ramrod data for rx create gft action
1097 enum gft_filter_update_action {
1100 MAX_GFT_FILTER_UPDATE_ACTION
1105 * Ramrod data for rx create gft action
1107 enum gft_logic_filter_type {
1108 GFT_FILTER_TYPE /* flow FW is GFT-logic as well */,
1109 RFS_FILTER_TYPE /* flow FW is A-RFS-logic */,
1110 MAX_GFT_LOGIC_FILTER_TYPE
1117 * Ramrod data for rx add openflow filter
1119 struct rx_add_openflow_filter_data {
1120 __le16 action_icid /* CID of Action to run for this filter */;
1121 u8 priority /* Searcher String - Packet priority */;
1123 __le32 tenant_id /* Searcher String - Tenant ID */;
1124 /* Searcher String - Destination Mac Bytes 0 to 1 */
1126 /* Searcher String - Destination Mac Bytes 2 to 3 */
1128 /* Searcher String - Destination Mac Bytes 4 to 5 */
1130 __le16 src_mac_hi /* Searcher String - Source Mac 0 to 1 */;
1131 __le16 src_mac_mid /* Searcher String - Source Mac 2 to 3 */;
1132 __le16 src_mac_lo /* Searcher String - Source Mac 4 to 5 */;
1133 __le16 vlan_id /* Searcher String - Vlan ID */;
1134 __le16 l2_eth_type /* Searcher String - Last L2 Ethertype */;
1135 u8 ipv4_dscp /* Searcher String - IPv4 6 MSBs of the TOS Field */;
1136 u8 ipv4_frag_type /* Searcher String - IPv4 Fragmentation Type */;
1137 u8 ipv4_over_ip /* Searcher String - IPv4 Over IP Type */;
1138 u8 tenant_id_exists /* Searcher String - Tenant ID Exists */;
1139 __le32 ipv4_dst_addr /* Searcher String - IPv4 Destination Address */;
1140 __le32 ipv4_src_addr /* Searcher String - IPv4 Source Address */;
1141 __le16 l4_dst_port /* Searcher String - TCP/UDP Destination Port */;
1142 __le16 l4_src_port /* Searcher String - TCP/UDP Source Port */;
1147 * Ramrod data for rx create gft action
1149 struct rx_create_gft_action_data {
1150 u8 vport_id /* Vport Id of GFT Action */;
1156 * Ramrod data for rx create openflow action
1158 struct rx_create_openflow_action_data {
1159 u8 vport_id /* ID of RX queue */;
1165 * Ramrod data for rx queue start ramrod
1167 struct rx_queue_start_ramrod_data {
1168 __le16 rx_queue_id /* ID of RX queue */;
1169 __le16 num_of_pbl_pages /* Num of pages in CQE PBL */;
1170 __le16 bd_max_bytes /* maximal bytes that can be places on the bd */;
1171 __le16 sb_id /* Status block ID */;
1172 u8 sb_index /* index of the protocol index */;
1173 u8 vport_id /* ID of virtual port */;
1174 u8 default_rss_queue_flg /* set queue as default rss queue if set */;
1175 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
1176 u8 complete_event_flg /* post completion to the event ring if set */;
1177 u8 stats_counter_id /* Statistics counter ID */;
1178 u8 pin_context /* Pin context in CCFC to improve performance */;
1179 u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD/SGE fetch */;
1180 /* PXP command TPH Valid - for packet placement */
1181 u8 pxp_tph_valid_pkt;
1182 /* PXP command Steering tag hint. Use enum pxp_tph_st_hint */
1184 __le16 pxp_st_index /* PXP command Steering tag index */;
1185 /* Indicates that current queue belongs to poll-mode driver */
1187 /* Indicates that the current queue is using the TX notification queue
1188 * mechanism - should be set only for PMD queue
1191 /* Initial value for the toggle valid bit - used in PMD mode */
1193 /* Index of RX producers in VF zone. Used for VF only. */
1194 u8 vf_rx_prod_index;
1195 /* Backward compatibility mode. If set, unprotected mStorm queue zone will used
1196 * for VF RX producers instead of VF zone.
1198 u8 vf_rx_prod_use_zone_a;
1200 __le16 reserved1 /* FW reserved. */;
1201 struct regpair cqe_pbl_addr /* Base address on host of CQE PBL */;
1202 struct regpair bd_base /* bd address of the first bd page */;
1203 struct regpair reserved2 /* FW reserved. */;
1208 * Ramrod data for rx queue stop ramrod
1210 struct rx_queue_stop_ramrod_data {
1211 __le16 rx_queue_id /* ID of RX queue */;
1212 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
1213 u8 complete_event_flg /* post completion to the event ring if set */;
1214 u8 vport_id /* ID of virtual port */;
1220 * Ramrod data for rx queue update ramrod
1222 struct rx_queue_update_ramrod_data {
1223 __le16 rx_queue_id /* ID of RX queue */;
1224 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
1225 u8 complete_event_flg /* post completion to the event ring if set */;
1226 u8 vport_id /* ID of virtual port */;
1228 u8 reserved1 /* FW reserved. */;
1229 u8 reserved2 /* FW reserved. */;
1230 u8 reserved3 /* FW reserved. */;
1231 __le16 reserved4 /* FW reserved. */;
1232 __le16 reserved5 /* FW reserved. */;
1233 struct regpair reserved6 /* FW reserved. */;
1238 * Ramrod data for rx Add UDP Filter
1240 struct rx_udp_filter_data {
1241 __le16 action_icid /* CID of Action to run for this filter */;
1242 __le16 vlan_id /* Searcher String - Vlan ID */;
1243 u8 ip_type /* Searcher String - IP Type */;
1244 u8 tenant_id_exists /* Searcher String - Tenant ID Exists */;
1246 /* Searcher String - IP Destination Address, for IPv4 use ip_dst_addr[0] only */
1247 __le32 ip_dst_addr[4];
1248 /* Searcher String - IP Source Address, for IPv4 use ip_dst_addr[0] only */
1249 __le32 ip_src_addr[4];
1250 __le16 udp_dst_port /* Searcher String - UDP Destination Port */;
1251 __le16 udp_src_port /* Searcher String - UDP Source Port */;
1252 __le32 tenant_id /* Searcher String - Tenant ID */;
1257 * Ramrod to add filter - filter is packet headr of type of packet wished to
1258 * pass certin FW flow
1260 struct rx_update_gft_filter_data {
1261 /* Pointer to Packet Header That Defines GFT Filter */
1262 struct regpair pkt_hdr_addr;
1263 __le16 pkt_hdr_length /* Packet Header Length */;
1264 /* If is_rfs flag is set: Queue Id to associate filter with else: action icid */
1265 __le16 rx_qid_or_action_icid;
1266 /* Field is used if is_rfs flag is set: vport Id of which to associate filter
1270 /* Use enum to set type of flow using gft HW logic blocks */
1272 u8 filter_action /* Use to set type of action on filter */;
1273 /* 0 - dont assert in case of error. Just return an error code. 1 - assert in
1282 * Ramrod data for tx queue start ramrod
1284 struct tx_queue_start_ramrod_data {
1285 __le16 sb_id /* Status block ID */;
1286 u8 sb_index /* Status block protocol index */;
1287 u8 vport_id /* VPort ID */;
1288 u8 reserved0 /* FW reserved. (qcn_rl_en) */;
1289 u8 stats_counter_id /* Statistics counter ID to use */;
1290 __le16 qm_pq_id /* QM PQ ID */;
1292 /* 0: Enable QM opportunistic flow. 1: Disable QM opportunistic flow */
1293 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
1294 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
1295 /* If set, Test Mode - packets will be duplicated by Xstorm handler */
1296 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
1297 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1
1298 /* If set, Test Mode - packets destination will be determined by dest_port_mode
1301 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1
1302 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2
1303 /* Indicates that current queue belongs to poll-mode driver */
1304 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
1305 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3
1306 /* Indicates that the current queue is using the TX notification queue
1307 * mechanism - should be set only for PMD queue
1309 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
1310 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4
1311 /* Pin context in CCFC to improve performance */
1312 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
1313 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5
1314 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3
1315 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6
1316 u8 pxp_st_hint /* PXP command Steering tag hint */;
1317 u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD fetch */;
1318 u8 pxp_tph_valid_pkt /* PXP command TPH Valid - for packet fetch */;
1319 __le16 pxp_st_index /* PXP command Steering tag index */;
1320 /* TX completion min agg size - for PMD queues */
1321 __le16 comp_agg_size;
1322 __le16 queue_zone_id /* queue zone ID to use */;
1323 __le16 reserved2 /* FW reserved. (test_dup_count) */;
1324 __le16 pbl_size /* Number of BD pages pointed by PBL */;
1325 /* unique Queue ID - currently used only by PMD flow */
1327 /* Unique Same-As-Last Resource ID - improves performance for same-as-last
1328 * packets per connection (range 0..ETH_TX_NUM_SAME_AS_LAST_ENTRIES-1 IDs
1331 __le16 same_as_last_id;
1333 struct regpair pbl_base_addr /* address of the pbl page */;
1334 /* BD consumer address in host - for PMD queues */
1335 struct regpair bd_cons_address;
1340 * Ramrod data for tx queue stop ramrod
1342 struct tx_queue_stop_ramrod_data {
1349 * Ramrod data for vport update ramrod
1351 struct vport_filter_update_ramrod_data {
1352 /* Header for Filter Commands (RX/TX, Add/Remove/Replace, etc) */
1353 struct eth_filter_cmd_header filter_cmd_hdr;
1354 /* Filter Commands */
1355 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
1360 * Ramrod data for vport start ramrod
1362 struct vport_start_ramrod_data {
1366 u8 drop_ttl0_en /* if set, drop packet with ttl=0 */;
1367 u8 inner_vlan_removal_en;
1368 struct eth_vport_rx_mode rx_mode /* Rx filter data */;
1369 struct eth_vport_tx_mode tx_mode /* Tx filter data */;
1370 /* TPA configuration parameters */
1371 struct eth_vport_tpa_param tpa_param;
1372 __le16 default_vlan /* Default Vlan value to be forced by FW */;
1373 u8 tx_switching_en /* Tx switching is enabled for current Vport */;
1374 /* Anti-spoofing verification is set for current Vport */
1375 u8 anti_spoofing_en;
1376 /* If set, the default Vlan value is forced by the FW */
1378 /* If set, the vport handles PTP Timesync Packets */
1380 /* If enable then innerVlan will be striped and not written to cqe */
1381 u8 silent_vlan_removal_en;
1382 /* If set untagged filter (vlan0) is added to current Vport, otherwise port is
1383 * marked as any-vlan
1386 /* Desired behavior per TX error type */
1387 struct eth_tx_err_vals tx_err_behav;
1388 /* If set, ETH header padding will not inserted. placement_offset will be zero.
1390 u8 zero_placement_offset;
1391 /* If set, Contorl frames will be filtered according to MAC check. */
1392 u8 ctl_frame_mac_check_en;
1393 /* If set, Contorl frames will be filtered according to ethtype check. */
1394 u8 ctl_frame_ethtype_check_en;
1400 * Ramrod data for vport stop ramrod
1402 struct vport_stop_ramrod_data {
1409 * Ramrod data for vport update ramrod
1411 struct vport_update_ramrod_data_cmn {
1413 u8 update_rx_active_flg /* set if rx active flag should be handled */;
1414 u8 rx_active_flg /* rx active flag value */;
1415 u8 update_tx_active_flg /* set if tx active flag should be handled */;
1416 u8 tx_active_flg /* tx active flag value */;
1417 u8 update_rx_mode_flg /* set if rx state data should be handled */;
1418 u8 update_tx_mode_flg /* set if tx state data should be handled */;
1419 /* set if approx. mcast data should be handled */
1420 u8 update_approx_mcast_flg;
1421 u8 update_rss_flg /* set if rss data should be handled */;
1422 /* set if inner_vlan_removal_en should be handled */
1423 u8 update_inner_vlan_removal_en_flg;
1424 u8 inner_vlan_removal_en;
1425 /* set if tpa parameters should be handled, TPA must be disable before */
1426 u8 update_tpa_param_flg;
1427 u8 update_tpa_en_flg /* set if tpa enable changes */;
1428 /* set if tx switching en flag should be handled */
1429 u8 update_tx_switching_en_flg;
1430 u8 tx_switching_en /* tx switching en value */;
1431 /* set if anti spoofing flag should be handled */
1432 u8 update_anti_spoofing_en_flg;
1433 u8 anti_spoofing_en /* Anti-spoofing verification en value */;
1434 /* set if handle_ptp_pkts should be handled. */
1435 u8 update_handle_ptp_pkts;
1436 /* If set, the vport handles PTP Timesync Packets */
1438 /* If set, the default Vlan enable flag is updated */
1439 u8 update_default_vlan_en_flg;
1440 /* If set, the default Vlan value is forced by the FW */
1442 /* If set, the default Vlan value is updated */
1443 u8 update_default_vlan_flg;
1444 __le16 default_vlan /* Default Vlan value to be forced by FW */;
1445 /* set if accept_any_vlan should be handled */
1446 u8 update_accept_any_vlan_flg;
1447 u8 accept_any_vlan /* accept_any_vlan updated value */;
1448 /* Set to remove vlan silently, update_inner_vlan_removal_en_flg must be enabled
1449 * as well. If Rx is in noSgl mode send rx_queue_update_ramrod_data
1451 u8 silent_vlan_removal_en;
1452 /* If set, MTU will be updated. Vport must be not active. */
1454 __le16 mtu /* New MTU value. Used if update_mtu_flg are set */;
1455 /* If set, ctl_frame_mac_check_en and ctl_frame_ethtype_check_en will be
1458 u8 update_ctl_frame_checks_en_flg;
1459 /* If set, Contorl frames will be filtered according to MAC check. */
1460 u8 ctl_frame_mac_check_en;
1461 /* If set, Contorl frames will be filtered according to ethtype check. */
1462 u8 ctl_frame_ethtype_check_en;
1466 struct vport_update_ramrod_mcast {
1467 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS] /* multicast bins */;
1471 * Ramrod data for vport update ramrod
1473 struct vport_update_ramrod_data {
1474 /* Common data for all vport update ramrods */
1475 struct vport_update_ramrod_data_cmn common;
1476 struct eth_vport_rx_mode rx_mode /* vport rx mode bitmap */;
1477 struct eth_vport_tx_mode tx_mode /* vport tx mode bitmap */;
1478 /* TPA configuration parameters */
1479 struct eth_vport_tpa_param tpa_param;
1480 struct vport_update_ramrod_mcast approx_mcast;
1481 struct eth_vport_rss_config rss_config /* rss config data */;
1489 struct E4XstormEthConnAgCtxDqExtLdPart {
1490 u8 reserved0 /* cdu_validation */;
1491 u8 eth_state /* state */;
1494 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
1495 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
1497 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1
1498 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1
1500 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1
1501 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2
1503 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
1504 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
1506 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1
1507 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4
1508 /* cf_array_active */
1509 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1
1510 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5
1512 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1
1513 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6
1515 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1
1516 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7
1519 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1
1520 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0
1522 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1
1523 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1
1525 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1
1526 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2
1528 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
1529 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
1531 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
1532 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
1534 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_MASK 0x1
1535 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_SHIFT 5
1537 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1
1538 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6
1540 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1
1541 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7
1544 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
1545 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0
1547 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
1548 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2
1550 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
1551 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4
1552 /* timer_stop_all */
1553 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
1554 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6
1557 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
1558 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0
1560 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
1561 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2
1563 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
1564 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4
1566 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
1567 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6
1570 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
1571 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0
1573 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
1574 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2
1576 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
1577 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4
1579 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
1580 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6
1583 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
1584 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0
1586 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
1587 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2
1589 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
1590 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4
1592 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
1593 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6
1596 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
1597 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0
1599 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
1600 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2
1602 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
1603 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4
1605 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
1606 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6
1609 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
1610 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0
1612 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
1613 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2
1615 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
1616 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
1618 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
1619 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
1621 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
1622 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
1625 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
1626 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
1628 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
1629 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
1631 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
1632 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
1634 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
1635 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
1637 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
1638 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
1640 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1
1641 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5
1643 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
1644 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
1646 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
1647 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
1650 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
1651 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
1653 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
1654 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
1656 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
1657 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
1659 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
1660 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
1662 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
1663 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
1665 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
1666 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
1668 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1
1669 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6
1670 /* cf_array_cf_en */
1671 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1
1672 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7
1675 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1
1676 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0
1678 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1
1679 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1
1681 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1
1682 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2
1684 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1
1685 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3
1687 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
1688 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
1690 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1
1691 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5
1693 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1
1694 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6
1696 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1
1697 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7
1700 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1
1701 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0
1703 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1
1704 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1
1706 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1
1707 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2
1709 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
1710 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
1712 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
1713 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
1715 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
1716 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
1718 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
1719 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
1721 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
1722 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
1725 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
1726 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
1728 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
1729 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
1731 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
1732 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
1734 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
1735 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
1737 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
1738 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
1740 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
1741 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
1743 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
1744 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
1746 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
1747 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
1750 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
1751 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
1753 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
1754 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
1756 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
1757 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
1759 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
1760 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
1762 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
1763 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
1765 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
1766 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
1768 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
1769 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
1771 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
1772 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
1775 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1
1776 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0
1778 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1
1779 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1
1781 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1
1782 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2
1784 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1
1785 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3
1787 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1
1788 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4
1790 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
1791 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
1793 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
1794 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6
1795 u8 edpm_event_id /* byte2 */;
1796 __le16 physical_q0 /* physical_q0 */;
1797 __le16 e5_reserved1 /* physical_q1 */;
1798 __le16 edpm_num_bds /* physical_q2 */;
1799 __le16 tx_bd_cons /* word3 */;
1800 __le16 tx_bd_prod /* word4 */;
1801 __le16 tx_class /* word5 */;
1802 __le16 conn_dpi /* conn_dpi */;
1803 u8 byte3 /* byte3 */;
1804 u8 byte4 /* byte4 */;
1805 u8 byte5 /* byte5 */;
1806 u8 byte6 /* byte6 */;
1807 __le32 reg0 /* reg0 */;
1808 __le32 reg1 /* reg1 */;
1809 __le32 reg2 /* reg2 */;
1810 __le32 reg3 /* reg3 */;
1811 __le32 reg4 /* reg4 */;
1815 struct e4_mstorm_eth_conn_ag_ctx {
1816 u8 byte0 /* cdu_validation */;
1817 u8 byte1 /* state */;
1819 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1820 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1821 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1822 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
1823 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
1824 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2
1825 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1826 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4
1827 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
1828 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
1830 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1831 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
1832 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1833 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1
1834 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1835 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
1836 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1837 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
1838 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1839 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
1840 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1841 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
1842 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1843 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
1844 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1845 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
1846 __le16 word0 /* word0 */;
1847 __le16 word1 /* word1 */;
1848 __le32 reg0 /* reg0 */;
1849 __le32 reg1 /* reg1 */;
1856 struct e4_xstorm_eth_hw_conn_ag_ctx {
1857 u8 reserved0 /* cdu_validation */;
1858 u8 eth_state /* state */;
1861 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
1862 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1864 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
1865 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1
1867 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
1868 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2
1870 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
1871 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
1873 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
1874 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4
1875 /* cf_array_active */
1876 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
1877 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5
1878 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */
1879 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6
1880 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */
1881 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7
1883 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */
1884 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0
1885 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */
1886 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1
1888 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
1889 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2
1891 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
1892 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3
1894 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK 0x1
1895 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT 4
1897 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK 0x1
1898 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT 5
1900 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
1901 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
1903 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
1904 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
1907 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
1908 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0
1910 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
1911 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2
1913 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
1914 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4
1915 /* timer_stop_all */
1916 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
1917 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6
1919 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
1920 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0
1921 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
1922 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2
1923 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
1924 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4
1925 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
1926 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6
1928 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
1929 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0
1930 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
1931 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2
1932 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
1933 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4
1934 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
1935 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6
1937 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
1938 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
1939 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
1940 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2
1941 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */
1942 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4
1943 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
1944 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6
1946 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */
1947 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
1949 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
1950 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
1951 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */
1952 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4
1953 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */
1954 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
1956 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */
1957 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
1958 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */
1959 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2
1960 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
1961 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4
1963 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
1964 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6
1966 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
1967 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7
1970 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
1971 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0
1973 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
1974 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1
1976 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
1977 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2
1979 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
1980 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3
1982 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
1983 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4
1985 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
1986 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5
1988 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
1989 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6
1991 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
1992 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7
1995 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
1996 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0
1998 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
1999 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1
2001 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
2002 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2
2004 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
2005 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3
2007 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
2008 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4
2010 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
2011 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5
2013 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
2014 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
2015 /* cf_array_cf_en */
2016 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
2017 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
2020 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
2021 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
2023 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
2024 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
2026 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
2027 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
2029 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
2030 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3
2032 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
2033 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
2035 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
2036 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
2038 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
2039 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6
2041 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
2042 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7
2045 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
2046 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0
2048 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
2049 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1
2051 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
2052 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
2054 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
2055 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3
2057 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
2058 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4
2060 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
2061 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5
2063 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
2064 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
2066 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
2067 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7
2070 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
2071 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0
2073 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
2074 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1
2076 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
2077 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
2079 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
2080 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
2082 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
2083 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4
2085 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
2086 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5
2088 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
2089 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6
2091 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
2092 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7
2095 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
2096 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0
2098 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
2099 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1
2101 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
2102 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
2104 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
2105 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
2107 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
2108 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
2110 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
2111 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
2113 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
2114 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
2116 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
2117 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
2120 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
2121 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
2123 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
2124 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
2126 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
2127 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
2129 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
2130 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
2132 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
2133 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
2135 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
2136 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
2137 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */
2138 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
2139 u8 edpm_event_id /* byte2 */;
2140 __le16 physical_q0 /* physical_q0 */;
2141 __le16 e5_reserved1 /* physical_q1 */;
2142 __le16 edpm_num_bds /* physical_q2 */;
2143 __le16 tx_bd_cons /* word3 */;
2144 __le16 tx_bd_prod /* word4 */;
2145 __le16 tx_class /* word5 */;
2146 __le16 conn_dpi /* conn_dpi */;
2152 * GFT CAM line struct
2154 struct gft_cam_line {
2156 /* Indication if the line is valid. */
2157 #define GFT_CAM_LINE_VALID_MASK 0x1
2158 #define GFT_CAM_LINE_VALID_SHIFT 0
2159 /* Data bits, the word that compared with the profile key */
2160 #define GFT_CAM_LINE_DATA_MASK 0x3FFF
2161 #define GFT_CAM_LINE_DATA_SHIFT 1
2162 /* Mask bits, indicate the bits in the data that are Dont-Care */
2163 #define GFT_CAM_LINE_MASK_BITS_MASK 0x3FFF
2164 #define GFT_CAM_LINE_MASK_BITS_SHIFT 15
2165 #define GFT_CAM_LINE_RESERVED1_MASK 0x7
2166 #define GFT_CAM_LINE_RESERVED1_SHIFT 29
2171 * GFT CAM line struct (for driversim use)
2173 struct gft_cam_line_mapped {
2175 /* Indication if the line is valid. */
2176 #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1
2177 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0
2178 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
2179 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1
2180 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1
2181 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
2182 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1
2183 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2
2184 /* use enum gft_profile_upper_protocol_type
2185 * (use enum gft_profile_upper_protocol_type)
2187 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF
2188 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3
2189 /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */
2190 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF
2191 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7
2192 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF
2193 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11
2194 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
2195 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1
2196 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15
2197 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
2198 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1
2199 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16
2200 /* use enum gft_profile_upper_protocol_type
2201 * (use enum gft_profile_upper_protocol_type)
2203 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF
2204 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17
2205 /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */
2206 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF
2207 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21
2208 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF
2209 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25
2210 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7
2211 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29
2215 union gft_cam_line_union {
2216 struct gft_cam_line cam_line;
2217 struct gft_cam_line_mapped cam_line_mapped;
2222 * Used in gft_profile_key: Indication for ip version
2224 enum gft_profile_ip_version {
2225 GFT_PROFILE_IPV4 = 0,
2226 GFT_PROFILE_IPV6 = 1,
2227 MAX_GFT_PROFILE_IP_VERSION
2232 * Profile key stucr fot GFT logic in Prs
2234 struct gft_profile_key {
2236 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
2237 #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1
2238 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0
2239 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
2240 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1
2241 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1
2242 /* use enum gft_profile_upper_protocol_type
2243 * (use enum gft_profile_upper_protocol_type)
2245 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF
2246 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2
2247 /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */
2248 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF
2249 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6
2250 #define GFT_PROFILE_KEY_PF_ID_MASK 0xF
2251 #define GFT_PROFILE_KEY_PF_ID_SHIFT 10
2252 #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3
2253 #define GFT_PROFILE_KEY_RESERVED0_SHIFT 14
2258 * Used in gft_profile_key: Indication for tunnel type
2260 enum gft_profile_tunnel_type {
2261 GFT_PROFILE_NO_TUNNEL = 0,
2262 GFT_PROFILE_VXLAN_TUNNEL = 1,
2263 GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2,
2264 GFT_PROFILE_GRE_IP_TUNNEL = 3,
2265 GFT_PROFILE_GENEVE_MAC_TUNNEL = 4,
2266 GFT_PROFILE_GENEVE_IP_TUNNEL = 5,
2267 MAX_GFT_PROFILE_TUNNEL_TYPE
2272 * Used in gft_profile_key: Indication for protocol type
2274 enum gft_profile_upper_protocol_type {
2275 GFT_PROFILE_ROCE_PROTOCOL = 0,
2276 GFT_PROFILE_RROCE_PROTOCOL = 1,
2277 GFT_PROFILE_FCOE_PROTOCOL = 2,
2278 GFT_PROFILE_ICMP_PROTOCOL = 3,
2279 GFT_PROFILE_ARP_PROTOCOL = 4,
2280 GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5,
2281 GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6,
2282 GFT_PROFILE_TCP_PROTOCOL = 7,
2283 GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8,
2284 GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9,
2285 GFT_PROFILE_UDP_PROTOCOL = 10,
2286 GFT_PROFILE_USER_IP_1_INNER = 11,
2287 GFT_PROFILE_USER_IP_2_OUTER = 12,
2288 GFT_PROFILE_USER_ETH_1_INNER = 13,
2289 GFT_PROFILE_USER_ETH_2_OUTER = 14,
2290 GFT_PROFILE_RAW = 15,
2291 MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE
2296 * GFT RAM line struct
2298 struct gft_ram_line {
2300 #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3
2301 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0
2302 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1
2303 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2
2304 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1
2305 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3
2306 #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1
2307 #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4
2308 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1
2309 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5
2310 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1
2311 #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6
2312 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1
2313 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7
2314 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1
2315 #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8
2316 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1
2317 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9
2318 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1
2319 #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10
2320 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1
2321 #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11
2322 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1
2323 #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12
2324 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1
2325 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13
2326 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1
2327 #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14
2328 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1
2329 #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15
2330 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1
2331 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16
2332 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1
2333 #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17
2334 #define GFT_RAM_LINE_TTL_MASK 0x1
2335 #define GFT_RAM_LINE_TTL_SHIFT 18
2336 #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1
2337 #define GFT_RAM_LINE_ETHERTYPE_SHIFT 19
2338 #define GFT_RAM_LINE_RESERVED0_MASK 0x1
2339 #define GFT_RAM_LINE_RESERVED0_SHIFT 20
2340 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1
2341 #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21
2342 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1
2343 #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22
2344 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1
2345 #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23
2346 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1
2347 #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24
2348 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1
2349 #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25
2350 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1
2351 #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26
2352 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1
2353 #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27
2354 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1
2355 #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28
2356 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1
2357 #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29
2358 #define GFT_RAM_LINE_DST_PORT_MASK 0x1
2359 #define GFT_RAM_LINE_DST_PORT_SHIFT 30
2360 #define GFT_RAM_LINE_SRC_PORT_MASK 0x1
2361 #define GFT_RAM_LINE_SRC_PORT_SHIFT 31
2363 #define GFT_RAM_LINE_DSCP_MASK 0x1
2364 #define GFT_RAM_LINE_DSCP_SHIFT 0
2365 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1
2366 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1
2367 #define GFT_RAM_LINE_DST_IP_MASK 0x1
2368 #define GFT_RAM_LINE_DST_IP_SHIFT 2
2369 #define GFT_RAM_LINE_SRC_IP_MASK 0x1
2370 #define GFT_RAM_LINE_SRC_IP_SHIFT 3
2371 #define GFT_RAM_LINE_PRIORITY_MASK 0x1
2372 #define GFT_RAM_LINE_PRIORITY_SHIFT 4
2373 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1
2374 #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5
2375 #define GFT_RAM_LINE_VLAN_MASK 0x1
2376 #define GFT_RAM_LINE_VLAN_SHIFT 6
2377 #define GFT_RAM_LINE_DST_MAC_MASK 0x1
2378 #define GFT_RAM_LINE_DST_MAC_SHIFT 7
2379 #define GFT_RAM_LINE_SRC_MAC_MASK 0x1
2380 #define GFT_RAM_LINE_SRC_MAC_SHIFT 8
2381 #define GFT_RAM_LINE_TENANT_ID_MASK 0x1
2382 #define GFT_RAM_LINE_TENANT_ID_SHIFT 9
2383 #define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF
2384 #define GFT_RAM_LINE_RESERVED1_SHIFT 10
2389 * Used in the first 2 bits for gft_ram_line: Indication for vlan mask
2391 enum gft_vlan_select {
2392 INNER_PROVIDER_VLAN = 0,
2394 OUTER_PROVIDER_VLAN = 2,
2400 #endif /* __ECORE_HSI_ETH__ */