2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #ifndef __ECORE_HSI_ETH__
10 #define __ECORE_HSI_ETH__
11 /************************************************************************/
12 /* Add include to common eth target for both eCore and protocol driver */
13 /************************************************************************/
14 #include "eth_common.h"
17 * The eth storm context for the Tstorm
19 struct tstorm_eth_conn_st_ctx {
24 * The eth storm context for the Pstorm
26 struct pstorm_eth_conn_st_ctx {
31 * The eth storm context for the Xstorm
33 struct xstorm_eth_conn_st_ctx {
37 struct xstorm_eth_conn_ag_ctx {
38 u8 reserved0 /* cdu_validation */;
39 u8 eth_state /* state */;
41 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
42 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
43 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
44 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
45 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
46 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
47 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
48 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
49 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
50 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
51 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
52 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
53 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
54 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
55 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
56 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
58 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
59 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
60 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
61 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
62 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
63 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
64 #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
65 #define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
66 #define XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1
67 #define XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4
68 #define XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1
69 #define XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5
70 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
71 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
72 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
73 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
75 #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
76 #define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
77 #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
78 #define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
79 #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
80 #define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
81 #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
82 #define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
84 #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
85 #define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
86 #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
87 #define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
88 #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
89 #define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
90 #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
91 #define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
93 #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
94 #define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
95 #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
96 #define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
97 #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
98 #define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
99 #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
100 #define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
102 #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
103 #define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
104 #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
105 #define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
106 #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
107 #define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
108 #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
109 #define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
111 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
112 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
113 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
114 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
115 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
116 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
117 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
118 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
120 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
121 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
122 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
123 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
124 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
125 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
126 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
127 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
128 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
129 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
131 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
132 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
133 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
134 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
135 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
136 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
137 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
138 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
139 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
140 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
141 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
142 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
143 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
144 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
145 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
146 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
148 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
149 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
150 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
151 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
152 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
153 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
154 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
155 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
156 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
157 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
158 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
159 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
160 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
161 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
162 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
163 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
165 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
166 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
167 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
168 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
169 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
170 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
171 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
172 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
173 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
174 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
175 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
176 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
177 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
178 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
179 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
180 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
182 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
183 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
184 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
185 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
186 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
187 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
188 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
189 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
190 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
191 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
192 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
193 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
194 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
195 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
196 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
197 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
199 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
200 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
201 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
202 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
203 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
204 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
205 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
206 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
207 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
208 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
209 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
210 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
211 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
212 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
213 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
214 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
216 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
217 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
218 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
219 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
220 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
221 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
222 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
223 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
224 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
225 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
226 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
227 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
228 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
229 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
230 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
231 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
233 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
234 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
235 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
236 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
237 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
238 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
239 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
240 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
241 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
242 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
243 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
244 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
245 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
246 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
247 u8 edpm_event_id /* byte2 */;
248 __le16 physical_q0 /* physical_q0 */;
249 __le16 quota /* physical_q1 */;
250 __le16 edpm_num_bds /* physical_q2 */;
251 __le16 tx_bd_cons /* word3 */;
252 __le16 tx_bd_prod /* word4 */;
253 __le16 tx_class /* word5 */;
254 __le16 conn_dpi /* conn_dpi */;
255 u8 byte3 /* byte3 */;
256 u8 byte4 /* byte4 */;
257 u8 byte5 /* byte5 */;
258 u8 byte6 /* byte6 */;
259 __le32 reg0 /* reg0 */;
260 __le32 reg1 /* reg1 */;
261 __le32 reg2 /* reg2 */;
262 __le32 reg3 /* reg3 */;
263 __le32 reg4 /* reg4 */;
264 __le32 reg5 /* cf_array0 */;
265 __le32 reg6 /* cf_array1 */;
266 __le16 word7 /* word7 */;
267 __le16 word8 /* word8 */;
268 __le16 word9 /* word9 */;
269 __le16 word10 /* word10 */;
270 __le32 reg7 /* reg7 */;
271 __le32 reg8 /* reg8 */;
272 __le32 reg9 /* reg9 */;
273 u8 byte7 /* byte7 */;
274 u8 byte8 /* byte8 */;
275 u8 byte9 /* byte9 */;
276 u8 byte10 /* byte10 */;
277 u8 byte11 /* byte11 */;
278 u8 byte12 /* byte12 */;
279 u8 byte13 /* byte13 */;
280 u8 byte14 /* byte14 */;
281 u8 byte15 /* byte15 */;
282 u8 byte16 /* byte16 */;
283 __le16 word11 /* word11 */;
284 __le32 reg10 /* reg10 */;
285 __le32 reg11 /* reg11 */;
286 __le32 reg12 /* reg12 */;
287 __le32 reg13 /* reg13 */;
288 __le32 reg14 /* reg14 */;
289 __le32 reg15 /* reg15 */;
290 __le32 reg16 /* reg16 */;
291 __le32 reg17 /* reg17 */;
292 __le32 reg18 /* reg18 */;
293 __le32 reg19 /* reg19 */;
294 __le16 word12 /* word12 */;
295 __le16 word13 /* word13 */;
296 __le16 word14 /* word14 */;
297 __le16 word15 /* word15 */;
301 * The eth storm context for the Ystorm
303 struct ystorm_eth_conn_st_ctx {
307 struct ystorm_eth_conn_ag_ctx {
308 u8 byte0 /* cdu_validation */;
309 u8 state /* state */;
311 #define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
312 #define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
313 #define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
314 #define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
315 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
316 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2
317 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3
318 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4
319 #define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
320 #define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
322 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
323 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
324 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
325 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1
326 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
327 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
328 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
329 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
330 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
331 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
332 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
333 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
334 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
335 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
336 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
337 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
338 u8 tx_q0_int_coallecing_timeset /* byte2 */;
339 u8 byte3 /* byte3 */;
340 __le16 word0 /* word0 */;
341 __le32 terminate_spqe /* reg0 */;
342 __le32 reg1 /* reg1 */;
343 __le16 tx_bd_cons_upd /* word1 */;
344 __le16 word2 /* word2 */;
345 __le16 word3 /* word3 */;
346 __le16 word4 /* word4 */;
347 __le32 reg2 /* reg2 */;
348 __le32 reg3 /* reg3 */;
351 struct tstorm_eth_conn_ag_ctx {
352 u8 byte0 /* cdu_validation */;
353 u8 byte1 /* state */;
355 #define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
356 #define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
357 #define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
358 #define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
359 #define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1
360 #define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
361 #define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1
362 #define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
363 #define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1
364 #define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
365 #define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1
366 #define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
367 #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
368 #define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
370 #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
371 #define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
372 #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
373 #define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
374 #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
375 #define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
376 #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
377 #define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
379 #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
380 #define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
381 #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
382 #define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
383 #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
384 #define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
385 #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
386 #define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
388 #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
389 #define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
390 #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
391 #define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
392 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
393 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
394 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
395 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
396 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
397 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
398 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
399 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
401 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
402 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
403 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
404 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
405 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
406 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
407 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
408 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
409 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
410 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
411 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
412 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
413 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
414 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
415 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
416 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
418 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
419 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
420 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
421 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
422 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
423 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
424 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
425 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
426 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
427 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
428 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1
429 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
430 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
431 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
432 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
433 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
434 __le32 reg0 /* reg0 */;
435 __le32 reg1 /* reg1 */;
436 __le32 reg2 /* reg2 */;
437 __le32 reg3 /* reg3 */;
438 __le32 reg4 /* reg4 */;
439 __le32 reg5 /* reg5 */;
440 __le32 reg6 /* reg6 */;
441 __le32 reg7 /* reg7 */;
442 __le32 reg8 /* reg8 */;
443 u8 byte2 /* byte2 */;
444 u8 byte3 /* byte3 */;
445 __le16 rx_bd_cons /* word0 */;
446 u8 byte4 /* byte4 */;
447 u8 byte5 /* byte5 */;
448 __le16 rx_bd_prod /* word1 */;
449 __le16 word2 /* conn_dpi */;
450 __le16 word3 /* word3 */;
451 __le32 reg9 /* reg9 */;
452 __le32 reg10 /* reg10 */;
455 struct ustorm_eth_conn_ag_ctx {
456 u8 byte0 /* cdu_validation */;
457 u8 byte1 /* state */;
459 #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
460 #define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
461 #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
462 #define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
463 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
464 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2
465 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
466 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4
467 #define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
468 #define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
470 #define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
471 #define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
472 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
473 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
474 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
475 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
476 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
477 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
479 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
480 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
481 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
482 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
483 #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
484 #define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
485 #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
486 #define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
487 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
488 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
489 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
490 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
491 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
492 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
493 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
494 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
496 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
497 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
498 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
499 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
500 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
501 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
502 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
503 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
504 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
505 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
506 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
507 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
508 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
509 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
510 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
511 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
512 u8 byte2 /* byte2 */;
513 u8 byte3 /* byte3 */;
514 __le16 word0 /* conn_dpi */;
515 __le16 tx_bd_cons /* word1 */;
516 __le32 reg0 /* reg0 */;
517 __le32 reg1 /* reg1 */;
518 __le32 reg2 /* reg2 */;
519 __le32 tx_int_coallecing_timeset /* reg3 */;
520 __le16 tx_drv_bd_cons /* word2 */;
521 __le16 rx_drv_cqe_cons /* word3 */;
525 * The eth storm context for the Ustorm
527 struct ustorm_eth_conn_st_ctx {
532 * The eth storm context for the Mstorm
534 struct mstorm_eth_conn_st_ctx {
539 * eth connection context
541 struct eth_conn_context {
542 struct tstorm_eth_conn_st_ctx tstorm_st_context
543 /* tstorm storm context */;
544 struct regpair tstorm_st_padding[2] /* padding */;
545 struct pstorm_eth_conn_st_ctx pstorm_st_context
546 /* pstorm storm context */;
547 struct xstorm_eth_conn_st_ctx xstorm_st_context
548 /* xstorm storm context */;
549 struct xstorm_eth_conn_ag_ctx xstorm_ag_context
550 /* xstorm aggregative context */;
551 struct ystorm_eth_conn_st_ctx ystorm_st_context
552 /* ystorm storm context */;
553 struct ystorm_eth_conn_ag_ctx ystorm_ag_context
554 /* ystorm aggregative context */;
555 struct tstorm_eth_conn_ag_ctx tstorm_ag_context
556 /* tstorm aggregative context */;
557 struct ustorm_eth_conn_ag_ctx ustorm_ag_context
558 /* ustorm aggregative context */;
559 struct ustorm_eth_conn_st_ctx ustorm_st_context
560 /* ustorm storm context */;
561 struct mstorm_eth_conn_st_ctx mstorm_st_context
562 /* mstorm storm context */;
566 * Ethernet filter types: mac/vlan/pair
568 enum eth_error_code {
569 ETH_OK = 0x00 /* command succeeded */,
570 ETH_FILTERS_MAC_ADD_FAIL_FULL
571 /* mac add filters command failed due to cam full state */,
572 ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2
573 /* mac add filters command failed due to mtt2 full state */,
574 ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2
575 /* mac add filters command failed due to duplicate mac address */,
576 ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2
577 /* mac add filters command failed due to duplicate mac address */,
578 ETH_FILTERS_MAC_DEL_FAIL_NOF
579 /* mac delete filters command failed due to not found state */,
580 ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2
581 /* mac delete filters command failed due to not found state */,
582 ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2
583 /* mac delete filters command failed due to not found state */,
584 ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC
585 /* mac add filters command failed due to MAC Address of
589 ETH_FILTERS_VLAN_ADD_FAIL_FULL
590 /* vlan add filters command failed due to cam full state */,
591 ETH_FILTERS_VLAN_ADD_FAIL_DUP
592 /* vlan add filters command failed due to duplicate VLAN filter */,
593 ETH_FILTERS_VLAN_DEL_FAIL_NOF
594 /* vlan delete filters command failed due to not found state */,
595 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1
596 /* vlan delete filters command failed due to not found state */,
597 ETH_FILTERS_PAIR_ADD_FAIL_DUP
598 /* pair add filters command failed due to duplicate request */,
599 ETH_FILTERS_PAIR_ADD_FAIL_FULL
600 /* pair add filters command failed due to full state */,
601 ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC
602 /* pair add filters command failed due to full state */,
603 ETH_FILTERS_PAIR_DEL_FAIL_NOF
604 /* pair add filters command failed due not found state */,
605 ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1
606 /* pair add filters command failed due not found state */,
607 ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC
608 /* pair add filters command failed due to MAC Address of
612 ETH_FILTERS_VNI_ADD_FAIL_FULL
613 /* vni add filters command failed due to cam full state */,
614 ETH_FILTERS_VNI_ADD_FAIL_DUP
615 /* vni add filters command failed due to duplicate VNI filter */,
620 * opcodes for the event ring
622 enum eth_event_opcode {
624 ETH_EVENT_VPORT_START,
625 ETH_EVENT_VPORT_UPDATE,
626 ETH_EVENT_VPORT_STOP,
627 ETH_EVENT_TX_QUEUE_START,
628 ETH_EVENT_TX_QUEUE_STOP,
629 ETH_EVENT_RX_QUEUE_START,
630 ETH_EVENT_RX_QUEUE_UPDATE,
631 ETH_EVENT_RX_QUEUE_STOP,
632 ETH_EVENT_FILTERS_UPDATE,
633 ETH_EVENT_RX_ADD_OPENFLOW_FILTER,
634 ETH_EVENT_RX_DELETE_OPENFLOW_FILTER,
635 ETH_EVENT_RX_CREATE_OPENFLOW_ACTION,
636 ETH_EVENT_RX_ADD_UDP_FILTER,
637 ETH_EVENT_RX_DELETE_UDP_FILTER,
638 ETH_EVENT_RX_CREATE_GFT_ACTION,
639 ETH_EVENT_RX_GFT_UPDATE_FILTER,
644 * Classify rule types in E2/E3
646 enum eth_filter_action {
647 ETH_FILTER_ACTION_UNUSED,
648 ETH_FILTER_ACTION_REMOVE,
649 ETH_FILTER_ACTION_ADD,
650 ETH_FILTER_ACTION_REMOVE_ALL
651 /* Remove all filters of given type and vport ID. */,
652 MAX_ETH_FILTER_ACTION
656 * Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$
658 struct eth_filter_cmd {
659 u8 type /* Filter Type (MAC/VLAN/Pair/VNI) */;
660 u8 vport_id /* the vport id */;
661 u8 action /* filter command action: add/remove/replace */;
671 * $$KEEP_ENDIANNESS$$
673 struct eth_filter_cmd_header {
674 u8 rx /* If set, apply these commands to the RX path */;
675 u8 tx /* If set, apply these commands to the TX path */;
676 u8 cmd_cnt /* Number of filter commands */;
682 * Ethernet filter types: mac/vlan/pair
684 enum eth_filter_type {
685 ETH_FILTER_TYPE_UNUSED,
686 ETH_FILTER_TYPE_MAC /* Add/remove a MAC address */,
687 ETH_FILTER_TYPE_VLAN /* Add/remove a VLAN */,
688 ETH_FILTER_TYPE_PAIR /* Add/remove a MAC-VLAN pair */,
689 ETH_FILTER_TYPE_INNER_MAC /* Add/remove a inner MAC address */,
690 ETH_FILTER_TYPE_INNER_VLAN /* Add/remove a inner VLAN */,
691 ETH_FILTER_TYPE_INNER_PAIR /* Add/remove a inner MAC-VLAN pair */,
692 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR /* Add/remove a inner MAC-VNI pair */
694 ETH_FILTER_TYPE_MAC_VNI_PAIR /* Add/remove a MAC-VNI pair */,
695 ETH_FILTER_TYPE_VNI /* Add/remove a VNI */,
700 * eth IPv4 Fragment Type
702 enum eth_ipv4_frag_type {
703 ETH_IPV4_NOT_FRAG /* IPV4 Packet Not Fragmented */,
705 /* First Fragment of IPv4 Packet (contains headers) */,
706 ETH_IPV4_NON_FIRST_FRAG
707 /* Non-First Fragment of IPv4 Packet (does not contain headers) */,
708 MAX_ETH_IPV4_FRAG_TYPE
712 * eth IPv4 Fragment Type
721 * Ethernet Ramrod Command IDs
723 enum eth_ramrod_cmd_id {
725 ETH_RAMROD_VPORT_START /* VPort Start Ramrod */,
726 ETH_RAMROD_VPORT_UPDATE /* VPort Update Ramrod */,
727 ETH_RAMROD_VPORT_STOP /* VPort Stop Ramrod */,
728 ETH_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */,
729 ETH_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */,
730 ETH_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */,
731 ETH_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */,
732 ETH_RAMROD_FILTERS_UPDATE /* Add or Remove Mac/Vlan/Pair filters */,
733 ETH_RAMROD_RX_QUEUE_UPDATE /* RX Queue Update Ramrod */,
734 /* RX - Create an Openflow Action */
735 ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION,
736 /* RX - Add an Openflow Filter to the Searcher */
737 ETH_RAMROD_RX_ADD_OPENFLOW_FILTER,
738 /* RX - Delete an Openflow Filter to the Searcher */
739 ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER,
740 /* RX - Add a UDP Filter to the Searcher */
741 ETH_RAMROD_RX_ADD_UDP_FILTER,
742 /* RX - Delete a UDP Filter to the Searcher */
743 ETH_RAMROD_RX_DELETE_UDP_FILTER,
744 ETH_RAMROD_RX_CREATE_GFT_ACTION /* RX - Create a Gft Action */,
745 /* RX - Add/Delete a GFT Filter to the Searcher */
746 ETH_RAMROD_GFT_UPDATE_FILTER,
747 MAX_ETH_RAMROD_CMD_ID
751 * return code from eth sp ramrods
753 struct eth_return_code {
755 #define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F
756 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
757 #define ETH_RETURN_CODE_RESERVED_MASK 0x3
758 #define ETH_RETURN_CODE_RESERVED_SHIFT 5
759 #define ETH_RETURN_CODE_RX_TX_MASK 0x1
760 #define ETH_RETURN_CODE_RX_TX_SHIFT 7
764 * What to do in case an error occurs
767 ETH_TX_ERR_DROP /* Drop erroneous packet. */,
768 ETH_TX_ERR_ASSERT_MALICIOUS
769 /* Assert an interrupt for PF, declare as malicious for VF */,
774 * Array of the different error type behaviors
776 struct eth_tx_err_vals {
778 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1
779 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0
780 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1
781 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1
782 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1
783 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2
784 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1
785 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3
786 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1
787 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4
788 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1
789 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5
790 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
791 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6
792 #define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF
793 #define ETH_TX_ERR_VALS_RESERVED_SHIFT 7
797 * vport rss configuration data
799 struct eth_vport_rss_config {
801 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
802 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0
803 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
804 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1
805 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
806 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2
807 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
808 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3
809 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
810 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4
811 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
812 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5
813 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
814 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
815 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF
816 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7
818 u8 rss_mode /* The RSS mode for this function */;
819 u8 update_rss_key /* if set update the rss key */;
820 u8 update_rss_ind_table /* if set update the indirection table */;
821 u8 update_rss_capabilities /* if set update the capabilities */;
822 u8 tbl_size /* rss mask (Tbl size) */;
824 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM]
825 /* RSS indirection table */;
826 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS] /* RSS key supplied to us by OS */
834 enum eth_vport_rss_mode {
835 ETH_VPORT_RSS_MODE_DISABLED /* RSS Disabled */,
836 ETH_VPORT_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */,
837 MAX_ETH_VPORT_RSS_MODE
841 * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$
843 struct eth_vport_rx_mode {
845 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
846 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0
847 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
848 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
849 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
850 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
851 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
852 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3
853 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
854 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4
855 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
856 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5
857 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF
858 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6
863 * Command for setting tpa parameters
865 struct eth_vport_tpa_param {
866 u8 tpa_ipv4_en_flg /* Enable TPA for IPv4 packets */;
867 u8 tpa_ipv6_en_flg /* Enable TPA for IPv6 packets */;
868 u8 tpa_ipv4_tunn_en_flg /* Enable TPA for IPv4 over tunnel */;
869 u8 tpa_ipv6_tunn_en_flg /* Enable TPA for IPv6 over tunnel */;
870 u8 tpa_pkt_split_flg;
871 u8 tpa_hdr_data_split_flg
872 /* If set, put header of first TPA segment on bd and data on SGE */
874 u8 tpa_gro_consistent_flg
875 /* If set, GRO data consistent will checked for TPA continue */;
877 /* maximum number of opened aggregations per v-port */;
878 __le16 tpa_max_size /* maximal size for the aggregated TPA packets */;
879 __le16 tpa_min_size_to_start
880 /* minimum TCP payload size for a packet to start aggregation */;
881 __le16 tpa_min_size_to_cont
882 /* minimum TCP payload size for a packet to continue aggregation */
885 /* maximal number of buffers that can be used for one aggregation */
891 * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$
893 struct eth_vport_tx_mode {
895 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
896 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0
897 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
898 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
899 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
900 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2
901 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
902 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
903 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
904 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
905 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF
906 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5
911 * Ramrod data for rx create gft action
913 enum gft_filter_update_action {
916 MAX_GFT_FILTER_UPDATE_ACTION
920 * Ramrod data for rx create gft action
922 enum gft_logic_filter_type {
923 GFT_FILTER_TYPE /* flow FW is GFT-logic as well */,
924 RFS_FILTER_TYPE /* flow FW is A-RFS-logic */,
925 MAX_GFT_LOGIC_FILTER_TYPE
929 * Ramrod data for rx add openflow filter
931 struct rx_add_openflow_filter_data {
932 __le16 action_icid /* CID of Action to run for this filter */;
933 u8 priority /* Searcher String - Packet priority */;
935 __le32 tenant_id /* Searcher String - Tenant ID */;
936 __le16 dst_mac_hi /* Searcher String - Destination Mac Bytes 0 to 1 */;
937 __le16 dst_mac_mid /* Searcher String - Destination Mac Bytes 2 to 3 */
939 __le16 dst_mac_lo /* Searcher String - Destination Mac Bytes 4 to 5 */;
940 __le16 src_mac_hi /* Searcher String - Source Mac 0 to 1 */;
941 __le16 src_mac_mid /* Searcher String - Source Mac 2 to 3 */;
942 __le16 src_mac_lo /* Searcher String - Source Mac 4 to 5 */;
943 __le16 vlan_id /* Searcher String - Vlan ID */;
944 __le16 l2_eth_type /* Searcher String - Last L2 Ethertype */;
945 u8 ipv4_dscp /* Searcher String - IPv4 6 MSBs of the TOS Field */;
946 u8 ipv4_frag_type /* Searcher String - IPv4 Fragmentation Type */;
947 u8 ipv4_over_ip /* Searcher String - IPv4 Over IP Type */;
948 u8 tenant_id_exists /* Searcher String - Tenant ID Exists */;
949 __le32 ipv4_dst_addr /* Searcher String - IPv4 Destination Address */;
950 __le32 ipv4_src_addr /* Searcher String - IPv4 Source Address */;
951 __le16 l4_dst_port /* Searcher String - TCP/UDP Destination Port */;
952 __le16 l4_src_port /* Searcher String - TCP/UDP Source Port */;
956 * Ramrod data for rx create gft action
958 struct rx_create_gft_action_data {
959 u8 vport_id /* Vport Id of GFT Action */;
964 * Ramrod data for rx create openflow action
966 struct rx_create_openflow_action_data {
967 u8 vport_id /* ID of RX queue */;
972 * Ramrod data for rx queue start ramrod
974 struct rx_queue_start_ramrod_data {
975 __le16 rx_queue_id /* ID of RX queue */;
976 __le16 num_of_pbl_pages /* Num of pages in CQE PBL */;
977 __le16 bd_max_bytes /* maximal bytes that can be places on the bd */;
978 __le16 sb_id /* Status block ID */;
979 u8 sb_index /* index of the protocol index */;
980 u8 vport_id /* ID of virtual port */;
981 u8 default_rss_queue_flg /* set queue as default rss queue if set */;
982 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
983 u8 complete_event_flg /* post completion to the event ring if set */;
984 u8 stats_counter_id /* Statistics counter ID */;
985 u8 pin_context /* Pin context in CCFC to improve performance */;
986 u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD/SGE fetch */;
987 u8 pxp_tph_valid_pkt /* PXP command TPH Valid - for packet placement */
990 /* PXP command Steering tag hint. Use enum pxp_tph_st_hint */;
991 __le16 pxp_st_index /* PXP command Steering tag index */;
993 /* Indicates that current queue belongs to poll-mode driver */;
996 /* Initial value for the toggle valid bit - used in PMD mode */;
997 /* Index of RX producers in VF zone. Used for VF only. */
999 /* Backward compatibility mode. If set, unprotected mStorm queue zone will used
1000 * for VF RX producers instead of VF zone.
1002 u8 vf_rx_prod_use_zone_a;
1004 __le16 reserved1 /* FW reserved. */;
1005 struct regpair cqe_pbl_addr /* Base address on host of CQE PBL */;
1006 struct regpair bd_base /* bd address of the first bd page */;
1007 struct regpair reserved2 /* FW reserved. */;
1011 * Ramrod data for rx queue stop ramrod
1013 struct rx_queue_stop_ramrod_data {
1014 __le16 rx_queue_id /* ID of RX queue */;
1015 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
1016 u8 complete_event_flg /* post completion to the event ring if set */;
1017 u8 vport_id /* ID of virtual port */;
1022 * Ramrod data for rx queue update ramrod
1024 struct rx_queue_update_ramrod_data {
1025 __le16 rx_queue_id /* ID of RX queue */;
1026 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
1027 u8 complete_event_flg /* post completion to the event ring if set */;
1028 u8 vport_id /* ID of virtual port */;
1030 u8 reserved1 /* FW reserved. */;
1031 u8 reserved2 /* FW reserved. */;
1032 u8 reserved3 /* FW reserved. */;
1033 __le16 reserved4 /* FW reserved. */;
1034 __le16 reserved5 /* FW reserved. */;
1035 struct regpair reserved6 /* FW reserved. */;
1039 * Ramrod data for rx Add UDP Filter
1041 struct rx_udp_filter_data {
1042 __le16 action_icid /* CID of Action to run for this filter */;
1043 __le16 vlan_id /* Searcher String - Vlan ID */;
1044 u8 ip_type /* Searcher String - IP Type */;
1045 u8 tenant_id_exists /* Searcher String - Tenant ID Exists */;
1047 __le32 ip_dst_addr[4];
1048 /* Searcher String-IP Dest Addr for IPv4 use ip_dst_addr[0] only */
1050 __le32 ip_src_addr[4]
1051 /* Searcher String-IP Src Addr, for IPv4 use ip_dst_addr[0] only */
1053 __le16 udp_dst_port /* Searcher String - UDP Destination Port */;
1054 __le16 udp_src_port /* Searcher String - UDP Source Port */;
1055 __le32 tenant_id /* Searcher String - Tenant ID */;
1059 * Ramrod to add filter - filter is packet headr of type of packet wished to
1060 * pass certin FW flow
1062 struct rx_update_gft_filter_data {
1063 /* Pointer to Packet Header That Defines GFT Filter */
1064 struct regpair pkt_hdr_addr;
1065 __le16 pkt_hdr_length /* Packet Header Length */;
1066 /* If is_rfs flag is set: Queue Id to associate filter with else: action icid */
1067 __le16 rx_qid_or_action_icid;
1068 /* Field is used if is_rfs flag is set: vport Id of which to associate filter
1072 /* Use enum to set type of flow using gft HW logic blocks */
1074 u8 filter_action /* Use to set type of action on filter */;
1079 * Ramrod data for tx queue start ramrod
1081 struct tx_queue_start_ramrod_data {
1082 __le16 sb_id /* Status block ID */;
1083 u8 sb_index /* Status block protocol index */;
1084 u8 vport_id /* VPort ID */;
1085 u8 reserved0 /* FW reserved. (qcn_rl_en) */;
1086 u8 stats_counter_id /* Statistics counter ID to use */;
1087 __le16 qm_pq_id /* QM PQ ID */;
1089 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
1090 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
1091 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
1092 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1
1093 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1
1094 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2
1095 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
1096 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3
1097 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
1098 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4
1099 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
1100 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5
1101 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3
1102 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6
1103 u8 pxp_st_hint /* PXP command Steering tag hint */;
1104 u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD fetch */;
1105 u8 pxp_tph_valid_pkt /* PXP command TPH Valid - for packet fetch */;
1106 __le16 pxp_st_index /* PXP command Steering tag index */;
1107 __le16 comp_agg_size /* TX completion min agg size - for PMD queues */;
1108 __le16 queue_zone_id /* queue zone ID to use */;
1109 __le16 reserved2 /* FW reserved. (test_dup_count) */;
1110 __le16 pbl_size /* Number of BD pages pointed by PBL */;
1112 /* unique Queue ID - currently used only by PMD flow */;
1113 /* Unique Same-As-Last Resource ID - improves performance for same-as-last
1114 * packets per connection (range 0..ETH_TX_NUM_SAME_AS_LAST_ENTRIES-1 IDs
1117 __le16 same_as_last_id;
1119 struct regpair pbl_base_addr /* address of the pbl page */;
1120 struct regpair bd_cons_address
1121 /* BD consumer address in host - for PMD queues */;
1125 * Ramrod data for tx queue stop ramrod
1127 struct tx_queue_stop_ramrod_data {
1132 * Ramrod data for vport update ramrod
1134 struct vport_filter_update_ramrod_data {
1135 struct eth_filter_cmd_header filter_cmd_hdr
1136 /* Header for Filter Commands (RX/TX, Add/Remove/Replace, etc) */;
1137 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT]
1138 /* Filter Commands */;
1142 * Ramrod data for vport start ramrod
1144 struct vport_start_ramrod_data {
1148 u8 drop_ttl0_en /* if set, drop packet with ttl=0 */;
1149 u8 inner_vlan_removal_en;
1150 struct eth_vport_rx_mode rx_mode /* Rx filter data */;
1151 struct eth_vport_tx_mode tx_mode /* Tx filter data */;
1152 struct eth_vport_tpa_param tpa_param /* TPA configuration parameters */
1154 __le16 default_vlan /* Default Vlan value to be forced by FW */;
1155 u8 tx_switching_en /* Tx switching is enabled for current Vport */;
1157 /* Anti-spoofing verification is set for current Vport */;
1159 /* If set, the default Vlan value is forced by the FW */;
1160 u8 handle_ptp_pkts /* If set, the vport handles PTP Timesync Packets */
1162 u8 silent_vlan_removal_en;
1163 /* If enable then innerVlan will be striped and not written to cqe */
1165 struct eth_tx_err_vals tx_err_behav
1166 /* Desired behavior per TX error type */;
1167 u8 zero_placement_offset;
1168 /* If set, Contorl frames will be filtered according to MAC check. */
1169 u8 ctl_frame_mac_check_en;
1170 /* If set, Contorl frames will be filtered according to ethtype check. */
1171 u8 ctl_frame_ethtype_check_en;
1176 * Ramrod data for vport stop ramrod
1178 struct vport_stop_ramrod_data {
1184 * Ramrod data for vport update ramrod
1186 struct vport_update_ramrod_data_cmn {
1188 u8 update_rx_active_flg /* set if rx active flag should be handled */;
1189 u8 rx_active_flg /* rx active flag value */;
1190 u8 update_tx_active_flg /* set if tx active flag should be handled */;
1191 u8 tx_active_flg /* tx active flag value */;
1192 u8 update_rx_mode_flg /* set if rx state data should be handled */;
1193 u8 update_tx_mode_flg /* set if tx state data should be handled */;
1194 u8 update_approx_mcast_flg
1195 /* set if approx. mcast data should be handled */;
1196 u8 update_rss_flg /* set if rss data should be handled */;
1197 u8 update_inner_vlan_removal_en_flg
1198 /* set if inner_vlan_removal_en should be handled */;
1199 u8 inner_vlan_removal_en;
1200 u8 update_tpa_param_flg;
1201 u8 update_tpa_en_flg /* set if tpa enable changes */;
1202 u8 update_tx_switching_en_flg
1203 /* set if tx switching en flag should be handled */;
1204 u8 tx_switching_en /* tx switching en value */;
1205 u8 update_anti_spoofing_en_flg
1206 /* set if anti spoofing flag should be handled */;
1207 u8 anti_spoofing_en /* Anti-spoofing verification en value */;
1208 u8 update_handle_ptp_pkts
1209 /* set if handle_ptp_pkts should be handled. */;
1210 u8 handle_ptp_pkts /* If set, the vport handles PTP Timesync Packets */
1212 u8 update_default_vlan_en_flg
1213 /* If set, the default Vlan enable flag is updated */;
1215 /* If set, the default Vlan value is forced by the FW */;
1216 u8 update_default_vlan_flg
1217 /* If set, the default Vlan value is updated */;
1218 __le16 default_vlan /* Default Vlan value to be forced by FW */;
1219 u8 update_accept_any_vlan_flg
1220 /* set if accept_any_vlan should be handled */;
1221 u8 accept_any_vlan /* accept_any_vlan updated value */;
1222 u8 silent_vlan_removal_en;
1224 /* If set, MTU will be updated. Vport must be not active. */;
1225 __le16 mtu /* New MTU value. Used if update_mtu_flg are set */;
1229 struct vport_update_ramrod_mcast {
1230 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS] /* multicast bins */;
1234 * Ramrod data for vport update ramrod
1236 struct vport_update_ramrod_data {
1237 struct vport_update_ramrod_data_cmn common
1238 /* Common data for all vport update ramrods */;
1239 struct eth_vport_rx_mode rx_mode /* vport rx mode bitmap */;
1240 struct eth_vport_tx_mode tx_mode /* vport tx mode bitmap */;
1241 struct eth_vport_tpa_param tpa_param /* TPA configuration parameters */
1243 struct vport_update_ramrod_mcast approx_mcast;
1244 struct eth_vport_rss_config rss_config /* rss config data */;
1248 * GFT CAM line struct
1250 struct gft_cam_line {
1252 #define GFT_CAM_LINE_VALID_MASK 0x1
1253 #define GFT_CAM_LINE_VALID_SHIFT 0
1254 #define GFT_CAM_LINE_DATA_MASK 0x3FFF
1255 #define GFT_CAM_LINE_DATA_SHIFT 1
1256 #define GFT_CAM_LINE_MASK_BITS_MASK 0x3FFF
1257 #define GFT_CAM_LINE_MASK_BITS_SHIFT 15
1258 #define GFT_CAM_LINE_RESERVED1_MASK 0x7
1259 #define GFT_CAM_LINE_RESERVED1_SHIFT 29
1263 * GFT CAM line struct (for driversim use)
1265 struct gft_cam_line_mapped {
1267 #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1
1268 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0
1269 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1
1270 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1
1271 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1
1272 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2
1273 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF
1274 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3
1275 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF
1276 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7
1277 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF
1278 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11
1279 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1
1280 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15
1281 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1
1282 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16
1283 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF
1284 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17
1285 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF
1286 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21
1287 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF
1288 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25
1289 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7
1290 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29
1293 union gft_cam_line_union {
1294 struct gft_cam_line cam_line;
1295 struct gft_cam_line_mapped cam_line_mapped;
1299 * Used in gft_profile_key: Indication for ip version
1301 enum gft_profile_ip_version {
1302 GFT_PROFILE_IPV4 = 0,
1303 GFT_PROFILE_IPV6 = 1,
1304 MAX_GFT_PROFILE_IP_VERSION
1308 * Profile key stucr fot GFT logic in Prs
1310 struct gft_profile_key {
1312 #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1
1313 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0
1314 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1
1315 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1
1316 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF
1317 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2
1318 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF
1319 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6
1320 #define GFT_PROFILE_KEY_PF_ID_MASK 0xF
1321 #define GFT_PROFILE_KEY_PF_ID_SHIFT 10
1322 #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3
1323 #define GFT_PROFILE_KEY_RESERVED0_SHIFT 14
1327 * Used in gft_profile_key: Indication for tunnel type
1329 enum gft_profile_tunnel_type {
1330 GFT_PROFILE_NO_TUNNEL = 0,
1331 GFT_PROFILE_VXLAN_TUNNEL = 1,
1332 GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2,
1333 GFT_PROFILE_GRE_IP_TUNNEL = 3,
1334 GFT_PROFILE_GENEVE_MAC_TUNNEL = 4,
1335 GFT_PROFILE_GENEVE_IP_TUNNEL = 5,
1336 MAX_GFT_PROFILE_TUNNEL_TYPE
1340 * Used in gft_profile_key: Indication for protocol type
1342 enum gft_profile_upper_protocol_type {
1343 GFT_PROFILE_ROCE_PROTOCOL = 0,
1344 GFT_PROFILE_RROCE_PROTOCOL = 1,
1345 GFT_PROFILE_FCOE_PROTOCOL = 2,
1346 GFT_PROFILE_ICMP_PROTOCOL = 3,
1347 GFT_PROFILE_ARP_PROTOCOL = 4,
1348 GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5,
1349 GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6,
1350 GFT_PROFILE_TCP_PROTOCOL = 7,
1351 GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8,
1352 GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9,
1353 GFT_PROFILE_UDP_PROTOCOL = 10,
1354 GFT_PROFILE_USER_IP_1_INNER = 11,
1355 GFT_PROFILE_USER_IP_2_OUTER = 12,
1356 GFT_PROFILE_USER_ETH_1_INNER = 13,
1357 GFT_PROFILE_USER_ETH_2_OUTER = 14,
1358 GFT_PROFILE_RAW = 15,
1359 MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE
1363 * GFT RAM line struct
1365 struct gft_ram_line {
1367 #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3
1368 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0
1369 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1
1370 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2
1371 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1
1372 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3
1373 #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1
1374 #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4
1375 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1
1376 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5
1377 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1
1378 #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6
1379 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1
1380 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7
1381 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1
1382 #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8
1383 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1
1384 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9
1385 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1
1386 #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10
1387 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1
1388 #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11
1389 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1
1390 #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12
1391 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1
1392 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13
1393 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1
1394 #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14
1395 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1
1396 #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15
1397 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1
1398 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16
1399 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1
1400 #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17
1401 #define GFT_RAM_LINE_TTL_MASK 0x1
1402 #define GFT_RAM_LINE_TTL_SHIFT 18
1403 #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1
1404 #define GFT_RAM_LINE_ETHERTYPE_SHIFT 19
1405 #define GFT_RAM_LINE_RESERVED0_MASK 0x1
1406 #define GFT_RAM_LINE_RESERVED0_SHIFT 20
1407 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1
1408 #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21
1409 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1
1410 #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22
1411 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1
1412 #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23
1413 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1
1414 #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24
1415 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1
1416 #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25
1417 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1
1418 #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26
1419 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1
1420 #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27
1421 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1
1422 #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28
1423 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1
1424 #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29
1425 #define GFT_RAM_LINE_DST_PORT_MASK 0x1
1426 #define GFT_RAM_LINE_DST_PORT_SHIFT 30
1427 #define GFT_RAM_LINE_SRC_PORT_MASK 0x1
1428 #define GFT_RAM_LINE_SRC_PORT_SHIFT 31
1430 #define GFT_RAM_LINE_DSCP_MASK 0x1
1431 #define GFT_RAM_LINE_DSCP_SHIFT 0
1432 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1
1433 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1
1434 #define GFT_RAM_LINE_DST_IP_MASK 0x1
1435 #define GFT_RAM_LINE_DST_IP_SHIFT 2
1436 #define GFT_RAM_LINE_SRC_IP_MASK 0x1
1437 #define GFT_RAM_LINE_SRC_IP_SHIFT 3
1438 #define GFT_RAM_LINE_PRIORITY_MASK 0x1
1439 #define GFT_RAM_LINE_PRIORITY_SHIFT 4
1440 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1
1441 #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5
1442 #define GFT_RAM_LINE_VLAN_MASK 0x1
1443 #define GFT_RAM_LINE_VLAN_SHIFT 6
1444 #define GFT_RAM_LINE_DST_MAC_MASK 0x1
1445 #define GFT_RAM_LINE_DST_MAC_SHIFT 7
1446 #define GFT_RAM_LINE_SRC_MAC_MASK 0x1
1447 #define GFT_RAM_LINE_SRC_MAC_SHIFT 8
1448 #define GFT_RAM_LINE_TENANT_ID_MASK 0x1
1449 #define GFT_RAM_LINE_TENANT_ID_SHIFT 9
1450 #define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF
1451 #define GFT_RAM_LINE_RESERVED1_SHIFT 10
1455 * Used in the first 2 bits for gft_ram_line: Indication for vlan mask
1457 enum gft_vlan_select {
1458 INNER_PROVIDER_VLAN = 0,
1460 OUTER_PROVIDER_VLAN = 2,
1465 struct mstorm_eth_conn_ag_ctx {
1466 u8 byte0 /* cdu_validation */;
1467 u8 byte1 /* state */;
1469 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
1470 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1471 #define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
1472 #define MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
1473 #define MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
1474 #define MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2
1475 #define MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
1476 #define MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4
1477 #define MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
1478 #define MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
1480 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
1481 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
1482 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
1483 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1
1484 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
1485 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
1486 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
1487 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
1488 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
1489 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
1490 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
1491 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
1492 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
1493 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
1494 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
1495 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
1496 __le16 word0 /* word0 */;
1497 __le16 word1 /* word1 */;
1498 __le32 reg0 /* reg0 */;
1499 __le32 reg1 /* reg1 */;
1503 struct xstormEthConnAgCtxDqExtLdPart {
1504 u8 reserved0 /* cdu_validation */;
1505 u8 eth_state /* state */;
1507 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
1508 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
1509 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1
1510 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1
1511 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1
1512 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2
1513 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
1514 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
1515 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1
1516 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4
1517 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1
1518 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5
1519 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1
1520 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6
1521 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1
1522 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7
1524 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1
1525 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0
1526 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1
1527 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1
1528 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1
1529 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2
1530 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
1531 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
1532 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
1533 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
1534 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_MASK 0x1
1535 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_SHIFT 5
1536 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1
1537 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6
1538 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1
1539 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7
1541 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
1542 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0
1543 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
1544 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2
1545 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
1546 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4
1547 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
1548 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6
1550 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
1551 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0
1552 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
1553 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2
1554 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
1555 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4
1556 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
1557 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6
1559 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
1560 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0
1561 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
1562 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2
1563 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
1564 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4
1565 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
1566 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6
1568 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
1569 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0
1570 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
1571 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2
1572 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
1573 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4
1574 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
1575 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6
1577 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
1578 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0
1579 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
1580 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2
1581 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
1582 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4
1583 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
1584 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6
1586 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
1587 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0
1588 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
1589 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2
1590 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
1591 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
1592 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
1593 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
1594 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
1595 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
1597 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
1598 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
1599 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
1600 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
1601 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
1602 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
1603 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
1604 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
1605 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
1606 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
1607 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1
1608 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5
1609 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
1610 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
1611 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
1612 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
1614 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
1615 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
1616 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
1617 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
1618 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
1619 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
1620 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
1621 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
1622 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
1623 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
1624 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
1625 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
1626 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1
1627 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6
1628 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1
1629 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7
1631 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1
1632 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0
1633 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1
1634 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1
1635 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1
1636 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2
1637 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1
1638 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3
1639 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
1640 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
1641 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1
1642 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5
1643 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1
1644 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6
1645 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1
1646 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7
1648 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1
1649 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0
1650 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1
1651 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1
1652 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1
1653 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2
1654 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
1655 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
1656 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
1657 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
1658 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
1659 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
1660 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
1661 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
1662 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
1663 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
1665 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
1666 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
1667 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
1668 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
1669 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
1670 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
1671 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
1672 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
1673 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
1674 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
1675 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
1676 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
1677 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
1678 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
1679 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
1680 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
1682 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
1683 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
1684 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
1685 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
1686 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
1687 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
1688 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
1689 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
1690 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
1691 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
1692 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
1693 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
1694 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
1695 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
1696 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
1697 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
1699 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1
1700 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0
1701 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1
1702 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1
1703 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1
1704 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2
1705 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1
1706 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3
1707 #define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1
1708 #define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4
1709 #define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
1710 #define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
1711 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
1712 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6
1713 u8 edpm_event_id /* byte2 */;
1714 __le16 physical_q0 /* physical_q0 */;
1715 __le16 quota /* physical_q1 */;
1716 __le16 edpm_num_bds /* physical_q2 */;
1717 __le16 tx_bd_cons /* word3 */;
1718 __le16 tx_bd_prod /* word4 */;
1719 __le16 tx_class /* word5 */;
1720 __le16 conn_dpi /* conn_dpi */;
1721 u8 byte3 /* byte3 */;
1722 u8 byte4 /* byte4 */;
1723 u8 byte5 /* byte5 */;
1724 u8 byte6 /* byte6 */;
1725 __le32 reg0 /* reg0 */;
1726 __le32 reg1 /* reg1 */;
1727 __le32 reg2 /* reg2 */;
1728 __le32 reg3 /* reg3 */;
1729 __le32 reg4 /* reg4 */;
1732 struct xstorm_eth_hw_conn_ag_ctx {
1733 u8 reserved0 /* cdu_validation */;
1734 u8 eth_state /* state */;
1736 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
1737 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1738 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
1739 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1
1740 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
1741 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2
1742 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
1743 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
1744 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
1745 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4
1746 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
1747 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5
1748 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1
1749 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6
1750 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1
1751 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7
1753 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1
1754 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0
1755 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1
1756 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1
1757 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
1758 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2
1759 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
1760 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3
1761 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK 0x1
1762 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT 4
1763 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK 0x1
1764 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT 5
1765 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
1766 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
1767 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
1768 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
1770 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
1771 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0
1772 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
1773 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2
1774 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
1775 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4
1776 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
1777 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6
1779 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3
1780 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0
1781 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3
1782 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2
1783 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3
1784 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4
1785 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3
1786 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6
1788 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3
1789 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0
1790 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3
1791 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2
1792 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3
1793 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4
1794 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3
1795 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6
1797 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3
1798 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
1799 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3
1800 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2
1801 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3
1802 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4
1803 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3
1804 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6
1806 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
1807 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
1808 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
1809 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
1810 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3
1811 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4
1812 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
1813 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
1815 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
1816 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
1817 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3
1818 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2
1819 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3
1820 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4
1821 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
1822 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6
1823 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
1824 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7
1826 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
1827 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0
1828 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
1829 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1
1830 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
1831 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2
1832 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
1833 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3
1834 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
1835 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4
1836 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
1837 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5
1838 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
1839 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6
1840 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
1841 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7
1843 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
1844 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0
1845 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
1846 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1
1847 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
1848 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2
1849 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
1850 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3
1851 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
1852 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4
1853 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
1854 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5
1855 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
1856 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
1857 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
1858 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
1860 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
1861 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
1862 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
1863 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
1864 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
1865 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
1866 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
1867 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3
1868 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
1869 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
1870 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
1871 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
1872 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
1873 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6
1874 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
1875 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7
1877 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
1878 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0
1879 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
1880 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1
1881 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
1882 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
1883 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
1884 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3
1885 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
1886 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4
1887 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
1888 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5
1889 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
1890 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
1891 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
1892 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7
1894 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
1895 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0
1896 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
1897 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1
1898 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
1899 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
1900 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
1901 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
1902 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
1903 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4
1904 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
1905 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5
1906 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
1907 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6
1908 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
1909 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7
1911 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
1912 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0
1913 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
1914 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1
1915 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
1916 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
1917 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
1918 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
1919 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
1920 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
1921 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
1922 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
1923 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
1924 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
1925 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
1926 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
1928 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
1929 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
1930 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
1931 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
1932 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
1933 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
1934 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
1935 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
1936 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
1937 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
1938 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
1939 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
1940 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
1941 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
1942 u8 edpm_event_id /* byte2 */;
1943 __le16 physical_q0 /* physical_q0 */;
1944 __le16 quota /* physical_q1 */;
1945 __le16 edpm_num_bds /* physical_q2 */;
1946 __le16 tx_bd_cons /* word3 */;
1947 __le16 tx_bd_prod /* word4 */;
1948 __le16 tx_class /* word5 */;
1949 __le16 conn_dpi /* conn_dpi */;
1952 #endif /* __ECORE_HSI_ETH__ */