2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #ifndef __ECORE_HSI_ETH__
10 #define __ECORE_HSI_ETH__
11 /************************************************************************/
12 /* Add include to common eth target for both eCore and protocol driver */
13 /************************************************************************/
14 #include "eth_common.h"
17 * The eth storm context for the Tstorm
19 struct tstorm_eth_conn_st_ctx {
24 * The eth storm context for the Pstorm
26 struct pstorm_eth_conn_st_ctx {
31 * The eth storm context for the Xstorm
33 struct xstorm_eth_conn_st_ctx {
37 struct e4_xstorm_eth_conn_ag_ctx {
38 u8 reserved0 /* cdu_validation */;
39 u8 eth_state /* state */;
42 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
43 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
45 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
46 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
48 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
49 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
51 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
52 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
54 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
55 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
57 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
58 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
60 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
61 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
63 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
64 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
67 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
68 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
70 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
71 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
73 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
74 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
76 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
77 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
79 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1
80 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4
82 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1
83 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5
85 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
86 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
88 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
89 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
92 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
93 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
95 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
96 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
98 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
99 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
101 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
102 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
105 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
106 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
108 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
109 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
111 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
112 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
114 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
115 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
118 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
119 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
121 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
122 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
124 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
125 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
127 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
128 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
131 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
132 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
134 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
135 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
137 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
138 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
140 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
141 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
144 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
145 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
147 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
148 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
150 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
151 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
153 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
154 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
157 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
158 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
160 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
161 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
163 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
164 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
166 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
167 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
169 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
170 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
173 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
174 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
176 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
177 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
179 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
180 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
182 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
183 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
185 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
186 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
188 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
189 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
191 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
192 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
194 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
195 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
198 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
199 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
201 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
202 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
204 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
205 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
207 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
208 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
210 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
211 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
213 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
214 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
216 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
217 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
219 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
220 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
223 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
224 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
226 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
227 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
229 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
230 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
232 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
233 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
235 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
236 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
238 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
239 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
241 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
242 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
244 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
245 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
248 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
249 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
251 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
252 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
254 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
255 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
257 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
258 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
260 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
261 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
263 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
264 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
266 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
267 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
269 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
270 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
273 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
274 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
276 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
277 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
279 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
280 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
282 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
283 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
285 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
286 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
288 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
289 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
291 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
292 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
294 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
295 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
298 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
299 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
301 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
302 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
304 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
305 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
307 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
308 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
310 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
311 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
313 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
314 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
316 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
317 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
319 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
320 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
323 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
324 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
326 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
327 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
329 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
330 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
332 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
333 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
335 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
336 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
338 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
339 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
341 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
342 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
343 u8 edpm_event_id /* byte2 */;
344 __le16 physical_q0 /* physical_q0 */;
345 __le16 e5_reserved1 /* physical_q1 */;
346 __le16 edpm_num_bds /* physical_q2 */;
347 __le16 tx_bd_cons /* word3 */;
348 __le16 tx_bd_prod /* word4 */;
349 __le16 tx_class /* word5 */;
350 __le16 conn_dpi /* conn_dpi */;
351 u8 byte3 /* byte3 */;
352 u8 byte4 /* byte4 */;
353 u8 byte5 /* byte5 */;
354 u8 byte6 /* byte6 */;
355 __le32 reg0 /* reg0 */;
356 __le32 reg1 /* reg1 */;
357 __le32 reg2 /* reg2 */;
358 __le32 reg3 /* reg3 */;
359 __le32 reg4 /* reg4 */;
360 __le32 reg5 /* cf_array0 */;
361 __le32 reg6 /* cf_array1 */;
362 __le16 word7 /* word7 */;
363 __le16 word8 /* word8 */;
364 __le16 word9 /* word9 */;
365 __le16 word10 /* word10 */;
366 __le32 reg7 /* reg7 */;
367 __le32 reg8 /* reg8 */;
368 __le32 reg9 /* reg9 */;
369 u8 byte7 /* byte7 */;
370 u8 byte8 /* byte8 */;
371 u8 byte9 /* byte9 */;
372 u8 byte10 /* byte10 */;
373 u8 byte11 /* byte11 */;
374 u8 byte12 /* byte12 */;
375 u8 byte13 /* byte13 */;
376 u8 byte14 /* byte14 */;
377 u8 byte15 /* byte15 */;
378 u8 e5_reserved /* e5_reserved */;
379 __le16 word11 /* word11 */;
380 __le32 reg10 /* reg10 */;
381 __le32 reg11 /* reg11 */;
382 __le32 reg12 /* reg12 */;
383 __le32 reg13 /* reg13 */;
384 __le32 reg14 /* reg14 */;
385 __le32 reg15 /* reg15 */;
386 __le32 reg16 /* reg16 */;
387 __le32 reg17 /* reg17 */;
388 __le32 reg18 /* reg18 */;
389 __le32 reg19 /* reg19 */;
390 __le16 word12 /* word12 */;
391 __le16 word13 /* word13 */;
392 __le16 word14 /* word14 */;
393 __le16 word15 /* word15 */;
397 * The eth storm context for the Ystorm
399 struct ystorm_eth_conn_st_ctx {
403 struct e4_ystorm_eth_conn_ag_ctx {
404 u8 byte0 /* cdu_validation */;
405 u8 state /* state */;
408 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
409 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
411 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
412 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
413 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf0 */
414 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2
415 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 /* cf1 */
416 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4
417 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
418 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
421 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
422 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
424 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
425 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1
427 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
428 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
430 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
431 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
433 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
434 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
436 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
437 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
439 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
440 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
442 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
443 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
444 u8 tx_q0_int_coallecing_timeset /* byte2 */;
445 u8 byte3 /* byte3 */;
446 __le16 word0 /* word0 */;
447 __le32 terminate_spqe /* reg0 */;
448 __le32 reg1 /* reg1 */;
449 __le16 tx_bd_cons_upd /* word1 */;
450 __le16 word2 /* word2 */;
451 __le16 word3 /* word3 */;
452 __le16 word4 /* word4 */;
453 __le32 reg2 /* reg2 */;
454 __le32 reg3 /* reg3 */;
457 struct e4_tstorm_eth_conn_ag_ctx {
458 u8 byte0 /* cdu_validation */;
459 u8 byte1 /* state */;
461 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
462 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
463 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
464 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
465 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
466 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
467 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
468 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
469 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
470 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
471 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
472 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
473 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
474 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
476 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
477 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
478 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
479 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
480 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
481 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
482 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
483 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
485 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
486 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
487 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
488 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
489 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
490 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
491 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
492 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
494 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
495 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
496 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
497 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
498 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
499 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
500 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
501 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
502 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
503 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
504 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
505 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
507 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
508 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
509 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
510 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
511 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
512 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
513 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
514 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
515 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
516 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
517 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
518 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
519 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
520 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
521 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
522 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
524 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
525 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
526 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
527 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
528 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
529 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
530 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
531 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
532 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
533 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
534 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 /* rule6en */
535 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
536 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
537 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
538 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
539 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
540 __le32 reg0 /* reg0 */;
541 __le32 reg1 /* reg1 */;
542 __le32 reg2 /* reg2 */;
543 __le32 reg3 /* reg3 */;
544 __le32 reg4 /* reg4 */;
545 __le32 reg5 /* reg5 */;
546 __le32 reg6 /* reg6 */;
547 __le32 reg7 /* reg7 */;
548 __le32 reg8 /* reg8 */;
549 u8 byte2 /* byte2 */;
550 u8 byte3 /* byte3 */;
551 __le16 rx_bd_cons /* word0 */;
552 u8 byte4 /* byte4 */;
553 u8 byte5 /* byte5 */;
554 __le16 rx_bd_prod /* word1 */;
555 __le16 word2 /* conn_dpi */;
556 __le16 word3 /* word3 */;
557 __le32 reg9 /* reg9 */;
558 __le32 reg10 /* reg10 */;
561 struct e4_ustorm_eth_conn_ag_ctx {
562 u8 byte0 /* cdu_validation */;
563 u8 byte1 /* state */;
566 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
567 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
569 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
570 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
572 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
573 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2
575 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
576 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4
578 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
579 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
582 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
583 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
585 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
586 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
588 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
589 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
591 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
592 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
595 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
596 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
598 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
599 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
601 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
602 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
604 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
605 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
607 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
608 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
610 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
611 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
613 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
614 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
616 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
617 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
620 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
621 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
623 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
624 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
626 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
627 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
629 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
630 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
632 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
633 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
635 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
636 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
638 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
639 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
641 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
642 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
643 u8 byte2 /* byte2 */;
644 u8 byte3 /* byte3 */;
645 __le16 word0 /* conn_dpi */;
646 __le16 tx_bd_cons /* word1 */;
647 __le32 reg0 /* reg0 */;
648 __le32 reg1 /* reg1 */;
649 __le32 reg2 /* reg2 */;
650 __le32 tx_int_coallecing_timeset /* reg3 */;
651 __le16 tx_drv_bd_cons /* word2 */;
652 __le16 rx_drv_cqe_cons /* word3 */;
656 * The eth storm context for the Ustorm
658 struct ustorm_eth_conn_st_ctx {
663 * The eth storm context for the Mstorm
665 struct mstorm_eth_conn_st_ctx {
670 * eth connection context
672 struct e4_eth_conn_context {
673 /* tstorm storm context */
674 struct tstorm_eth_conn_st_ctx tstorm_st_context;
675 struct regpair tstorm_st_padding[2] /* padding */;
676 /* pstorm storm context */
677 struct pstorm_eth_conn_st_ctx pstorm_st_context;
678 /* xstorm storm context */
679 struct xstorm_eth_conn_st_ctx xstorm_st_context;
680 /* xstorm aggregative context */
681 struct e4_xstorm_eth_conn_ag_ctx xstorm_ag_context;
682 /* ystorm storm context */
683 struct ystorm_eth_conn_st_ctx ystorm_st_context;
684 /* ystorm aggregative context */
685 struct e4_ystorm_eth_conn_ag_ctx ystorm_ag_context;
686 /* tstorm aggregative context */
687 struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context;
688 /* ustorm aggregative context */
689 struct e4_ustorm_eth_conn_ag_ctx ustorm_ag_context;
690 /* ustorm storm context */
691 struct ustorm_eth_conn_st_ctx ustorm_st_context;
692 /* mstorm storm context */
693 struct mstorm_eth_conn_st_ctx mstorm_st_context;
698 * Ethernet filter types: mac/vlan/pair
700 enum eth_error_code {
701 ETH_OK = 0x00 /* command succeeded */,
702 /* mac add filters command failed due to cam full state */
703 ETH_FILTERS_MAC_ADD_FAIL_FULL,
704 /* mac add filters command failed due to mtt2 full state */
705 ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2,
706 /* mac add filters command failed due to duplicate mac address */
707 ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2,
708 /* mac add filters command failed due to duplicate mac address */
709 ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2,
710 /* mac delete filters command failed due to not found state */
711 ETH_FILTERS_MAC_DEL_FAIL_NOF,
712 /* mac delete filters command failed due to not found state */
713 ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2,
714 /* mac delete filters command failed due to not found state */
715 ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2,
716 /* mac add filters command failed due to MAC Address of 00:00:00:00:00:00 */
717 ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC,
718 /* vlan add filters command failed due to cam full state */
719 ETH_FILTERS_VLAN_ADD_FAIL_FULL,
720 /* vlan add filters command failed due to duplicate VLAN filter */
721 ETH_FILTERS_VLAN_ADD_FAIL_DUP,
722 /* vlan delete filters command failed due to not found state */
723 ETH_FILTERS_VLAN_DEL_FAIL_NOF,
724 /* vlan delete filters command failed due to not found state */
725 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1,
726 /* pair add filters command failed due to duplicate request */
727 ETH_FILTERS_PAIR_ADD_FAIL_DUP,
728 /* pair add filters command failed due to full state */
729 ETH_FILTERS_PAIR_ADD_FAIL_FULL,
730 /* pair add filters command failed due to full state */
731 ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC,
732 /* pair add filters command failed due not found state */
733 ETH_FILTERS_PAIR_DEL_FAIL_NOF,
734 /* pair add filters command failed due not found state */
735 ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1,
736 /* pair add filters command failed due to MAC Address of 00:00:00:00:00:00 */
737 ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC,
738 /* vni add filters command failed due to cam full state */
739 ETH_FILTERS_VNI_ADD_FAIL_FULL,
740 /* vni add filters command failed due to duplicate VNI filter */
741 ETH_FILTERS_VNI_ADD_FAIL_DUP,
742 ETH_FILTERS_GFT_UPDATE_FAIL /* Fail update GFT filter. */,
748 * opcodes for the event ring
750 enum eth_event_opcode {
752 ETH_EVENT_VPORT_START,
753 ETH_EVENT_VPORT_UPDATE,
754 ETH_EVENT_VPORT_STOP,
755 ETH_EVENT_TX_QUEUE_START,
756 ETH_EVENT_TX_QUEUE_STOP,
757 ETH_EVENT_RX_QUEUE_START,
758 ETH_EVENT_RX_QUEUE_UPDATE,
759 ETH_EVENT_RX_QUEUE_STOP,
760 ETH_EVENT_FILTERS_UPDATE,
761 ETH_EVENT_RX_ADD_OPENFLOW_FILTER,
762 ETH_EVENT_RX_DELETE_OPENFLOW_FILTER,
763 ETH_EVENT_RX_CREATE_OPENFLOW_ACTION,
764 ETH_EVENT_RX_ADD_UDP_FILTER,
765 ETH_EVENT_RX_DELETE_UDP_FILTER,
766 ETH_EVENT_RX_CREATE_GFT_ACTION,
767 ETH_EVENT_RX_GFT_UPDATE_FILTER,
768 ETH_EVENT_TX_QUEUE_UPDATE,
774 * Classify rule types in E2/E3
776 enum eth_filter_action {
777 ETH_FILTER_ACTION_UNUSED,
778 ETH_FILTER_ACTION_REMOVE,
779 ETH_FILTER_ACTION_ADD,
780 /* Remove all filters of given type and vport ID. */
781 ETH_FILTER_ACTION_REMOVE_ALL,
782 MAX_ETH_FILTER_ACTION
787 * Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$
789 struct eth_filter_cmd {
790 u8 type /* Filter Type (MAC/VLAN/Pair/VNI) */;
791 u8 vport_id /* the vport id */;
792 u8 action /* filter command action: add/remove/replace */;
803 * $$KEEP_ENDIANNESS$$
805 struct eth_filter_cmd_header {
806 u8 rx /* If set, apply these commands to the RX path */;
807 u8 tx /* If set, apply these commands to the TX path */;
808 u8 cmd_cnt /* Number of filter commands */;
809 /* 0 - dont assert in case of filter configuration error. Just return an error
810 * code. 1 - assert in case of filter configuration error.
818 * Ethernet filter types: mac/vlan/pair
820 enum eth_filter_type {
821 ETH_FILTER_TYPE_UNUSED,
822 ETH_FILTER_TYPE_MAC /* Add/remove a MAC address */,
823 ETH_FILTER_TYPE_VLAN /* Add/remove a VLAN */,
824 ETH_FILTER_TYPE_PAIR /* Add/remove a MAC-VLAN pair */,
825 ETH_FILTER_TYPE_INNER_MAC /* Add/remove a inner MAC address */,
826 ETH_FILTER_TYPE_INNER_VLAN /* Add/remove a inner VLAN */,
827 ETH_FILTER_TYPE_INNER_PAIR /* Add/remove a inner MAC-VLAN pair */,
828 /* Add/remove a inner MAC-VNI pair */
829 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
830 ETH_FILTER_TYPE_MAC_VNI_PAIR /* Add/remove a MAC-VNI pair */,
831 ETH_FILTER_TYPE_VNI /* Add/remove a VNI */,
837 * eth IPv4 Fragment Type
839 enum eth_ipv4_frag_type {
840 ETH_IPV4_NOT_FRAG /* IPV4 Packet Not Fragmented */,
841 /* First Fragment of IPv4 Packet (contains headers) */
843 /* Non-First Fragment of IPv4 Packet (does not contain headers) */
844 ETH_IPV4_NON_FIRST_FRAG,
845 MAX_ETH_IPV4_FRAG_TYPE
850 * eth IPv4 Fragment Type
860 * Ethernet Ramrod Command IDs
862 enum eth_ramrod_cmd_id {
864 ETH_RAMROD_VPORT_START /* VPort Start Ramrod */,
865 ETH_RAMROD_VPORT_UPDATE /* VPort Update Ramrod */,
866 ETH_RAMROD_VPORT_STOP /* VPort Stop Ramrod */,
867 ETH_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */,
868 ETH_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */,
869 ETH_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */,
870 ETH_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */,
871 ETH_RAMROD_FILTERS_UPDATE /* Add or Remove Mac/Vlan/Pair filters */,
872 ETH_RAMROD_RX_QUEUE_UPDATE /* RX Queue Update Ramrod */,
873 /* RX - Create an Openflow Action */
874 ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION,
875 /* RX - Add an Openflow Filter to the Searcher */
876 ETH_RAMROD_RX_ADD_OPENFLOW_FILTER,
877 /* RX - Delete an Openflow Filter to the Searcher */
878 ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER,
879 /* RX - Add a UDP Filter to the Searcher */
880 ETH_RAMROD_RX_ADD_UDP_FILTER,
881 /* RX - Delete a UDP Filter to the Searcher */
882 ETH_RAMROD_RX_DELETE_UDP_FILTER,
883 ETH_RAMROD_RX_CREATE_GFT_ACTION /* RX - Create a Gft Action */,
884 /* RX - Add/Delete a GFT Filter to the Searcher */
885 ETH_RAMROD_GFT_UPDATE_FILTER,
886 ETH_RAMROD_TX_QUEUE_UPDATE /* TX Queue Update Ramrod */,
887 MAX_ETH_RAMROD_CMD_ID
892 * return code from eth sp ramrods
894 struct eth_return_code {
896 /* error code (use enum eth_error_code) */
897 #define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F
898 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
899 #define ETH_RETURN_CODE_RESERVED_MASK 0x3
900 #define ETH_RETURN_CODE_RESERVED_SHIFT 5
901 /* rx path - 0, tx path - 1 */
902 #define ETH_RETURN_CODE_RX_TX_MASK 0x1
903 #define ETH_RETURN_CODE_RX_TX_SHIFT 7
908 * What to do in case an error occurs
911 ETH_TX_ERR_DROP /* Drop erroneous packet. */,
912 /* Assert an interrupt for PF, declare as malicious for VF */
913 ETH_TX_ERR_ASSERT_MALICIOUS,
919 * Array of the different error type behaviors
921 struct eth_tx_err_vals {
923 /* Wrong VLAN insertion mode (use enum eth_tx_err) */
924 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1
925 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0
926 /* Packet is below minimal size (use enum eth_tx_err) */
927 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1
928 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1
929 /* Vport has sent spoofed packet (use enum eth_tx_err) */
930 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1
931 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2
932 /* Packet with illegal type of inband tag (use enum eth_tx_err) */
933 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1
934 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3
935 /* Packet marked for VLAN insertion when inband tag is present
936 * (use enum eth_tx_err)
938 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1
939 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4
940 /* Non LSO packet larger than MTU (use enum eth_tx_err) */
941 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1
942 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5
943 /* VF/PF has sent LLDP/PFC or any other type of control packet which is not
944 * allowed to (use enum eth_tx_err)
946 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
947 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6
948 #define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF
949 #define ETH_TX_ERR_VALS_RESERVED_SHIFT 7
954 * vport rss configuration data
956 struct eth_vport_rss_config {
958 /* configuration of the IpV4 2-tuple capability */
959 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
960 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0
961 /* configuration of the IpV6 2-tuple capability */
962 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
963 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1
964 /* configuration of the IpV4 4-tuple capability for TCP */
965 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
966 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2
967 /* configuration of the IpV6 4-tuple capability for TCP */
968 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
969 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3
970 /* configuration of the IpV4 4-tuple capability for UDP */
971 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
972 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4
973 /* configuration of the IpV6 4-tuple capability for UDP */
974 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
975 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5
976 /* configuration of the 5-tuple capability */
977 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
978 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
979 /* if set update the rss keys */
980 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF
981 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7
982 /* The RSS engine ID. Must be allocated to each vport with RSS enabled.
983 * Total number of RSS engines is ETH_RSS_ENGINE_NUM_ , according to chip type.
986 u8 rss_mode /* The RSS mode for this function */;
987 u8 update_rss_key /* if set update the rss key */;
988 /* if set update the indirection table values */
989 u8 update_rss_ind_table;
990 /* if set update the capabilities and indirection table size. */
991 u8 update_rss_capabilities;
992 u8 tbl_size /* rss mask (Tbl size) */;
994 /* RSS indirection table */
995 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
996 /* RSS key supplied to us by OS */
997 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
1003 * eth vport RSS mode
1005 enum eth_vport_rss_mode {
1006 ETH_VPORT_RSS_MODE_DISABLED /* RSS Disabled */,
1007 ETH_VPORT_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */,
1008 MAX_ETH_VPORT_RSS_MODE
1013 * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$
1015 struct eth_vport_rx_mode {
1017 /* drop all unicast packets */
1018 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
1019 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0
1020 /* accept all unicast packets (subject to vlan) */
1021 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
1022 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
1023 /* accept all unmatched unicast packets */
1024 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
1025 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
1026 /* drop all multicast packets */
1027 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
1028 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3
1029 /* accept all multicast packets (subject to vlan) */
1030 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
1031 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4
1032 /* accept all broadcast packets (subject to vlan) */
1033 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
1034 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5
1035 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF
1036 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6
1037 __le16 reserved2[3];
1042 * Command for setting tpa parameters
1044 struct eth_vport_tpa_param {
1045 u8 tpa_ipv4_en_flg /* Enable TPA for IPv4 packets */;
1046 u8 tpa_ipv6_en_flg /* Enable TPA for IPv6 packets */;
1047 u8 tpa_ipv4_tunn_en_flg /* Enable TPA for IPv4 over tunnel */;
1048 u8 tpa_ipv6_tunn_en_flg /* Enable TPA for IPv6 over tunnel */;
1049 /* If set, start each tpa segment on new SGE (GRO mode). One SGE per segment
1052 u8 tpa_pkt_split_flg;
1053 /* If set, put header of first TPA segment on bd and data on SGE */
1054 u8 tpa_hdr_data_split_flg;
1055 /* If set, GRO data consistent will checked for TPA continue */
1056 u8 tpa_gro_consistent_flg;
1057 /* maximum number of opened aggregations per v-port */
1058 u8 tpa_max_aggs_num;
1059 __le16 tpa_max_size /* maximal size for the aggregated TPA packets */;
1060 /* minimum TCP payload size for a packet to start aggregation */
1061 __le16 tpa_min_size_to_start;
1062 /* minimum TCP payload size for a packet to continue aggregation */
1063 __le16 tpa_min_size_to_cont;
1064 /* maximal number of buffers that can be used for one aggregation */
1071 * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$
1073 struct eth_vport_tx_mode {
1075 /* drop all unicast packets */
1076 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
1077 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0
1078 /* accept all unicast packets (subject to vlan) */
1079 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
1080 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
1081 /* drop all multicast packets */
1082 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
1083 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2
1084 /* accept all multicast packets (subject to vlan) */
1085 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
1086 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
1087 /* accept all broadcast packets (subject to vlan) */
1088 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
1089 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
1090 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF
1091 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5
1092 __le16 reserved2[3];
1097 * GFT filter update action type.
1099 enum gft_filter_update_action {
1102 MAX_GFT_FILTER_UPDATE_ACTION
1109 * Ramrod data for rx add openflow filter
1111 struct rx_add_openflow_filter_data {
1112 __le16 action_icid /* CID of Action to run for this filter */;
1113 u8 priority /* Searcher String - Packet priority */;
1115 __le32 tenant_id /* Searcher String - Tenant ID */;
1116 /* Searcher String - Destination Mac Bytes 0 to 1 */
1118 /* Searcher String - Destination Mac Bytes 2 to 3 */
1120 /* Searcher String - Destination Mac Bytes 4 to 5 */
1122 __le16 src_mac_hi /* Searcher String - Source Mac 0 to 1 */;
1123 __le16 src_mac_mid /* Searcher String - Source Mac 2 to 3 */;
1124 __le16 src_mac_lo /* Searcher String - Source Mac 4 to 5 */;
1125 __le16 vlan_id /* Searcher String - Vlan ID */;
1126 __le16 l2_eth_type /* Searcher String - Last L2 Ethertype */;
1127 u8 ipv4_dscp /* Searcher String - IPv4 6 MSBs of the TOS Field */;
1128 u8 ipv4_frag_type /* Searcher String - IPv4 Fragmentation Type */;
1129 u8 ipv4_over_ip /* Searcher String - IPv4 Over IP Type */;
1130 u8 tenant_id_exists /* Searcher String - Tenant ID Exists */;
1131 __le32 ipv4_dst_addr /* Searcher String - IPv4 Destination Address */;
1132 __le32 ipv4_src_addr /* Searcher String - IPv4 Source Address */;
1133 __le16 l4_dst_port /* Searcher String - TCP/UDP Destination Port */;
1134 __le16 l4_src_port /* Searcher String - TCP/UDP Source Port */;
1139 * Ramrod data for rx create gft action
1141 struct rx_create_gft_action_data {
1142 u8 vport_id /* Vport Id of GFT Action */;
1148 * Ramrod data for rx create openflow action
1150 struct rx_create_openflow_action_data {
1151 u8 vport_id /* ID of RX queue */;
1157 * Ramrod data for rx queue start ramrod
1159 struct rx_queue_start_ramrod_data {
1160 __le16 rx_queue_id /* ID of RX queue */;
1161 __le16 num_of_pbl_pages /* Number of pages in CQE PBL */;
1162 __le16 bd_max_bytes /* maximal bytes that can be places on the bd */;
1163 __le16 sb_id /* Status block ID */;
1164 u8 sb_index /* index of the protocol index */;
1165 u8 vport_id /* ID of virtual port */;
1166 u8 default_rss_queue_flg /* set queue as default rss queue if set */;
1167 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
1168 u8 complete_event_flg /* post completion to the event ring if set */;
1169 u8 stats_counter_id /* Statistics counter ID */;
1170 u8 pin_context /* Pin context in CCFC to improve performance */;
1171 u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD/SGE fetch */;
1172 /* PXP command TPH Valid - for packet placement */
1173 u8 pxp_tph_valid_pkt;
1174 /* PXP command Steering tag hint. Use enum pxp_tph_st_hint */
1176 __le16 pxp_st_index /* PXP command Steering tag index */;
1177 /* Indicates that current queue belongs to poll-mode driver */
1179 /* Indicates that the current queue is using the TX notification queue
1180 * mechanism - should be set only for PMD queue
1183 /* Initial value for the toggle valid bit - used in PMD mode */
1185 /* Index of RX producers in VF zone. Used for VF only. */
1186 u8 vf_rx_prod_index;
1187 /* Backward compatibility mode. If set, unprotected mStorm queue zone will used
1188 * for VF RX producers instead of VF zone.
1190 u8 vf_rx_prod_use_zone_a;
1192 __le16 reserved1 /* FW reserved. */;
1193 struct regpair cqe_pbl_addr /* Base address on host of CQE PBL */;
1194 struct regpair bd_base /* bd address of the first bd page */;
1195 struct regpair reserved2 /* FW reserved. */;
1200 * Ramrod data for rx queue stop ramrod
1202 struct rx_queue_stop_ramrod_data {
1203 __le16 rx_queue_id /* ID of RX queue */;
1204 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
1205 u8 complete_event_flg /* post completion to the event ring if set */;
1206 u8 vport_id /* ID of virtual port */;
1212 * Ramrod data for rx queue update ramrod
1214 struct rx_queue_update_ramrod_data {
1215 __le16 rx_queue_id /* ID of RX queue */;
1216 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
1217 u8 complete_event_flg /* post completion to the event ring if set */;
1218 u8 vport_id /* ID of virtual port */;
1220 u8 reserved1 /* FW reserved. */;
1221 u8 reserved2 /* FW reserved. */;
1222 u8 reserved3 /* FW reserved. */;
1223 __le16 reserved4 /* FW reserved. */;
1224 __le16 reserved5 /* FW reserved. */;
1225 struct regpair reserved6 /* FW reserved. */;
1230 * Ramrod data for rx Add UDP Filter
1232 struct rx_udp_filter_data {
1233 __le16 action_icid /* CID of Action to run for this filter */;
1234 __le16 vlan_id /* Searcher String - Vlan ID */;
1235 u8 ip_type /* Searcher String - IP Type */;
1236 u8 tenant_id_exists /* Searcher String - Tenant ID Exists */;
1238 /* Searcher String - IP Destination Address, for IPv4 use ip_dst_addr[0] only */
1239 __le32 ip_dst_addr[4];
1240 /* Searcher String - IP Source Address, for IPv4 use ip_dst_addr[0] only */
1241 __le32 ip_src_addr[4];
1242 __le16 udp_dst_port /* Searcher String - UDP Destination Port */;
1243 __le16 udp_src_port /* Searcher String - UDP Source Port */;
1244 __le32 tenant_id /* Searcher String - Tenant ID */;
1249 * add or delete GFT filter - filter is packet header of type of packet wished
1250 * to pass certain FW flow
1252 struct rx_update_gft_filter_data {
1253 /* Pointer to Packet Header That Defines GFT Filter */
1254 struct regpair pkt_hdr_addr;
1255 __le16 pkt_hdr_length /* Packet Header Length */;
1256 /* Action icid. Valid if action_icid_valid flag set. */
1258 __le16 rx_qid /* RX queue ID. Valid if rx_qid_valid set. */;
1259 __le16 flow_id /* RX flow ID. Valid if flow_id_valid set. */;
1260 u8 vport_id /* RX vport Id. */;
1261 /* If set, action_icid will used for GFT filter update. */
1262 u8 action_icid_valid;
1263 /* If set, rx_qid will used for traffic steering, in additional to vport_id.
1264 * flow_id_valid must be cleared. If cleared, queue ID will selected by RSS.
1267 /* If set, flow_id will reported by CQE, rx_qid_valid must be cleared. If
1268 * cleared, flow_id 0 will reported by CQE.
1271 u8 filter_action /* Use to set type of action on filter */;
1272 /* 0 - dont assert in case of error. Just return an error code. 1 - assert in
1282 * Ramrod data for tx queue start ramrod
1284 struct tx_queue_start_ramrod_data {
1285 __le16 sb_id /* Status block ID */;
1286 u8 sb_index /* Status block protocol index */;
1287 u8 vport_id /* VPort ID */;
1288 u8 reserved0 /* FW reserved. (qcn_rl_en) */;
1289 u8 stats_counter_id /* Statistics counter ID to use */;
1290 __le16 qm_pq_id /* QM PQ ID */;
1292 /* 0: Enable QM opportunistic flow. 1: Disable QM opportunistic flow */
1293 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
1294 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
1295 /* If set, Test Mode - packets will be duplicated by Xstorm handler */
1296 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
1297 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1
1298 /* If set, Test Mode - packets destination will be determined by dest_port_mode
1301 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1
1302 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2
1303 /* Indicates that current queue belongs to poll-mode driver */
1304 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
1305 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3
1306 /* Indicates that the current queue is using the TX notification queue
1307 * mechanism - should be set only for PMD queue
1309 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
1310 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4
1311 /* Pin context in CCFC to improve performance */
1312 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
1313 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5
1314 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3
1315 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6
1316 u8 pxp_st_hint /* PXP command Steering tag hint */;
1317 u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD fetch */;
1318 u8 pxp_tph_valid_pkt /* PXP command TPH Valid - for packet fetch */;
1319 __le16 pxp_st_index /* PXP command Steering tag index */;
1320 /* TX completion min agg size - for PMD queues */
1321 __le16 comp_agg_size;
1322 __le16 queue_zone_id /* queue zone ID to use */;
1323 __le16 reserved2 /* FW reserved. (test_dup_count) */;
1324 __le16 pbl_size /* Number of BD pages pointed by PBL */;
1325 /* unique Queue ID - currently used only by PMD flow */
1327 /* Unique Same-As-Last Resource ID - improves performance for same-as-last
1328 * packets per connection (range 0..ETH_TX_NUM_SAME_AS_LAST_ENTRIES-1 IDs
1331 __le16 same_as_last_id;
1333 struct regpair pbl_base_addr /* address of the pbl page */;
1334 /* BD consumer address in host - for PMD queues */
1335 struct regpair bd_cons_address;
1340 * Ramrod data for tx queue stop ramrod
1342 struct tx_queue_stop_ramrod_data {
1348 * Ramrod data for tx queue update ramrod
1350 struct tx_queue_update_ramrod_data {
1351 __le16 update_qm_pq_id_flg /* Flag to Update QM PQ ID */;
1352 __le16 qm_pq_id /* Updated QM PQ ID */;
1354 struct regpair reserved1[5];
1360 * Ramrod data for vport update ramrod
1362 struct vport_filter_update_ramrod_data {
1363 /* Header for Filter Commands (RX/TX, Add/Remove/Replace, etc) */
1364 struct eth_filter_cmd_header filter_cmd_hdr;
1365 /* Filter Commands */
1366 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
1371 * Ramrod data for vport start ramrod
1373 struct vport_start_ramrod_data {
1377 u8 drop_ttl0_en /* if set, drop packet with ttl=0 */;
1378 u8 inner_vlan_removal_en;
1379 struct eth_vport_rx_mode rx_mode /* Rx filter data */;
1380 struct eth_vport_tx_mode tx_mode /* Tx filter data */;
1381 /* TPA configuration parameters */
1382 struct eth_vport_tpa_param tpa_param;
1383 __le16 default_vlan /* Default Vlan value to be forced by FW */;
1384 u8 tx_switching_en /* Tx switching is enabled for current Vport */;
1385 /* Anti-spoofing verification is set for current Vport */
1386 u8 anti_spoofing_en;
1387 /* If set, the default Vlan value is forced by the FW */
1389 /* If set, the vport handles PTP Timesync Packets */
1391 /* If enable then innerVlan will be striped and not written to cqe */
1392 u8 silent_vlan_removal_en;
1393 /* If set untagged filter (vlan0) is added to current Vport, otherwise port is
1394 * marked as any-vlan
1397 /* Desired behavior per TX error type */
1398 struct eth_tx_err_vals tx_err_behav;
1399 /* If set, ETH header padding will not inserted. placement_offset will be zero.
1401 u8 zero_placement_offset;
1402 /* If set, control frames will be filtered according to MAC check. */
1403 u8 ctl_frame_mac_check_en;
1404 /* If set, control frames will be filtered according to ethtype check. */
1405 u8 ctl_frame_ethtype_check_en;
1411 * Ramrod data for vport stop ramrod
1413 struct vport_stop_ramrod_data {
1420 * Ramrod data for vport update ramrod
1422 struct vport_update_ramrod_data_cmn {
1424 u8 update_rx_active_flg /* set if rx active flag should be handled */;
1425 u8 rx_active_flg /* rx active flag value */;
1426 u8 update_tx_active_flg /* set if tx active flag should be handled */;
1427 u8 tx_active_flg /* tx active flag value */;
1428 u8 update_rx_mode_flg /* set if rx state data should be handled */;
1429 u8 update_tx_mode_flg /* set if tx state data should be handled */;
1430 /* set if approx. mcast data should be handled */
1431 u8 update_approx_mcast_flg;
1432 u8 update_rss_flg /* set if rss data should be handled */;
1433 /* set if inner_vlan_removal_en should be handled */
1434 u8 update_inner_vlan_removal_en_flg;
1435 u8 inner_vlan_removal_en;
1436 /* set if tpa parameters should be handled, TPA must be disable before */
1437 u8 update_tpa_param_flg;
1438 u8 update_tpa_en_flg /* set if tpa enable changes */;
1439 /* set if tx switching en flag should be handled */
1440 u8 update_tx_switching_en_flg;
1441 u8 tx_switching_en /* tx switching en value */;
1442 /* set if anti spoofing flag should be handled */
1443 u8 update_anti_spoofing_en_flg;
1444 u8 anti_spoofing_en /* Anti-spoofing verification en value */;
1445 /* set if handle_ptp_pkts should be handled. */
1446 u8 update_handle_ptp_pkts;
1447 /* If set, the vport handles PTP Timesync Packets */
1449 /* If set, the default Vlan enable flag is updated */
1450 u8 update_default_vlan_en_flg;
1451 /* If set, the default Vlan value is forced by the FW */
1453 /* If set, the default Vlan value is updated */
1454 u8 update_default_vlan_flg;
1455 __le16 default_vlan /* Default Vlan value to be forced by FW */;
1456 /* set if accept_any_vlan should be handled */
1457 u8 update_accept_any_vlan_flg;
1458 u8 accept_any_vlan /* accept_any_vlan updated value */;
1459 /* Set to remove vlan silently, update_inner_vlan_removal_en_flg must be enabled
1460 * as well. If Rx is in noSgl mode send rx_queue_update_ramrod_data
1462 u8 silent_vlan_removal_en;
1463 /* If set, MTU will be updated. Vport must be not active. */
1465 __le16 mtu /* New MTU value. Used if update_mtu_flg are set */;
1466 /* If set, ctl_frame_mac_check_en and ctl_frame_ethtype_check_en will be
1469 u8 update_ctl_frame_checks_en_flg;
1470 /* If set, control frames will be filtered according to MAC check. */
1471 u8 ctl_frame_mac_check_en;
1472 /* If set, control frames will be filtered according to ethtype check. */
1473 u8 ctl_frame_ethtype_check_en;
1477 struct vport_update_ramrod_mcast {
1478 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS] /* multicast bins */;
1482 * Ramrod data for vport update ramrod
1484 struct vport_update_ramrod_data {
1485 /* Common data for all vport update ramrods */
1486 struct vport_update_ramrod_data_cmn common;
1487 struct eth_vport_rx_mode rx_mode /* vport rx mode bitmap */;
1488 struct eth_vport_tx_mode tx_mode /* vport tx mode bitmap */;
1489 /* TPA configuration parameters */
1490 struct eth_vport_tpa_param tpa_param;
1491 struct vport_update_ramrod_mcast approx_mcast;
1492 struct eth_vport_rss_config rss_config /* rss config data */;
1500 struct E4XstormEthConnAgCtxDqExtLdPart {
1501 u8 reserved0 /* cdu_validation */;
1502 u8 eth_state /* state */;
1505 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
1506 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
1508 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1
1509 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1
1511 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1
1512 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2
1514 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
1515 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
1517 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1
1518 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4
1519 /* cf_array_active */
1520 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1
1521 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5
1523 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1
1524 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6
1526 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1
1527 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7
1530 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1
1531 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0
1533 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1
1534 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1
1536 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1
1537 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2
1539 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
1540 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
1542 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
1543 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
1545 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_MASK 0x1
1546 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_SHIFT 5
1548 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1
1549 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6
1551 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1
1552 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7
1555 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
1556 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0
1558 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
1559 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2
1561 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
1562 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4
1563 /* timer_stop_all */
1564 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
1565 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6
1568 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
1569 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0
1571 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
1572 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2
1574 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
1575 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4
1577 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
1578 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6
1581 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
1582 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0
1584 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
1585 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2
1587 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
1588 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4
1590 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
1591 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6
1594 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
1595 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0
1597 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
1598 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2
1600 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
1601 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4
1603 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
1604 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6
1607 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
1608 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0
1610 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
1611 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2
1613 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
1614 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4
1616 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
1617 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6
1620 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
1621 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0
1623 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
1624 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2
1626 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
1627 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
1629 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
1630 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
1632 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
1633 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
1636 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
1637 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
1639 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
1640 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
1642 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
1643 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
1645 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
1646 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
1648 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
1649 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
1651 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1
1652 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5
1654 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
1655 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
1657 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
1658 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
1661 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
1662 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
1664 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
1665 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
1667 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
1668 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
1670 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
1671 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
1673 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
1674 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
1676 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
1677 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
1679 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1
1680 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6
1681 /* cf_array_cf_en */
1682 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1
1683 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7
1686 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1
1687 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0
1689 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1
1690 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1
1692 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1
1693 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2
1695 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1
1696 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3
1698 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
1699 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
1701 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1
1702 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5
1704 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1
1705 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6
1707 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1
1708 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7
1711 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1
1712 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0
1714 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1
1715 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1
1717 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1
1718 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2
1720 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
1721 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
1723 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
1724 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
1726 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
1727 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
1729 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
1730 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
1732 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
1733 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
1736 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
1737 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
1739 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
1740 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
1742 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
1743 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
1745 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
1746 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
1748 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
1749 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
1751 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
1752 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
1754 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
1755 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
1757 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
1758 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
1761 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
1762 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
1764 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
1765 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
1767 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
1768 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
1770 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
1771 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
1773 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
1774 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
1776 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
1777 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
1779 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
1780 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
1782 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
1783 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
1786 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1
1787 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0
1789 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1
1790 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1
1792 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1
1793 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2
1795 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1
1796 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3
1798 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1
1799 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4
1801 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
1802 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
1804 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
1805 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6
1806 u8 edpm_event_id /* byte2 */;
1807 __le16 physical_q0 /* physical_q0 */;
1808 __le16 e5_reserved1 /* physical_q1 */;
1809 __le16 edpm_num_bds /* physical_q2 */;
1810 __le16 tx_bd_cons /* word3 */;
1811 __le16 tx_bd_prod /* word4 */;
1812 __le16 tx_class /* word5 */;
1813 __le16 conn_dpi /* conn_dpi */;
1814 u8 byte3 /* byte3 */;
1815 u8 byte4 /* byte4 */;
1816 u8 byte5 /* byte5 */;
1817 u8 byte6 /* byte6 */;
1818 __le32 reg0 /* reg0 */;
1819 __le32 reg1 /* reg1 */;
1820 __le32 reg2 /* reg2 */;
1821 __le32 reg3 /* reg3 */;
1822 __le32 reg4 /* reg4 */;
1826 struct e4_mstorm_eth_conn_ag_ctx {
1827 u8 byte0 /* cdu_validation */;
1828 u8 byte1 /* state */;
1830 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1831 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1832 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1833 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
1834 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
1835 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2
1836 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1837 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4
1838 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
1839 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
1841 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1842 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
1843 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1844 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1
1845 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1846 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
1847 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1848 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
1849 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1850 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
1851 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1852 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
1853 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1854 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
1855 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1856 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
1857 __le16 word0 /* word0 */;
1858 __le16 word1 /* word1 */;
1859 __le32 reg0 /* reg0 */;
1860 __le32 reg1 /* reg1 */;
1867 struct e4_xstorm_eth_hw_conn_ag_ctx {
1868 u8 reserved0 /* cdu_validation */;
1869 u8 eth_state /* state */;
1872 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
1873 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1875 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
1876 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1
1878 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
1879 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2
1881 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
1882 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
1884 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
1885 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4
1886 /* cf_array_active */
1887 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
1888 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5
1889 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */
1890 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6
1891 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */
1892 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7
1894 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */
1895 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0
1896 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */
1897 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1
1899 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
1900 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2
1902 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
1903 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3
1905 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK 0x1
1906 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT 4
1908 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK 0x1
1909 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT 5
1911 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
1912 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
1914 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
1915 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
1918 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
1919 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0
1921 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
1922 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2
1924 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
1925 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4
1926 /* timer_stop_all */
1927 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
1928 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6
1930 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
1931 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0
1932 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
1933 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2
1934 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
1935 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4
1936 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
1937 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6
1939 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
1940 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0
1941 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
1942 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2
1943 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
1944 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4
1945 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
1946 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6
1948 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
1949 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
1950 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
1951 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2
1952 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */
1953 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4
1954 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
1955 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6
1957 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */
1958 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
1960 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
1961 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
1962 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */
1963 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4
1964 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */
1965 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
1967 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */
1968 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
1969 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */
1970 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2
1971 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
1972 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4
1974 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
1975 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6
1977 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
1978 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7
1981 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
1982 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0
1984 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
1985 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1
1987 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
1988 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2
1990 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
1991 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3
1993 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
1994 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4
1996 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
1997 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5
1999 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
2000 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6
2002 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
2003 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7
2006 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
2007 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0
2009 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
2010 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1
2012 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
2013 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2
2015 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
2016 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3
2018 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
2019 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4
2021 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
2022 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5
2024 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
2025 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
2026 /* cf_array_cf_en */
2027 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
2028 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
2031 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
2032 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
2034 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
2035 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
2037 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
2038 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
2040 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
2041 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3
2043 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
2044 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
2046 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
2047 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
2049 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
2050 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6
2052 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
2053 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7
2056 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
2057 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0
2059 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
2060 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1
2062 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
2063 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
2065 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
2066 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3
2068 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
2069 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4
2071 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
2072 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5
2074 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
2075 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
2077 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
2078 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7
2081 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
2082 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0
2084 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
2085 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1
2087 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
2088 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
2090 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
2091 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
2093 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
2094 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4
2096 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
2097 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5
2099 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
2100 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6
2102 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
2103 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7
2106 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
2107 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0
2109 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
2110 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1
2112 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
2113 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
2115 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
2116 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
2118 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
2119 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
2121 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
2122 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
2124 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
2125 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
2127 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
2128 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
2131 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
2132 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
2134 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
2135 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
2137 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
2138 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
2140 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
2141 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
2143 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
2144 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
2146 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
2147 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
2148 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */
2149 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
2150 u8 edpm_event_id /* byte2 */;
2151 __le16 physical_q0 /* physical_q0 */;
2152 __le16 e5_reserved1 /* physical_q1 */;
2153 __le16 edpm_num_bds /* physical_q2 */;
2154 __le16 tx_bd_cons /* word3 */;
2155 __le16 tx_bd_prod /* word4 */;
2156 __le16 tx_class /* word5 */;
2157 __le16 conn_dpi /* conn_dpi */;
2163 * GFT CAM line struct
2165 struct gft_cam_line {
2167 /* Indication if the line is valid. */
2168 #define GFT_CAM_LINE_VALID_MASK 0x1
2169 #define GFT_CAM_LINE_VALID_SHIFT 0
2170 /* Data bits, the word that compared with the profile key */
2171 #define GFT_CAM_LINE_DATA_MASK 0x3FFF
2172 #define GFT_CAM_LINE_DATA_SHIFT 1
2173 /* Mask bits, indicate the bits in the data that are Dont-Care */
2174 #define GFT_CAM_LINE_MASK_BITS_MASK 0x3FFF
2175 #define GFT_CAM_LINE_MASK_BITS_SHIFT 15
2176 #define GFT_CAM_LINE_RESERVED1_MASK 0x7
2177 #define GFT_CAM_LINE_RESERVED1_SHIFT 29
2182 * GFT CAM line struct (for driversim use)
2184 struct gft_cam_line_mapped {
2186 /* Indication if the line is valid. */
2187 #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1
2188 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0
2189 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
2190 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1
2191 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1
2192 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
2193 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1
2194 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2
2195 /* use enum gft_profile_upper_protocol_type
2196 * (use enum gft_profile_upper_protocol_type)
2198 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF
2199 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3
2200 /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */
2201 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF
2202 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7
2203 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF
2204 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11
2205 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
2206 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1
2207 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15
2208 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
2209 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1
2210 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16
2211 /* use enum gft_profile_upper_protocol_type
2212 * (use enum gft_profile_upper_protocol_type)
2214 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF
2215 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17
2216 /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */
2217 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF
2218 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21
2219 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF
2220 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25
2221 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7
2222 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29
2226 union gft_cam_line_union {
2227 struct gft_cam_line cam_line;
2228 struct gft_cam_line_mapped cam_line_mapped;
2233 * Used in gft_profile_key: Indication for ip version
2235 enum gft_profile_ip_version {
2236 GFT_PROFILE_IPV4 = 0,
2237 GFT_PROFILE_IPV6 = 1,
2238 MAX_GFT_PROFILE_IP_VERSION
2243 * Profile key stucr fot GFT logic in Prs
2245 struct gft_profile_key {
2247 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
2248 #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1
2249 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0
2250 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
2251 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1
2252 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1
2253 /* use enum gft_profile_upper_protocol_type
2254 * (use enum gft_profile_upper_protocol_type)
2256 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF
2257 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2
2258 /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */
2259 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF
2260 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6
2261 #define GFT_PROFILE_KEY_PF_ID_MASK 0xF
2262 #define GFT_PROFILE_KEY_PF_ID_SHIFT 10
2263 #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3
2264 #define GFT_PROFILE_KEY_RESERVED0_SHIFT 14
2269 * Used in gft_profile_key: Indication for tunnel type
2271 enum gft_profile_tunnel_type {
2272 GFT_PROFILE_NO_TUNNEL = 0,
2273 GFT_PROFILE_VXLAN_TUNNEL = 1,
2274 GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2,
2275 GFT_PROFILE_GRE_IP_TUNNEL = 3,
2276 GFT_PROFILE_GENEVE_MAC_TUNNEL = 4,
2277 GFT_PROFILE_GENEVE_IP_TUNNEL = 5,
2278 MAX_GFT_PROFILE_TUNNEL_TYPE
2283 * Used in gft_profile_key: Indication for protocol type
2285 enum gft_profile_upper_protocol_type {
2286 GFT_PROFILE_ROCE_PROTOCOL = 0,
2287 GFT_PROFILE_RROCE_PROTOCOL = 1,
2288 GFT_PROFILE_FCOE_PROTOCOL = 2,
2289 GFT_PROFILE_ICMP_PROTOCOL = 3,
2290 GFT_PROFILE_ARP_PROTOCOL = 4,
2291 GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5,
2292 GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6,
2293 GFT_PROFILE_TCP_PROTOCOL = 7,
2294 GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8,
2295 GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9,
2296 GFT_PROFILE_UDP_PROTOCOL = 10,
2297 GFT_PROFILE_USER_IP_1_INNER = 11,
2298 GFT_PROFILE_USER_IP_2_OUTER = 12,
2299 GFT_PROFILE_USER_ETH_1_INNER = 13,
2300 GFT_PROFILE_USER_ETH_2_OUTER = 14,
2301 GFT_PROFILE_RAW = 15,
2302 MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE
2307 * GFT RAM line struct
2309 struct gft_ram_line {
2311 #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3
2312 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0
2313 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1
2314 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2
2315 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1
2316 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3
2317 #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1
2318 #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4
2319 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1
2320 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5
2321 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1
2322 #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6
2323 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1
2324 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7
2325 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1
2326 #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8
2327 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1
2328 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9
2329 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1
2330 #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10
2331 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1
2332 #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11
2333 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1
2334 #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12
2335 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1
2336 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13
2337 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1
2338 #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14
2339 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1
2340 #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15
2341 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1
2342 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16
2343 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1
2344 #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17
2345 #define GFT_RAM_LINE_TTL_MASK 0x1
2346 #define GFT_RAM_LINE_TTL_SHIFT 18
2347 #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1
2348 #define GFT_RAM_LINE_ETHERTYPE_SHIFT 19
2349 #define GFT_RAM_LINE_RESERVED0_MASK 0x1
2350 #define GFT_RAM_LINE_RESERVED0_SHIFT 20
2351 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1
2352 #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21
2353 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1
2354 #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22
2355 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1
2356 #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23
2357 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1
2358 #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24
2359 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1
2360 #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25
2361 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1
2362 #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26
2363 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1
2364 #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27
2365 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1
2366 #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28
2367 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1
2368 #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29
2369 #define GFT_RAM_LINE_DST_PORT_MASK 0x1
2370 #define GFT_RAM_LINE_DST_PORT_SHIFT 30
2371 #define GFT_RAM_LINE_SRC_PORT_MASK 0x1
2372 #define GFT_RAM_LINE_SRC_PORT_SHIFT 31
2374 #define GFT_RAM_LINE_DSCP_MASK 0x1
2375 #define GFT_RAM_LINE_DSCP_SHIFT 0
2376 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1
2377 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1
2378 #define GFT_RAM_LINE_DST_IP_MASK 0x1
2379 #define GFT_RAM_LINE_DST_IP_SHIFT 2
2380 #define GFT_RAM_LINE_SRC_IP_MASK 0x1
2381 #define GFT_RAM_LINE_SRC_IP_SHIFT 3
2382 #define GFT_RAM_LINE_PRIORITY_MASK 0x1
2383 #define GFT_RAM_LINE_PRIORITY_SHIFT 4
2384 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1
2385 #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5
2386 #define GFT_RAM_LINE_VLAN_MASK 0x1
2387 #define GFT_RAM_LINE_VLAN_SHIFT 6
2388 #define GFT_RAM_LINE_DST_MAC_MASK 0x1
2389 #define GFT_RAM_LINE_DST_MAC_SHIFT 7
2390 #define GFT_RAM_LINE_SRC_MAC_MASK 0x1
2391 #define GFT_RAM_LINE_SRC_MAC_SHIFT 8
2392 #define GFT_RAM_LINE_TENANT_ID_MASK 0x1
2393 #define GFT_RAM_LINE_TENANT_ID_SHIFT 9
2394 #define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF
2395 #define GFT_RAM_LINE_RESERVED1_SHIFT 10
2400 * Used in the first 2 bits for gft_ram_line: Indication for vlan mask
2402 enum gft_vlan_select {
2403 INNER_PROVIDER_VLAN = 0,
2405 OUTER_PROVIDER_VLAN = 2,
2411 #endif /* __ECORE_HSI_ETH__ */