1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
7 #ifndef __ECORE_HSI_ETH__
8 #define __ECORE_HSI_ETH__
9 /************************************************************************/
10 /* Add include to common eth target for both eCore and protocol driver */
11 /************************************************************************/
12 #include "eth_common.h"
15 * The eth storm context for the Tstorm
17 struct tstorm_eth_conn_st_ctx {
22 * The eth storm context for the Pstorm
24 struct pstorm_eth_conn_st_ctx {
29 * The eth storm context for the Xstorm
31 struct xstorm_eth_conn_st_ctx {
35 struct e4_xstorm_eth_conn_ag_ctx {
36 u8 reserved0 /* cdu_validation */;
37 u8 eth_state /* state */;
40 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
41 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
43 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
44 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
46 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
47 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
49 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
50 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
52 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
53 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
55 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
56 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
58 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
59 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
61 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
62 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
65 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
66 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
68 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
69 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
71 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
72 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
74 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
75 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
77 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1
78 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4
80 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1
81 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5
83 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
84 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
86 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
87 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
90 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
91 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
93 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
94 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
96 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
97 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
99 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
100 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
103 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
104 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
106 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
107 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
109 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
110 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
112 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
113 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
116 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
117 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
119 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
120 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
122 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
123 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
125 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
126 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
129 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
130 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
132 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
133 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
135 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
136 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
138 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
139 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
142 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
143 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
145 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
146 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
148 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
149 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
151 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
152 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
155 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
156 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
158 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
159 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
161 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
162 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
164 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
165 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
167 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
168 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
171 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
172 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
174 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
175 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
177 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
178 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
180 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
181 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
183 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
184 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
186 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
187 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
189 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
190 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
192 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
193 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
196 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
197 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
199 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
200 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
202 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
203 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
205 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
206 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
208 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
209 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
211 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
212 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
214 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
215 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
217 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
218 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
221 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
222 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
224 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
225 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
227 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
228 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
230 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
231 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
233 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
234 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
236 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
237 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
239 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
240 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
242 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
243 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
246 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
247 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
249 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
250 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
252 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
253 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
255 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
256 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
258 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
259 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
261 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
262 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
264 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
265 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
267 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
268 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
271 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
272 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
274 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
275 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
277 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
278 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
280 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
281 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
283 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
284 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
286 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
287 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
289 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
290 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
292 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
293 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
296 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
297 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
299 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
300 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
302 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
303 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
305 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
306 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
308 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
309 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
311 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
312 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
314 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
315 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
317 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
318 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
321 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
322 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
324 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
325 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
327 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
328 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
330 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
331 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
333 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
334 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
336 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
337 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
339 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
340 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
341 u8 edpm_event_id /* byte2 */;
342 __le16 physical_q0 /* physical_q0 */;
343 __le16 e5_reserved1 /* physical_q1 */;
344 __le16 edpm_num_bds /* physical_q2 */;
345 __le16 tx_bd_cons /* word3 */;
346 __le16 tx_bd_prod /* word4 */;
347 __le16 updated_qm_pq_id /* word5 */;
348 __le16 conn_dpi /* conn_dpi */;
349 u8 byte3 /* byte3 */;
350 u8 byte4 /* byte4 */;
351 u8 byte5 /* byte5 */;
352 u8 byte6 /* byte6 */;
353 __le32 reg0 /* reg0 */;
354 __le32 reg1 /* reg1 */;
355 __le32 reg2 /* reg2 */;
356 __le32 reg3 /* reg3 */;
357 __le32 reg4 /* reg4 */;
358 __le32 reg5 /* cf_array0 */;
359 __le32 reg6 /* cf_array1 */;
360 __le16 word7 /* word7 */;
361 __le16 word8 /* word8 */;
362 __le16 word9 /* word9 */;
363 __le16 word10 /* word10 */;
364 __le32 reg7 /* reg7 */;
365 __le32 reg8 /* reg8 */;
366 __le32 reg9 /* reg9 */;
367 u8 byte7 /* byte7 */;
368 u8 byte8 /* byte8 */;
369 u8 byte9 /* byte9 */;
370 u8 byte10 /* byte10 */;
371 u8 byte11 /* byte11 */;
372 u8 byte12 /* byte12 */;
373 u8 byte13 /* byte13 */;
374 u8 byte14 /* byte14 */;
375 u8 byte15 /* byte15 */;
376 u8 e5_reserved /* e5_reserved */;
377 __le16 word11 /* word11 */;
378 __le32 reg10 /* reg10 */;
379 __le32 reg11 /* reg11 */;
380 __le32 reg12 /* reg12 */;
381 __le32 reg13 /* reg13 */;
382 __le32 reg14 /* reg14 */;
383 __le32 reg15 /* reg15 */;
384 __le32 reg16 /* reg16 */;
385 __le32 reg17 /* reg17 */;
386 __le32 reg18 /* reg18 */;
387 __le32 reg19 /* reg19 */;
388 __le16 word12 /* word12 */;
389 __le16 word13 /* word13 */;
390 __le16 word14 /* word14 */;
391 __le16 word15 /* word15 */;
395 * The eth storm context for the Ystorm
397 struct ystorm_eth_conn_st_ctx {
401 struct e4_ystorm_eth_conn_ag_ctx {
402 u8 byte0 /* cdu_validation */;
403 u8 state /* state */;
406 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
407 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
409 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
410 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
411 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf0 */
412 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2
413 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 /* cf1 */
414 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4
415 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
416 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
419 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
420 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
422 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
423 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1
425 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
426 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
428 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
429 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
431 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
432 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
434 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
435 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
437 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
438 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
440 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
441 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
442 u8 tx_q0_int_coallecing_timeset /* byte2 */;
443 u8 byte3 /* byte3 */;
444 __le16 word0 /* word0 */;
445 __le32 terminate_spqe /* reg0 */;
446 __le32 reg1 /* reg1 */;
447 __le16 tx_bd_cons_upd /* word1 */;
448 __le16 word2 /* word2 */;
449 __le16 word3 /* word3 */;
450 __le16 word4 /* word4 */;
451 __le32 reg2 /* reg2 */;
452 __le32 reg3 /* reg3 */;
455 struct e4_tstorm_eth_conn_ag_ctx {
456 u8 byte0 /* cdu_validation */;
457 u8 byte1 /* state */;
459 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
460 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
461 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
462 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
463 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
464 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
465 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
466 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
467 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
468 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
469 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
470 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
471 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
472 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
474 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
475 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
476 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
477 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
478 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
479 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
480 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
481 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
483 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
484 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
485 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
486 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
487 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
488 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
489 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
490 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
492 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
493 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
494 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
495 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
496 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
497 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
498 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
499 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
500 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
501 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
502 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
503 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
505 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
506 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
507 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
508 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
509 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
510 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
511 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
512 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
513 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
514 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
515 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
516 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
517 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
518 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
519 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
520 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
522 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
523 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
524 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
525 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
526 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
527 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
528 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
529 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
530 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
531 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
532 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 /* rule6en */
533 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
534 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
535 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
536 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
537 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
538 __le32 reg0 /* reg0 */;
539 __le32 reg1 /* reg1 */;
540 __le32 reg2 /* reg2 */;
541 __le32 reg3 /* reg3 */;
542 __le32 reg4 /* reg4 */;
543 __le32 reg5 /* reg5 */;
544 __le32 reg6 /* reg6 */;
545 __le32 reg7 /* reg7 */;
546 __le32 reg8 /* reg8 */;
547 u8 byte2 /* byte2 */;
548 u8 byte3 /* byte3 */;
549 __le16 rx_bd_cons /* word0 */;
550 u8 byte4 /* byte4 */;
551 u8 byte5 /* byte5 */;
552 __le16 rx_bd_prod /* word1 */;
553 __le16 word2 /* conn_dpi */;
554 __le16 word3 /* word3 */;
555 __le32 reg9 /* reg9 */;
556 __le32 reg10 /* reg10 */;
559 struct e4_ustorm_eth_conn_ag_ctx {
560 u8 byte0 /* cdu_validation */;
561 u8 byte1 /* state */;
564 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
565 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
567 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
568 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
570 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
571 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2
573 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
574 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4
576 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
577 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
580 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
581 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
583 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
584 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
586 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
587 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
589 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
590 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
593 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
594 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
596 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
597 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
599 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
600 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
602 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
603 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
605 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
606 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
608 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
609 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
611 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
612 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
614 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
615 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
618 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
619 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
621 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
622 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
624 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
625 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
627 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
628 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
630 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
631 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
633 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
634 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
636 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
637 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
639 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
640 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
641 u8 byte2 /* byte2 */;
642 u8 byte3 /* byte3 */;
643 __le16 word0 /* conn_dpi */;
644 __le16 tx_bd_cons /* word1 */;
645 __le32 reg0 /* reg0 */;
646 __le32 reg1 /* reg1 */;
647 __le32 reg2 /* reg2 */;
648 __le32 tx_int_coallecing_timeset /* reg3 */;
649 __le16 tx_drv_bd_cons /* word2 */;
650 __le16 rx_drv_cqe_cons /* word3 */;
654 * The eth storm context for the Ustorm
656 struct ustorm_eth_conn_st_ctx {
661 * The eth storm context for the Mstorm
663 struct mstorm_eth_conn_st_ctx {
668 * eth connection context
670 struct e4_eth_conn_context {
671 /* tstorm storm context */
672 struct tstorm_eth_conn_st_ctx tstorm_st_context;
673 struct regpair tstorm_st_padding[2] /* padding */;
674 /* pstorm storm context */
675 struct pstorm_eth_conn_st_ctx pstorm_st_context;
676 /* xstorm storm context */
677 struct xstorm_eth_conn_st_ctx xstorm_st_context;
678 /* xstorm aggregative context */
679 struct e4_xstorm_eth_conn_ag_ctx xstorm_ag_context;
680 /* ystorm storm context */
681 struct ystorm_eth_conn_st_ctx ystorm_st_context;
682 /* ystorm aggregative context */
683 struct e4_ystorm_eth_conn_ag_ctx ystorm_ag_context;
684 /* tstorm aggregative context */
685 struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context;
686 /* ustorm aggregative context */
687 struct e4_ustorm_eth_conn_ag_ctx ustorm_ag_context;
688 /* ustorm storm context */
689 struct ustorm_eth_conn_st_ctx ustorm_st_context;
690 /* mstorm storm context */
691 struct mstorm_eth_conn_st_ctx mstorm_st_context;
696 * Ethernet filter types: mac/vlan/pair
698 enum eth_error_code {
699 ETH_OK = 0x00 /* command succeeded */,
700 /* mac add filters command failed due to cam full state */
701 ETH_FILTERS_MAC_ADD_FAIL_FULL,
702 /* mac add filters command failed due to mtt2 full state */
703 ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2,
704 /* mac add filters command failed due to duplicate mac address */
705 ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2,
706 /* mac add filters command failed due to duplicate mac address */
707 ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2,
708 /* mac delete filters command failed due to not found state */
709 ETH_FILTERS_MAC_DEL_FAIL_NOF,
710 /* mac delete filters command failed due to not found state */
711 ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2,
712 /* mac delete filters command failed due to not found state */
713 ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2,
714 /* mac add filters command failed due to MAC Address of 00:00:00:00:00:00 */
715 ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC,
716 /* vlan add filters command failed due to cam full state */
717 ETH_FILTERS_VLAN_ADD_FAIL_FULL,
718 /* vlan add filters command failed due to duplicate VLAN filter */
719 ETH_FILTERS_VLAN_ADD_FAIL_DUP,
720 /* vlan delete filters command failed due to not found state */
721 ETH_FILTERS_VLAN_DEL_FAIL_NOF,
722 /* vlan delete filters command failed due to not found state */
723 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1,
724 /* pair add filters command failed due to duplicate request */
725 ETH_FILTERS_PAIR_ADD_FAIL_DUP,
726 /* pair add filters command failed due to full state */
727 ETH_FILTERS_PAIR_ADD_FAIL_FULL,
728 /* pair add filters command failed due to full state */
729 ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC,
730 /* pair add filters command failed due not found state */
731 ETH_FILTERS_PAIR_DEL_FAIL_NOF,
732 /* pair add filters command failed due not found state */
733 ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1,
734 /* pair add filters command failed due to MAC Address of 00:00:00:00:00:00 */
735 ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC,
736 /* vni add filters command failed due to cam full state */
737 ETH_FILTERS_VNI_ADD_FAIL_FULL,
738 /* vni add filters command failed due to duplicate VNI filter */
739 ETH_FILTERS_VNI_ADD_FAIL_DUP,
740 ETH_FILTERS_GFT_UPDATE_FAIL /* Fail update GFT filter. */,
746 * opcodes for the event ring
748 enum eth_event_opcode {
750 ETH_EVENT_VPORT_START,
751 ETH_EVENT_VPORT_UPDATE,
752 ETH_EVENT_VPORT_STOP,
753 ETH_EVENT_TX_QUEUE_START,
754 ETH_EVENT_TX_QUEUE_STOP,
755 ETH_EVENT_RX_QUEUE_START,
756 ETH_EVENT_RX_QUEUE_UPDATE,
757 ETH_EVENT_RX_QUEUE_STOP,
758 ETH_EVENT_FILTERS_UPDATE,
759 ETH_EVENT_RX_ADD_OPENFLOW_FILTER,
760 ETH_EVENT_RX_DELETE_OPENFLOW_FILTER,
761 ETH_EVENT_RX_CREATE_OPENFLOW_ACTION,
762 ETH_EVENT_RX_ADD_UDP_FILTER,
763 ETH_EVENT_RX_DELETE_UDP_FILTER,
764 ETH_EVENT_RX_CREATE_GFT_ACTION,
765 ETH_EVENT_RX_GFT_UPDATE_FILTER,
766 ETH_EVENT_TX_QUEUE_UPDATE,
772 * Classify rule types in E2/E3
774 enum eth_filter_action {
775 ETH_FILTER_ACTION_UNUSED,
776 ETH_FILTER_ACTION_REMOVE,
777 ETH_FILTER_ACTION_ADD,
778 /* Remove all filters of given type and vport ID. */
779 ETH_FILTER_ACTION_REMOVE_ALL,
780 MAX_ETH_FILTER_ACTION
785 * Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$
787 struct eth_filter_cmd {
788 u8 type /* Filter Type (MAC/VLAN/Pair/VNI) */;
789 u8 vport_id /* the vport id */;
790 u8 action /* filter command action: add/remove/replace */;
801 * $$KEEP_ENDIANNESS$$
803 struct eth_filter_cmd_header {
804 u8 rx /* If set, apply these commands to the RX path */;
805 u8 tx /* If set, apply these commands to the TX path */;
806 u8 cmd_cnt /* Number of filter commands */;
807 /* 0 - dont assert in case of filter configuration error. Just return an error
808 * code. 1 - assert in case of filter configuration error.
816 * Ethernet filter types: mac/vlan/pair
818 enum eth_filter_type {
819 ETH_FILTER_TYPE_UNUSED,
820 ETH_FILTER_TYPE_MAC /* Add/remove a MAC address */,
821 ETH_FILTER_TYPE_VLAN /* Add/remove a VLAN */,
822 ETH_FILTER_TYPE_PAIR /* Add/remove a MAC-VLAN pair */,
823 ETH_FILTER_TYPE_INNER_MAC /* Add/remove a inner MAC address */,
824 ETH_FILTER_TYPE_INNER_VLAN /* Add/remove a inner VLAN */,
825 ETH_FILTER_TYPE_INNER_PAIR /* Add/remove a inner MAC-VLAN pair */,
826 /* Add/remove a inner MAC-VNI pair */
827 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
828 ETH_FILTER_TYPE_MAC_VNI_PAIR /* Add/remove a MAC-VNI pair */,
829 ETH_FILTER_TYPE_VNI /* Add/remove a VNI */,
835 * inner to inner vlan priority translation configurations
837 struct eth_in_to_in_pri_map_cfg {
838 /* If set, non_rdma_in_to_in_pri_map or rdma_in_to_in_pri_map will be used for
839 * inner to inner priority mapping depending on protocol type
841 u8 inner_vlan_pri_remap_en;
843 /* Map for inner to inner vlan priority translation for Non RDMA protocols, used
844 * for TenantDcb. Set inner_vlan_pri_remap_en, when init the map.
846 u8 non_rdma_in_to_in_pri_map[8];
847 /* Map for inner to inner vlan priority translation for RDMA protocols, used for
848 * TenantDcb. Set inner_vlan_pri_remap_en, when init the map.
850 u8 rdma_in_to_in_pri_map[8];
855 * eth IPv4 Fragment Type
857 enum eth_ipv4_frag_type {
858 ETH_IPV4_NOT_FRAG /* IPV4 Packet Not Fragmented */,
859 /* First Fragment of IPv4 Packet (contains headers) */
861 /* Non-First Fragment of IPv4 Packet (does not contain headers) */
862 ETH_IPV4_NON_FIRST_FRAG,
863 MAX_ETH_IPV4_FRAG_TYPE
868 * eth IPv4 Fragment Type
878 * Ethernet Ramrod Command IDs
880 enum eth_ramrod_cmd_id {
882 ETH_RAMROD_VPORT_START /* VPort Start Ramrod */,
883 ETH_RAMROD_VPORT_UPDATE /* VPort Update Ramrod */,
884 ETH_RAMROD_VPORT_STOP /* VPort Stop Ramrod */,
885 ETH_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */,
886 ETH_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */,
887 ETH_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */,
888 ETH_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */,
889 ETH_RAMROD_FILTERS_UPDATE /* Add or Remove Mac/Vlan/Pair filters */,
890 ETH_RAMROD_RX_QUEUE_UPDATE /* RX Queue Update Ramrod */,
891 /* RX - Create an Openflow Action */
892 ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION,
893 /* RX - Add an Openflow Filter to the Searcher */
894 ETH_RAMROD_RX_ADD_OPENFLOW_FILTER,
895 /* RX - Delete an Openflow Filter to the Searcher */
896 ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER,
897 /* RX - Add a UDP Filter to the Searcher */
898 ETH_RAMROD_RX_ADD_UDP_FILTER,
899 /* RX - Delete a UDP Filter to the Searcher */
900 ETH_RAMROD_RX_DELETE_UDP_FILTER,
901 ETH_RAMROD_RX_CREATE_GFT_ACTION /* RX - Create a Gft Action */,
902 /* RX - Add/Delete a GFT Filter to the Searcher */
903 ETH_RAMROD_GFT_UPDATE_FILTER,
904 ETH_RAMROD_TX_QUEUE_UPDATE /* TX Queue Update Ramrod */,
905 MAX_ETH_RAMROD_CMD_ID
910 * return code from eth sp ramrods
912 struct eth_return_code {
914 /* error code (use enum eth_error_code) */
915 #define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F
916 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
917 #define ETH_RETURN_CODE_RESERVED_MASK 0x3
918 #define ETH_RETURN_CODE_RESERVED_SHIFT 5
919 /* rx path - 0, tx path - 1 */
920 #define ETH_RETURN_CODE_RX_TX_MASK 0x1
921 #define ETH_RETURN_CODE_RX_TX_SHIFT 7
926 * What to do in case an error occurs
929 ETH_TX_ERR_DROP /* Drop erroneous packet. */,
930 /* Assert an interrupt for PF, declare as malicious for VF */
931 ETH_TX_ERR_ASSERT_MALICIOUS,
937 * Array of the different error type behaviors
939 struct eth_tx_err_vals {
941 /* Wrong VLAN insertion mode (use enum eth_tx_err) */
942 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1
943 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0
944 /* Packet is below minimal size (use enum eth_tx_err) */
945 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1
946 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1
947 /* Vport has sent spoofed packet (use enum eth_tx_err) */
948 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1
949 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2
950 /* Packet with illegal type of inband tag (use enum eth_tx_err) */
951 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1
952 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3
953 /* Packet marked for VLAN insertion when inband tag is present
954 * (use enum eth_tx_err)
956 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1
957 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4
958 /* Non LSO packet larger than MTU (use enum eth_tx_err) */
959 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1
960 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5
961 /* VF/PF has sent LLDP/PFC or any other type of control packet which is not
962 * allowed to (use enum eth_tx_err)
964 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
965 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6
966 #define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF
967 #define ETH_TX_ERR_VALS_RESERVED_SHIFT 7
972 * vport rss configuration data
974 struct eth_vport_rss_config {
976 /* configuration of the IpV4 2-tuple capability */
977 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
978 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0
979 /* configuration of the IpV6 2-tuple capability */
980 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
981 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1
982 /* configuration of the IpV4 4-tuple capability for TCP */
983 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
984 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2
985 /* configuration of the IpV6 4-tuple capability for TCP */
986 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
987 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3
988 /* configuration of the IpV4 4-tuple capability for UDP */
989 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
990 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4
991 /* configuration of the IpV6 4-tuple capability for UDP */
992 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
993 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5
994 /* configuration of the 5-tuple capability */
995 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
996 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
997 /* if set update the rss keys */
998 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF
999 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7
1000 /* The RSS engine ID. Must be allocated to each vport with RSS enabled.
1001 * Total number of RSS engines is ETH_RSS_ENGINE_NUM_ , according to chip type.
1004 u8 rss_mode /* The RSS mode for this function */;
1005 u8 update_rss_key /* if set update the rss key */;
1006 /* if set update the indirection table values */
1007 u8 update_rss_ind_table;
1008 /* if set update the capabilities and indirection table size. */
1009 u8 update_rss_capabilities;
1010 u8 tbl_size /* rss mask (Tbl size) */;
1011 __le32 reserved2[2];
1012 /* RSS indirection table */
1013 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
1014 /* RSS key supplied to us by OS */
1015 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
1016 __le32 reserved3[2];
1021 * eth vport RSS mode
1023 enum eth_vport_rss_mode {
1024 ETH_VPORT_RSS_MODE_DISABLED /* RSS Disabled */,
1025 ETH_VPORT_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */,
1026 MAX_ETH_VPORT_RSS_MODE
1031 * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$
1033 struct eth_vport_rx_mode {
1035 /* drop all unicast packets */
1036 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
1037 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0
1038 /* accept all unicast packets (subject to vlan) */
1039 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
1040 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
1041 /* accept all unmatched unicast packets */
1042 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
1043 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
1044 /* drop all multicast packets */
1045 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
1046 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3
1047 /* accept all multicast packets (subject to vlan) */
1048 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
1049 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4
1050 /* accept all broadcast packets (subject to vlan) */
1051 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
1052 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5
1053 /* accept any VNI in tunnel VNI classification. Used for default queue. */
1054 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_MASK 0x1
1055 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_SHIFT 6
1056 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x1FF
1057 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 7
1062 * Command for setting tpa parameters
1064 struct eth_vport_tpa_param {
1065 u8 tpa_ipv4_en_flg /* Enable TPA for IPv4 packets */;
1066 u8 tpa_ipv6_en_flg /* Enable TPA for IPv6 packets */;
1067 u8 tpa_ipv4_tunn_en_flg /* Enable TPA for IPv4 over tunnel */;
1068 u8 tpa_ipv6_tunn_en_flg /* Enable TPA for IPv6 over tunnel */;
1069 /* If set, start each TPA segment on new BD (GRO mode). One BD per segment
1072 u8 tpa_pkt_split_flg;
1073 /* If set, put header of first TPA segment on first BD and data on second BD. */
1074 u8 tpa_hdr_data_split_flg;
1075 /* If set, GRO data consistent will checked for TPA continue */
1076 u8 tpa_gro_consistent_flg;
1077 /* maximum number of opened aggregations per v-port */
1078 u8 tpa_max_aggs_num;
1079 __le16 tpa_max_size /* maximal size for the aggregated TPA packets */;
1080 /* minimum TCP payload size for a packet to start aggregation */
1081 __le16 tpa_min_size_to_start;
1082 /* minimum TCP payload size for a packet to continue aggregation */
1083 __le16 tpa_min_size_to_cont;
1084 /* maximal number of buffers that can be used for one aggregation */
1091 * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$
1093 struct eth_vport_tx_mode {
1095 /* drop all unicast packets */
1096 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
1097 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0
1098 /* accept all unicast packets (subject to vlan) */
1099 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
1100 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
1101 /* drop all multicast packets */
1102 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
1103 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2
1104 /* accept all multicast packets (subject to vlan) */
1105 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
1106 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
1107 /* accept all broadcast packets (subject to vlan) */
1108 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
1109 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
1110 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF
1111 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5
1116 * GFT filter update action type.
1118 enum gft_filter_update_action {
1121 MAX_GFT_FILTER_UPDATE_ACTION
1128 * Ramrod data for rx add openflow filter
1130 struct rx_add_openflow_filter_data {
1131 __le16 action_icid /* CID of Action to run for this filter */;
1132 u8 priority /* Searcher String - Packet priority */;
1134 __le32 tenant_id /* Searcher String - Tenant ID */;
1135 /* Searcher String - Destination Mac Bytes 0 to 1 */
1137 /* Searcher String - Destination Mac Bytes 2 to 3 */
1139 /* Searcher String - Destination Mac Bytes 4 to 5 */
1141 __le16 src_mac_hi /* Searcher String - Source Mac 0 to 1 */;
1142 __le16 src_mac_mid /* Searcher String - Source Mac 2 to 3 */;
1143 __le16 src_mac_lo /* Searcher String - Source Mac 4 to 5 */;
1144 __le16 vlan_id /* Searcher String - Vlan ID */;
1145 __le16 l2_eth_type /* Searcher String - Last L2 Ethertype */;
1146 u8 ipv4_dscp /* Searcher String - IPv4 6 MSBs of the TOS Field */;
1147 u8 ipv4_frag_type /* Searcher String - IPv4 Fragmentation Type */;
1148 u8 ipv4_over_ip /* Searcher String - IPv4 Over IP Type */;
1149 u8 tenant_id_exists /* Searcher String - Tenant ID Exists */;
1150 __le32 ipv4_dst_addr /* Searcher String - IPv4 Destination Address */;
1151 __le32 ipv4_src_addr /* Searcher String - IPv4 Source Address */;
1152 __le16 l4_dst_port /* Searcher String - TCP/UDP Destination Port */;
1153 __le16 l4_src_port /* Searcher String - TCP/UDP Source Port */;
1158 * Ramrod data for rx create gft action
1160 struct rx_create_gft_action_data {
1161 u8 vport_id /* Vport Id of GFT Action */;
1167 * Ramrod data for rx create openflow action
1169 struct rx_create_openflow_action_data {
1170 u8 vport_id /* ID of RX queue */;
1176 * Ramrod data for rx queue start ramrod
1178 struct rx_queue_start_ramrod_data {
1179 __le16 rx_queue_id /* ID of RX queue */;
1180 __le16 num_of_pbl_pages /* Number of pages in CQE PBL */;
1181 __le16 bd_max_bytes /* maximal bytes that can be places on the bd */;
1182 __le16 sb_id /* Status block ID */;
1183 u8 sb_index /* index of the protocol index */;
1184 u8 vport_id /* ID of virtual port */;
1185 u8 default_rss_queue_flg /* set queue as default rss queue if set */;
1186 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
1187 u8 complete_event_flg /* post completion to the event ring if set */;
1188 u8 stats_counter_id /* Statistics counter ID */;
1189 u8 pin_context /* Pin context in CCFC to improve performance */;
1190 u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD/SGE fetch */;
1191 /* PXP command TPH Valid - for packet placement */
1192 u8 pxp_tph_valid_pkt;
1193 /* PXP command Steering tag hint. Use enum pxp_tph_st_hint */
1195 __le16 pxp_st_index /* PXP command Steering tag index */;
1196 /* Indicates that current queue belongs to poll-mode driver */
1198 /* Indicates that the current queue is using the TX notification queue
1199 * mechanism - should be set only for PMD queue
1202 /* Initial value for the toggle valid bit - used in PMD mode */
1204 /* Index of RX producers in VF zone. Used for VF only. */
1205 u8 vf_rx_prod_index;
1206 /* Backward compatibility mode. If set, unprotected mStorm queue zone will used
1207 * for VF RX producers instead of VF zone.
1209 u8 vf_rx_prod_use_zone_a;
1211 __le16 reserved1 /* FW reserved. */;
1212 struct regpair cqe_pbl_addr /* Base address on host of CQE PBL */;
1213 struct regpair bd_base /* bd address of the first bd page */;
1214 struct regpair reserved2 /* FW reserved. */;
1219 * Ramrod data for rx queue stop ramrod
1221 struct rx_queue_stop_ramrod_data {
1222 __le16 rx_queue_id /* ID of RX queue */;
1223 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
1224 u8 complete_event_flg /* post completion to the event ring if set */;
1225 u8 vport_id /* ID of virtual port */;
1231 * Ramrod data for rx queue update ramrod
1233 struct rx_queue_update_ramrod_data {
1234 __le16 rx_queue_id /* ID of RX queue */;
1235 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
1236 u8 complete_event_flg /* post completion to the event ring if set */;
1237 u8 vport_id /* ID of virtual port */;
1238 /* If set, update default rss queue to this RX queue. */
1239 u8 set_default_rss_queue;
1241 u8 reserved1 /* FW reserved. */;
1242 u8 reserved2 /* FW reserved. */;
1243 u8 reserved3 /* FW reserved. */;
1244 __le16 reserved4 /* FW reserved. */;
1245 __le16 reserved5 /* FW reserved. */;
1246 struct regpair reserved6 /* FW reserved. */;
1251 * Ramrod data for rx Add UDP Filter
1253 struct rx_udp_filter_data {
1254 __le16 action_icid /* CID of Action to run for this filter */;
1255 __le16 vlan_id /* Searcher String - Vlan ID */;
1256 u8 ip_type /* Searcher String - IP Type */;
1257 u8 tenant_id_exists /* Searcher String - Tenant ID Exists */;
1259 /* Searcher String - IP Destination Address, for IPv4 use ip_dst_addr[0] only */
1260 __le32 ip_dst_addr[4];
1261 /* Searcher String - IP Source Address, for IPv4 use ip_dst_addr[0] only */
1262 __le32 ip_src_addr[4];
1263 __le16 udp_dst_port /* Searcher String - UDP Destination Port */;
1264 __le16 udp_src_port /* Searcher String - UDP Source Port */;
1265 __le32 tenant_id /* Searcher String - Tenant ID */;
1270 * add or delete GFT filter - filter is packet header of type of packet wished
1271 * to pass certain FW flow
1273 struct rx_update_gft_filter_data {
1274 /* Pointer to Packet Header That Defines GFT Filter */
1275 struct regpair pkt_hdr_addr;
1276 __le16 pkt_hdr_length /* Packet Header Length */;
1277 /* Action icid. Valid if action_icid_valid flag set. */
1279 __le16 rx_qid /* RX queue ID. Valid if rx_qid_valid set. */;
1280 __le16 flow_id /* RX flow ID. Valid if flow_id_valid set. */;
1281 /* RX vport Id. For drop flow, set to ETH_GFT_TRASHCAN_VPORT. */
1283 /* If set, action_icid will used for GFT filter update. */
1284 u8 action_icid_valid;
1285 /* If set, rx_qid will used for traffic steering, in additional to vport_id.
1286 * flow_id_valid must be cleared. If cleared, queue ID will selected by RSS.
1289 /* If set, flow_id will reported by CQE, rx_qid_valid must be cleared. If
1290 * cleared, flow_id 0 will reported by CQE.
1293 u8 filter_action /* Use to set type of action on filter */;
1294 /* 0 - dont assert in case of error. Just return an error code. 1 - assert in
1298 /* If set, inner VLAN will be removed regardless to VPORT configuration.
1299 * Supported by E4 only.
1301 u8 inner_vlan_removal_en;
1307 * Ramrod data for tx queue start ramrod
1309 struct tx_queue_start_ramrod_data {
1310 __le16 sb_id /* Status block ID */;
1311 u8 sb_index /* Status block protocol index */;
1312 u8 vport_id /* VPort ID */;
1313 u8 reserved0 /* FW reserved. (qcn_rl_en) */;
1314 u8 stats_counter_id /* Statistics counter ID to use */;
1315 __le16 qm_pq_id /* QM PQ ID */;
1317 /* 0: Enable QM opportunistic flow. 1: Disable QM opportunistic flow */
1318 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
1319 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
1320 /* If set, Test Mode - packets will be duplicated by Xstorm handler */
1321 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
1322 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1
1323 /* If set, Test Mode - packets destination will be determined by dest_port_mode
1326 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1
1327 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2
1328 /* Indicates that current queue belongs to poll-mode driver */
1329 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
1330 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3
1331 /* Indicates that the current queue is using the TX notification queue
1332 * mechanism - should be set only for PMD queue
1334 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
1335 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4
1336 /* Pin context in CCFC to improve performance */
1337 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
1338 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5
1339 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3
1340 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6
1341 u8 pxp_st_hint /* PXP command Steering tag hint */;
1342 u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD fetch */;
1343 u8 pxp_tph_valid_pkt /* PXP command TPH Valid - for packet fetch */;
1344 __le16 pxp_st_index /* PXP command Steering tag index */;
1345 /* TX completion min agg size - for PMD queues */
1346 __le16 comp_agg_size;
1347 __le16 queue_zone_id /* queue zone ID to use */;
1348 __le16 reserved2 /* FW reserved. (test_dup_count) */;
1349 __le16 pbl_size /* Number of BD pages pointed by PBL */;
1350 /* unique Queue ID - currently used only by PMD flow */
1352 /* Unique Same-As-Last Resource ID - improves performance for same-as-last
1353 * packets per connection (range 0..ETH_TX_NUM_SAME_AS_LAST_ENTRIES-1 IDs
1356 __le16 same_as_last_id;
1358 struct regpair pbl_base_addr /* address of the pbl page */;
1359 /* BD consumer address in host - for PMD queues */
1360 struct regpair bd_cons_address;
1365 * Ramrod data for tx queue stop ramrod
1367 struct tx_queue_stop_ramrod_data {
1373 * Ramrod data for tx queue update ramrod
1375 struct tx_queue_update_ramrod_data {
1376 __le16 update_qm_pq_id_flg /* Flag to Update QM PQ ID */;
1377 __le16 qm_pq_id /* Updated QM PQ ID */;
1379 struct regpair reserved1[5];
1384 * Inner to Inner VLAN priority map update mode
1386 enum update_in_to_in_pri_map_mode_enum {
1387 /* Inner to Inner VLAN priority map update Disabled */
1388 ETH_IN_TO_IN_PRI_MAP_UPDATE_DISABLED,
1389 /* Update Inner to Inner VLAN priority map for non RDMA protocols */
1390 ETH_IN_TO_IN_PRI_MAP_UPDATE_NON_RDMA_TBL,
1391 /* Update Inner to Inner VLAN priority map for RDMA protocols */
1392 ETH_IN_TO_IN_PRI_MAP_UPDATE_RDMA_TBL,
1393 MAX_UPDATE_IN_TO_IN_PRI_MAP_MODE_ENUM
1399 * Ramrod data for vport update ramrod
1401 struct vport_filter_update_ramrod_data {
1402 /* Header for Filter Commands (RX/TX, Add/Remove/Replace, etc) */
1403 struct eth_filter_cmd_header filter_cmd_hdr;
1404 /* Filter Commands */
1405 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
1410 * Ramrod data for vport start ramrod
1412 struct vport_start_ramrod_data {
1416 u8 drop_ttl0_en /* if set, drop packet with ttl=0 */;
1417 u8 inner_vlan_removal_en;
1418 struct eth_vport_rx_mode rx_mode /* Rx filter data */;
1419 struct eth_vport_tx_mode tx_mode /* Tx filter data */;
1420 /* TPA configuration parameters */
1421 struct eth_vport_tpa_param tpa_param;
1422 __le16 default_vlan /* Default Vlan value to be forced by FW */;
1423 u8 tx_switching_en /* Tx switching is enabled for current Vport */;
1424 /* Anti-spoofing verification is set for current Vport */
1425 u8 anti_spoofing_en;
1426 /* If set, the default Vlan value is forced by the FW */
1428 /* If set, the vport handles PTP Timesync Packets */
1430 /* If enable then innerVlan will be striped and not written to cqe */
1431 u8 silent_vlan_removal_en;
1432 /* If set untagged filter (vlan0) is added to current Vport, otherwise port is
1433 * marked as any-vlan
1436 /* Desired behavior per TX error type */
1437 struct eth_tx_err_vals tx_err_behav;
1438 /* If set, ETH header padding will not inserted. placement_offset will be zero.
1440 u8 zero_placement_offset;
1441 /* If set, control frames will be filtered according to MAC check. */
1442 u8 ctl_frame_mac_check_en;
1443 /* If set, control frames will be filtered according to ethtype check. */
1444 u8 ctl_frame_ethtype_check_en;
1445 /* If set, the inner vlan (802.1q tag) priority that is written to cqe will be
1446 * zero out, used for TenantDcb
1448 u8 wipe_inner_vlan_pri_en;
1449 /* inner to inner vlan priority translation configurations */
1450 struct eth_in_to_in_pri_map_cfg in_to_in_vlan_pri_map_cfg;
1455 * Ramrod data for vport stop ramrod
1457 struct vport_stop_ramrod_data {
1464 * Ramrod data for vport update ramrod
1466 struct vport_update_ramrod_data_cmn {
1468 u8 update_rx_active_flg /* set if rx active flag should be handled */;
1469 u8 rx_active_flg /* rx active flag value */;
1470 u8 update_tx_active_flg /* set if tx active flag should be handled */;
1471 u8 tx_active_flg /* tx active flag value */;
1472 u8 update_rx_mode_flg /* set if rx state data should be handled */;
1473 u8 update_tx_mode_flg /* set if tx state data should be handled */;
1474 /* set if approx. mcast data should be handled */
1475 u8 update_approx_mcast_flg;
1476 u8 update_rss_flg /* set if rss data should be handled */;
1477 /* set if inner_vlan_removal_en should be handled */
1478 u8 update_inner_vlan_removal_en_flg;
1479 u8 inner_vlan_removal_en;
1480 /* set if tpa parameters should be handled, TPA must be disable before */
1481 u8 update_tpa_param_flg;
1482 u8 update_tpa_en_flg /* set if tpa enable changes */;
1483 /* set if tx switching en flag should be handled */
1484 u8 update_tx_switching_en_flg;
1485 u8 tx_switching_en /* tx switching en value */;
1486 /* set if anti spoofing flag should be handled */
1487 u8 update_anti_spoofing_en_flg;
1488 u8 anti_spoofing_en /* Anti-spoofing verification en value */;
1489 /* set if handle_ptp_pkts should be handled. */
1490 u8 update_handle_ptp_pkts;
1491 /* If set, the vport handles PTP Timesync Packets */
1493 /* If set, the default Vlan enable flag is updated */
1494 u8 update_default_vlan_en_flg;
1495 /* If set, the default Vlan value is forced by the FW */
1497 /* If set, the default Vlan value is updated */
1498 u8 update_default_vlan_flg;
1499 __le16 default_vlan /* Default Vlan value to be forced by FW */;
1500 /* set if accept_any_vlan should be handled */
1501 u8 update_accept_any_vlan_flg;
1502 u8 accept_any_vlan /* accept_any_vlan updated value */;
1503 /* Set to remove vlan silently, update_inner_vlan_removal_en_flg must be enabled
1504 * as well. If Rx is in noSgl mode send rx_queue_update_ramrod_data
1506 u8 silent_vlan_removal_en;
1507 /* If set, MTU will be updated. Vport must be not active. */
1509 __le16 mtu /* New MTU value. Used if update_mtu_flg are set */;
1510 /* If set, ctl_frame_mac_check_en and ctl_frame_ethtype_check_en will be
1513 u8 update_ctl_frame_checks_en_flg;
1514 /* If set, control frames will be filtered according to MAC check. */
1515 u8 ctl_frame_mac_check_en;
1516 /* If set, control frames will be filtered according to ethtype check. */
1517 u8 ctl_frame_ethtype_check_en;
1518 /* Indicates to update RDMA or NON-RDMA vlan remapping priority table according
1519 * to update_in_to_in_pri_map_mode_enum, used for TenantDcb (use enum
1520 * update_in_to_in_pri_map_mode_enum)
1522 u8 update_in_to_in_pri_map_mode;
1523 /* Map for inner to inner vlan priority translation, used for TenantDcb. */
1524 u8 in_to_in_pri_map[8];
1528 struct vport_update_ramrod_mcast {
1529 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS] /* multicast bins */;
1533 * Ramrod data for vport update ramrod
1535 struct vport_update_ramrod_data {
1536 /* Common data for all vport update ramrods */
1537 struct vport_update_ramrod_data_cmn common;
1538 struct eth_vport_rx_mode rx_mode /* vport rx mode bitmap */;
1539 struct eth_vport_tx_mode tx_mode /* vport tx mode bitmap */;
1541 /* TPA configuration parameters */
1542 struct eth_vport_tpa_param tpa_param;
1543 struct vport_update_ramrod_mcast approx_mcast;
1544 struct eth_vport_rss_config rss_config /* rss config data */;
1552 struct E4XstormEthConnAgCtxDqExtLdPart {
1553 u8 reserved0 /* cdu_validation */;
1554 u8 eth_state /* state */;
1557 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
1558 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
1560 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1
1561 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1
1563 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1
1564 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2
1566 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
1567 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
1569 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1
1570 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4
1571 /* cf_array_active */
1572 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1
1573 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5
1575 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1
1576 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6
1578 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1
1579 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7
1582 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1
1583 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0
1585 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1
1586 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1
1588 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1
1589 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2
1591 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
1592 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
1594 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
1595 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
1597 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_MASK 0x1
1598 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_SHIFT 5
1600 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1
1601 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6
1603 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1
1604 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7
1607 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
1608 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0
1610 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
1611 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2
1613 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
1614 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4
1615 /* timer_stop_all */
1616 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
1617 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6
1620 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
1621 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0
1623 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
1624 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2
1626 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
1627 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4
1629 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
1630 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6
1633 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
1634 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0
1636 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
1637 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2
1639 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
1640 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4
1642 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
1643 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6
1646 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
1647 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0
1649 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
1650 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2
1652 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
1653 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4
1655 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
1656 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6
1659 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
1660 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0
1662 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
1663 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2
1665 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
1666 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4
1668 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
1669 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6
1672 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
1673 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0
1675 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
1676 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2
1678 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
1679 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
1681 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
1682 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
1684 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
1685 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
1688 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
1689 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
1691 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
1692 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
1694 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
1695 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
1697 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
1698 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
1700 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
1701 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
1703 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1
1704 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5
1706 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
1707 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
1709 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
1710 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
1713 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
1714 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
1716 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
1717 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
1719 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
1720 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
1722 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
1723 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
1725 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
1726 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
1728 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
1729 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
1731 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1
1732 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6
1733 /* cf_array_cf_en */
1734 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1
1735 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7
1738 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1
1739 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0
1741 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1
1742 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1
1744 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1
1745 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2
1747 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1
1748 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3
1750 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
1751 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
1753 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1
1754 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5
1756 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1
1757 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6
1759 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1
1760 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7
1763 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1
1764 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0
1766 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1
1767 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1
1769 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1
1770 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2
1772 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
1773 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
1775 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
1776 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
1778 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
1779 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
1781 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
1782 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
1784 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
1785 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
1788 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
1789 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
1791 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
1792 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
1794 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
1795 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
1797 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
1798 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
1800 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
1801 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
1803 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
1804 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
1806 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
1807 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
1809 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
1810 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
1813 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
1814 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
1816 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
1817 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
1819 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
1820 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
1822 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
1823 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
1825 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
1826 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
1828 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
1829 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
1831 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
1832 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
1834 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
1835 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
1838 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1
1839 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0
1841 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1
1842 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1
1844 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1
1845 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2
1847 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1
1848 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3
1850 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1
1851 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4
1853 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
1854 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
1856 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
1857 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6
1858 u8 edpm_event_id /* byte2 */;
1859 __le16 physical_q0 /* physical_q0 */;
1860 __le16 e5_reserved1 /* physical_q1 */;
1861 __le16 edpm_num_bds /* physical_q2 */;
1862 __le16 tx_bd_cons /* word3 */;
1863 __le16 tx_bd_prod /* word4 */;
1864 __le16 updated_qm_pq_id /* word5 */;
1865 __le16 conn_dpi /* conn_dpi */;
1866 u8 byte3 /* byte3 */;
1867 u8 byte4 /* byte4 */;
1868 u8 byte5 /* byte5 */;
1869 u8 byte6 /* byte6 */;
1870 __le32 reg0 /* reg0 */;
1871 __le32 reg1 /* reg1 */;
1872 __le32 reg2 /* reg2 */;
1873 __le32 reg3 /* reg3 */;
1874 __le32 reg4 /* reg4 */;
1878 struct e4_mstorm_eth_conn_ag_ctx {
1879 u8 byte0 /* cdu_validation */;
1880 u8 byte1 /* state */;
1882 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1883 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1884 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1885 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
1886 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
1887 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2
1888 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1889 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4
1890 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
1891 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
1893 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1894 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
1895 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1896 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1
1897 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1898 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
1899 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1900 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
1901 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1902 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
1903 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1904 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
1905 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1906 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
1907 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1908 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
1909 __le16 word0 /* word0 */;
1910 __le16 word1 /* word1 */;
1911 __le32 reg0 /* reg0 */;
1912 __le32 reg1 /* reg1 */;
1919 struct e4_xstorm_eth_hw_conn_ag_ctx {
1920 u8 reserved0 /* cdu_validation */;
1921 u8 eth_state /* state */;
1924 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
1925 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1927 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
1928 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1
1930 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
1931 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2
1933 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
1934 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
1936 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
1937 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4
1938 /* cf_array_active */
1939 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
1940 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5
1941 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */
1942 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6
1943 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */
1944 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7
1946 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */
1947 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0
1948 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */
1949 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1
1951 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
1952 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2
1954 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
1955 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3
1957 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK 0x1
1958 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT 4
1960 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK 0x1
1961 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT 5
1963 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
1964 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
1966 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
1967 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
1970 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
1971 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0
1973 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
1974 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2
1976 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
1977 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4
1978 /* timer_stop_all */
1979 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
1980 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6
1982 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
1983 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0
1984 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
1985 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2
1986 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
1987 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4
1988 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
1989 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6
1991 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
1992 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0
1993 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
1994 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2
1995 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
1996 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4
1997 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
1998 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6
2000 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
2001 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
2002 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
2003 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2
2004 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */
2005 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4
2006 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
2007 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6
2009 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */
2010 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
2012 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
2013 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
2014 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */
2015 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4
2016 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */
2017 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
2019 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */
2020 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
2021 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */
2022 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2
2023 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
2024 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4
2026 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
2027 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6
2029 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
2030 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7
2033 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
2034 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0
2036 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
2037 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1
2039 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
2040 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2
2042 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
2043 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3
2045 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
2046 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4
2048 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
2049 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5
2051 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
2052 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6
2054 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
2055 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7
2058 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
2059 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0
2061 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
2062 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1
2064 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
2065 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2
2067 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
2068 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3
2070 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
2071 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4
2073 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
2074 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5
2076 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
2077 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
2078 /* cf_array_cf_en */
2079 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
2080 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
2083 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
2084 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
2086 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
2087 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
2089 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
2090 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
2092 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
2093 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3
2095 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
2096 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
2098 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
2099 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
2101 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
2102 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6
2104 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
2105 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7
2108 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
2109 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0
2111 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
2112 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1
2114 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
2115 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
2117 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
2118 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3
2120 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
2121 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4
2123 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
2124 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5
2126 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
2127 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
2129 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
2130 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7
2133 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
2134 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0
2136 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
2137 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1
2139 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
2140 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
2142 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
2143 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
2145 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
2146 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4
2148 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
2149 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5
2151 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
2152 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6
2154 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
2155 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7
2158 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
2159 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0
2161 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
2162 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1
2164 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
2165 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
2167 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
2168 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
2170 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
2171 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
2173 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
2174 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
2176 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
2177 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
2179 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
2180 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
2183 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
2184 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
2186 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
2187 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
2189 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
2190 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
2192 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
2193 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
2195 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
2196 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
2198 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
2199 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
2200 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */
2201 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
2202 u8 edpm_event_id /* byte2 */;
2203 __le16 physical_q0 /* physical_q0 */;
2204 __le16 e5_reserved1 /* physical_q1 */;
2205 __le16 edpm_num_bds /* physical_q2 */;
2206 __le16 tx_bd_cons /* word3 */;
2207 __le16 tx_bd_prod /* word4 */;
2208 __le16 updated_qm_pq_id /* word5 */;
2209 __le16 conn_dpi /* conn_dpi */;
2215 * GFT CAM line struct
2217 struct gft_cam_line {
2219 /* Indication if the line is valid. */
2220 #define GFT_CAM_LINE_VALID_MASK 0x1
2221 #define GFT_CAM_LINE_VALID_SHIFT 0
2222 /* Data bits, the word that compared with the profile key */
2223 #define GFT_CAM_LINE_DATA_MASK 0x3FFF
2224 #define GFT_CAM_LINE_DATA_SHIFT 1
2225 /* Mask bits, indicate the bits in the data that are Dont-Care */
2226 #define GFT_CAM_LINE_MASK_BITS_MASK 0x3FFF
2227 #define GFT_CAM_LINE_MASK_BITS_SHIFT 15
2228 #define GFT_CAM_LINE_RESERVED1_MASK 0x7
2229 #define GFT_CAM_LINE_RESERVED1_SHIFT 29
2234 * GFT CAM line struct (for driversim use)
2236 struct gft_cam_line_mapped {
2238 /* Indication if the line is valid. */
2239 #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1
2240 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0
2241 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
2242 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1
2243 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1
2244 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
2245 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1
2246 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2
2247 /* use enum gft_profile_upper_protocol_type
2248 * (use enum gft_profile_upper_protocol_type)
2250 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF
2251 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3
2252 /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */
2253 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF
2254 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7
2255 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF
2256 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11
2257 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
2258 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1
2259 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15
2260 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
2261 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1
2262 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16
2263 /* use enum gft_profile_upper_protocol_type
2264 * (use enum gft_profile_upper_protocol_type)
2266 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF
2267 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17
2268 /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */
2269 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF
2270 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21
2271 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF
2272 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25
2273 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7
2274 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29
2278 union gft_cam_line_union {
2279 struct gft_cam_line cam_line;
2280 struct gft_cam_line_mapped cam_line_mapped;
2285 * Used in gft_profile_key: Indication for ip version
2287 enum gft_profile_ip_version {
2288 GFT_PROFILE_IPV4 = 0,
2289 GFT_PROFILE_IPV6 = 1,
2290 MAX_GFT_PROFILE_IP_VERSION
2295 * Profile key stucr fot GFT logic in Prs
2297 struct gft_profile_key {
2299 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
2300 #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1
2301 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0
2302 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
2303 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1
2304 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1
2305 /* use enum gft_profile_upper_protocol_type
2306 * (use enum gft_profile_upper_protocol_type)
2308 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF
2309 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2
2310 /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */
2311 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF
2312 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6
2313 #define GFT_PROFILE_KEY_PF_ID_MASK 0xF
2314 #define GFT_PROFILE_KEY_PF_ID_SHIFT 10
2315 #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3
2316 #define GFT_PROFILE_KEY_RESERVED0_SHIFT 14
2321 * Used in gft_profile_key: Indication for tunnel type
2323 enum gft_profile_tunnel_type {
2324 GFT_PROFILE_NO_TUNNEL = 0,
2325 GFT_PROFILE_VXLAN_TUNNEL = 1,
2326 GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2,
2327 GFT_PROFILE_GRE_IP_TUNNEL = 3,
2328 GFT_PROFILE_GENEVE_MAC_TUNNEL = 4,
2329 GFT_PROFILE_GENEVE_IP_TUNNEL = 5,
2330 MAX_GFT_PROFILE_TUNNEL_TYPE
2335 * Used in gft_profile_key: Indication for protocol type
2337 enum gft_profile_upper_protocol_type {
2338 GFT_PROFILE_ROCE_PROTOCOL = 0,
2339 GFT_PROFILE_RROCE_PROTOCOL = 1,
2340 GFT_PROFILE_FCOE_PROTOCOL = 2,
2341 GFT_PROFILE_ICMP_PROTOCOL = 3,
2342 GFT_PROFILE_ARP_PROTOCOL = 4,
2343 GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5,
2344 GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6,
2345 GFT_PROFILE_TCP_PROTOCOL = 7,
2346 GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8,
2347 GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9,
2348 GFT_PROFILE_UDP_PROTOCOL = 10,
2349 GFT_PROFILE_USER_IP_1_INNER = 11,
2350 GFT_PROFILE_USER_IP_2_OUTER = 12,
2351 GFT_PROFILE_USER_ETH_1_INNER = 13,
2352 GFT_PROFILE_USER_ETH_2_OUTER = 14,
2353 GFT_PROFILE_RAW = 15,
2354 MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE
2359 * GFT RAM line struct
2361 struct gft_ram_line {
2363 #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3
2364 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0
2365 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1
2366 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2
2367 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1
2368 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3
2369 #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1
2370 #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4
2371 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1
2372 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5
2373 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1
2374 #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6
2375 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1
2376 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7
2377 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1
2378 #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8
2379 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1
2380 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9
2381 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1
2382 #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10
2383 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1
2384 #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11
2385 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1
2386 #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12
2387 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1
2388 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13
2389 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1
2390 #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14
2391 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1
2392 #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15
2393 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1
2394 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16
2395 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1
2396 #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17
2397 #define GFT_RAM_LINE_TTL_MASK 0x1
2398 #define GFT_RAM_LINE_TTL_SHIFT 18
2399 #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1
2400 #define GFT_RAM_LINE_ETHERTYPE_SHIFT 19
2401 #define GFT_RAM_LINE_RESERVED0_MASK 0x1
2402 #define GFT_RAM_LINE_RESERVED0_SHIFT 20
2403 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1
2404 #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21
2405 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1
2406 #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22
2407 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1
2408 #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23
2409 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1
2410 #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24
2411 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1
2412 #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25
2413 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1
2414 #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26
2415 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1
2416 #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27
2417 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1
2418 #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28
2419 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1
2420 #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29
2421 #define GFT_RAM_LINE_DST_PORT_MASK 0x1
2422 #define GFT_RAM_LINE_DST_PORT_SHIFT 30
2423 #define GFT_RAM_LINE_SRC_PORT_MASK 0x1U
2424 #define GFT_RAM_LINE_SRC_PORT_SHIFT 31
2426 #define GFT_RAM_LINE_DSCP_MASK 0x1
2427 #define GFT_RAM_LINE_DSCP_SHIFT 0
2428 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1
2429 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1
2430 #define GFT_RAM_LINE_DST_IP_MASK 0x1
2431 #define GFT_RAM_LINE_DST_IP_SHIFT 2
2432 #define GFT_RAM_LINE_SRC_IP_MASK 0x1
2433 #define GFT_RAM_LINE_SRC_IP_SHIFT 3
2434 #define GFT_RAM_LINE_PRIORITY_MASK 0x1
2435 #define GFT_RAM_LINE_PRIORITY_SHIFT 4
2436 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1
2437 #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5
2438 #define GFT_RAM_LINE_VLAN_MASK 0x1
2439 #define GFT_RAM_LINE_VLAN_SHIFT 6
2440 #define GFT_RAM_LINE_DST_MAC_MASK 0x1
2441 #define GFT_RAM_LINE_DST_MAC_SHIFT 7
2442 #define GFT_RAM_LINE_SRC_MAC_MASK 0x1
2443 #define GFT_RAM_LINE_SRC_MAC_SHIFT 8
2444 #define GFT_RAM_LINE_TENANT_ID_MASK 0x1
2445 #define GFT_RAM_LINE_TENANT_ID_SHIFT 9
2446 #define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF
2447 #define GFT_RAM_LINE_RESERVED1_SHIFT 10
2452 * Used in the first 2 bits for gft_ram_line: Indication for vlan mask
2454 enum gft_vlan_select {
2455 INNER_PROVIDER_VLAN = 0,
2457 OUTER_PROVIDER_VLAN = 2,
2463 #endif /* __ECORE_HSI_ETH__ */