2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #ifndef __ECORE_HSI_ETH__
10 #define __ECORE_HSI_ETH__
11 /************************************************************************/
12 /* Add include to common eth target for both eCore and protocol driver */
13 /************************************************************************/
14 #include "eth_common.h"
17 * The eth storm context for the Tstorm
19 struct tstorm_eth_conn_st_ctx {
24 * The eth storm context for the Pstorm
26 struct pstorm_eth_conn_st_ctx {
31 * The eth storm context for the Xstorm
33 struct xstorm_eth_conn_st_ctx {
37 struct xstorm_eth_conn_ag_ctx {
38 u8 reserved0 /* cdu_validation */;
39 u8 eth_state /* state */;
41 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
42 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
43 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
44 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
45 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
46 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
47 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
48 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
49 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
50 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
51 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
52 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
53 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
54 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
55 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
56 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
58 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
59 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
60 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
61 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
62 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
63 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
64 #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
65 #define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
66 #define XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1
67 #define XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4
68 #define XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1
69 #define XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5
70 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
71 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
72 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
73 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
75 #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
76 #define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
77 #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
78 #define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
79 #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
80 #define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
81 #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
82 #define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
84 #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
85 #define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
86 #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
87 #define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
88 #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
89 #define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
90 #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
91 #define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
93 #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
94 #define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
95 #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
96 #define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
97 #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
98 #define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
99 #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
100 #define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
102 #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
103 #define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
104 #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
105 #define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
106 #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
107 #define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
108 #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
109 #define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
111 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
112 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
113 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
114 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
115 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
116 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
117 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
118 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
120 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
121 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
122 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
123 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
124 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
125 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
126 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
127 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
128 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
129 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
131 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
132 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
133 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
134 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
135 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
136 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
137 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
138 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
139 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
140 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
141 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
142 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
143 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
144 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
145 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
146 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
148 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
149 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
150 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
151 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
152 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
153 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
154 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
155 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
156 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
157 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
158 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
159 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
160 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
161 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
162 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
163 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
165 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
166 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
167 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
168 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
169 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
170 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
171 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
172 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
173 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
174 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
175 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
176 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
177 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
178 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
179 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
180 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
182 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
183 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
184 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
185 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
186 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
187 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
188 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
189 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
190 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
191 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
192 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
193 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
194 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
195 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
196 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
197 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
199 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
200 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
201 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
202 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
203 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
204 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
205 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
206 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
207 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
208 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
209 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
210 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
211 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
212 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
213 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
214 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
216 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
217 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
218 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
219 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
220 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
221 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
222 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
223 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
224 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
225 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
226 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
227 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
228 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
229 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
230 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
231 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
233 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
234 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
235 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
236 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
237 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
238 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
239 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
240 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
241 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
242 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
243 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
244 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
245 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
246 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
247 u8 edpm_event_id /* byte2 */;
248 __le16 physical_q0 /* physical_q0 */;
249 __le16 word1 /* physical_q1 */;
250 __le16 edpm_num_bds /* physical_q2 */;
251 __le16 tx_bd_cons /* word3 */;
252 __le16 tx_bd_prod /* word4 */;
253 __le16 go_to_bd_cons /* word5 */;
254 __le16 conn_dpi /* conn_dpi */;
255 u8 byte3 /* byte3 */;
256 u8 byte4 /* byte4 */;
257 u8 byte5 /* byte5 */;
258 u8 byte6 /* byte6 */;
259 __le32 reg0 /* reg0 */;
260 __le32 reg1 /* reg1 */;
261 __le32 reg2 /* reg2 */;
262 __le32 reg3 /* reg3 */;
263 __le32 reg4 /* reg4 */;
264 __le32 reg5 /* cf_array0 */;
265 __le32 reg6 /* cf_array1 */;
266 __le16 word7 /* word7 */;
267 __le16 word8 /* word8 */;
268 __le16 word9 /* word9 */;
269 __le16 word10 /* word10 */;
270 __le32 reg7 /* reg7 */;
271 __le32 reg8 /* reg8 */;
272 __le32 reg9 /* reg9 */;
273 u8 byte7 /* byte7 */;
274 u8 byte8 /* byte8 */;
275 u8 byte9 /* byte9 */;
276 u8 byte10 /* byte10 */;
277 u8 byte11 /* byte11 */;
278 u8 byte12 /* byte12 */;
279 u8 byte13 /* byte13 */;
280 u8 byte14 /* byte14 */;
281 u8 byte15 /* byte15 */;
282 u8 byte16 /* byte16 */;
283 __le16 word11 /* word11 */;
284 __le32 reg10 /* reg10 */;
285 __le32 reg11 /* reg11 */;
286 __le32 reg12 /* reg12 */;
287 __le32 reg13 /* reg13 */;
288 __le32 reg14 /* reg14 */;
289 __le32 reg15 /* reg15 */;
290 __le32 reg16 /* reg16 */;
291 __le32 reg17 /* reg17 */;
292 __le32 reg18 /* reg18 */;
293 __le32 reg19 /* reg19 */;
294 __le16 word12 /* word12 */;
295 __le16 word13 /* word13 */;
296 __le16 word14 /* word14 */;
297 __le16 word15 /* word15 */;
301 * The eth storm context for the Ystorm
303 struct ystorm_eth_conn_st_ctx {
307 struct ystorm_eth_conn_ag_ctx {
308 u8 byte0 /* cdu_validation */;
309 u8 byte1 /* state */;
311 #define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
312 #define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
313 #define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
314 #define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
315 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
316 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2
317 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3
318 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4
319 #define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
320 #define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
322 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
323 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
324 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
325 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1
326 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
327 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
328 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
329 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
330 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
331 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
332 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
333 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
334 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
335 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
336 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
337 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
338 u8 byte2 /* byte2 */;
339 u8 byte3 /* byte3 */;
340 __le16 word0 /* word0 */;
341 __le32 terminate_spqe /* reg0 */;
342 __le32 reg1 /* reg1 */;
343 __le16 tx_bd_cons_upd /* word1 */;
344 __le16 word2 /* word2 */;
345 __le16 word3 /* word3 */;
346 __le16 word4 /* word4 */;
347 __le32 reg2 /* reg2 */;
348 __le32 reg3 /* reg3 */;
351 struct tstorm_eth_conn_ag_ctx {
352 u8 byte0 /* cdu_validation */;
353 u8 byte1 /* state */;
355 #define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
356 #define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
357 #define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
358 #define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
359 #define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1
360 #define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
361 #define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1
362 #define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
363 #define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1
364 #define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
365 #define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1
366 #define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
367 #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
368 #define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
370 #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
371 #define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
372 #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
373 #define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
374 #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
375 #define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
376 #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
377 #define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
379 #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
380 #define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
381 #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
382 #define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
383 #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
384 #define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
385 #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
386 #define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
388 #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
389 #define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
390 #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
391 #define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
392 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
393 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
394 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
395 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
396 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
397 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
398 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
399 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
401 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
402 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
403 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
404 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
405 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
406 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
407 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
408 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
409 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
410 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
411 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
412 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
413 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
414 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
415 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
416 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
418 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
419 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
420 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
421 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
422 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
423 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
424 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
425 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
426 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
427 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
428 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1
429 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
430 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
431 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
432 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
433 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
434 __le32 reg0 /* reg0 */;
435 __le32 reg1 /* reg1 */;
436 __le32 reg2 /* reg2 */;
437 __le32 reg3 /* reg3 */;
438 __le32 reg4 /* reg4 */;
439 __le32 reg5 /* reg5 */;
440 __le32 reg6 /* reg6 */;
441 __le32 reg7 /* reg7 */;
442 __le32 reg8 /* reg8 */;
443 u8 byte2 /* byte2 */;
444 u8 byte3 /* byte3 */;
445 __le16 rx_bd_cons /* word0 */;
446 u8 byte4 /* byte4 */;
447 u8 byte5 /* byte5 */;
448 __le16 rx_bd_prod /* word1 */;
449 __le16 word2 /* conn_dpi */;
450 __le16 word3 /* word3 */;
451 __le32 reg9 /* reg9 */;
452 __le32 reg10 /* reg10 */;
455 struct ustorm_eth_conn_ag_ctx {
456 u8 byte0 /* cdu_validation */;
457 u8 byte1 /* state */;
459 #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
460 #define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
461 #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
462 #define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
463 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
464 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2
465 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
466 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4
467 #define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
468 #define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
470 #define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
471 #define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
472 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
473 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
474 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
475 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
476 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
477 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
479 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
480 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
481 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
482 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
483 #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
484 #define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
485 #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
486 #define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
487 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
488 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
489 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
490 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
491 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
492 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
493 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
494 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
496 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
497 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
498 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
499 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
500 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
501 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
502 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
503 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
504 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
505 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
506 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
507 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
508 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
509 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
510 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
511 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
512 u8 byte2 /* byte2 */;
513 u8 byte3 /* byte3 */;
514 __le16 word0 /* conn_dpi */;
515 __le16 tx_bd_cons /* word1 */;
516 __le32 reg0 /* reg0 */;
517 __le32 reg1 /* reg1 */;
518 __le32 reg2 /* reg2 */;
519 __le32 tx_int_coallecing_timeset /* reg3 */;
520 __le16 tx_drv_bd_cons /* word2 */;
521 __le16 rx_drv_cqe_cons /* word3 */;
525 * The eth storm context for the Ustorm
527 struct ustorm_eth_conn_st_ctx {
532 * The eth storm context for the Mstorm
534 struct mstorm_eth_conn_st_ctx {
539 * eth connection context
541 struct eth_conn_context {
542 struct tstorm_eth_conn_st_ctx tstorm_st_context
543 /* tstorm storm context */;
544 struct regpair tstorm_st_padding[2] /* padding */;
545 struct pstorm_eth_conn_st_ctx pstorm_st_context
546 /* pstorm storm context */;
547 struct xstorm_eth_conn_st_ctx xstorm_st_context
548 /* xstorm storm context */;
549 struct xstorm_eth_conn_ag_ctx xstorm_ag_context
550 /* xstorm aggregative context */;
551 struct ystorm_eth_conn_st_ctx ystorm_st_context
552 /* ystorm storm context */;
553 struct ystorm_eth_conn_ag_ctx ystorm_ag_context
554 /* ystorm aggregative context */;
555 struct tstorm_eth_conn_ag_ctx tstorm_ag_context
556 /* tstorm aggregative context */;
557 struct ustorm_eth_conn_ag_ctx ustorm_ag_context
558 /* ustorm aggregative context */;
559 struct ustorm_eth_conn_st_ctx ustorm_st_context
560 /* ustorm storm context */;
561 struct mstorm_eth_conn_st_ctx mstorm_st_context
562 /* mstorm storm context */;
566 * Ethernet filter types: mac/vlan/pair
568 enum eth_error_code {
569 ETH_OK = 0x00 /* command succeeded */,
570 ETH_FILTERS_MAC_ADD_FAIL_FULL
571 /* mac add filters command failed due to cam full state */,
572 ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2
573 /* mac add filters command failed due to mtt2 full state */,
574 ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2
575 /* mac add filters command failed due to duplicate mac address */,
576 ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2
577 /* mac add filters command failed due to duplicate mac address */,
578 ETH_FILTERS_MAC_DEL_FAIL_NOF
579 /* mac delete filters command failed due to not found state */,
580 ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2
581 /* mac delete filters command failed due to not found state */,
582 ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2
583 /* mac delete filters command failed due to not found state */,
584 ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC
585 /* mac add filters command failed due to MAC Address of
589 ETH_FILTERS_VLAN_ADD_FAIL_FULL
590 /* vlan add filters command failed due to cam full state */,
591 ETH_FILTERS_VLAN_ADD_FAIL_DUP
592 /* vlan add filters command failed due to duplicate VLAN filter */,
593 ETH_FILTERS_VLAN_DEL_FAIL_NOF
594 /* vlan delete filters command failed due to not found state */,
595 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1
596 /* vlan delete filters command failed due to not found state */,
597 ETH_FILTERS_PAIR_ADD_FAIL_DUP
598 /* pair add filters command failed due to duplicate request */,
599 ETH_FILTERS_PAIR_ADD_FAIL_FULL
600 /* pair add filters command failed due to full state */,
601 ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC
602 /* pair add filters command failed due to full state */,
603 ETH_FILTERS_PAIR_DEL_FAIL_NOF
604 /* pair add filters command failed due not found state */,
605 ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1
606 /* pair add filters command failed due not found state */,
607 ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC
608 /* pair add filters command failed due to MAC Address of
612 ETH_FILTERS_VNI_ADD_FAIL_FULL
613 /* vni add filters command failed due to cam full state */,
614 ETH_FILTERS_VNI_ADD_FAIL_DUP
615 /* vni add filters command failed due to duplicate VNI filter */,
620 * opcodes for the event ring
622 enum eth_event_opcode {
624 ETH_EVENT_VPORT_START,
625 ETH_EVENT_VPORT_UPDATE,
626 ETH_EVENT_VPORT_STOP,
627 ETH_EVENT_TX_QUEUE_START,
628 ETH_EVENT_TX_QUEUE_STOP,
629 ETH_EVENT_RX_QUEUE_START,
630 ETH_EVENT_RX_QUEUE_UPDATE,
631 ETH_EVENT_RX_QUEUE_STOP,
632 ETH_EVENT_FILTERS_UPDATE,
633 ETH_EVENT_RX_ADD_OPENFLOW_FILTER,
634 ETH_EVENT_RX_DELETE_OPENFLOW_FILTER,
635 ETH_EVENT_RX_CREATE_OPENFLOW_ACTION,
636 ETH_EVENT_RX_ADD_UDP_FILTER,
637 ETH_EVENT_RX_DELETE_UDP_FILTER,
638 ETH_EVENT_RX_ADD_GFT_FILTER,
639 ETH_EVENT_RX_DELETE_GFT_FILTER,
640 ETH_EVENT_RX_CREATE_GFT_ACTION,
645 * Classify rule types in E2/E3
647 enum eth_filter_action {
648 ETH_FILTER_ACTION_UNUSED,
649 ETH_FILTER_ACTION_REMOVE,
650 ETH_FILTER_ACTION_ADD,
651 ETH_FILTER_ACTION_REMOVE_ALL
652 /* Remove all filters of given type and vport ID. */,
653 MAX_ETH_FILTER_ACTION
657 * Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$
659 struct eth_filter_cmd {
660 u8 type /* Filter Type (MAC/VLAN/Pair/VNI) */;
661 u8 vport_id /* the vport id */;
662 u8 action /* filter command action: add/remove/replace */;
672 * $$KEEP_ENDIANNESS$$
674 struct eth_filter_cmd_header {
675 u8 rx /* If set, apply these commands to the RX path */;
676 u8 tx /* If set, apply these commands to the TX path */;
677 u8 cmd_cnt /* Number of filter commands */;
683 * Ethernet filter types: mac/vlan/pair
685 enum eth_filter_type {
686 ETH_FILTER_TYPE_UNUSED,
687 ETH_FILTER_TYPE_MAC /* Add/remove a MAC address */,
688 ETH_FILTER_TYPE_VLAN /* Add/remove a VLAN */,
689 ETH_FILTER_TYPE_PAIR /* Add/remove a MAC-VLAN pair */,
690 ETH_FILTER_TYPE_INNER_MAC /* Add/remove a inner MAC address */,
691 ETH_FILTER_TYPE_INNER_VLAN /* Add/remove a inner VLAN */,
692 ETH_FILTER_TYPE_INNER_PAIR /* Add/remove a inner MAC-VLAN pair */,
693 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR /* Add/remove a inner MAC-VNI pair */
695 ETH_FILTER_TYPE_MAC_VNI_PAIR /* Add/remove a MAC-VNI pair */,
696 ETH_FILTER_TYPE_VNI /* Add/remove a VNI */,
701 * eth IPv4 Fragment Type
703 enum eth_ipv4_frag_type {
704 ETH_IPV4_NOT_FRAG /* IPV4 Packet Not Fragmented */,
706 /* First Fragment of IPv4 Packet (contains headers) */,
707 ETH_IPV4_NON_FIRST_FRAG
708 /* Non-First Fragment of IPv4 Packet (does not contain headers) */,
709 MAX_ETH_IPV4_FRAG_TYPE
713 * eth IPv4 Fragment Type
722 * Ethernet Ramrod Command IDs
724 enum eth_ramrod_cmd_id {
726 ETH_RAMROD_VPORT_START /* VPort Start Ramrod */,
727 ETH_RAMROD_VPORT_UPDATE /* VPort Update Ramrod */,
728 ETH_RAMROD_VPORT_STOP /* VPort Stop Ramrod */,
729 ETH_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */,
730 ETH_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */,
731 ETH_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */,
732 ETH_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */,
733 ETH_RAMROD_FILTERS_UPDATE /* Add or Remove Mac/Vlan/Pair filters */,
734 ETH_RAMROD_RX_QUEUE_UPDATE /* RX Queue Update Ramrod */,
735 ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION
736 /* RX - Create an Openflow Action */,
737 ETH_RAMROD_RX_ADD_OPENFLOW_FILTER
738 /* RX - Add an Openflow Filter to the Searcher */,
739 ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER
740 /* RX - Delete an Openflow Filter to the Searcher */,
741 ETH_RAMROD_RX_ADD_UDP_FILTER /* RX - Add a UDP Filter to the Searcher */
743 ETH_RAMROD_RX_DELETE_UDP_FILTER
744 /* RX - Delete a UDP Filter to the Searcher */,
745 ETH_RAMROD_RX_CREATE_GFT_ACTION /* RX - Create an Gft Action */,
746 ETH_RAMROD_RX_DELETE_GFT_FILTER
747 /* RX - Delete an GFT Filter to the Searcher */,
748 ETH_RAMROD_RX_ADD_GFT_FILTER
749 /* RX - Add an GFT Filter to the Searcher */,
750 MAX_ETH_RAMROD_CMD_ID
754 * return code from eth sp ramrods
756 struct eth_return_code {
758 #define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F
759 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
760 #define ETH_RETURN_CODE_RESERVED_MASK 0x3
761 #define ETH_RETURN_CODE_RESERVED_SHIFT 5
762 #define ETH_RETURN_CODE_RX_TX_MASK 0x1
763 #define ETH_RETURN_CODE_RX_TX_SHIFT 7
767 * What to do in case an error occurs
770 ETH_TX_ERR_DROP /* Drop erroneous packet. */,
771 ETH_TX_ERR_ASSERT_MALICIOUS
772 /* Assert an interrupt for PF, declare as malicious for VF */,
777 * Array of the different error type behaviors
779 struct eth_tx_err_vals {
781 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1
782 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0
783 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1
784 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1
785 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1
786 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2
787 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1
788 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3
789 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1
790 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4
791 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1
792 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5
793 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
794 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6
795 #define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF
796 #define ETH_TX_ERR_VALS_RESERVED_SHIFT 7
800 * vport rss configuration data
802 struct eth_vport_rss_config {
804 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
805 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0
806 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
807 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1
808 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
809 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2
810 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
811 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3
812 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
813 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4
814 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
815 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5
816 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
817 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
818 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF
819 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7
821 u8 rss_mode /* The RSS mode for this function */;
822 u8 update_rss_key /* if set update the rss key */;
823 u8 update_rss_ind_table /* if set update the indirection table */;
824 u8 update_rss_capabilities /* if set update the capabilities */;
825 u8 tbl_size /* rss mask (Tbl size) */;
827 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM]
828 /* RSS indirection table */;
829 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS] /* RSS key supplied to us by OS */
837 enum eth_vport_rss_mode {
838 ETH_VPORT_RSS_MODE_DISABLED /* RSS Disabled */,
839 ETH_VPORT_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */,
840 MAX_ETH_VPORT_RSS_MODE
844 * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$
846 struct eth_vport_rx_mode {
848 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
849 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0
850 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
851 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
852 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
853 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
854 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
855 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3
856 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
857 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4
858 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
859 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5
860 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF
861 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6
866 * Command for setting tpa parameters
868 struct eth_vport_tpa_param {
869 u8 tpa_ipv4_en_flg /* Enable TPA for IPv4 packets */;
870 u8 tpa_ipv6_en_flg /* Enable TPA for IPv6 packets */;
871 u8 tpa_ipv4_tunn_en_flg /* Enable TPA for IPv4 over tunnel */;
872 u8 tpa_ipv6_tunn_en_flg /* Enable TPA for IPv6 over tunnel */;
873 u8 tpa_pkt_split_flg;
874 u8 tpa_hdr_data_split_flg
875 /* If set, put header of first TPA segment on bd and data on SGE */
877 u8 tpa_gro_consistent_flg
878 /* If set, GRO data consistent will checked for TPA continue */;
880 /* maximum number of opened aggregations per v-port */;
881 __le16 tpa_max_size /* maximal size for the aggregated TPA packets */;
882 __le16 tpa_min_size_to_start
883 /* minimum TCP payload size for a packet to start aggregation */;
884 __le16 tpa_min_size_to_cont
885 /* minimum TCP payload size for a packet to continue aggregation */
888 /* maximal number of buffers that can be used for one aggregation */
894 * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$
896 struct eth_vport_tx_mode {
898 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
899 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0
900 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
901 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
902 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
903 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2
904 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
905 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
906 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
907 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
908 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF
909 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5
914 * Ramrod data for rx add gft filter data
916 struct rx_add_gft_filter_data {
917 struct regpair pkt_hdr_addr /* Packet Header That Defines GFT Filter */
919 __le16 action_icid /* ICID of Action to run for this filter */;
920 __le16 pkt_hdr_length /* Packet Header Length */;
925 * Ramrod data for rx add openflow filter
927 struct rx_add_openflow_filter_data {
928 __le16 action_icid /* CID of Action to run for this filter */;
929 u8 priority /* Searcher String - Packet priority */;
931 __le32 tenant_id /* Searcher String - Tenant ID */;
932 __le16 dst_mac_hi /* Searcher String - Destination Mac Bytes 0 to 1 */;
933 __le16 dst_mac_mid /* Searcher String - Destination Mac Bytes 2 to 3 */
935 __le16 dst_mac_lo /* Searcher String - Destination Mac Bytes 4 to 5 */;
936 __le16 src_mac_hi /* Searcher String - Source Mac 0 to 1 */;
937 __le16 src_mac_mid /* Searcher String - Source Mac 2 to 3 */;
938 __le16 src_mac_lo /* Searcher String - Source Mac 4 to 5 */;
939 __le16 vlan_id /* Searcher String - Vlan ID */;
940 __le16 l2_eth_type /* Searcher String - Last L2 Ethertype */;
941 u8 ipv4_dscp /* Searcher String - IPv4 6 MSBs of the TOS Field */;
942 u8 ipv4_frag_type /* Searcher String - IPv4 Fragmentation Type */;
943 u8 ipv4_over_ip /* Searcher String - IPv4 Over IP Type */;
944 u8 tenant_id_exists /* Searcher String - Tenant ID Exists */;
945 __le32 ipv4_dst_addr /* Searcher String - IPv4 Destination Address */;
946 __le32 ipv4_src_addr /* Searcher String - IPv4 Source Address */;
947 __le16 l4_dst_port /* Searcher String - TCP/UDP Destination Port */;
948 __le16 l4_src_port /* Searcher String - TCP/UDP Source Port */;
952 * Ramrod data for rx create gft action
954 struct rx_create_gft_action_data {
955 u8 vport_id /* Vport Id of GFT Action */;
960 * Ramrod data for rx create openflow action
962 struct rx_create_openflow_action_data {
963 u8 vport_id /* ID of RX queue */;
968 * Ramrod data for rx queue start ramrod
970 struct rx_queue_start_ramrod_data {
971 __le16 rx_queue_id /* ID of RX queue */;
972 __le16 num_of_pbl_pages /* Num of pages in CQE PBL */;
973 __le16 bd_max_bytes /* maximal bytes that can be places on the bd */;
974 __le16 sb_id /* Status block ID */;
975 u8 sb_index /* index of the protocol index */;
976 u8 vport_id /* ID of virtual port */;
977 u8 default_rss_queue_flg /* set queue as default rss queue if set */;
978 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
979 u8 complete_event_flg /* post completion to the event ring if set */;
980 u8 stats_counter_id /* Statistics counter ID */;
981 u8 pin_context /* Pin context in CCFC to improve performance */;
982 u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD/SGE fetch */;
983 u8 pxp_tph_valid_pkt /* PXP command TPH Valid - for packet placement */
986 /* PXP command Steering tag hint. Use enum pxp_tph_st_hint */;
987 __le16 pxp_st_index /* PXP command Steering tag index */;
989 /* Indicates that current queue belongs to poll-mode driver */;
992 /* Initial value for the toggle valid bit - used in PMD mode */;
994 __le16 reserved1 /* FW reserved. */;
995 struct regpair cqe_pbl_addr /* Base address on host of CQE PBL */;
996 struct regpair bd_base /* bd address of the first bd page */;
997 struct regpair reserved2 /* FW reserved. */;
1001 * Ramrod data for rx queue start ramrod
1003 struct rx_queue_stop_ramrod_data {
1004 __le16 rx_queue_id /* ID of RX queue */;
1005 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
1006 u8 complete_event_flg /* post completion to the event ring if set */;
1007 u8 vport_id /* ID of virtual port */;
1012 * Ramrod data for rx queue update ramrod
1014 struct rx_queue_update_ramrod_data {
1015 __le16 rx_queue_id /* ID of RX queue */;
1016 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
1017 u8 complete_event_flg /* post completion to the event ring if set */;
1018 u8 vport_id /* ID of virtual port */;
1020 u8 reserved1 /* FW reserved. */;
1021 u8 reserved2 /* FW reserved. */;
1022 u8 reserved3 /* FW reserved. */;
1023 __le16 reserved4 /* FW reserved. */;
1024 __le16 reserved5 /* FW reserved. */;
1025 struct regpair reserved6 /* FW reserved. */;
1029 * Ramrod data for rx Add UDP Filter
1031 struct rx_udp_filter_data {
1032 __le16 action_icid /* CID of Action to run for this filter */;
1033 __le16 vlan_id /* Searcher String - Vlan ID */;
1034 u8 ip_type /* Searcher String - IP Type */;
1035 u8 tenant_id_exists /* Searcher String - Tenant ID Exists */;
1037 __le32 ip_dst_addr[4];
1038 /* Searcher String-IP Dest Addr for IPv4 use ip_dst_addr[0] only */
1040 __le32 ip_src_addr[4]
1041 /* Searcher String-IP Src Addr, for IPv4 use ip_dst_addr[0] only */
1043 __le16 udp_dst_port /* Searcher String - UDP Destination Port */;
1044 __le16 udp_src_port /* Searcher String - UDP Source Port */;
1045 __le32 tenant_id /* Searcher String - Tenant ID */;
1049 * Ramrod data for rx queue start ramrod
1051 struct tx_queue_start_ramrod_data {
1052 __le16 sb_id /* Status block ID */;
1053 u8 sb_index /* Status block protocol index */;
1054 u8 vport_id /* VPort ID */;
1055 u8 reserved0 /* FW reserved. */;
1056 u8 stats_counter_id /* Statistics counter ID to use */;
1057 __le16 qm_pq_id /* QM PQ ID */;
1059 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
1060 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
1061 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
1062 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1
1063 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1
1064 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2
1065 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
1066 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3
1067 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
1068 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4
1069 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
1070 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5
1071 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3
1072 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6
1073 u8 pxp_st_hint /* PXP command Steering tag hint */;
1074 u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD fetch */;
1075 u8 pxp_tph_valid_pkt /* PXP command TPH Valid - for packet fetch */;
1076 __le16 pxp_st_index /* PXP command Steering tag index */;
1077 __le16 comp_agg_size /* TX completion min agg size - for PMD queues */;
1078 __le16 queue_zone_id /* queue zone ID to use */;
1079 __le16 test_dup_count /* In Test Mode, number of duplications */;
1080 __le16 pbl_size /* Number of BD pages pointed by PBL */;
1082 /* unique Queue ID - currently used only by PMD flow */;
1083 struct regpair pbl_base_addr /* address of the pbl page */;
1084 struct regpair bd_cons_address
1085 /* BD consumer address in host - for PMD queues */;
1089 * Ramrod data for tx queue stop ramrod
1091 struct tx_queue_stop_ramrod_data {
1096 * Ramrod data for vport update ramrod
1098 struct vport_filter_update_ramrod_data {
1099 struct eth_filter_cmd_header filter_cmd_hdr
1100 /* Header for Filter Commands (RX/TX, Add/Remove/Replace, etc) */;
1101 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT]
1102 /* Filter Commands */;
1106 * Ramrod data for vport start ramrod
1108 struct vport_start_ramrod_data {
1112 u8 drop_ttl0_en /* if set, drop packet with ttl=0 */;
1113 u8 inner_vlan_removal_en;
1114 struct eth_vport_rx_mode rx_mode /* Rx filter data */;
1115 struct eth_vport_tx_mode tx_mode /* Tx filter data */;
1116 struct eth_vport_tpa_param tpa_param /* TPA configuration parameters */
1118 __le16 default_vlan /* Default Vlan value to be forced by FW */;
1119 u8 tx_switching_en /* Tx switching is enabled for current Vport */;
1121 /* Anti-spoofing verification is set for current Vport */;
1123 /* If set, the default Vlan value is forced by the FW */;
1124 u8 handle_ptp_pkts /* If set, the vport handles PTP Timesync Packets */
1126 u8 silent_vlan_removal_en;
1127 /* If enable then innerVlan will be striped and not written to cqe */
1129 struct eth_tx_err_vals tx_err_behav
1130 /* Desired behavior per TX error type */;
1131 u8 zero_placement_offset;
1136 * Ramrod data for vport stop ramrod
1138 struct vport_stop_ramrod_data {
1144 * Ramrod data for vport update ramrod
1146 struct vport_update_ramrod_data_cmn {
1148 u8 update_rx_active_flg /* set if rx active flag should be handled */;
1149 u8 rx_active_flg /* rx active flag value */;
1150 u8 update_tx_active_flg /* set if tx active flag should be handled */;
1151 u8 tx_active_flg /* tx active flag value */;
1152 u8 update_rx_mode_flg /* set if rx state data should be handled */;
1153 u8 update_tx_mode_flg /* set if tx state data should be handled */;
1154 u8 update_approx_mcast_flg
1155 /* set if approx. mcast data should be handled */;
1156 u8 update_rss_flg /* set if rss data should be handled */;
1157 u8 update_inner_vlan_removal_en_flg
1158 /* set if inner_vlan_removal_en should be handled */;
1159 u8 inner_vlan_removal_en;
1160 u8 update_tpa_param_flg;
1161 u8 update_tpa_en_flg /* set if tpa enable changes */;
1162 u8 update_tx_switching_en_flg
1163 /* set if tx switching en flag should be handled */;
1164 u8 tx_switching_en /* tx switching en value */;
1165 u8 update_anti_spoofing_en_flg
1166 /* set if anti spoofing flag should be handled */;
1167 u8 anti_spoofing_en /* Anti-spoofing verification en value */;
1168 u8 update_handle_ptp_pkts
1169 /* set if handle_ptp_pkts should be handled. */;
1170 u8 handle_ptp_pkts /* If set, the vport handles PTP Timesync Packets */
1172 u8 update_default_vlan_en_flg
1173 /* If set, the default Vlan enable flag is updated */;
1175 /* If set, the default Vlan value is forced by the FW */;
1176 u8 update_default_vlan_flg
1177 /* If set, the default Vlan value is updated */;
1178 __le16 default_vlan /* Default Vlan value to be forced by FW */;
1179 u8 update_accept_any_vlan_flg
1180 /* set if accept_any_vlan should be handled */;
1181 u8 accept_any_vlan /* accept_any_vlan updated value */;
1182 u8 silent_vlan_removal_en;
1184 /* If set, MTU will be updated. Vport must be not active. */;
1185 __le16 mtu /* New MTU value. Used if update_mtu_flg are set */;
1189 struct vport_update_ramrod_mcast {
1190 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS] /* multicast bins */;
1194 * Ramrod data for vport update ramrod
1196 struct vport_update_ramrod_data {
1197 struct vport_update_ramrod_data_cmn common
1198 /* Common data for all vport update ramrods */;
1199 struct eth_vport_rx_mode rx_mode /* vport rx mode bitmap */;
1200 struct eth_vport_tx_mode tx_mode /* vport tx mode bitmap */;
1201 struct eth_vport_tpa_param tpa_param /* TPA configuration parameters */
1203 struct vport_update_ramrod_mcast approx_mcast;
1204 struct eth_vport_rss_config rss_config /* rss config data */;
1208 * GFT CAM line struct
1210 struct gft_cam_line {
1212 #define GFT_CAM_LINE_VALID_MASK 0x1
1213 #define GFT_CAM_LINE_VALID_SHIFT 0
1214 #define GFT_CAM_LINE_DATA_MASK 0x3FFF
1215 #define GFT_CAM_LINE_DATA_SHIFT 1
1216 #define GFT_CAM_LINE_MASK_BITS_MASK 0x3FFF
1217 #define GFT_CAM_LINE_MASK_BITS_SHIFT 15
1218 #define GFT_CAM_LINE_RESERVED1_MASK 0x7
1219 #define GFT_CAM_LINE_RESERVED1_SHIFT 29
1223 * GFT CAM line struct (for driversim use)
1225 struct gft_cam_line_mapped {
1227 #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1
1228 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0
1229 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1
1230 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1
1231 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1
1232 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2
1233 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF
1234 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3
1235 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF
1236 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7
1237 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF
1238 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11
1239 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1
1240 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15
1241 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1
1242 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16
1243 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF
1244 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17
1245 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF
1246 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21
1247 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF
1248 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25
1249 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7
1250 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29
1253 union gft_cam_line_union {
1254 struct gft_cam_line cam_line;
1255 struct gft_cam_line_mapped cam_line_mapped;
1259 * Used in gft_profile_key: Indication for ip version
1261 enum gft_profile_ip_version {
1262 GFT_PROFILE_IPV4 = 0,
1263 GFT_PROFILE_IPV6 = 1,
1264 MAX_GFT_PROFILE_IP_VERSION
1268 * Profile key stucr fot GFT logic in Prs
1270 struct gft_profile_key {
1272 #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1
1273 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0
1274 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1
1275 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1
1276 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF
1277 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2
1278 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF
1279 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6
1280 #define GFT_PROFILE_KEY_PF_ID_MASK 0xF
1281 #define GFT_PROFILE_KEY_PF_ID_SHIFT 10
1282 #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3
1283 #define GFT_PROFILE_KEY_RESERVED0_SHIFT 14
1287 * Used in gft_profile_key: Indication for tunnel type
1289 enum gft_profile_tunnel_type {
1290 GFT_PROFILE_NO_TUNNEL = 0,
1291 GFT_PROFILE_VXLAN_TUNNEL = 1,
1292 GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2,
1293 GFT_PROFILE_GRE_IP_TUNNEL = 3,
1294 GFT_PROFILE_GENEVE_MAC_TUNNEL = 4,
1295 GFT_PROFILE_GENEVE_IP_TUNNEL = 5,
1296 MAX_GFT_PROFILE_TUNNEL_TYPE
1300 * Used in gft_profile_key: Indication for protocol type
1302 enum gft_profile_upper_protocol_type {
1303 GFT_PROFILE_ROCE_PROTOCOL = 0,
1304 GFT_PROFILE_RROCE_PROTOCOL = 1,
1305 GFT_PROFILE_FCOE_PROTOCOL = 2,
1306 GFT_PROFILE_ICMP_PROTOCOL = 3,
1307 GFT_PROFILE_ARP_PROTOCOL = 4,
1308 GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5,
1309 GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6,
1310 GFT_PROFILE_TCP_PROTOCOL = 7,
1311 GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8,
1312 GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9,
1313 GFT_PROFILE_UDP_PROTOCOL = 10,
1314 GFT_PROFILE_USER_IP_1_INNER = 11,
1315 GFT_PROFILE_USER_IP_2_OUTER = 12,
1316 GFT_PROFILE_USER_ETH_1_INNER = 13,
1317 GFT_PROFILE_USER_ETH_2_OUTER = 14,
1318 GFT_PROFILE_RAW = 15,
1319 MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE
1323 * GFT RAM line struct
1325 struct gft_ram_line {
1327 #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3
1328 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0
1329 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1
1330 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2
1331 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1
1332 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3
1333 #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1
1334 #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4
1335 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1
1336 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5
1337 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1
1338 #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6
1339 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1
1340 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7
1341 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1
1342 #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8
1343 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1
1344 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9
1345 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1
1346 #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10
1347 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1
1348 #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11
1349 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1
1350 #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12
1351 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1
1352 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13
1353 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1
1354 #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14
1355 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1
1356 #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15
1357 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1
1358 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16
1359 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1
1360 #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17
1361 #define GFT_RAM_LINE_TTL_MASK 0x1
1362 #define GFT_RAM_LINE_TTL_SHIFT 18
1363 #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1
1364 #define GFT_RAM_LINE_ETHERTYPE_SHIFT 19
1365 #define GFT_RAM_LINE_RESERVED0_MASK 0x1
1366 #define GFT_RAM_LINE_RESERVED0_SHIFT 20
1367 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1
1368 #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21
1369 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1
1370 #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22
1371 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1
1372 #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23
1373 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1
1374 #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24
1375 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1
1376 #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25
1377 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1
1378 #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26
1379 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1
1380 #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27
1381 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1
1382 #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28
1383 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1
1384 #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29
1385 #define GFT_RAM_LINE_DST_PORT_MASK 0x1
1386 #define GFT_RAM_LINE_DST_PORT_SHIFT 30
1387 #define GFT_RAM_LINE_SRC_PORT_MASK 0x1
1388 #define GFT_RAM_LINE_SRC_PORT_SHIFT 31
1390 #define GFT_RAM_LINE_DSCP_MASK 0x1
1391 #define GFT_RAM_LINE_DSCP_SHIFT 0
1392 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1
1393 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1
1394 #define GFT_RAM_LINE_DST_IP_MASK 0x1
1395 #define GFT_RAM_LINE_DST_IP_SHIFT 2
1396 #define GFT_RAM_LINE_SRC_IP_MASK 0x1
1397 #define GFT_RAM_LINE_SRC_IP_SHIFT 3
1398 #define GFT_RAM_LINE_PRIORITY_MASK 0x1
1399 #define GFT_RAM_LINE_PRIORITY_SHIFT 4
1400 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1
1401 #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5
1402 #define GFT_RAM_LINE_VLAN_MASK 0x1
1403 #define GFT_RAM_LINE_VLAN_SHIFT 6
1404 #define GFT_RAM_LINE_DST_MAC_MASK 0x1
1405 #define GFT_RAM_LINE_DST_MAC_SHIFT 7
1406 #define GFT_RAM_LINE_SRC_MAC_MASK 0x1
1407 #define GFT_RAM_LINE_SRC_MAC_SHIFT 8
1408 #define GFT_RAM_LINE_TENANT_ID_MASK 0x1
1409 #define GFT_RAM_LINE_TENANT_ID_SHIFT 9
1410 #define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF
1411 #define GFT_RAM_LINE_RESERVED1_SHIFT 10
1415 * Used in the first 2 bits for gft_ram_line: Indication for vlan mask
1417 enum gft_vlan_select {
1418 INNER_PROVIDER_VLAN = 0,
1420 OUTER_PROVIDER_VLAN = 2,
1425 struct mstorm_eth_conn_ag_ctx {
1426 u8 byte0 /* cdu_validation */;
1427 u8 byte1 /* state */;
1429 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
1430 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1431 #define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
1432 #define MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
1433 #define MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
1434 #define MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2
1435 #define MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
1436 #define MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4
1437 #define MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
1438 #define MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
1440 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
1441 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
1442 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
1443 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1
1444 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
1445 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
1446 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
1447 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
1448 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
1449 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
1450 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
1451 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
1452 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
1453 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
1454 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
1455 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
1456 __le16 word0 /* word0 */;
1457 __le16 word1 /* word1 */;
1458 __le32 reg0 /* reg0 */;
1459 __le32 reg1 /* reg1 */;
1462 /* @DPDK: xstormEthConnAgCtxDqExtLdPart */
1463 struct xstorm_eth_conn_ag_ctx_dq_ext_ld_part {
1464 u8 reserved0 /* cdu_validation */;
1465 u8 eth_state /* state */;
1467 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
1468 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
1469 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1
1470 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1
1471 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1
1472 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2
1473 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
1474 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
1475 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1
1476 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4
1477 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1
1478 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5
1479 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1
1480 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6
1481 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1
1482 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7
1484 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1
1485 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0
1486 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1
1487 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1
1488 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1
1489 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2
1490 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
1491 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
1492 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
1493 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
1494 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_MASK 0x1
1495 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_SHIFT 5
1496 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1
1497 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6
1498 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1
1499 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7
1501 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
1502 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0
1503 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
1504 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2
1505 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
1506 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4
1507 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
1508 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6
1510 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
1511 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0
1512 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
1513 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2
1514 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
1515 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4
1516 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
1517 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6
1519 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
1520 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0
1521 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
1522 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2
1523 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
1524 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4
1525 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
1526 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6
1528 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
1529 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0
1530 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
1531 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2
1532 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
1533 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4
1534 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
1535 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6
1537 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
1538 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0
1539 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
1540 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2
1541 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
1542 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4
1543 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
1544 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6
1546 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
1547 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0
1548 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
1549 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2
1550 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
1551 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
1552 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
1553 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
1554 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
1555 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
1557 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
1558 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
1559 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
1560 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
1561 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
1562 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
1563 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
1564 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
1565 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
1566 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
1567 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1
1568 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5
1569 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
1570 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
1571 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
1572 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
1574 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
1575 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
1576 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
1577 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
1578 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
1579 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
1580 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
1581 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
1582 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
1583 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
1584 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
1585 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
1586 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1
1587 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6
1588 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1
1589 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7
1591 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1
1592 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0
1593 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1
1594 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1
1595 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1
1596 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2
1597 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1
1598 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3
1599 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
1600 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
1601 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1
1602 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5
1603 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1
1604 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6
1605 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1
1606 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7
1608 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1
1609 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0
1610 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1
1611 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1
1612 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1
1613 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2
1614 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
1615 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
1616 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
1617 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
1618 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
1619 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
1620 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
1621 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
1622 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
1623 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
1625 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
1626 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
1627 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
1628 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
1629 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
1630 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
1631 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
1632 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
1633 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
1634 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
1635 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
1636 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
1637 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
1638 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
1639 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
1640 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
1642 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
1643 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
1644 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
1645 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
1646 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
1647 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
1648 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
1649 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
1650 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
1651 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
1652 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
1653 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
1654 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
1655 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
1656 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
1657 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
1659 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1
1660 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0
1661 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1
1662 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1
1663 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1
1664 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2
1665 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1
1666 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3
1667 #define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1
1668 #define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4
1669 #define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
1670 #define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
1671 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
1672 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6
1673 u8 edpm_event_id /* byte2 */;
1674 __le16 physical_q0 /* physical_q0 */;
1675 __le16 word1 /* physical_q1 */;
1676 __le16 edpm_num_bds /* physical_q2 */;
1677 __le16 tx_bd_cons /* word3 */;
1678 __le16 tx_bd_prod /* word4 */;
1679 __le16 go_to_bd_cons /* word5 */;
1680 __le16 conn_dpi /* conn_dpi */;
1681 u8 byte3 /* byte3 */;
1682 u8 byte4 /* byte4 */;
1683 u8 byte5 /* byte5 */;
1684 u8 byte6 /* byte6 */;
1685 __le32 reg0 /* reg0 */;
1686 __le32 reg1 /* reg1 */;
1687 __le32 reg2 /* reg2 */;
1688 __le32 reg3 /* reg3 */;
1689 __le32 reg4 /* reg4 */;
1692 struct xstorm_eth_hw_conn_ag_ctx {
1693 u8 reserved0 /* cdu_validation */;
1694 u8 eth_state /* state */;
1696 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
1697 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1698 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
1699 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1
1700 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
1701 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2
1702 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
1703 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
1704 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
1705 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4
1706 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
1707 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5
1708 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1
1709 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6
1710 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1
1711 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7
1713 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1
1714 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0
1715 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1
1716 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1
1717 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
1718 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2
1719 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
1720 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3
1721 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK 0x1
1722 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT 4
1723 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK 0x1
1724 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT 5
1725 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
1726 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
1727 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
1728 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
1730 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
1731 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0
1732 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
1733 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2
1734 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
1735 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4
1736 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
1737 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6
1739 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3
1740 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0
1741 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3
1742 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2
1743 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3
1744 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4
1745 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3
1746 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6
1748 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3
1749 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0
1750 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3
1751 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2
1752 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3
1753 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4
1754 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3
1755 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6
1757 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3
1758 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
1759 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3
1760 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2
1761 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3
1762 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4
1763 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3
1764 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6
1766 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
1767 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
1768 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
1769 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
1770 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3
1771 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4
1772 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
1773 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
1775 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
1776 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
1777 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3
1778 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2
1779 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3
1780 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4
1781 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
1782 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6
1783 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
1784 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7
1786 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
1787 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0
1788 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
1789 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1
1790 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
1791 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2
1792 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
1793 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3
1794 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
1795 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4
1796 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
1797 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5
1798 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
1799 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6
1800 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
1801 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7
1803 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
1804 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0
1805 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
1806 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1
1807 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
1808 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2
1809 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
1810 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3
1811 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
1812 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4
1813 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
1814 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5
1815 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
1816 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
1817 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
1818 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
1820 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
1821 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
1822 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
1823 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
1824 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
1825 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
1826 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
1827 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3
1828 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
1829 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
1830 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
1831 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
1832 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
1833 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6
1834 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
1835 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7
1837 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
1838 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0
1839 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
1840 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1
1841 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
1842 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
1843 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
1844 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3
1845 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
1846 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4
1847 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
1848 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5
1849 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
1850 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
1851 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
1852 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7
1854 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
1855 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0
1856 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
1857 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1
1858 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
1859 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
1860 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
1861 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
1862 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
1863 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4
1864 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
1865 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5
1866 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
1867 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6
1868 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
1869 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7
1871 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
1872 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0
1873 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
1874 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1
1875 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
1876 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
1877 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
1878 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
1879 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
1880 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
1881 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
1882 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
1883 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
1884 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
1885 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
1886 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
1888 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
1889 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
1890 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
1891 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
1892 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
1893 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
1894 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
1895 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
1896 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
1897 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
1898 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
1899 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
1900 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
1901 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
1902 u8 edpm_event_id /* byte2 */;
1903 __le16 physical_q0 /* physical_q0 */;
1904 __le16 word1 /* physical_q1 */;
1905 __le16 edpm_num_bds /* physical_q2 */;
1906 __le16 tx_bd_cons /* word3 */;
1907 __le16 tx_bd_prod /* word4 */;
1908 __le16 go_to_bd_cons /* word5 */;
1909 __le16 conn_dpi /* conn_dpi */;
1912 #endif /* __ECORE_HSI_ETH__ */