1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
7 #ifndef __ECORE_HSI_INIT_TOOL__
8 #define __ECORE_HSI_INIT_TOOL__
9 /**************************************/
10 /* Init Tool HSI constants and macros */
11 /**************************************/
13 /* Width of GRC address in bits (addresses are specified in dwords) */
14 #define GRC_ADDR_BITS 23
15 #define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1)
17 /* indicates an init that should be applied to any phase ID */
18 #define ANY_PHASE_ID 0xffff
20 /* Max size in dwords of a zipped array */
21 #define MAX_ZIPPED_SIZE 8192
31 * Binary buffer header
33 struct bin_buffer_hdr {
34 /* buffer offset in bytes from the beginning of the binary file */
36 u32 length /* buffer length in bytes */;
41 * binary init buffer types
43 enum bin_init_buffer_type {
44 BIN_BUF_INIT_FW_VER_INFO /* fw_ver_info struct */,
45 BIN_BUF_INIT_CMD /* init commands */,
46 BIN_BUF_INIT_VAL /* init data */,
47 BIN_BUF_INIT_MODE_TREE /* init modes tree */,
48 BIN_BUF_INIT_IRO /* internal RAM offsets */,
49 MAX_BIN_INIT_BUFFER_TYPE
54 * init array header: raw
56 struct init_array_raw_hdr {
58 /* Init array type, from init_array_types enum */
59 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
60 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
61 /* init array params */
62 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF
63 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
67 * init array header: standard
69 struct init_array_standard_hdr {
71 /* Init array type, from init_array_types enum */
72 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
73 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
74 /* Init array size (in dwords) */
75 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
76 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
80 * init array header: zipped
82 struct init_array_zipped_hdr {
84 /* Init array type, from init_array_types enum */
85 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
86 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
87 /* Init array zipped size (in bytes) */
88 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
89 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
93 * init array header: pattern
95 struct init_array_pattern_hdr {
97 /* Init array type, from init_array_types enum */
98 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
99 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
100 /* pattern size in dword */
101 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
102 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
103 /* pattern repetitions */
104 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
105 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
109 * init array header union
111 union init_array_hdr {
112 struct init_array_raw_hdr raw /* raw init array header */;
113 /* standard init array header */
114 struct init_array_standard_hdr standard;
115 struct init_array_zipped_hdr zipped /* zipped init array header */;
116 struct init_array_pattern_hdr pattern /* pattern init array header */;
121 MODE_BB_A0_DEPRECATED,
132 MODE_PORTS_PER_ENG_1,
133 MODE_PORTS_PER_ENG_2,
134 MODE_PORTS_PER_ENG_4,
152 enum init_split_types {
165 enum init_array_types {
166 INIT_ARR_STANDARD /* standard init array */,
167 INIT_ARR_ZIPPED /* zipped init array */,
168 INIT_ARR_PATTERN /* a repeated pattern */,
175 * init operation: callback
177 struct init_callback_op {
179 /* Init operation, from init_op_types enum */
180 #define INIT_CALLBACK_OP_OP_MASK 0xF
181 #define INIT_CALLBACK_OP_OP_SHIFT 0
182 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
183 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4
184 u16 callback_id /* Callback ID */;
185 u16 block_id /* Blocks ID */;
190 * init operation: delay
192 struct init_delay_op {
194 /* Init operation, from init_op_types enum */
195 #define INIT_DELAY_OP_OP_MASK 0xF
196 #define INIT_DELAY_OP_OP_SHIFT 0
197 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
198 #define INIT_DELAY_OP_RESERVED_SHIFT 4
199 __le32 delay /* delay in us */;
204 * init operation: if_mode
206 struct init_if_mode_op {
208 /* Init operation, from init_op_types enum */
209 #define INIT_IF_MODE_OP_OP_MASK 0xF
210 #define INIT_IF_MODE_OP_OP_SHIFT 0
211 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
212 #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
213 /* Commands to skip if the modes dont match */
214 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
215 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
217 u16 modes_buf_offset /* offset (in bytes) in modes expression buffer */;
222 * init operation: if_phase
224 struct init_if_phase_op {
226 /* Init operation, from init_op_types enum */
227 #define INIT_IF_PHASE_OP_OP_MASK 0xF
228 #define INIT_IF_PHASE_OP_OP_SHIFT 0
229 /* Indicates if DMAE is enabled in this phase */
230 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1
231 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
232 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF
233 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5
234 /* Commands to skip if the phases dont match */
235 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
236 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
238 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF /* Init phase */
239 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0
240 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
241 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
242 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF /* Init phase ID */
243 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
248 * init mode operators
251 INIT_MODE_OP_NOT /* init mode not operator */,
252 INIT_MODE_OP_OR /* init mode or operator */,
253 INIT_MODE_OP_AND /* init mode and operator */,
259 * init operation: raw
263 /* Init operation, from init_op_types enum */
264 #define INIT_RAW_OP_OP_MASK 0xF
265 #define INIT_RAW_OP_OP_SHIFT 0
266 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF /* init param 1 */
267 #define INIT_RAW_OP_PARAM1_SHIFT 4
268 u32 param2 /* Init param 2 */;
274 struct init_op_array_params {
275 u16 size /* array size in dwords */;
276 u16 offset /* array start offset in dwords */;
280 * Write init operation arguments
282 union init_write_args {
283 /* value to write, used when init source is INIT_SRC_INLINE */
285 /* number of zeros to write, used when init source is INIT_SRC_ZEROS */
287 /* array offset to write, used when init source is INIT_SRC_ARRAY */
289 /* runtime array params to write, used when init source is INIT_SRC_RUNTIME */
290 struct init_op_array_params runtime;
294 * init operation: write
296 struct init_write_op {
298 /* init operation, from init_op_types enum */
299 #define INIT_WRITE_OP_OP_MASK 0xF
300 #define INIT_WRITE_OP_OP_SHIFT 0
301 /* init source type, taken from init_source_types enum */
302 #define INIT_WRITE_OP_SOURCE_MASK 0x7
303 #define INIT_WRITE_OP_SOURCE_SHIFT 4
304 #define INIT_WRITE_OP_RESERVED_MASK 0x1
305 #define INIT_WRITE_OP_RESERVED_SHIFT 7
306 /* indicates if the register is wide-bus */
307 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
308 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
309 /* internal (absolute) GRC address, in dwords */
310 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
311 #define INIT_WRITE_OP_ADDRESS_SHIFT 9
312 union init_write_args args /* Write init operation arguments */;
316 * init operation: read
318 struct init_read_op {
320 /* init operation, from init_op_types enum */
321 #define INIT_READ_OP_OP_MASK 0xF
322 #define INIT_READ_OP_OP_SHIFT 0
323 /* polling type, from init_poll_types enum */
324 #define INIT_READ_OP_POLL_TYPE_MASK 0xF
325 #define INIT_READ_OP_POLL_TYPE_SHIFT 4
326 #define INIT_READ_OP_RESERVED_MASK 0x1
327 #define INIT_READ_OP_RESERVED_SHIFT 8
328 /* internal (absolute) GRC address, in dwords */
329 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
330 #define INIT_READ_OP_ADDRESS_SHIFT 9
331 /* expected polling value, used only when polling is done */
336 * Init operations union
339 struct init_raw_op raw /* raw init operation */;
340 struct init_write_op write /* write init operation */;
341 struct init_read_op read /* read init operation */;
342 struct init_if_mode_op if_mode /* if_mode init operation */;
343 struct init_if_phase_op if_phase /* if_phase init operation */;
344 struct init_callback_op callback /* callback init operation */;
345 struct init_delay_op delay /* delay init operation */;
351 * Init command operation types
354 INIT_OP_READ /* GRC read init command */,
355 INIT_OP_WRITE /* GRC write init command */,
356 /* Skip init commands if the init modes expression doesn't match */
358 /* Skip init commands if the init phase doesn't match */
360 INIT_OP_DELAY /* delay init command */,
361 INIT_OP_CALLBACK /* callback init command */,
369 enum init_poll_types {
370 INIT_POLL_NONE /* No polling */,
371 INIT_POLL_EQ /* init value is included in the init command */,
372 INIT_POLL_OR /* init value is all zeros */,
373 INIT_POLL_AND /* init value is an array of values */,
383 enum init_source_types {
384 INIT_SRC_INLINE /* init value is included in the init command */,
385 INIT_SRC_ZEROS /* init value is all zeros */,
386 INIT_SRC_ARRAY /* init value is an array of values */,
387 INIT_SRC_RUNTIME /* init value is provided during runtime */,
388 MAX_INIT_SOURCE_TYPES
395 * Internal RAM Offsets macro data
398 u32 base /* RAM field offset */;
399 u16 m1 /* multiplier 1 */;
400 u16 m2 /* multiplier 2 */;
401 u16 m3 /* multiplier 3 */;
402 u16 size /* RAM field size */;
405 #endif /* __ECORE_HSI_INIT_TOOL__ */