1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
7 #ifndef __ECORE_HSI_INIT_TOOL__
8 #define __ECORE_HSI_INIT_TOOL__
9 /**************************************/
10 /* Init Tool HSI constants and macros */
11 /**************************************/
13 /* Width of GRC address in bits (addresses are specified in dwords) */
14 #define GRC_ADDR_BITS 23
15 #define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1)
17 /* indicates an init that should be applied to any phase ID */
18 #define ANY_PHASE_ID 0xffff
20 /* Max size in dwords of a zipped array */
21 #define MAX_ZIPPED_SIZE 8192
31 * Binary buffer header
33 struct bin_buffer_hdr {
34 /* buffer offset in bytes from the beginning of the binary file */
36 u32 length /* buffer length in bytes */;
41 * binary init buffer types
43 enum bin_init_buffer_type {
44 BIN_BUF_INIT_FW_VER_INFO /* fw_ver_info struct */,
45 BIN_BUF_INIT_CMD /* init commands */,
46 BIN_BUF_INIT_VAL /* init data */,
47 BIN_BUF_INIT_MODE_TREE /* init modes tree */,
48 BIN_BUF_INIT_IRO /* internal RAM offsets */,
49 BIN_BUF_INIT_OVERLAYS /* FW overlays (except overlay 0) */,
50 MAX_BIN_INIT_BUFFER_TYPE
55 * FW overlay buffer header
57 struct fw_overlay_buf_hdr {
59 #define FW_OVERLAY_BUF_HDR_STORM_ID_MASK 0xFF /* Storm ID */
60 #define FW_OVERLAY_BUF_HDR_STORM_ID_SHIFT 0
61 /* Size of Storm FW overlay buffer in dwords */
62 #define FW_OVERLAY_BUF_HDR_BUF_SIZE_MASK 0xFFFFFF
63 #define FW_OVERLAY_BUF_HDR_BUF_SIZE_SHIFT 8
68 * init array header: raw
70 struct init_array_raw_hdr {
72 /* Init array type, from init_array_types enum */
73 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
74 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
75 /* init array params */
76 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF
77 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
81 * init array header: standard
83 struct init_array_standard_hdr {
85 /* Init array type, from init_array_types enum */
86 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
87 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
88 /* Init array size (in dwords) */
89 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
90 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
94 * init array header: zipped
96 struct init_array_zipped_hdr {
98 /* Init array type, from init_array_types enum */
99 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
100 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
101 /* Init array zipped size (in bytes) */
102 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
103 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
107 * init array header: pattern
109 struct init_array_pattern_hdr {
111 /* Init array type, from init_array_types enum */
112 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
113 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
114 /* pattern size in dword */
115 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
116 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
117 /* pattern repetitions */
118 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
119 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
123 * init array header union
125 union init_array_hdr {
126 struct init_array_raw_hdr raw /* raw init array header */;
127 /* standard init array header */
128 struct init_array_standard_hdr standard;
129 struct init_array_zipped_hdr zipped /* zipped init array header */;
130 struct init_array_pattern_hdr pattern /* pattern init array header */;
134 enum dbg_bus_clients {
145 DBG_BUS_CLIENT_OTHER_ENGINE,
146 DBG_BUS_CLIENT_TIMESTAMP,
159 MODE_BB_A0_DEPRECATED,
170 MODE_PORTS_PER_ENG_1,
171 MODE_PORTS_PER_ENG_2,
172 MODE_PORTS_PER_ENG_4,
190 enum init_split_types {
203 enum init_array_types {
204 INIT_ARR_STANDARD /* standard init array */,
205 INIT_ARR_ZIPPED /* zipped init array */,
206 INIT_ARR_PATTERN /* a repeated pattern */,
213 * init operation: callback
215 struct init_callback_op {
217 /* Init operation, from init_op_types enum */
218 #define INIT_CALLBACK_OP_OP_MASK 0xF
219 #define INIT_CALLBACK_OP_OP_SHIFT 0
220 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
221 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4
222 u16 callback_id /* Callback ID */;
223 u16 block_id /* Blocks ID */;
228 * init operation: delay
230 struct init_delay_op {
232 /* Init operation, from init_op_types enum */
233 #define INIT_DELAY_OP_OP_MASK 0xF
234 #define INIT_DELAY_OP_OP_SHIFT 0
235 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
236 #define INIT_DELAY_OP_RESERVED_SHIFT 4
237 __le32 delay /* delay in us */;
242 * init operation: if_mode
244 struct init_if_mode_op {
246 /* Init operation, from init_op_types enum */
247 #define INIT_IF_MODE_OP_OP_MASK 0xF
248 #define INIT_IF_MODE_OP_OP_SHIFT 0
249 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
250 #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
251 /* Commands to skip if the modes dont match */
252 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
253 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
255 u16 modes_buf_offset /* offset (in bytes) in modes expression buffer */;
260 * init operation: if_phase
262 struct init_if_phase_op {
264 /* Init operation, from init_op_types enum */
265 #define INIT_IF_PHASE_OP_OP_MASK 0xF
266 #define INIT_IF_PHASE_OP_OP_SHIFT 0
267 /* Indicates if DMAE is enabled in this phase */
268 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1
269 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
270 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF
271 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5
272 /* Commands to skip if the phases dont match */
273 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
274 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
276 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF /* Init phase */
277 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0
278 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
279 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
280 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF /* Init phase ID */
281 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
286 * init mode operators
289 INIT_MODE_OP_NOT /* init mode not operator */,
290 INIT_MODE_OP_OR /* init mode or operator */,
291 INIT_MODE_OP_AND /* init mode and operator */,
297 * init operation: raw
301 /* Init operation, from init_op_types enum */
302 #define INIT_RAW_OP_OP_MASK 0xF
303 #define INIT_RAW_OP_OP_SHIFT 0
304 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF /* init param 1 */
305 #define INIT_RAW_OP_PARAM1_SHIFT 4
306 u32 param2 /* Init param 2 */;
312 struct init_op_array_params {
313 u16 size /* array size in dwords */;
314 u16 offset /* array start offset in dwords */;
318 * Write init operation arguments
320 union init_write_args {
321 /* value to write, used when init source is INIT_SRC_INLINE */
323 /* number of zeros to write, used when init source is INIT_SRC_ZEROS */
325 /* array offset to write, used when init source is INIT_SRC_ARRAY */
327 /* runtime array params to write, used when init source is INIT_SRC_RUNTIME */
328 struct init_op_array_params runtime;
332 * init operation: write
334 struct init_write_op {
336 /* init operation, from init_op_types enum */
337 #define INIT_WRITE_OP_OP_MASK 0xF
338 #define INIT_WRITE_OP_OP_SHIFT 0
339 /* init source type, taken from init_source_types enum */
340 #define INIT_WRITE_OP_SOURCE_MASK 0x7
341 #define INIT_WRITE_OP_SOURCE_SHIFT 4
342 #define INIT_WRITE_OP_RESERVED_MASK 0x1
343 #define INIT_WRITE_OP_RESERVED_SHIFT 7
344 /* indicates if the register is wide-bus */
345 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
346 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
347 /* internal (absolute) GRC address, in dwords */
348 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
349 #define INIT_WRITE_OP_ADDRESS_SHIFT 9
350 union init_write_args args /* Write init operation arguments */;
354 * init operation: read
356 struct init_read_op {
358 /* init operation, from init_op_types enum */
359 #define INIT_READ_OP_OP_MASK 0xF
360 #define INIT_READ_OP_OP_SHIFT 0
361 /* polling type, from init_poll_types enum */
362 #define INIT_READ_OP_POLL_TYPE_MASK 0xF
363 #define INIT_READ_OP_POLL_TYPE_SHIFT 4
364 #define INIT_READ_OP_RESERVED_MASK 0x1
365 #define INIT_READ_OP_RESERVED_SHIFT 8
366 /* internal (absolute) GRC address, in dwords */
367 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
368 #define INIT_READ_OP_ADDRESS_SHIFT 9
369 /* expected polling value, used only when polling is done */
374 * Init operations union
377 struct init_raw_op raw /* raw init operation */;
378 struct init_write_op write /* write init operation */;
379 struct init_read_op read /* read init operation */;
380 struct init_if_mode_op if_mode /* if_mode init operation */;
381 struct init_if_phase_op if_phase /* if_phase init operation */;
382 struct init_callback_op callback /* callback init operation */;
383 struct init_delay_op delay /* delay init operation */;
389 * Init command operation types
392 INIT_OP_READ /* GRC read init command */,
393 INIT_OP_WRITE /* GRC write init command */,
394 /* Skip init commands if the init modes expression doesn't match */
396 /* Skip init commands if the init phase doesn't match */
398 INIT_OP_DELAY /* delay init command */,
399 INIT_OP_CALLBACK /* callback init command */,
407 enum init_poll_types {
408 INIT_POLL_NONE /* No polling */,
409 INIT_POLL_EQ /* init value is included in the init command */,
410 INIT_POLL_OR /* init value is all zeros */,
411 INIT_POLL_AND /* init value is an array of values */,
421 enum init_source_types {
422 INIT_SRC_INLINE /* init value is included in the init command */,
423 INIT_SRC_ZEROS /* init value is all zeros */,
424 INIT_SRC_ARRAY /* init value is an array of values */,
425 INIT_SRC_RUNTIME /* init value is provided during runtime */,
426 MAX_INIT_SOURCE_TYPES
433 * Internal RAM Offsets macro data
436 u32 base /* RAM field offset */;
437 u16 m1 /* multiplier 1 */;
438 u16 m2 /* multiplier 2 */;
439 u16 m3 /* multiplier 3 */;
440 u16 size /* RAM field size */;
443 #endif /* __ECORE_HSI_INIT_TOOL__ */