2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #ifndef __ECORE_HSI_TOOLS__
10 #define __ECORE_HSI_TOOLS__
11 /**********************************/
12 /* Tools HSI constants and macros */
13 /**********************************/
15 /*********************************** Init ************************************/
17 /* Width of GRC address in bits (addresses are specified in dwords) */
18 #define GRC_ADDR_BITS 23
19 #define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1)
21 /* indicates an init that should be applied to any phase ID */
22 #define ANY_PHASE_ID 0xffff
24 /* init pattern size in bytes */
25 #define INIT_PATTERN_SIZE_BITS 4
26 #define MAX_INIT_PATTERN_SIZE (1 << INIT_PATTERN_SIZE_BITS)
28 /* Max size in dwords of a zipped array */
29 #define MAX_ZIPPED_SIZE 8192
31 /* Global PXP window */
32 #define NUM_OF_PXP_WIN 19
33 #define PXP_WIN_DWORD_SIZE_BITS 10
34 #define PXP_WIN_DWORD_SIZE (1 << PXP_WIN_DWORD_SIZE_BITS)
35 #define PXP_WIN_BYTE_SIZE_BITS (PXP_WIN_DWORD_SIZE_BITS + 2)
36 #define PXP_WIN_BYTE_SIZE (PXP_WIN_DWORD_SIZE * 4)
38 /********************************* GRC Dump **********************************/
40 /* width of GRC dump register sequence length in bits */
41 #define DUMP_SEQ_LEN_BITS 8
42 #define DUMP_SEQ_LEN_MAX_VAL ((1 << DUMP_SEQ_LEN_BITS) - 1)
44 /* width of GRC dump memory length in bits */
45 #define DUMP_MEM_LEN_BITS 18
46 #define DUMP_MEM_LEN_MAX_VAL ((1 << DUMP_MEM_LEN_BITS) - 1)
48 /* width of register type ID in bits */
49 #define REG_TYPE_ID_BITS 6
50 #define REG_TYPE_ID_MAX_VAL ((1 << REG_TYPE_ID_BITS) - 1)
52 /* width of block ID in bits */
53 #define BLOCK_ID_BITS 8
54 #define BLOCK_ID_MAX_VAL ((1 << BLOCK_ID_BITS) - 1)
56 /******************************** Idle Check *********************************/
58 /* max number of idle check predicate immediates */
59 #define MAX_IDLE_CHK_PRED_IMM 3
61 /* max number of idle check argument registers */
62 #define MAX_IDLE_CHK_READ_REGS 3
64 /* max number of idle check loops */
65 #define MAX_IDLE_CHK_LOOPS 0x10000
67 /* max idle check address increment */
68 #define MAX_IDLE_CHK_INCREMENT 0x10000
70 /* inicates an undefined idle check line index */
71 #define IDLE_CHK_UNDEFINED_LINE_IDX 0xffffff
73 /* max number of register values following the idle check header for LSI */
74 #define IDLE_CHK_MAX_LSI_DUMP_REGS 2
76 /* arguments for IDLE_CHK_MACRO_TYPE_QM_RD_WR */
77 #define IDLE_CHK_QM_RD_WR_PTR 0
78 #define IDLE_CHK_QM_RD_WR_BANK 1
80 /**************************************/
81 /* HSI Functions constants and macros */
82 /**************************************/
84 /* Number of VLAN priorities */
85 #define NUM_OF_VLAN_PRIORITIES 8
87 /* the MCP Trace meta data signautre is duplicated in the
88 * perl script that generats the NVRAM images
90 #define MCP_TRACE_META_IMAGE_SIGNATURE 0x669955aa
92 /* Maximal number of RAM lines occupied by FW Asserts data */
93 #define MAX_FW_ASSERTS_RAM_LINES 800
96 * Binary buffer header
98 struct bin_buffer_hdr {
100 /* buffer offset in bytes from the beginning of the binary file */;
101 __le32 length /* buffer length in bytes */;
105 * binary buffer types
107 enum bin_buffer_type {
108 BIN_BUF_FW_VER_INFO /* fw_ver_info struct */,
109 BIN_BUF_INIT_CMD /* init commands */,
110 BIN_BUF_INIT_VAL /* init data */,
111 BIN_BUF_INIT_MODE_TREE /* init modes tree */,
112 BIN_BUF_IRO /* internal RAM offsets array */,
120 CHIP_BB_A0 /* BB A0 chip ID */,
121 CHIP_BB_B0 /* BB B0 chip ID */,
122 CHIP_K2 /* AH chip ID */,
127 * memory dump descriptor
129 struct dbg_dump_mem_desc {
131 #define DBG_DUMP_MEM_DESC_ADDRESS_MASK 0xFFFFFF
132 #define DBG_DUMP_MEM_DESC_ADDRESS_SHIFT 0
133 #define DBG_DUMP_MEM_DESC_ASIC_CHIP_MASK_MASK 0xF
134 #define DBG_DUMP_MEM_DESC_ASIC_CHIP_MASK_SHIFT 24
135 #define DBG_DUMP_MEM_DESC_SIM_CHIP_MASK_MASK 0xF
136 #define DBG_DUMP_MEM_DESC_SIM_CHIP_MASK_SHIFT 28
138 #define DBG_DUMP_MEM_DESC_LENGTH_MASK 0x3FFFF
139 #define DBG_DUMP_MEM_DESC_LENGTH_SHIFT 0
140 #define DBG_DUMP_MEM_DESC_REG_TYPE_ID_MASK 0x3F
141 #define DBG_DUMP_MEM_DESC_REG_TYPE_ID_SHIFT 18
142 #define DBG_DUMP_MEM_DESC_BLOCK_ID_MASK 0xFF
143 #define DBG_DUMP_MEM_DESC_BLOCK_ID_SHIFT 24
147 * registers dump descriptor: chip
149 struct dbg_dump_regs_chip_desc {
151 #define DBG_DUMP_REGS_CHIP_DESC_IS_CHIP_MASK_MASK 0x1
152 #define DBG_DUMP_REGS_CHIP_DESC_IS_CHIP_MASK_SHIFT 0
153 #define DBG_DUMP_REGS_CHIP_DESC_ASIC_CHIP_MASK_MASK 0x7FFFFF
154 #define DBG_DUMP_REGS_CHIP_DESC_ASIC_CHIP_MASK_SHIFT 1
155 #define DBG_DUMP_REGS_CHIP_DESC_SIM_CHIP_MASK_MASK 0xFF
156 #define DBG_DUMP_REGS_CHIP_DESC_SIM_CHIP_MASK_SHIFT 24
160 * registers dump descriptor: raw
162 struct dbg_dump_regs_raw_desc {
164 #define DBG_DUMP_REGS_RAW_DESC_IS_CHIP_MASK_MASK 0x1
165 #define DBG_DUMP_REGS_RAW_DESC_IS_CHIP_MASK_SHIFT 0
166 #define DBG_DUMP_REGS_RAW_DESC_PARAM1_MASK 0x7FFFFF
167 #define DBG_DUMP_REGS_RAW_DESC_PARAM1_SHIFT 1
168 #define DBG_DUMP_REGS_RAW_DESC_PARAM2_MASK 0xFF
169 #define DBG_DUMP_REGS_RAW_DESC_PARAM2_SHIFT 24
173 * registers dump descriptor: sequence
175 struct dbg_dump_regs_seq_desc {
177 #define DBG_DUMP_REGS_SEQ_DESC_IS_CHIP_MASK_MASK 0x1
178 #define DBG_DUMP_REGS_SEQ_DESC_IS_CHIP_MASK_SHIFT 0
179 #define DBG_DUMP_REGS_SEQ_DESC_ADDRESS_MASK 0x7FFFFF
180 #define DBG_DUMP_REGS_SEQ_DESC_ADDRESS_SHIFT 1
181 #define DBG_DUMP_REGS_SEQ_DESC_LENGTH_MASK 0xFF
182 #define DBG_DUMP_REGS_SEQ_DESC_LENGTH_SHIFT 24
186 * registers dump descriptor
188 union dbg_dump_regs_desc {
189 struct dbg_dump_regs_raw_desc raw /* dumped registers raw descriptor */
191 struct dbg_dump_regs_seq_desc seq /* dumped registers seq descriptor */
193 struct dbg_dump_regs_chip_desc chip
194 /* dumped registers chip descriptor */;
198 * idle check macro types
200 enum idle_chk_macro_types {
201 IDLE_CHK_MACRO_TYPE_COMPARE /* parametric register comparison */,
202 IDLE_CHK_MACRO_TYPE_QM_RD_WR /* compare QM r/w pointers and banks */,
203 MAX_IDLE_CHK_MACRO_TYPES
207 * Idle Check result header
209 struct idle_chk_result_hdr {
210 __le16 rule_idx /* Idle check rule index in CSV file */;
211 __le16 loop_idx /* the loop index in which the failure occurred */;
212 __le16 num_fw_values;
214 #define IDLE_CHK_RESULT_HDR_NUM_LSI_VALUES_MASK 0xF
215 #define IDLE_CHK_RESULT_HDR_NUM_LSI_VALUES_SHIFT 0
216 #define IDLE_CHK_RESULT_HDR_LOOP_VALID_MASK 0x1
217 #define IDLE_CHK_RESULT_HDR_LOOP_VALID_SHIFT 4
218 #define IDLE_CHK_RESULT_HDR_SEVERITY_MASK 0x7
219 #define IDLE_CHK_RESULT_HDR_SEVERITY_SHIFT 5
220 #define IDLE_CHK_RESULT_HDR_MACRO_TYPE_MASK 0xF
221 #define IDLE_CHK_RESULT_HDR_MACRO_TYPE_SHIFT 8
222 #define IDLE_CHK_RESULT_HDR_MACRO_TYPE_ARG_MASK 0xF
223 #define IDLE_CHK_RESULT_HDR_MACRO_TYPE_ARG_SHIFT 12
229 struct idle_chk_rule {
231 #define IDLE_CHK_RULE_ASIC_CHIP_MASK_MASK 0xF
232 #define IDLE_CHK_RULE_ASIC_CHIP_MASK_SHIFT 0
233 #define IDLE_CHK_RULE_SIM_CHIP_MASK_MASK 0xF
234 #define IDLE_CHK_RULE_SIM_CHIP_MASK_SHIFT 4
235 #define IDLE_CHK_RULE_BLOCK_ID_MASK 0xFF
236 #define IDLE_CHK_RULE_BLOCK_ID_SHIFT 8
237 #define IDLE_CHK_RULE_MACRO_TYPE_MASK 0xF
238 #define IDLE_CHK_RULE_MACRO_TYPE_SHIFT 16
239 #define IDLE_CHK_RULE_SEVERITY_MASK 0x7
240 #define IDLE_CHK_RULE_SEVERITY_SHIFT 20
241 #define IDLE_CHK_RULE_RESERVED_MASK 0x1
242 #define IDLE_CHK_RULE_RESERVED_SHIFT 23
243 #define IDLE_CHK_RULE_PRED_ID_MASK 0xFF
244 #define IDLE_CHK_RULE_PRED_ID_SHIFT 24
247 /* address increment of first argument register on each iteration */
251 /* immediate values passed as arguments to the idle check rule */;
255 * idle check severity types
257 enum idle_chk_severity_types {
258 IDLE_CHK_SEVERITY_ERROR /* idle check failure should cause an error */,
259 IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC
261 IDLE_CHK_SEVERITY_WARNING
262 /* idle check failure should cause a warning */,
263 MAX_IDLE_CHK_SEVERITY_TYPES
267 * init array header: raw
269 struct init_array_raw_hdr {
271 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
272 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
273 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF
274 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
278 * init array header: standard
280 struct init_array_standard_hdr {
282 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
283 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
284 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
285 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
289 * init array header: zipped
291 struct init_array_zipped_hdr {
293 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
294 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
295 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
296 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
300 * init array header: pattern
302 struct init_array_pattern_hdr {
304 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
305 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
306 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
307 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
308 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
309 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
313 * init array header union
315 union init_array_hdr {
316 struct init_array_raw_hdr raw /* raw init array header */;
317 struct init_array_standard_hdr standard /* standard init array header */
319 struct init_array_zipped_hdr zipped /* zipped init array header */;
320 struct init_array_pattern_hdr pattern /* pattern init array header */;
326 enum init_array_types {
327 INIT_ARR_STANDARD /* standard init array */,
328 INIT_ARR_ZIPPED /* zipped init array */,
329 INIT_ARR_PATTERN /* a repeated pattern */,
334 * init operation: callback
336 struct init_callback_op {
338 #define INIT_CALLBACK_OP_OP_MASK 0xF
339 #define INIT_CALLBACK_OP_OP_SHIFT 0
340 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
341 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4
342 __le16 callback_id /* Callback ID */;
343 __le16 block_id /* Blocks ID */;
347 * init operation: delay
349 struct init_delay_op {
351 #define INIT_DELAY_OP_OP_MASK 0xF
352 #define INIT_DELAY_OP_OP_SHIFT 0
353 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
354 #define INIT_DELAY_OP_RESERVED_SHIFT 4
355 __le32 delay /* delay in us */;
359 * init operation: if_mode
361 struct init_if_mode_op {
363 #define INIT_IF_MODE_OP_OP_MASK 0xF
364 #define INIT_IF_MODE_OP_OP_SHIFT 0
365 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
366 #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
367 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
368 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
370 __le16 modes_buf_offset
371 /* offset (in bytes) in modes expression buffer */;
375 * init operation: if_phase
377 struct init_if_phase_op {
379 #define INIT_IF_PHASE_OP_OP_MASK 0xF
380 #define INIT_IF_PHASE_OP_OP_SHIFT 0
381 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1
382 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
383 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF
384 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5
385 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
386 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
388 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF
389 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0
390 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
391 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
392 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF
393 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
397 * init mode operators
400 INIT_MODE_OP_NOT /* init mode not operator */,
401 INIT_MODE_OP_OR /* init mode or operator */,
402 INIT_MODE_OP_AND /* init mode and operator */,
407 * init operation: raw
411 #define INIT_RAW_OP_OP_MASK 0xF
412 #define INIT_RAW_OP_OP_SHIFT 0
413 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF
414 #define INIT_RAW_OP_PARAM1_SHIFT 4
415 __le32 param2 /* Init param 2 */;
421 struct init_op_array_params {
422 __le16 size /* array size in dwords */;
423 __le16 offset /* array start offset in dwords */;
427 * Write init operation arguments
429 union init_write_args {
431 /* value to write, used when init source is INIT_SRC_INLINE */;
434 /* array offset to write, used when init source is INIT_SRC_ARRAY */
436 struct init_op_array_params runtime;
440 * init operation: write
442 struct init_write_op {
444 #define INIT_WRITE_OP_OP_MASK 0xF
445 #define INIT_WRITE_OP_OP_SHIFT 0
446 #define INIT_WRITE_OP_SOURCE_MASK 0x7
447 #define INIT_WRITE_OP_SOURCE_SHIFT 4
448 #define INIT_WRITE_OP_RESERVED_MASK 0x1
449 #define INIT_WRITE_OP_RESERVED_SHIFT 7
450 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
451 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
452 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
453 #define INIT_WRITE_OP_ADDRESS_SHIFT 9
454 union init_write_args args /* Write init operation arguments */;
458 * init operation: read
460 struct init_read_op {
462 #define INIT_READ_OP_OP_MASK 0xF
463 #define INIT_READ_OP_OP_SHIFT 0
464 #define INIT_READ_OP_POLL_TYPE_MASK 0xF
465 #define INIT_READ_OP_POLL_TYPE_SHIFT 4
466 #define INIT_READ_OP_RESERVED_MASK 0x1
467 #define INIT_READ_OP_RESERVED_SHIFT 8
468 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
469 #define INIT_READ_OP_ADDRESS_SHIFT 9
471 /* expected polling value, used only when polling is done */;
475 * Init operations union
478 struct init_raw_op raw /* raw init operation */;
479 struct init_write_op write /* write init operation */;
480 struct init_read_op read /* read init operation */;
481 struct init_if_mode_op if_mode /* if_mode init operation */;
482 struct init_if_phase_op if_phase /* if_phase init operation */;
483 struct init_callback_op callback /* callback init operation */;
484 struct init_delay_op delay /* delay init operation */;
488 * Init command operation types
491 INIT_OP_READ /* GRC read init command */,
492 INIT_OP_WRITE /* GRC write init command */,
494 /* Skip init commands if the init modes expression doesn't match */,
496 /* Skip init commands if the init phase doesn't match */,
497 INIT_OP_DELAY /* delay init command */,
498 INIT_OP_CALLBACK /* callback init command */,
505 enum init_poll_types {
506 INIT_POLL_NONE /* No polling */,
507 INIT_POLL_EQ /* init value is included in the init command */,
508 INIT_POLL_OR /* init value is all zeros */,
509 INIT_POLL_AND /* init value is an array of values */,
516 enum init_source_types {
517 INIT_SRC_INLINE /* init value is included in the init command */,
518 INIT_SRC_ZEROS /* init value is all zeros */,
519 INIT_SRC_ARRAY /* init value is an array of values */,
520 INIT_SRC_RUNTIME /* init value is provided during runtime */,
521 MAX_INIT_SOURCE_TYPES
525 * Internal RAM Offsets macro data
528 __le32 base /* RAM field offset */;
529 __le16 m1 /* multiplier 1 */;
530 __le16 m2 /* multiplier 2 */;
531 __le16 m3 /* multiplier 3 */;
532 __le16 size /* RAM field size */;
536 * register descriptor
540 #define REG_DESC_ADDRESS_MASK 0xFFFFFF
541 #define REG_DESC_ADDRESS_SHIFT 0
542 #define REG_DESC_SIZE_MASK 0xFF
543 #define REG_DESC_SIZE_SHIFT 24
547 * Debug Bus block data
549 struct dbg_bus_block_data {
550 u8 enabled /* Indicates if the block is enabled for recording (0/1) */;
551 u8 hw_id /* HW ID associated with the block */;
552 u8 line_num /* Debug line number to select */;
553 u8 right_shift /* Number of units to right the debug data (0-3) */;
554 u8 cycle_en /* 4-bit value: bit i set -> unit i is enabled. */;
555 u8 force_valid /* 4-bit value: bit i set -> unit i is forced valid. */;
557 /* 4-bit value: bit i set -> unit i frame bit is forced. */;
564 enum dbg_bus_clients {
575 DBG_BUS_CLIENT_OTHER_ENGINE,
576 DBG_BUS_CLIENT_TIMESTAMP,
588 * Debug Bus constraint operation types
590 enum dbg_bus_constraint_ops {
591 DBG_BUS_CONSTRAINT_OP_EQ /* equal */,
592 DBG_BUS_CONSTRAINT_OP_NE /* not equal */,
593 DBG_BUS_CONSTRAINT_OP_LT /* less than */,
594 DBG_BUS_CONSTRAINT_OP_LTC /* less than (cyclic) */,
595 DBG_BUS_CONSTRAINT_OP_LE /* less than or equal */,
596 DBG_BUS_CONSTRAINT_OP_LEC /* less than or equal (cyclic) */,
597 DBG_BUS_CONSTRAINT_OP_GT /* greater than */,
598 DBG_BUS_CONSTRAINT_OP_GTC /* greater than (cyclic) */,
599 DBG_BUS_CONSTRAINT_OP_GE /* greater than or equal */,
600 DBG_BUS_CONSTRAINT_OP_GEC /* greater than or equal (cyclic) */,
601 MAX_DBG_BUS_CONSTRAINT_OPS
605 * Debug Bus memory address
607 struct dbg_bus_mem_addr {
613 * Debug Bus PCI buffer data
615 struct dbg_bus_pci_buf_data {
616 struct dbg_bus_mem_addr phys_addr /* PCI buffer physical address */;
617 struct dbg_bus_mem_addr virt_addr /* PCI buffer virtual address */;
618 __le32 size /* PCI buffer size in bytes */;
622 * Debug Bus Storm EID range filter params
624 struct dbg_bus_storm_eid_range_params {
625 u8 min /* Minimal event ID to filter on */;
626 u8 max /* Maximal event ID to filter on */;
630 * Debug Bus Storm EID mask filter params
632 struct dbg_bus_storm_eid_mask_params {
633 u8 val /* Event ID value */;
634 u8 mask /* Event ID mask. 1s in the mask = dont care bits. */;
638 * Debug Bus Storm EID filter params
640 union dbg_bus_storm_eid_params {
641 struct dbg_bus_storm_eid_range_params range
642 /* EID range filter params */;
643 struct dbg_bus_storm_eid_mask_params mask /* EID mask filter params */;
647 * Debug Bus Storm data
649 struct dbg_bus_storm_data {
652 /* Fast debug Storm mode, valid only if fast_enabled is set */;
655 /* Slow debug Storm mode, valid only if slow_enabled is set */;
656 u8 hw_id /* HW ID associated with the Storm */;
657 u8 eid_filter_en /* Indicates if EID filtering is performed (0/1) */;
658 u8 eid_range_not_mask;
659 u8 cid_filter_en /* Indicates if CID filtering is performed (0/1) */;
660 union dbg_bus_storm_eid_params eid_filter_params;
662 __le32 cid /* CID to filter on. Valid only if cid_filter_en is set. */;
668 struct dbg_bus_data {
669 __le32 app_version /* The tools version number of the application */;
670 u8 state /* The current debug bus state */;
671 u8 hw_dwords /* HW dwords per cycle */;
672 u8 next_hw_id /* Next HW ID to be associated with an input */;
673 u8 num_enabled_blocks /* Number of blocks enabled for recording */;
674 u8 num_enabled_storms /* Number of Storms enabled for recording */;
675 u8 target /* Output target */;
676 u8 next_trigger_state /* ID of next trigger state to be added */;
677 u8 next_constraint_id
678 /* ID of next filter/trigger constraint to be added */;
679 u8 one_shot_en /* Indicates if one-shot mode is enabled (0/1) */;
680 u8 grc_input_en /* Indicates if GRC recording is enabled (0/1) */;
681 u8 timestamp_input_en
682 /* Indicates if timestamp recording is enabled (0/1) */;
683 u8 filter_en /* Indicates if the recording filter is enabled (0/1) */;
684 u8 trigger_en /* Indicates if the recording trigger is enabled (0/1) */
687 u8 filter_pre_trigger;
688 u8 filter_post_trigger;
690 u8 rcv_from_other_engine;
691 struct dbg_bus_pci_buf_data pci_buf;
693 struct dbg_bus_block_data blocks[80] /* Debug Bus data for each block */
695 struct dbg_bus_storm_data storms[6] /* Debug Bus data for each block */
700 * Debug bus filter types
702 enum dbg_bus_filter_types {
703 DBG_BUS_FILTER_TYPE_OFF /* filter always off */,
704 DBG_BUS_FILTER_TYPE_PRE /* filter before trigger only */,
705 DBG_BUS_FILTER_TYPE_POST /* filter after trigger only */,
706 DBG_BUS_FILTER_TYPE_ON /* filter always on */,
707 MAX_DBG_BUS_FILTER_TYPES
711 * Debug bus frame modes
713 enum dbg_bus_frame_modes {
714 DBG_BUS_FRAME_MODE_0HW_4ST = 0 /* 0 HW dwords, 4 Storm dwords */,
715 DBG_BUS_FRAME_MODE_4HW_0ST = 3 /* 4 HW dwords, 0 Storm dwords */,
716 DBG_BUS_FRAME_MODE_8HW_0ST = 4 /* 8 HW dwords, 0 Storm dwords */,
717 MAX_DBG_BUS_FRAME_MODES
721 * Debug bus input types
723 enum dbg_bus_input_types {
724 DBG_BUS_INPUT_TYPE_STORM,
725 DBG_BUS_INPUT_TYPE_BLOCK,
726 MAX_DBG_BUS_INPUT_TYPES
730 * Debug bus other engine mode
732 enum dbg_bus_other_engine_modes {
733 DBG_BUS_OTHER_ENGINE_MODE_NONE,
734 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX,
735 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX,
736 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX,
737 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX,
738 MAX_DBG_BUS_OTHER_ENGINE_MODES
742 * Debug bus post-trigger recording types
744 enum dbg_bus_post_trigger_types {
745 DBG_BUS_POST_TRIGGER_RECORD /* start recording after trigger */,
746 DBG_BUS_POST_TRIGGER_DROP /* drop data after trigger */,
747 MAX_DBG_BUS_POST_TRIGGER_TYPES
751 * Debug bus pre-trigger recording types
753 enum dbg_bus_pre_trigger_types {
754 DBG_BUS_PRE_TRIGGER_START_FROM_ZERO /* start recording from time 0 */,
755 DBG_BUS_PRE_TRIGGER_NUM_CHUNKS
756 /* start recording some chunks before trigger */,
757 DBG_BUS_PRE_TRIGGER_DROP /* drop data before trigger */,
758 MAX_DBG_BUS_PRE_TRIGGER_TYPES
762 * Debug bus SEMI frame modes
764 enum dbg_bus_semi_frame_modes {
765 DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST =
766 0 /* 0 slow dwords, 4 fast dwords */,
767 DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST =
768 3 /* 4 slow dwords, 0 fast dwords */,
769 MAX_DBG_BUS_SEMI_FRAME_MODES
775 enum dbg_bus_states {
776 DBG_BUS_STATE_BEFORE_RECORD /* before debug bus the recording starts */
778 DBG_BUS_STATE_DURING_RECORD /* during debug bus recording */,
779 DBG_BUS_STATE_AFTER_RECORD /* after debug bus recording */,
784 * Debug Bus Storm modes
786 enum dbg_bus_storm_modes {
787 DBG_BUS_STORM_MODE_PRINTF /* store data (fast debug) */,
788 DBG_BUS_STORM_MODE_PRAM_ADDR /* pram address (fast debug) */,
789 DBG_BUS_STORM_MODE_DRA_RW /* DRA read/write data (fast debug) */,
790 DBG_BUS_STORM_MODE_DRA_W /* DRA write data (fast debug) */,
791 DBG_BUS_STORM_MODE_LD_ST_ADDR /* load/store address (fast debug) */,
792 DBG_BUS_STORM_MODE_DRA_FSM /* DRA state machines (fast debug) */,
793 DBG_BUS_STORM_MODE_RH /* recording handlers (fast debug) */,
794 DBG_BUS_STORM_MODE_FOC /* FOC: FIN + DRA Rd (slow debug) */,
795 DBG_BUS_STORM_MODE_EXT_STORE /* FOC: External Store (slow) */,
796 MAX_DBG_BUS_STORM_MODES
800 * Debug bus target IDs
802 enum dbg_bus_targets {
803 DBG_BUS_TARGET_ID_INT_BUF
804 /* records debug bus to DBG block internal buffer */,
805 DBG_BUS_TARGET_ID_NIG /* records debug bus to the NW */,
806 DBG_BUS_TARGET_ID_PCI /* records debug bus to a PCI buffer */,
813 struct dbg_grc_data {
814 u8 is_updated /* Indicates if the GRC Dump data is updated (0/1) */;
815 u8 chip_id /* Chip ID */;
816 u8 chip_mask /* Chip mask */;
818 __le32 max_dump_dwords /* Max GRC Dump size in dwords */;
819 __le32 param_val[40];
820 u8 param_set_by_user[40];
826 enum dbg_grc_params {
827 DBG_GRC_PARAM_DUMP_TSTORM /* dump Tstorm memories (0/1) */,
828 DBG_GRC_PARAM_DUMP_MSTORM /* dump Mstorm memories (0/1) */,
829 DBG_GRC_PARAM_DUMP_USTORM /* dump Ustorm memories (0/1) */,
830 DBG_GRC_PARAM_DUMP_XSTORM /* dump Xstorm memories (0/1) */,
831 DBG_GRC_PARAM_DUMP_YSTORM /* dump Ystorm memories (0/1) */,
832 DBG_GRC_PARAM_DUMP_PSTORM /* dump Pstorm memories (0/1) */,
833 DBG_GRC_PARAM_DUMP_REGS /* dump non-memory registers (0/1) */,
834 DBG_GRC_PARAM_DUMP_RAM /* dump Storm internal RAMs (0/1) */,
835 DBG_GRC_PARAM_DUMP_PBUF /* dump Storm passive buffer (0/1) */,
836 DBG_GRC_PARAM_DUMP_IOR /* dump Storm IORs (0/1) */,
837 DBG_GRC_PARAM_DUMP_VFC /* dump VFC memories (0/1) */,
838 DBG_GRC_PARAM_DUMP_CM_CTX /* dump CM contexts (0/1) */,
839 DBG_GRC_PARAM_DUMP_PXP /* dump PXP memories (0/1) */,
840 DBG_GRC_PARAM_DUMP_RSS /* dump RSS memories (0/1) */,
841 DBG_GRC_PARAM_DUMP_CAU /* dump CAU memories (0/1) */,
842 DBG_GRC_PARAM_DUMP_QM /* dump QM memories (0/1) */,
843 DBG_GRC_PARAM_DUMP_MCP /* dump MCP memories (0/1) */,
844 DBG_GRC_PARAM_RESERVED /* reserved */,
845 DBG_GRC_PARAM_DUMP_CFC /* dump CFC memories (0/1) */,
846 DBG_GRC_PARAM_DUMP_IGU /* dump IGU memories (0/1) */,
847 DBG_GRC_PARAM_DUMP_BRB /* dump BRB memories (0/1) */,
848 DBG_GRC_PARAM_DUMP_BTB /* dump BTB memories (0/1) */,
849 DBG_GRC_PARAM_DUMP_BMB /* dump BMB memories (0/1) */,
850 DBG_GRC_PARAM_DUMP_NIG /* dump NIG memories (0/1) */,
851 DBG_GRC_PARAM_DUMP_MULD /* dump MULD memories (0/1) */,
852 DBG_GRC_PARAM_DUMP_PRS /* dump PRS memories (0/1) */,
853 DBG_GRC_PARAM_DUMP_DMAE /* dump PRS memories (0/1) */,
854 DBG_GRC_PARAM_DUMP_TM /* dump TM (timers) memories (0/1) */,
855 DBG_GRC_PARAM_DUMP_SDM /* dump SDM memories (0/1) */,
856 DBG_GRC_PARAM_DUMP_STATIC /* dump static debug data (0/1) */,
857 DBG_GRC_PARAM_UNSTALL /* un-stall Storms after dump (0/1) */,
858 DBG_GRC_PARAM_NUM_LCIDS /* number of LCIDs (0..320) */,
859 DBG_GRC_PARAM_NUM_LTIDS /* number of LTIDs (0..320) */,
860 DBG_GRC_PARAM_EXCLUDE_ALL
861 /* preset: exclude all memories from dump (1 only) */,
863 /* preset: include memories for crash dump (1 only) */,
864 DBG_GRC_PARAM_PARITY_SAFE
865 /* perform dump only if MFW is responding (0/1) */,
866 DBG_GRC_PARAM_DUMP_CM /* dump CM memories (0/1) */,
871 * Debug reset registers
873 enum dbg_reset_regs {
874 DBG_RESET_REG_MISCS_PL_UA,
875 DBG_RESET_REG_MISCS_PL_HV,
876 DBG_RESET_REG_MISC_PL_UA,
877 DBG_RESET_REG_MISC_PL_HV,
878 DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
879 DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
880 DBG_RESET_REG_MISC_PL_PDA_VAUX,
885 * @DPDK Debug status codes
889 DBG_STATUS_APP_VERSION_NOT_SET,
890 DBG_STATUS_UNSUPPORTED_APP_VERSION,
891 DBG_STATUS_DBG_BLOCK_NOT_RESET,
892 DBG_STATUS_INVALID_ARGS,
893 DBG_STATUS_OUTPUT_ALREADY_SET,
894 DBG_STATUS_INVALID_PCI_BUF_SIZE,
895 DBG_STATUS_PCI_BUF_ALLOC_FAILED,
896 DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
897 DBG_STATUS_TOO_MANY_INPUTS,
898 DBG_STATUS_INPUT_OVERLAP,
899 DBG_STATUS_HW_ONLY_RECORDING,
900 DBG_STATUS_STORM_ALREADY_ENABLED,
901 DBG_STATUS_STORM_NOT_ENABLED,
902 DBG_STATUS_BLOCK_ALREADY_ENABLED,
903 DBG_STATUS_BLOCK_NOT_ENABLED,
904 DBG_STATUS_NO_INPUT_ENABLED,
905 DBG_STATUS_NO_FILTER_TRIGGER_64B,
906 DBG_STATUS_FILTER_ALREADY_ENABLED,
907 DBG_STATUS_TRIGGER_ALREADY_ENABLED,
908 DBG_STATUS_TRIGGER_NOT_ENABLED,
909 DBG_STATUS_CANT_ADD_CONSTRAINT,
910 DBG_STATUS_TOO_MANY_TRIGGER_STATES,
911 DBG_STATUS_TOO_MANY_CONSTRAINTS,
912 DBG_STATUS_RECORDING_NOT_STARTED,
913 DBG_STATUS_NO_DATA_TRIGGERED,
914 DBG_STATUS_NO_DATA_RECORDED,
915 DBG_STATUS_DUMP_BUF_TOO_SMALL,
916 DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,
917 DBG_STATUS_UNKNOWN_CHIP,
918 DBG_STATUS_VIRT_MEM_ALLOC_FAILED,
919 DBG_STATUS_BLOCK_IN_RESET,
920 DBG_STATUS_INVALID_TRACE_SIGNATURE,
921 DBG_STATUS_INVALID_NVRAM_BUNDLE,
922 DBG_STATUS_NVRAM_GET_IMAGE_FAILED,
923 DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,
924 DBG_STATUS_NVRAM_READ_FAILED,
925 DBG_STATUS_IDLE_CHK_PARSE_FAILED,
926 DBG_STATUS_MCP_TRACE_BAD_DATA,
927 DBG_STATUS_MCP_TRACE_NO_META,
928 DBG_STATUS_MCP_COULD_NOT_HALT,
929 DBG_STATUS_MCP_COULD_NOT_RESUME,
930 DBG_STATUS_DMAE_FAILED,
931 DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
932 DBG_STATUS_IGU_FIFO_BAD_DATA,
933 DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
934 DBG_STATUS_FW_ASSERTS_PARSE_FAILED,
935 DBG_STATUS_REG_FIFO_BAD_DATA,
936 DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
956 struct idle_chk_data {
957 __le32 buf_size /* Idle check buffer size in dwords */;
959 /* Indicates if the idle check buffer size was set (0/1) */;
967 struct mcp_trace_data {
968 __le32 buf_size /* MCP Trace buffer size in dwords */;
970 /* Indicates if the MCP Trace buffer size was set (0/1) */;
976 * Debug Tools data (per HW function)
978 struct dbg_tools_data {
979 struct dbg_grc_data grc /* GRC Dump data */;
980 struct dbg_bus_data bus /* Debug Bus data */;
981 struct idle_chk_data idle_chk /* Idle Check data */;
982 struct mcp_trace_data mcp_trace /* MCP Trace data */;
983 u8 block_in_reset[80] /* Indicates if a block is in reset state (0/1) */
985 u8 chip_id /* Chip ID (from enum chip_ids) */;
987 /* Chip mask = bit index chip_id is set, the rest are cleared */;
988 u8 initialized /* Indicates if the data was initialized */;
989 u8 reset_state_updated
990 /* Indicates if blocks reset state is updated (0/1) */;
994 * BRB RAM init requirements
996 struct init_brb_ram_req {
997 __le32 guranteed_per_tc /* guaranteed size per TC, in bytes */;
998 __le32 headroom_per_tc /* headroom size per TC, in bytes */;
999 __le32 min_pkt_size /* min packet size, in bytes */;
1000 __le32 max_ports_per_engine /* min packet size, in bytes */;
1001 u8 num_active_tcs[MAX_NUM_PORTS] /* number of active TCs per port */;
1005 * ETS per-TC init requirements
1007 struct init_ets_tc_req {
1010 __le16 weight /* An arbitration weight. Valid only if use_wfq is set. */
1015 * ETS init requirements
1017 struct init_ets_req {
1018 __le32 mtu /* Max packet size (in bytes) */;
1019 struct init_ets_tc_req tc_req[NUM_OF_TCS]
1020 /* ETS initialization requirements per TC. */;
1024 * NIG LB RL init requirements
1026 struct init_nig_lb_rl_req {
1029 __le32 mtu /* Max packet size (in bytes) */;
1030 __le16 tc_rate[NUM_OF_PHYS_TCS];
1034 * NIG TC mapping for each priority
1036 struct init_nig_pri_tc_map_entry {
1037 u8 tc_id /* the mapped TC ID */;
1038 u8 valid /* indicates if the mapping entry is valid */;
1042 * NIG priority to TC map init requirements
1044 struct init_nig_pri_tc_map_req {
1045 struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
1049 * QM per-port init parameters
1051 struct init_qm_port_params {
1052 u8 active /* Indicates if this port is active */;
1053 u8 num_active_phys_tcs /* number of physical TCs used by this port */;
1054 __le16 num_pbf_cmd_lines
1055 /* number of PBF command lines that can be used by this port */;
1056 __le16 num_btb_blocks
1057 /* number of BTB blocks that can be used by this port */;
1062 * QM per-PQ init parameters
1064 struct init_qm_pq_params {
1065 u8 vport_id /* VPORT ID */;
1066 u8 tc_id /* TC ID */;
1067 u8 wrr_group /* WRR group */;
1072 * QM per-vport init parameters
1074 struct init_qm_vport_params {
1077 __le16 first_tx_pq_id[NUM_OF_TCS]
1078 /* the first Tx PQ ID associated with this VPORT for each TC. */;
1081 #endif /* __ECORE_HSI_TOOLS__ */