2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
10 #include "ecore_hsi_common.h"
11 #include "ecore_status.h"
15 #include "ecore_utils.h"
18 #define ECORE_EMUL_FACTOR 2000
19 #define ECORE_FPGA_FACTOR 200
22 #define ECORE_BAR_ACQUIRE_TIMEOUT 1000
25 #define ECORE_BAR_INVALID_OFFSET -1
28 osal_list_entry_t list_entry;
30 struct pxp_ptt_entry pxp;
33 struct ecore_ptt_pool {
34 osal_list_t free_list;
36 struct ecore_ptt ptts[PXP_EXTERNAL_BAR_PF_WINDOW_NUM];
39 enum _ecore_status_t ecore_ptt_pool_alloc(struct ecore_hwfn *p_hwfn)
41 struct ecore_ptt_pool *p_pool;
44 p_pool = OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL,
45 sizeof(struct ecore_ptt_pool));
49 OSAL_LIST_INIT(&p_pool->free_list);
50 for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) {
51 p_pool->ptts[i].idx = i;
52 p_pool->ptts[i].pxp.offset = ECORE_BAR_INVALID_OFFSET;
53 p_pool->ptts[i].pxp.pretend.control = 0;
55 /* There are special PTT entries that are taken only by design.
56 * The rest are added ot the list for general usage.
58 if (i >= RESERVED_PTT_MAX)
59 OSAL_LIST_PUSH_HEAD(&p_pool->ptts[i].list_entry,
63 p_hwfn->p_ptt_pool = p_pool;
64 OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_pool->lock);
65 OSAL_SPIN_LOCK_INIT(&p_pool->lock);
70 void ecore_ptt_invalidate(struct ecore_hwfn *p_hwfn)
72 struct ecore_ptt *p_ptt;
75 for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) {
76 p_ptt = &p_hwfn->p_ptt_pool->ptts[i];
77 p_ptt->pxp.offset = ECORE_BAR_INVALID_OFFSET;
81 void ecore_ptt_pool_free(struct ecore_hwfn *p_hwfn)
83 if (p_hwfn->p_ptt_pool)
84 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->p_ptt_pool->lock);
85 OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_ptt_pool);
86 p_hwfn->p_ptt_pool = OSAL_NULL;
89 struct ecore_ptt *ecore_ptt_acquire(struct ecore_hwfn *p_hwfn)
91 struct ecore_ptt *p_ptt;
94 /* Take the free PTT from the list */
95 for (i = 0; i < ECORE_BAR_ACQUIRE_TIMEOUT; i++) {
96 OSAL_SPIN_LOCK(&p_hwfn->p_ptt_pool->lock);
97 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->p_ptt_pool->free_list))
99 OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);
103 /* We should not time-out, but it can happen... --> Lock isn't held */
104 if (i == ECORE_BAR_ACQUIRE_TIMEOUT) {
105 DP_NOTICE(p_hwfn, true, "Failed to allocate PTT\n");
109 p_ptt = OSAL_LIST_FIRST_ENTRY(&p_hwfn->p_ptt_pool->free_list,
110 struct ecore_ptt, list_entry);
111 OSAL_LIST_REMOVE_ENTRY(&p_ptt->list_entry,
112 &p_hwfn->p_ptt_pool->free_list);
113 OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);
115 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "allocated ptt %d\n", p_ptt->idx);
120 void ecore_ptt_release(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
122 /* This PTT should not be set to pretend if it is being released */
124 OSAL_SPIN_LOCK(&p_hwfn->p_ptt_pool->lock);
125 OSAL_LIST_PUSH_HEAD(&p_ptt->list_entry, &p_hwfn->p_ptt_pool->free_list);
126 OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);
129 u32 ecore_ptt_get_hw_addr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
131 /* The HW is using DWORDS and we need to translate it to Bytes */
132 return p_ptt->pxp.offset << 2;
135 static u32 ecore_ptt_config_addr(struct ecore_ptt *p_ptt)
137 return PXP_PF_WINDOW_ADMIN_PER_PF_START +
138 p_ptt->idx * sizeof(struct pxp_ptt_entry);
141 u32 ecore_ptt_get_bar_addr(struct ecore_ptt *p_ptt)
143 return PXP_EXTERNAL_BAR_PF_WINDOW_START +
144 p_ptt->idx * PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE;
147 void ecore_ptt_set_win(struct ecore_hwfn *p_hwfn,
148 struct ecore_ptt *p_ptt, u32 new_hw_addr)
152 prev_hw_addr = ecore_ptt_get_hw_addr(p_hwfn, p_ptt);
154 if (new_hw_addr == prev_hw_addr)
157 /* Update PTT entery in admin window */
158 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
159 "Updating PTT entry %d to offset 0x%x\n",
160 p_ptt->idx, new_hw_addr);
162 /* The HW is using DWORDS and the address is in Bytes */
163 p_ptt->pxp.offset = new_hw_addr >> 2;
166 ecore_ptt_config_addr(p_ptt) +
167 OFFSETOF(struct pxp_ptt_entry, offset), p_ptt->pxp.offset);
170 static u32 ecore_set_ptt(struct ecore_hwfn *p_hwfn,
171 struct ecore_ptt *p_ptt, u32 hw_addr)
173 u32 win_hw_addr = ecore_ptt_get_hw_addr(p_hwfn, p_ptt);
176 offset = hw_addr - win_hw_addr;
178 /* Verify the address is within the window */
179 if (hw_addr < win_hw_addr ||
180 offset >= PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) {
181 ecore_ptt_set_win(p_hwfn, p_ptt, hw_addr);
185 return ecore_ptt_get_bar_addr(p_ptt) + offset;
188 struct ecore_ptt *ecore_get_reserved_ptt(struct ecore_hwfn *p_hwfn,
189 enum reserved_ptts ptt_idx)
191 if (ptt_idx >= RESERVED_PTT_MAX) {
192 DP_NOTICE(p_hwfn, true,
193 "Requested PTT %d is out of range\n", ptt_idx);
197 return &p_hwfn->p_ptt_pool->ptts[ptt_idx];
200 void ecore_wr(struct ecore_hwfn *p_hwfn,
201 struct ecore_ptt *p_ptt, u32 hw_addr, u32 val)
203 u32 bar_addr = ecore_set_ptt(p_hwfn, p_ptt, hw_addr);
205 REG_WR(p_hwfn, bar_addr, val);
206 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
207 "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n",
208 bar_addr, hw_addr, val);
211 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
216 u32 ecore_rd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 hw_addr)
218 u32 bar_addr = ecore_set_ptt(p_hwfn, p_ptt, hw_addr);
219 u32 val = REG_RD(p_hwfn, bar_addr);
221 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
222 "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n",
223 bar_addr, hw_addr, val);
226 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
233 static void ecore_memcpy_hw(struct ecore_hwfn *p_hwfn,
234 struct ecore_ptt *p_ptt,
236 u32 hw_addr, osal_size_t n, bool to_device)
238 u32 dw_count, *host_addr, hw_offset;
239 osal_size_t quota, done = 0;
240 u32 OSAL_IOMEM *reg_addr;
243 quota = OSAL_MIN_T(osal_size_t, n - done,
244 PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE);
246 ecore_ptt_set_win(p_hwfn, p_ptt, hw_addr + done);
247 hw_offset = ecore_ptt_get_bar_addr(p_ptt);
249 dw_count = quota / 4;
250 host_addr = (u32 *)((u8 *)addr + done);
251 reg_addr = (u32 OSAL_IOMEM *)OSAL_REG_ADDR(p_hwfn, hw_offset);
255 DIRECT_REG_WR(p_hwfn, reg_addr++, *host_addr++);
258 *host_addr++ = DIRECT_REG_RD(p_hwfn,
265 void ecore_memcpy_from(struct ecore_hwfn *p_hwfn,
266 struct ecore_ptt *p_ptt,
267 void *dest, u32 hw_addr, osal_size_t n)
269 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
270 "hw_addr 0x%x, dest %p hw_addr 0x%x, size %lu\n",
271 hw_addr, dest, hw_addr, (unsigned long)n);
273 ecore_memcpy_hw(p_hwfn, p_ptt, dest, hw_addr, n, false);
276 void ecore_memcpy_to(struct ecore_hwfn *p_hwfn,
277 struct ecore_ptt *p_ptt,
278 u32 hw_addr, void *src, osal_size_t n)
280 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
281 "hw_addr 0x%x, hw_addr 0x%x, src %p size %lu\n",
282 hw_addr, hw_addr, src, (unsigned long)n);
284 ecore_memcpy_hw(p_hwfn, p_ptt, src, hw_addr, n, true);
287 void ecore_fid_pretend(struct ecore_hwfn *p_hwfn,
288 struct ecore_ptt *p_ptt, u16 fid)
293 SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1);
294 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1);
296 /* Every pretend undos prev pretends, including previous port pretend */
297 SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0);
298 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0);
299 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
300 p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
302 if (!GET_FIELD(fid, PXP_CONCRETE_FID_VFVALID))
303 fid = GET_FIELD(fid, PXP_CONCRETE_FID_PFID);
305 p_ptt->pxp.pretend.fid.concrete_fid.fid = OSAL_CPU_TO_LE16(fid);
307 p_pretend = &p_ptt->pxp.pretend;
309 ecore_ptt_config_addr(p_ptt) +
310 OFFSETOF(struct pxp_ptt_entry, pretend), *(u32 *)p_pretend);
313 void ecore_port_pretend(struct ecore_hwfn *p_hwfn,
314 struct ecore_ptt *p_ptt, u8 port_id)
319 SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id);
320 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1);
321 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
322 p_ptt->pxp.pretend.control = control;
324 p_pretend = &p_ptt->pxp.pretend;
326 ecore_ptt_config_addr(p_ptt) +
327 OFFSETOF(struct pxp_ptt_entry, pretend), *(u32 *)p_pretend);
330 void ecore_port_unpretend(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
335 SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0);
336 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0);
337 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
338 p_ptt->pxp.pretend.control = control;
340 p_pretend = &p_ptt->pxp.pretend;
342 ecore_ptt_config_addr(p_ptt) +
343 OFFSETOF(struct pxp_ptt_entry, pretend), *(u32 *)p_pretend);
346 u32 ecore_vfid_to_concrete(struct ecore_hwfn *p_hwfn, u8 vfid)
348 u32 concrete_fid = 0;
350 SET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID, p_hwfn->rel_pf_id);
351 SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID, vfid);
352 SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID, 1);
360 * Although the implementation is ready, today we don't have any flow that
361 * utliizes said locks - and we want to keep it this way.
362 * If this changes, this needs to be revisted.
368 static void ecore_dmae_opcode(struct ecore_hwfn *p_hwfn,
369 const u8 is_src_type_grc,
370 const u8 is_dst_type_grc,
371 struct ecore_dmae_params *p_params)
376 /* Whether the source is the PCIe or the GRC.
377 * 0- The source is the PCIe
378 * 1- The source is the GRC.
380 opcode |= (is_src_type_grc ? DMAE_CMD_SRC_MASK_GRC
381 : DMAE_CMD_SRC_MASK_PCIE) << DMAE_CMD_SRC_SHIFT;
382 opcode |= (p_hwfn->rel_pf_id & DMAE_CMD_SRC_PF_ID_MASK) <<
383 DMAE_CMD_SRC_PF_ID_SHIFT;
385 /* The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */
386 opcode |= (is_dst_type_grc ? DMAE_CMD_DST_MASK_GRC
387 : DMAE_CMD_DST_MASK_PCIE) << DMAE_CMD_DST_SHIFT;
388 opcode |= (p_hwfn->rel_pf_id & DMAE_CMD_DST_PF_ID_MASK) <<
389 DMAE_CMD_DST_PF_ID_SHIFT;
391 /* DMAE_E4_TODO need to check which value to specifiy here. */
392 /* opcode |= (!b_complete_to_host)<< DMAE_CMD_C_DST_SHIFT; */
394 /* Whether to write a completion word to the completion destination:
395 * 0-Do not write a completion word
396 * 1-Write the completion word
398 opcode |= DMAE_CMD_COMP_WORD_EN_MASK << DMAE_CMD_COMP_WORD_EN_SHIFT;
399 opcode |= DMAE_CMD_SRC_ADDR_RESET_MASK << DMAE_CMD_SRC_ADDR_RESET_SHIFT;
401 if (p_params->flags & ECORE_DMAE_FLAG_COMPLETION_DST)
402 opcode |= 1 << DMAE_CMD_COMP_FUNC_SHIFT;
404 /* swapping mode 3 - big endian there should be a define ifdefed in
405 * the HSI somewhere. Since it is currently
407 opcode |= DMAE_CMD_ENDIANITY << DMAE_CMD_ENDIANITY_MODE_SHIFT;
409 opcode |= p_hwfn->port_id << DMAE_CMD_PORT_ID_SHIFT;
411 /* reset source address in next go */
412 opcode |= DMAE_CMD_SRC_ADDR_RESET_MASK << DMAE_CMD_SRC_ADDR_RESET_SHIFT;
414 /* reset dest address in next go */
415 opcode |= DMAE_CMD_DST_ADDR_RESET_MASK << DMAE_CMD_DST_ADDR_RESET_SHIFT;
417 /* SRC/DST VFID: all 1's - pf, otherwise VF id */
418 if (p_params->flags & ECORE_DMAE_FLAG_VF_SRC) {
419 opcode |= (1 << DMAE_CMD_SRC_VF_ID_VALID_SHIFT);
420 opcode_b |= (p_params->src_vfid << DMAE_CMD_SRC_VF_ID_SHIFT);
422 opcode_b |= (DMAE_CMD_SRC_VF_ID_MASK <<
423 DMAE_CMD_SRC_VF_ID_SHIFT);
425 if (p_params->flags & ECORE_DMAE_FLAG_VF_DST) {
426 opcode |= 1 << DMAE_CMD_DST_VF_ID_VALID_SHIFT;
427 opcode_b |= p_params->dst_vfid << DMAE_CMD_DST_VF_ID_SHIFT;
429 opcode_b |= DMAE_CMD_DST_VF_ID_MASK << DMAE_CMD_DST_VF_ID_SHIFT;
432 p_hwfn->dmae_info.p_dmae_cmd->opcode = OSAL_CPU_TO_LE32(opcode);
433 p_hwfn->dmae_info.p_dmae_cmd->opcode_b = OSAL_CPU_TO_LE16(opcode_b);
436 static u32 ecore_dmae_idx_to_go_cmd(u8 idx)
438 OSAL_BUILD_BUG_ON((DMAE_REG_GO_C31 - DMAE_REG_GO_C0) != 31 * 4);
440 return DMAE_REG_GO_C0 + idx * 4;
443 static enum _ecore_status_t
444 ecore_dmae_post_command(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
446 struct dmae_cmd *p_command = p_hwfn->dmae_info.p_dmae_cmd;
447 enum _ecore_status_t ecore_status = ECORE_SUCCESS;
448 u8 idx_cmd = p_hwfn->dmae_info.channel, i;
450 /* verify address is not OSAL_NULL */
451 if ((((!p_command->dst_addr_lo) && (!p_command->dst_addr_hi)) ||
452 ((!p_command->src_addr_lo) && (!p_command->src_addr_hi)))) {
453 DP_NOTICE(p_hwfn, true,
454 "source or destination address 0 idx_cmd=%d\n"
455 "opcode = [0x%08x,0x%04x] len=0x%x"
456 " src=0x%x:%x dst=0x%x:%x\n",
457 idx_cmd, (u32)p_command->opcode,
458 (u16)p_command->opcode_b,
459 (int)p_command->length,
460 (int)p_command->src_addr_hi,
461 (int)p_command->src_addr_lo,
462 (int)p_command->dst_addr_hi,
463 (int)p_command->dst_addr_lo);
468 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
469 "Posting DMAE command [idx %d]: opcode = [0x%08x,0x%04x]"
470 "len=0x%x src=0x%x:%x dst=0x%x:%x\n",
471 idx_cmd, (u32)p_command->opcode,
472 (u16)p_command->opcode_b,
473 (int)p_command->length,
474 (int)p_command->src_addr_hi,
475 (int)p_command->src_addr_lo,
476 (int)p_command->dst_addr_hi, (int)p_command->dst_addr_lo);
478 /* Copy the command to DMAE - need to do it before every call
479 * for source/dest address no reset.
480 * The number of commands have been increased to 16 (previous was 14)
481 * The first 9 DWs are the command registers, the 10 DW is the
483 * the rest are result registers (which are read only by the client).
485 for (i = 0; i < DMAE_CMD_SIZE; i++) {
486 u32 data = (i < DMAE_CMD_SIZE_TO_FILL) ?
487 *(((u32 *)p_command) + i) : 0;
489 ecore_wr(p_hwfn, p_ptt,
491 (idx_cmd * DMAE_CMD_SIZE * sizeof(u32)) +
492 (i * sizeof(u32)), data);
495 ecore_wr(p_hwfn, p_ptt,
496 ecore_dmae_idx_to_go_cmd(idx_cmd), DMAE_GO_VALUE);
501 enum _ecore_status_t ecore_dmae_info_alloc(struct ecore_hwfn *p_hwfn)
503 dma_addr_t *p_addr = &p_hwfn->dmae_info.completion_word_phys_addr;
504 struct dmae_cmd **p_cmd = &p_hwfn->dmae_info.p_dmae_cmd;
505 u32 **p_buff = &p_hwfn->dmae_info.p_intermediate_buffer;
506 u32 **p_comp = &p_hwfn->dmae_info.p_completion_word;
508 *p_comp = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, p_addr, sizeof(u32));
509 if (*p_comp == OSAL_NULL) {
510 DP_NOTICE(p_hwfn, true,
511 "Failed to allocate `p_completion_word'\n");
512 ecore_dmae_info_free(p_hwfn);
516 p_addr = &p_hwfn->dmae_info.dmae_cmd_phys_addr;
517 *p_cmd = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, p_addr,
518 sizeof(struct dmae_cmd));
519 if (*p_cmd == OSAL_NULL) {
520 DP_NOTICE(p_hwfn, true,
521 "Failed to allocate `struct dmae_cmd'\n");
522 ecore_dmae_info_free(p_hwfn);
526 p_addr = &p_hwfn->dmae_info.intermediate_buffer_phys_addr;
527 *p_buff = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, p_addr,
528 sizeof(u32) * DMAE_MAX_RW_SIZE);
529 if (*p_buff == OSAL_NULL) {
530 DP_NOTICE(p_hwfn, true,
531 "Failed to allocate `intermediate_buffer'\n");
532 ecore_dmae_info_free(p_hwfn);
536 /* DMAE_E4_TODO : Need to change this to reflect proper channel */
537 p_hwfn->dmae_info.channel = p_hwfn->rel_pf_id;
539 return ECORE_SUCCESS;
542 void ecore_dmae_info_free(struct ecore_hwfn *p_hwfn)
546 /* Just make sure no one is in the middle */
547 OSAL_MUTEX_ACQUIRE(&p_hwfn->dmae_info.mutex);
549 if (p_hwfn->dmae_info.p_completion_word != OSAL_NULL) {
550 p_phys = p_hwfn->dmae_info.completion_word_phys_addr;
551 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
552 p_hwfn->dmae_info.p_completion_word,
553 p_phys, sizeof(u32));
554 p_hwfn->dmae_info.p_completion_word = OSAL_NULL;
557 if (p_hwfn->dmae_info.p_dmae_cmd != OSAL_NULL) {
558 p_phys = p_hwfn->dmae_info.dmae_cmd_phys_addr;
559 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
560 p_hwfn->dmae_info.p_dmae_cmd,
561 p_phys, sizeof(struct dmae_cmd));
562 p_hwfn->dmae_info.p_dmae_cmd = OSAL_NULL;
565 if (p_hwfn->dmae_info.p_intermediate_buffer != OSAL_NULL) {
566 p_phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr;
567 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
568 p_hwfn->dmae_info.p_intermediate_buffer,
569 p_phys, sizeof(u32) * DMAE_MAX_RW_SIZE);
570 p_hwfn->dmae_info.p_intermediate_buffer = OSAL_NULL;
573 OSAL_MUTEX_RELEASE(&p_hwfn->dmae_info.mutex);
576 static enum _ecore_status_t ecore_dmae_operation_wait(struct ecore_hwfn *p_hwfn)
578 enum _ecore_status_t ecore_status = ECORE_SUCCESS;
579 u32 wait_cnt_limit = 10000, wait_cnt = 0;
582 u32 factor = (CHIP_REV_IS_EMUL(p_hwfn->p_dev) ?
584 (CHIP_REV_IS_FPGA(p_hwfn->p_dev) ?
585 ECORE_FPGA_FACTOR : 1));
587 wait_cnt_limit *= factor;
590 /* DMAE_E4_TODO : TODO check if we have to call any other function
591 * other than BARRIER to sync the completion_word since we are not
592 * using the volatile keyword for this
594 OSAL_BARRIER(p_hwfn->p_dev);
595 while (*p_hwfn->dmae_info.p_completion_word != DMAE_COMPLETION_VAL) {
596 /* DMAE_E4_TODO : using OSAL_MSLEEP instead of mm_wait since mm
597 * functions are getting depriciated. Need to review for future.
599 OSAL_UDELAY(DMAE_MIN_WAIT_TIME);
600 if (++wait_cnt > wait_cnt_limit) {
601 DP_NOTICE(p_hwfn->p_dev, ECORE_MSG_HW,
602 "Timed-out waiting for operation to"
603 " complete. Completion word is 0x%08x"
604 " expected 0x%08x.\n",
605 *p_hwfn->dmae_info.p_completion_word,
606 DMAE_COMPLETION_VAL);
607 ecore_status = ECORE_TIMEOUT;
610 /* to sync the completion_word since we are not
611 * using the volatile keyword for p_completion_word
613 OSAL_BARRIER(p_hwfn->p_dev);
616 if (ecore_status == ECORE_SUCCESS)
617 *p_hwfn->dmae_info.p_completion_word = 0;
622 static enum _ecore_status_t
623 ecore_dmae_execute_sub_operation(struct ecore_hwfn *p_hwfn,
624 struct ecore_ptt *p_ptt,
627 u8 src_type, u8 dst_type, u32 length)
629 dma_addr_t phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr;
630 struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd;
631 enum _ecore_status_t ecore_status = ECORE_SUCCESS;
634 case ECORE_DMAE_ADDRESS_GRC:
635 case ECORE_DMAE_ADDRESS_HOST_PHYS:
636 cmd->src_addr_hi = DMA_HI(src_addr);
637 cmd->src_addr_lo = DMA_LO(src_addr);
639 /* for virt source addresses we use the intermediate buffer. */
640 case ECORE_DMAE_ADDRESS_HOST_VIRT:
641 cmd->src_addr_hi = DMA_HI(phys);
642 cmd->src_addr_lo = DMA_LO(phys);
643 OSAL_MEMCPY(&p_hwfn->dmae_info.p_intermediate_buffer[0],
644 (void *)(osal_uintptr_t)src_addr,
645 length * sizeof(u32));
652 case ECORE_DMAE_ADDRESS_GRC:
653 case ECORE_DMAE_ADDRESS_HOST_PHYS:
654 cmd->dst_addr_hi = DMA_HI(dst_addr);
655 cmd->dst_addr_lo = DMA_LO(dst_addr);
657 /* for virt destination address we use the intermediate buff. */
658 case ECORE_DMAE_ADDRESS_HOST_VIRT:
659 cmd->dst_addr_hi = DMA_HI(phys);
660 cmd->dst_addr_lo = DMA_LO(phys);
666 cmd->length = (u16)length;
668 if (src_type == ECORE_DMAE_ADDRESS_HOST_VIRT ||
669 src_type == ECORE_DMAE_ADDRESS_HOST_PHYS)
670 OSAL_DMA_SYNC(p_hwfn->p_dev,
671 (void *)HILO_U64(cmd->src_addr_hi,
673 length * sizeof(u32), false);
675 ecore_dmae_post_command(p_hwfn, p_ptt);
677 ecore_status = ecore_dmae_operation_wait(p_hwfn);
679 /* TODO - is it true ? */
680 if (src_type == ECORE_DMAE_ADDRESS_HOST_VIRT ||
681 src_type == ECORE_DMAE_ADDRESS_HOST_PHYS)
682 OSAL_DMA_SYNC(p_hwfn->p_dev,
683 (void *)HILO_U64(cmd->src_addr_hi,
685 length * sizeof(u32), true);
687 if (ecore_status != ECORE_SUCCESS) {
688 DP_NOTICE(p_hwfn, ECORE_MSG_HW,
689 "ecore_dmae_host2grc: Wait Failed. source_addr"
690 " 0x%lx, grc_addr 0x%lx, size_in_dwords 0x%x\n",
691 (unsigned long)src_addr, (unsigned long)dst_addr,
696 if (dst_type == ECORE_DMAE_ADDRESS_HOST_VIRT)
697 OSAL_MEMCPY((void *)(osal_uintptr_t)(dst_addr),
698 &p_hwfn->dmae_info.p_intermediate_buffer[0],
699 length * sizeof(u32));
701 return ECORE_SUCCESS;
704 static enum _ecore_status_t
705 ecore_dmae_execute_command(struct ecore_hwfn *p_hwfn,
706 struct ecore_ptt *p_ptt,
712 struct ecore_dmae_params *p_params)
714 dma_addr_t phys = p_hwfn->dmae_info.completion_word_phys_addr;
715 u16 length_cur = 0, i = 0, cnt_split = 0, length_mod = 0;
716 struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd;
717 enum _ecore_status_t ecore_status = ECORE_SUCCESS;
718 u64 src_addr_split = 0, dst_addr_split = 0;
719 u16 length_limit = DMAE_MAX_RW_SIZE;
722 ecore_dmae_opcode(p_hwfn,
723 (src_type == ECORE_DMAE_ADDRESS_GRC),
724 (dst_type == ECORE_DMAE_ADDRESS_GRC), p_params);
726 cmd->comp_addr_lo = DMA_LO(phys);
727 cmd->comp_addr_hi = DMA_HI(phys);
728 cmd->comp_val = DMAE_COMPLETION_VAL;
730 /* Check if the grc_addr is valid like < MAX_GRC_OFFSET */
731 cnt_split = size_in_dwords / length_limit;
732 length_mod = size_in_dwords % length_limit;
734 src_addr_split = src_addr;
735 dst_addr_split = dst_addr;
737 for (i = 0; i <= cnt_split; i++) {
738 offset = length_limit * i;
740 if (!(p_params->flags & ECORE_DMAE_FLAG_RW_REPL_SRC)) {
741 if (src_type == ECORE_DMAE_ADDRESS_GRC)
742 src_addr_split = src_addr + offset;
744 src_addr_split = src_addr + (offset * 4);
747 if (dst_type == ECORE_DMAE_ADDRESS_GRC)
748 dst_addr_split = dst_addr + offset;
750 dst_addr_split = dst_addr + (offset * 4);
752 length_cur = (cnt_split == i) ? length_mod : length_limit;
754 /* might be zero on last iteration */
758 ecore_status = ecore_dmae_execute_sub_operation(p_hwfn,
765 if (ecore_status != ECORE_SUCCESS) {
766 DP_NOTICE(p_hwfn, false,
767 "ecore_dmae_execute_sub_operation Failed"
768 " with error 0x%x. source_addr 0x%lx,"
769 " dest addr 0x%lx, size_in_dwords 0x%x\n",
770 ecore_status, (unsigned long)src_addr,
771 (unsigned long)dst_addr, length_cur);
773 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_DMAE_FAIL);
782 ecore_dmae_host2grc(struct ecore_hwfn *p_hwfn,
783 struct ecore_ptt *p_ptt,
785 u32 grc_addr, u32 size_in_dwords, u32 flags)
787 u32 grc_addr_in_dw = grc_addr / sizeof(u32);
788 struct ecore_dmae_params params;
789 enum _ecore_status_t rc;
791 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_dmae_params));
792 params.flags = flags;
794 OSAL_MUTEX_ACQUIRE(&p_hwfn->dmae_info.mutex);
796 rc = ecore_dmae_execute_command(p_hwfn, p_ptt, source_addr,
798 ECORE_DMAE_ADDRESS_HOST_VIRT,
799 ECORE_DMAE_ADDRESS_GRC,
800 size_in_dwords, ¶ms);
802 OSAL_MUTEX_RELEASE(&p_hwfn->dmae_info.mutex);
808 ecore_dmae_grc2host(struct ecore_hwfn *p_hwfn,
809 struct ecore_ptt *p_ptt,
811 dma_addr_t dest_addr, u32 size_in_dwords, u32 flags)
813 u32 grc_addr_in_dw = grc_addr / sizeof(u32);
814 struct ecore_dmae_params params;
815 enum _ecore_status_t rc;
817 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_dmae_params));
818 params.flags = flags;
820 OSAL_MUTEX_ACQUIRE(&p_hwfn->dmae_info.mutex);
822 rc = ecore_dmae_execute_command(p_hwfn, p_ptt, grc_addr_in_dw,
823 dest_addr, ECORE_DMAE_ADDRESS_GRC,
824 ECORE_DMAE_ADDRESS_HOST_VIRT,
825 size_in_dwords, ¶ms);
827 OSAL_MUTEX_RELEASE(&p_hwfn->dmae_info.mutex);
833 ecore_dmae_host2host(struct ecore_hwfn *p_hwfn,
834 struct ecore_ptt *p_ptt,
835 dma_addr_t source_addr,
836 dma_addr_t dest_addr,
837 u32 size_in_dwords, struct ecore_dmae_params *p_params)
839 enum _ecore_status_t rc;
841 OSAL_MUTEX_ACQUIRE(&p_hwfn->dmae_info.mutex);
843 rc = ecore_dmae_execute_command(p_hwfn, p_ptt, source_addr,
845 ECORE_DMAE_ADDRESS_HOST_PHYS,
846 ECORE_DMAE_ADDRESS_HOST_PHYS,
847 size_in_dwords, p_params);
849 OSAL_MUTEX_RELEASE(&p_hwfn->dmae_info.mutex);
854 u16 ecore_get_qm_pq(struct ecore_hwfn *p_hwfn,
855 enum protocol_type proto,
856 union ecore_qm_pq_params *p_params)
860 if ((proto == PROTOCOLID_CORE ||
861 proto == PROTOCOLID_ETH) && !p_params) {
862 DP_NOTICE(p_hwfn, true,
863 "Protocol %d received NULL PQ params\n", proto);
868 case PROTOCOLID_CORE:
869 if (p_params->core.tc == LB_TC)
870 pq_id = p_hwfn->qm_info.pure_lb_pq;
871 else if (p_params->core.tc == OOO_LB_TC)
872 pq_id = p_hwfn->qm_info.ooo_pq;
874 pq_id = p_hwfn->qm_info.offload_pq;
877 pq_id = p_params->eth.tc;
878 /* TODO - multi-CoS for VFs? */
879 if (p_params->eth.is_vf)
880 pq_id += p_hwfn->qm_info.vf_queues_offset +
887 pq_id = CM_TX_PQ_BASE + pq_id + RESC_START(p_hwfn, ECORE_PQ);
892 void ecore_hw_err_notify(struct ecore_hwfn *p_hwfn,
893 enum ecore_hw_err_type err_type)
895 /* Fan failure cannot be masked by handling of another HW error */
896 if (p_hwfn->p_dev->recov_in_prog && err_type != ECORE_HW_ERR_FAN_FAIL) {
897 DP_VERBOSE(p_hwfn, ECORE_MSG_DRV,
898 "Recovery is in progress."
899 "Avoid notifying about HW error %d.\n",
904 OSAL_HW_ERROR_OCCURRED(p_hwfn, err_type);