1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
8 #include "ecore_hsi_common.h"
9 #include "ecore_status.h"
13 #include "ecore_utils.h"
14 #include "ecore_iov_api.h"
15 #include "ecore_gtt_values.h"
16 #include "ecore_dev_api.h"
19 #define ECORE_EMUL_FACTOR 2000
20 #define ECORE_FPGA_FACTOR 200
23 #define ECORE_BAR_ACQUIRE_TIMEOUT 1000
26 #define ECORE_BAR_INVALID_OFFSET (OSAL_CPU_TO_LE32(-1))
29 osal_list_entry_t list_entry;
31 struct pxp_ptt_entry pxp;
35 struct ecore_ptt_pool {
36 osal_list_t free_list;
37 osal_spinlock_t lock; /* ptt synchronized access */
38 struct ecore_ptt ptts[PXP_EXTERNAL_BAR_PF_WINDOW_NUM];
41 void __ecore_ptt_pool_free(struct ecore_hwfn *p_hwfn)
43 OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_ptt_pool);
44 p_hwfn->p_ptt_pool = OSAL_NULL;
47 enum _ecore_status_t ecore_ptt_pool_alloc(struct ecore_hwfn *p_hwfn)
49 struct ecore_ptt_pool *p_pool = OSAL_ALLOC(p_hwfn->p_dev,
57 OSAL_LIST_INIT(&p_pool->free_list);
58 for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) {
59 p_pool->ptts[i].idx = i;
60 p_pool->ptts[i].pxp.offset = ECORE_BAR_INVALID_OFFSET;
61 p_pool->ptts[i].pxp.pretend.control = 0;
62 p_pool->ptts[i].hwfn_id = p_hwfn->my_id;
64 /* There are special PTT entries that are taken only by design.
65 * The rest are added ot the list for general usage.
67 if (i >= RESERVED_PTT_MAX)
68 OSAL_LIST_PUSH_HEAD(&p_pool->ptts[i].list_entry,
72 p_hwfn->p_ptt_pool = p_pool;
73 #ifdef CONFIG_ECORE_LOCK_ALLOC
74 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_pool->lock)) {
75 __ecore_ptt_pool_free(p_hwfn);
79 OSAL_SPIN_LOCK_INIT(&p_pool->lock);
83 void ecore_gtt_init(struct ecore_hwfn *p_hwfn)
88 /* Set the global windows */
89 gtt_base = PXP_PF_WINDOW_ADMIN_START + PXP_PF_WINDOW_ADMIN_GLOBAL_START;
91 for (i = 0; i < OSAL_ARRAY_SIZE(pxp_global_win); i++)
92 if (pxp_global_win[i])
93 REG_WR(p_hwfn, gtt_base + i * PXP_GLOBAL_ENTRY_SIZE,
97 void ecore_ptt_invalidate(struct ecore_hwfn *p_hwfn)
99 struct ecore_ptt *p_ptt;
102 for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) {
103 p_ptt = &p_hwfn->p_ptt_pool->ptts[i];
104 p_ptt->pxp.offset = ECORE_BAR_INVALID_OFFSET;
108 void ecore_ptt_pool_free(struct ecore_hwfn *p_hwfn)
110 #ifdef CONFIG_ECORE_LOCK_ALLOC
111 if (p_hwfn->p_ptt_pool)
112 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->p_ptt_pool->lock);
114 __ecore_ptt_pool_free(p_hwfn);
117 struct ecore_ptt *ecore_ptt_acquire(struct ecore_hwfn *p_hwfn)
119 struct ecore_ptt *p_ptt;
122 /* Take the free PTT from the list */
123 for (i = 0; i < ECORE_BAR_ACQUIRE_TIMEOUT; i++) {
124 OSAL_SPIN_LOCK(&p_hwfn->p_ptt_pool->lock);
125 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->p_ptt_pool->free_list)) {
126 p_ptt = OSAL_LIST_FIRST_ENTRY(
127 &p_hwfn->p_ptt_pool->free_list,
128 struct ecore_ptt, list_entry);
129 OSAL_LIST_REMOVE_ENTRY(&p_ptt->list_entry,
130 &p_hwfn->p_ptt_pool->free_list);
132 OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);
134 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
135 "allocated ptt %d\n", p_ptt->idx);
140 OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);
144 DP_NOTICE(p_hwfn, true,
145 "PTT acquire timeout - failed to allocate PTT\n");
149 void ecore_ptt_release(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
151 /* This PTT should not be set to pretend if it is being released */
152 /* TODO - add some pretend sanity checks, to make sure pretend
153 * isn't set on this ptt
156 OSAL_SPIN_LOCK(&p_hwfn->p_ptt_pool->lock);
157 OSAL_LIST_PUSH_HEAD(&p_ptt->list_entry, &p_hwfn->p_ptt_pool->free_list);
158 OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);
161 static u32 ecore_ptt_get_hw_addr(struct ecore_ptt *p_ptt)
163 /* The HW is using DWORDS and we need to translate it to Bytes */
164 return OSAL_LE32_TO_CPU(p_ptt->pxp.offset) << 2;
167 static u32 ecore_ptt_config_addr(struct ecore_ptt *p_ptt)
169 return PXP_PF_WINDOW_ADMIN_PER_PF_START +
170 p_ptt->idx * sizeof(struct pxp_ptt_entry);
173 u32 ecore_ptt_get_bar_addr(struct ecore_ptt *p_ptt)
175 return PXP_EXTERNAL_BAR_PF_WINDOW_START +
176 p_ptt->idx * PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE;
179 void ecore_ptt_set_win(struct ecore_hwfn *p_hwfn,
180 struct ecore_ptt *p_ptt, u32 new_hw_addr)
184 prev_hw_addr = ecore_ptt_get_hw_addr(p_ptt);
186 if (new_hw_addr == prev_hw_addr)
189 /* Update PTT entery in admin window */
190 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
191 "Updating PTT entry %d to offset 0x%x\n",
192 p_ptt->idx, new_hw_addr);
194 /* The HW is using DWORDS and the address is in Bytes */
195 p_ptt->pxp.offset = OSAL_CPU_TO_LE32(new_hw_addr >> 2);
198 ecore_ptt_config_addr(p_ptt) +
199 OFFSETOF(struct pxp_ptt_entry, offset),
200 OSAL_LE32_TO_CPU(p_ptt->pxp.offset));
203 static u32 ecore_set_ptt(struct ecore_hwfn *p_hwfn,
204 struct ecore_ptt *p_ptt, u32 hw_addr)
206 u32 win_hw_addr = ecore_ptt_get_hw_addr(p_ptt);
209 offset = hw_addr - win_hw_addr;
211 if (p_ptt->hwfn_id != p_hwfn->my_id)
212 DP_NOTICE(p_hwfn, true,
213 "ptt[%d] of hwfn[%02x] is used by hwfn[%02x]!\n",
214 p_ptt->idx, p_ptt->hwfn_id, p_hwfn->my_id);
216 /* Verify the address is within the window */
217 if (hw_addr < win_hw_addr ||
218 offset >= PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) {
219 ecore_ptt_set_win(p_hwfn, p_ptt, hw_addr);
223 return ecore_ptt_get_bar_addr(p_ptt) + offset;
226 struct ecore_ptt *ecore_get_reserved_ptt(struct ecore_hwfn *p_hwfn,
227 enum reserved_ptts ptt_idx)
229 if (ptt_idx >= RESERVED_PTT_MAX) {
230 DP_NOTICE(p_hwfn, true,
231 "Requested PTT %d is out of range\n", ptt_idx);
235 return &p_hwfn->p_ptt_pool->ptts[ptt_idx];
238 static bool ecore_is_reg_fifo_empty(struct ecore_hwfn *p_hwfn,
239 struct ecore_ptt *p_ptt)
241 bool is_empty = true;
244 if (!p_hwfn->p_dev->chk_reg_fifo)
247 /* ecore_rd() cannot be used here since it calls this function */
248 bar_addr = ecore_set_ptt(p_hwfn, p_ptt, GRC_REG_TRACE_FIFO_VALID_DATA);
249 is_empty = REG_RD(p_hwfn, bar_addr) == 0;
252 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
260 void ecore_wr(struct ecore_hwfn *p_hwfn,
261 struct ecore_ptt *p_ptt, u32 hw_addr, u32 val)
266 prev_fifo_err = !ecore_is_reg_fifo_empty(p_hwfn, p_ptt);
268 bar_addr = ecore_set_ptt(p_hwfn, p_ptt, hw_addr);
269 REG_WR(p_hwfn, bar_addr, val);
270 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
271 "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n",
272 bar_addr, hw_addr, val);
275 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
279 OSAL_WARN(!prev_fifo_err && !ecore_is_reg_fifo_empty(p_hwfn, p_ptt),
280 "reg_fifo err was caused by a call to ecore_wr(0x%x, 0x%x)\n",
284 u32 ecore_rd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 hw_addr)
289 prev_fifo_err = !ecore_is_reg_fifo_empty(p_hwfn, p_ptt);
291 bar_addr = ecore_set_ptt(p_hwfn, p_ptt, hw_addr);
292 val = REG_RD(p_hwfn, bar_addr);
294 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
295 "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n",
296 bar_addr, hw_addr, val);
299 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
303 OSAL_WARN(!prev_fifo_err && !ecore_is_reg_fifo_empty(p_hwfn, p_ptt),
304 "reg_fifo error was caused by a call to ecore_rd(0x%x)\n",
310 static void ecore_memcpy_hw(struct ecore_hwfn *p_hwfn,
311 struct ecore_ptt *p_ptt,
313 u32 hw_addr, osal_size_t n, bool to_device)
315 u32 dw_count, *host_addr, hw_offset;
316 osal_size_t quota, done = 0;
317 u32 OSAL_IOMEM *reg_addr;
320 quota = OSAL_MIN_T(osal_size_t, n - done,
321 PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE);
323 if (IS_PF(p_hwfn->p_dev)) {
324 ecore_ptt_set_win(p_hwfn, p_ptt, hw_addr + done);
325 hw_offset = ecore_ptt_get_bar_addr(p_ptt);
327 hw_offset = hw_addr + done;
330 dw_count = quota / 4;
331 host_addr = (u32 *)((u8 *)addr + done);
332 reg_addr = (u32 OSAL_IOMEM *)OSAL_REG_ADDR(p_hwfn, hw_offset);
336 DIRECT_REG_WR(p_hwfn, reg_addr++, *host_addr++);
339 *host_addr++ = DIRECT_REG_RD(p_hwfn,
346 void ecore_memcpy_from(struct ecore_hwfn *p_hwfn,
347 struct ecore_ptt *p_ptt,
348 void *dest, u32 hw_addr, osal_size_t n)
350 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
351 "hw_addr 0x%x, dest %p hw_addr 0x%x, size %lu\n",
352 hw_addr, dest, hw_addr, (unsigned long)n);
354 ecore_memcpy_hw(p_hwfn, p_ptt, dest, hw_addr, n, false);
357 void ecore_memcpy_to(struct ecore_hwfn *p_hwfn,
358 struct ecore_ptt *p_ptt,
359 u32 hw_addr, void *src, osal_size_t n)
361 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
362 "hw_addr 0x%x, hw_addr 0x%x, src %p size %lu\n",
363 hw_addr, hw_addr, src, (unsigned long)n);
365 ecore_memcpy_hw(p_hwfn, p_ptt, src, hw_addr, n, true);
368 void ecore_fid_pretend(struct ecore_hwfn *p_hwfn,
369 struct ecore_ptt *p_ptt, u16 fid)
373 SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1);
374 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1);
376 /* Every pretend undos prev pretends, including previous port pretend */
378 SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0);
379 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0);
380 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
382 if (!GET_FIELD(fid, PXP_CONCRETE_FID_VFVALID))
383 fid = GET_FIELD(fid, PXP_CONCRETE_FID_PFID);
385 p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
386 p_ptt->pxp.pretend.fid.concrete_fid.fid = OSAL_CPU_TO_LE16(fid);
389 ecore_ptt_config_addr(p_ptt) +
390 OFFSETOF(struct pxp_ptt_entry, pretend),
391 *(u32 *)&p_ptt->pxp.pretend);
394 void ecore_port_pretend(struct ecore_hwfn *p_hwfn,
395 struct ecore_ptt *p_ptt, u8 port_id)
399 SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id);
400 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1);
401 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
402 p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
405 ecore_ptt_config_addr(p_ptt) +
406 OFFSETOF(struct pxp_ptt_entry, pretend),
407 *(u32 *)&p_ptt->pxp.pretend);
410 void ecore_port_unpretend(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
414 SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0);
415 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0);
416 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
418 p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
421 ecore_ptt_config_addr(p_ptt) +
422 OFFSETOF(struct pxp_ptt_entry, pretend),
423 *(u32 *)&p_ptt->pxp.pretend);
426 void ecore_port_fid_pretend(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
431 SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id);
432 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1);
433 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
435 SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1);
436 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1);
438 if (!GET_FIELD(fid, PXP_CONCRETE_FID_VFVALID))
439 fid = GET_FIELD(fid, PXP_CONCRETE_FID_PFID);
441 p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
442 p_ptt->pxp.pretend.fid.concrete_fid.fid = OSAL_CPU_TO_LE16(fid);
445 ecore_ptt_config_addr(p_ptt) +
446 OFFSETOF(struct pxp_ptt_entry, pretend),
447 *(u32 *)&p_ptt->pxp.pretend);
450 u32 ecore_vfid_to_concrete(struct ecore_hwfn *p_hwfn, u8 vfid)
452 u32 concrete_fid = 0;
454 SET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID, p_hwfn->rel_pf_id);
455 SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID, vfid);
456 SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID, 1);
464 * Although the implementation is ready, today we don't have any flow that
465 * utliizes said locks - and we want to keep it this way.
466 * If this changes, this needs to be revisted.
471 #define ECORE_DMAE_FLAGS_IS_SET(params, flag) \
472 ((params) != OSAL_NULL && \
473 GET_FIELD((params)->flags, DMAE_PARAMS_##flag))
475 static void ecore_dmae_opcode(struct ecore_hwfn *p_hwfn,
476 const u8 is_src_type_grc,
477 const u8 is_dst_type_grc,
478 struct dmae_params *p_params)
480 u8 src_pf_id, dst_pf_id, port_id;
484 /* Whether the source is the PCIe or the GRC.
485 * 0- The source is the PCIe
486 * 1- The source is the GRC.
488 opcode |= (is_src_type_grc ? dmae_cmd_src_grc : dmae_cmd_src_pcie) <<
490 src_pf_id = ECORE_DMAE_FLAGS_IS_SET(p_params, SRC_PF_VALID) ?
491 p_params->src_pf_id : p_hwfn->rel_pf_id;
492 opcode |= (src_pf_id & DMAE_CMD_SRC_PF_ID_MASK) <<
493 DMAE_CMD_SRC_PF_ID_SHIFT;
495 /* The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */
496 opcode |= (is_dst_type_grc ? dmae_cmd_dst_grc : dmae_cmd_dst_pcie) <<
498 dst_pf_id = ECORE_DMAE_FLAGS_IS_SET(p_params, DST_PF_VALID) ?
499 p_params->dst_pf_id : p_hwfn->rel_pf_id;
500 opcode |= (dst_pf_id & DMAE_CMD_DST_PF_ID_MASK) <<
501 DMAE_CMD_DST_PF_ID_SHIFT;
503 /* DMAE_E4_TODO need to check which value to specify here. */
504 /* opcode |= (!b_complete_to_host)<< DMAE_CMD_C_DST_SHIFT; */
506 /* Whether to write a completion word to the completion destination:
507 * 0-Do not write a completion word
508 * 1-Write the completion word
510 opcode |= DMAE_CMD_COMP_WORD_EN_MASK << DMAE_CMD_COMP_WORD_EN_SHIFT;
511 opcode |= DMAE_CMD_SRC_ADDR_RESET_MASK << DMAE_CMD_SRC_ADDR_RESET_SHIFT;
513 if (ECORE_DMAE_FLAGS_IS_SET(p_params, COMPLETION_DST))
514 opcode |= 1 << DMAE_CMD_COMP_FUNC_SHIFT;
516 /* swapping mode 3 - big endian there should be a define ifdefed in
517 * the HSI somewhere. Since it is currently
519 opcode |= DMAE_CMD_ENDIANITY << DMAE_CMD_ENDIANITY_MODE_SHIFT;
521 port_id = (ECORE_DMAE_FLAGS_IS_SET(p_params, PORT_VALID)) ?
522 p_params->port_id : p_hwfn->port_id;
523 opcode |= port_id << DMAE_CMD_PORT_ID_SHIFT;
525 /* reset source address in next go */
526 opcode |= DMAE_CMD_SRC_ADDR_RESET_MASK << DMAE_CMD_SRC_ADDR_RESET_SHIFT;
528 /* reset dest address in next go */
529 opcode |= DMAE_CMD_DST_ADDR_RESET_MASK << DMAE_CMD_DST_ADDR_RESET_SHIFT;
531 /* SRC/DST VFID: all 1's - pf, otherwise VF id */
532 if (ECORE_DMAE_FLAGS_IS_SET(p_params, SRC_VF_VALID)) {
533 opcode |= (1 << DMAE_CMD_SRC_VF_ID_VALID_SHIFT);
534 opcode_b |= (p_params->src_vf_id << DMAE_CMD_SRC_VF_ID_SHIFT);
536 opcode_b |= (DMAE_CMD_SRC_VF_ID_MASK <<
537 DMAE_CMD_SRC_VF_ID_SHIFT);
539 if (ECORE_DMAE_FLAGS_IS_SET(p_params, DST_VF_VALID)) {
540 opcode |= 1 << DMAE_CMD_DST_VF_ID_VALID_SHIFT;
541 opcode_b |= p_params->dst_vf_id << DMAE_CMD_DST_VF_ID_SHIFT;
543 opcode_b |= DMAE_CMD_DST_VF_ID_MASK << DMAE_CMD_DST_VF_ID_SHIFT;
546 p_hwfn->dmae_info.p_dmae_cmd->opcode = OSAL_CPU_TO_LE32(opcode);
547 p_hwfn->dmae_info.p_dmae_cmd->opcode_b = OSAL_CPU_TO_LE16(opcode_b);
550 static u32 ecore_dmae_idx_to_go_cmd(u8 idx)
552 OSAL_BUILD_BUG_ON((DMAE_REG_GO_C31 - DMAE_REG_GO_C0) != 31 * 4);
554 /* All the DMAE 'go' registers form an array in internal memory */
555 return DMAE_REG_GO_C0 + (idx << 2);
558 static enum _ecore_status_t ecore_dmae_post_command(struct ecore_hwfn *p_hwfn,
559 struct ecore_ptt *p_ptt)
561 struct dmae_cmd *p_command = p_hwfn->dmae_info.p_dmae_cmd;
562 u8 idx_cmd = p_hwfn->dmae_info.channel, i;
563 enum _ecore_status_t ecore_status = ECORE_SUCCESS;
565 /* verify address is not OSAL_NULL */
566 if ((((!p_command->dst_addr_lo) && (!p_command->dst_addr_hi)) ||
567 ((!p_command->src_addr_lo) && (!p_command->src_addr_hi)))) {
568 DP_NOTICE(p_hwfn, true,
569 "source or destination address 0 idx_cmd=%d\n"
570 "opcode = [0x%08x,0x%04x] len=0x%x"
571 " src=0x%x:%x dst=0x%x:%x\n",
573 OSAL_LE32_TO_CPU(p_command->opcode),
574 OSAL_LE16_TO_CPU(p_command->opcode_b),
575 OSAL_LE16_TO_CPU(p_command->length_dw),
576 OSAL_LE32_TO_CPU(p_command->src_addr_hi),
577 OSAL_LE32_TO_CPU(p_command->src_addr_lo),
578 OSAL_LE32_TO_CPU(p_command->dst_addr_hi),
579 OSAL_LE32_TO_CPU(p_command->dst_addr_lo));
584 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
585 "Posting DMAE command [idx %d]: opcode = [0x%08x,0x%04x]"
586 "len=0x%x src=0x%x:%x dst=0x%x:%x\n",
588 OSAL_LE32_TO_CPU(p_command->opcode),
589 OSAL_LE16_TO_CPU(p_command->opcode_b),
590 OSAL_LE16_TO_CPU(p_command->length_dw),
591 OSAL_LE32_TO_CPU(p_command->src_addr_hi),
592 OSAL_LE32_TO_CPU(p_command->src_addr_lo),
593 OSAL_LE32_TO_CPU(p_command->dst_addr_hi),
594 OSAL_LE32_TO_CPU(p_command->dst_addr_lo));
596 /* Copy the command to DMAE - need to do it before every call
597 * for source/dest address no reset.
598 * The number of commands have been increased to 16 (previous was 14)
599 * The first 9 DWs are the command registers, the 10 DW is the
601 * the rest are result registers (which are read only by the client).
603 for (i = 0; i < DMAE_CMD_SIZE; i++) {
604 u32 data = (i < DMAE_CMD_SIZE_TO_FILL) ?
605 *(((u32 *)p_command) + i) : 0;
607 ecore_wr(p_hwfn, p_ptt,
609 (idx_cmd * DMAE_CMD_SIZE * sizeof(u32)) +
610 (i * sizeof(u32)), data);
613 ecore_wr(p_hwfn, p_ptt,
614 ecore_dmae_idx_to_go_cmd(idx_cmd), DMAE_GO_VALUE);
619 enum _ecore_status_t ecore_dmae_info_alloc(struct ecore_hwfn *p_hwfn)
621 dma_addr_t *p_addr = &p_hwfn->dmae_info.completion_word_phys_addr;
622 struct dmae_cmd **p_cmd = &p_hwfn->dmae_info.p_dmae_cmd;
623 u32 **p_buff = &p_hwfn->dmae_info.p_intermediate_buffer;
624 u32 **p_comp = &p_hwfn->dmae_info.p_completion_word;
626 *p_comp = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, p_addr, sizeof(u32));
627 if (*p_comp == OSAL_NULL) {
628 DP_NOTICE(p_hwfn, false,
629 "Failed to allocate `p_completion_word'\n");
633 p_addr = &p_hwfn->dmae_info.dmae_cmd_phys_addr;
634 *p_cmd = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, p_addr,
635 sizeof(struct dmae_cmd));
636 if (*p_cmd == OSAL_NULL) {
637 DP_NOTICE(p_hwfn, false,
638 "Failed to allocate `struct dmae_cmd'\n");
642 p_addr = &p_hwfn->dmae_info.intermediate_buffer_phys_addr;
643 *p_buff = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, p_addr,
644 sizeof(u32) * DMAE_MAX_RW_SIZE);
645 if (*p_buff == OSAL_NULL) {
646 DP_NOTICE(p_hwfn, false,
647 "Failed to allocate `intermediate_buffer'\n");
651 p_hwfn->dmae_info.channel = p_hwfn->rel_pf_id;
652 p_hwfn->dmae_info.b_mem_ready = true;
654 return ECORE_SUCCESS;
656 ecore_dmae_info_free(p_hwfn);
660 void ecore_dmae_info_free(struct ecore_hwfn *p_hwfn)
664 OSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);
665 p_hwfn->dmae_info.b_mem_ready = false;
666 OSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);
668 if (p_hwfn->dmae_info.p_completion_word != OSAL_NULL) {
669 p_phys = p_hwfn->dmae_info.completion_word_phys_addr;
670 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
671 p_hwfn->dmae_info.p_completion_word,
672 p_phys, sizeof(u32));
673 p_hwfn->dmae_info.p_completion_word = OSAL_NULL;
676 if (p_hwfn->dmae_info.p_dmae_cmd != OSAL_NULL) {
677 p_phys = p_hwfn->dmae_info.dmae_cmd_phys_addr;
678 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
679 p_hwfn->dmae_info.p_dmae_cmd,
680 p_phys, sizeof(struct dmae_cmd));
681 p_hwfn->dmae_info.p_dmae_cmd = OSAL_NULL;
684 if (p_hwfn->dmae_info.p_intermediate_buffer != OSAL_NULL) {
685 p_phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr;
686 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
687 p_hwfn->dmae_info.p_intermediate_buffer,
688 p_phys, sizeof(u32) * DMAE_MAX_RW_SIZE);
689 p_hwfn->dmae_info.p_intermediate_buffer = OSAL_NULL;
693 static enum _ecore_status_t ecore_dmae_operation_wait(struct ecore_hwfn *p_hwfn)
695 u32 wait_cnt_limit = 10000, wait_cnt = 0;
696 enum _ecore_status_t ecore_status = ECORE_SUCCESS;
699 u32 factor = (CHIP_REV_IS_EMUL(p_hwfn->p_dev) ?
701 (CHIP_REV_IS_FPGA(p_hwfn->p_dev) ?
702 ECORE_FPGA_FACTOR : 1));
704 wait_cnt_limit *= factor;
707 /* DMAE_E4_TODO : TODO check if we have to call any other function
708 * other than BARRIER to sync the completion_word since we are not
709 * using the volatile keyword for this
711 OSAL_BARRIER(p_hwfn->p_dev);
712 while (*p_hwfn->dmae_info.p_completion_word != DMAE_COMPLETION_VAL) {
713 OSAL_UDELAY(DMAE_MIN_WAIT_TIME);
714 if (++wait_cnt > wait_cnt_limit) {
715 DP_NOTICE(p_hwfn->p_dev, false,
716 "Timed-out waiting for operation to"
717 " complete. Completion word is 0x%08x"
718 " expected 0x%08x.\n",
719 *p_hwfn->dmae_info.p_completion_word,
720 DMAE_COMPLETION_VAL);
721 ecore_status = ECORE_TIMEOUT;
724 /* to sync the completion_word since we are not
725 * using the volatile keyword for p_completion_word
727 OSAL_BARRIER(p_hwfn->p_dev);
730 if (ecore_status == ECORE_SUCCESS)
731 *p_hwfn->dmae_info.p_completion_word = 0;
736 enum ecore_dmae_address_type {
737 ECORE_DMAE_ADDRESS_HOST_VIRT,
738 ECORE_DMAE_ADDRESS_HOST_PHYS,
739 ECORE_DMAE_ADDRESS_GRC
742 static enum _ecore_status_t
743 ecore_dmae_execute_sub_operation(struct ecore_hwfn *p_hwfn,
744 struct ecore_ptt *p_ptt,
747 u8 src_type, u8 dst_type, u32 length_dw)
749 dma_addr_t phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr;
750 struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd;
751 enum _ecore_status_t ecore_status = ECORE_SUCCESS;
754 case ECORE_DMAE_ADDRESS_GRC:
755 case ECORE_DMAE_ADDRESS_HOST_PHYS:
756 cmd->src_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(src_addr));
757 cmd->src_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(src_addr));
759 /* for virt source addresses we use the intermediate buffer. */
760 case ECORE_DMAE_ADDRESS_HOST_VIRT:
761 cmd->src_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(phys));
762 cmd->src_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(phys));
763 OSAL_MEMCPY(&p_hwfn->dmae_info.p_intermediate_buffer[0],
764 (void *)(osal_uintptr_t)src_addr,
765 length_dw * sizeof(u32));
772 case ECORE_DMAE_ADDRESS_GRC:
773 case ECORE_DMAE_ADDRESS_HOST_PHYS:
774 cmd->dst_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(dst_addr));
775 cmd->dst_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(dst_addr));
777 /* for virt destination address we use the intermediate buff. */
778 case ECORE_DMAE_ADDRESS_HOST_VIRT:
779 cmd->dst_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(phys));
780 cmd->dst_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(phys));
786 cmd->length_dw = OSAL_CPU_TO_LE16((u16)length_dw);
788 if (src_type == ECORE_DMAE_ADDRESS_HOST_VIRT ||
789 src_type == ECORE_DMAE_ADDRESS_HOST_PHYS)
790 OSAL_DMA_SYNC(p_hwfn->p_dev,
791 (void *)HILO_U64(cmd->src_addr_hi,
793 length_dw * sizeof(u32), false);
795 ecore_dmae_post_command(p_hwfn, p_ptt);
797 ecore_status = ecore_dmae_operation_wait(p_hwfn);
799 /* TODO - is it true ? */
800 if (src_type == ECORE_DMAE_ADDRESS_HOST_VIRT ||
801 src_type == ECORE_DMAE_ADDRESS_HOST_PHYS)
802 OSAL_DMA_SYNC(p_hwfn->p_dev,
803 (void *)HILO_U64(cmd->src_addr_hi,
805 length_dw * sizeof(u32), true);
807 if (ecore_status != ECORE_SUCCESS) {
808 DP_NOTICE(p_hwfn, false,
809 "Wait Failed. source_addr 0x%lx, grc_addr 0x%lx, size_in_dwords 0x%x, intermediate buffer 0x%lx.\n",
810 (unsigned long)src_addr, (unsigned long)dst_addr,
812 (unsigned long)p_hwfn->dmae_info.intermediate_buffer_phys_addr);
816 if (dst_type == ECORE_DMAE_ADDRESS_HOST_VIRT)
817 OSAL_MEMCPY((void *)(osal_uintptr_t)(dst_addr),
818 &p_hwfn->dmae_info.p_intermediate_buffer[0],
819 length_dw * sizeof(u32));
821 return ECORE_SUCCESS;
824 static enum _ecore_status_t
825 ecore_dmae_execute_command(struct ecore_hwfn *p_hwfn,
826 struct ecore_ptt *p_ptt,
832 struct dmae_params *p_params)
834 dma_addr_t phys = p_hwfn->dmae_info.completion_word_phys_addr;
835 u16 length_cur = 0, i = 0, cnt_split = 0, length_mod = 0;
836 struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd;
837 u64 src_addr_split = 0, dst_addr_split = 0;
838 u16 length_limit = DMAE_MAX_RW_SIZE;
839 enum _ecore_status_t ecore_status = ECORE_SUCCESS;
842 if (!p_hwfn->dmae_info.b_mem_ready) {
843 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
844 "No buffers allocated. Avoid DMAE transaction [{src: addr 0x%lx, type %d}, {dst: addr 0x%lx, type %d}, size %d].\n",
845 (unsigned long)src_addr, src_type,
846 (unsigned long)dst_addr, dst_type,
851 if (p_hwfn->p_dev->recov_in_prog) {
852 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
853 "Recovery is in progress. Avoid DMAE transaction [{src: addr 0x%lx, type %d}, {dst: addr 0x%lx, type %d}, size %d].\n",
854 (unsigned long)src_addr, src_type,
855 (unsigned long)dst_addr, dst_type,
857 /* Return success to let the flow to be completed successfully
858 * w/o any error handling.
860 return ECORE_SUCCESS;
864 DP_NOTICE(p_hwfn, true,
865 "ecore_dmae_execute_sub_operation failed. Invalid state. source_addr 0x%lx, destination addr 0x%lx, size_in_dwords 0x%x\n",
866 (unsigned long)src_addr,
867 (unsigned long)dst_addr,
872 ecore_dmae_opcode(p_hwfn,
873 (src_type == ECORE_DMAE_ADDRESS_GRC),
874 (dst_type == ECORE_DMAE_ADDRESS_GRC), p_params);
876 cmd->comp_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(phys));
877 cmd->comp_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(phys));
878 cmd->comp_val = OSAL_CPU_TO_LE32(DMAE_COMPLETION_VAL);
880 /* Check if the grc_addr is valid like < MAX_GRC_OFFSET */
881 cnt_split = size_in_dwords / length_limit;
882 length_mod = size_in_dwords % length_limit;
884 src_addr_split = src_addr;
885 dst_addr_split = dst_addr;
887 for (i = 0; i <= cnt_split; i++) {
888 offset = length_limit * i;
890 if (!ECORE_DMAE_FLAGS_IS_SET(p_params, RW_REPL_SRC)) {
891 if (src_type == ECORE_DMAE_ADDRESS_GRC)
892 src_addr_split = src_addr + offset;
894 src_addr_split = src_addr + (offset * 4);
897 if (dst_type == ECORE_DMAE_ADDRESS_GRC)
898 dst_addr_split = dst_addr + offset;
900 dst_addr_split = dst_addr + (offset * 4);
902 length_cur = (cnt_split == i) ? length_mod : length_limit;
904 /* might be zero on last iteration */
908 ecore_status = ecore_dmae_execute_sub_operation(p_hwfn,
915 if (ecore_status != ECORE_SUCCESS) {
916 DP_NOTICE(p_hwfn, false,
917 "ecore_dmae_execute_sub_operation Failed"
918 " with error 0x%x. source_addr 0x%lx,"
919 " dest addr 0x%lx, size_in_dwords 0x%x\n",
920 ecore_status, (unsigned long)src_addr,
921 (unsigned long)dst_addr, length_cur);
923 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_DMAE_FAIL);
931 enum _ecore_status_t ecore_dmae_host2grc(struct ecore_hwfn *p_hwfn,
932 struct ecore_ptt *p_ptt,
936 struct dmae_params *p_params)
938 u32 grc_addr_in_dw = grc_addr / sizeof(u32);
939 enum _ecore_status_t rc;
941 OSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);
943 rc = ecore_dmae_execute_command(p_hwfn, p_ptt, source_addr,
945 ECORE_DMAE_ADDRESS_HOST_VIRT,
946 ECORE_DMAE_ADDRESS_GRC,
947 size_in_dwords, p_params);
949 OSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);
954 enum _ecore_status_t ecore_dmae_grc2host(struct ecore_hwfn *p_hwfn,
955 struct ecore_ptt *p_ptt,
957 dma_addr_t dest_addr,
959 struct dmae_params *p_params)
961 u32 grc_addr_in_dw = grc_addr / sizeof(u32);
962 enum _ecore_status_t rc;
964 OSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);
966 rc = ecore_dmae_execute_command(p_hwfn, p_ptt, grc_addr_in_dw,
967 dest_addr, ECORE_DMAE_ADDRESS_GRC,
968 ECORE_DMAE_ADDRESS_HOST_VIRT,
969 size_in_dwords, p_params);
971 OSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);
977 ecore_dmae_host2host(struct ecore_hwfn *p_hwfn,
978 struct ecore_ptt *p_ptt,
979 dma_addr_t source_addr,
980 dma_addr_t dest_addr,
982 struct dmae_params *p_params)
984 enum _ecore_status_t rc;
986 OSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);
988 rc = ecore_dmae_execute_command(p_hwfn, p_ptt, source_addr,
990 ECORE_DMAE_ADDRESS_HOST_PHYS,
991 ECORE_DMAE_ADDRESS_HOST_PHYS,
992 size_in_dwords, p_params);
994 OSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);
999 void ecore_hw_err_notify(struct ecore_hwfn *p_hwfn,
1000 enum ecore_hw_err_type err_type)
1002 /* Fan failure cannot be masked by handling of another HW error */
1003 if (p_hwfn->p_dev->recov_in_prog && err_type != ECORE_HW_ERR_FAN_FAIL) {
1004 DP_VERBOSE(p_hwfn, ECORE_MSG_DRV,
1005 "Recovery is in progress."
1006 "Avoid notifying about HW error %d.\n",
1011 OSAL_HW_ERROR_OCCURRED(p_hwfn, err_type);
1014 enum _ecore_status_t ecore_dmae_sanity(struct ecore_hwfn *p_hwfn,
1015 struct ecore_ptt *p_ptt,
1018 u32 size = OSAL_PAGE_SIZE / 2, val;
1019 enum _ecore_status_t rc = ECORE_SUCCESS;
1024 p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, &p_phys, 2 * size);
1026 DP_NOTICE(p_hwfn, false,
1027 "DMAE sanity [%s]: failed to allocate memory\n",
1032 /* Fill the bottom half of the allocated memory with a known pattern */
1033 for (p_tmp = (u32 *)p_virt;
1034 p_tmp < (u32 *)((u8 *)p_virt + size);
1036 /* Save the address itself as the value */
1037 val = (u32)(osal_uintptr_t)p_tmp;
1041 /* Zero the top half of the allocated memory */
1042 OSAL_MEM_ZERO((u8 *)p_virt + size, size);
1044 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1045 "DMAE sanity [%s]: src_addr={phys 0x%lx, virt %p}, dst_addr={phys 0x%lx, virt %p}, size 0x%x\n",
1046 phase, (unsigned long)p_phys, p_virt,
1047 (unsigned long)(p_phys + size),
1048 (u8 *)p_virt + size, size);
1050 rc = ecore_dmae_host2host(p_hwfn, p_ptt, p_phys, p_phys + size,
1051 size / 4 /* size_in_dwords */,
1052 OSAL_NULL /* default parameters */);
1053 if (rc != ECORE_SUCCESS) {
1054 DP_NOTICE(p_hwfn, false,
1055 "DMAE sanity [%s]: ecore_dmae_host2host() failed. rc = %d.\n",
1060 /* Verify that the top half of the allocated memory has the pattern */
1061 for (p_tmp = (u32 *)((u8 *)p_virt + size);
1062 p_tmp < (u32 *)((u8 *)p_virt + (2 * size));
1064 /* The corresponding address in the bottom half */
1065 val = (u32)(osal_uintptr_t)p_tmp - size;
1067 if (*p_tmp != val) {
1068 DP_NOTICE(p_hwfn, false,
1069 "DMAE sanity [%s]: addr={phys 0x%lx, virt %p}, read_val 0x%08x, expected_val 0x%08x\n",
1071 (unsigned long)p_phys +
1072 ((u8 *)p_tmp - (u8 *)p_virt),
1073 p_tmp, *p_tmp, val);
1074 rc = ECORE_UNKNOWN_ERROR;
1080 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, p_virt, p_phys, 2 * size);
1084 void ecore_ppfid_wr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1085 u8 abs_ppfid, u32 hw_addr, u32 val)
1087 u8 pfid = ECORE_PFID_BY_PPFID(p_hwfn, abs_ppfid);
1089 ecore_fid_pretend(p_hwfn, p_ptt,
1090 pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
1091 ecore_wr(p_hwfn, p_ptt, hw_addr, val);
1092 ecore_fid_pretend(p_hwfn, p_ptt,
1093 p_hwfn->rel_pf_id <<
1094 PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
1097 u32 ecore_ppfid_rd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1098 u8 abs_ppfid, u32 hw_addr)
1100 u8 pfid = ECORE_PFID_BY_PPFID(p_hwfn, abs_ppfid);
1103 ecore_fid_pretend(p_hwfn, p_ptt,
1104 pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
1105 val = ecore_rd(p_hwfn, p_ptt, hw_addr);
1106 ecore_fid_pretend(p_hwfn, p_ptt,
1107 p_hwfn->rel_pf_id <<
1108 PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);