1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
8 #include "ecore_hsi_common.h"
9 #include "ecore_status.h"
13 #include "ecore_utils.h"
14 #include "ecore_iov_api.h"
17 #define ECORE_EMUL_FACTOR 2000
18 #define ECORE_FPGA_FACTOR 200
21 #define ECORE_BAR_ACQUIRE_TIMEOUT 1000
24 #define ECORE_BAR_INVALID_OFFSET (OSAL_CPU_TO_LE32(-1))
27 osal_list_entry_t list_entry;
29 struct pxp_ptt_entry pxp;
33 struct ecore_ptt_pool {
34 osal_list_t free_list;
35 osal_spinlock_t lock; /* ptt synchronized access */
36 struct ecore_ptt ptts[PXP_EXTERNAL_BAR_PF_WINDOW_NUM];
39 void __ecore_ptt_pool_free(struct ecore_hwfn *p_hwfn)
41 OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_ptt_pool);
42 p_hwfn->p_ptt_pool = OSAL_NULL;
45 enum _ecore_status_t ecore_ptt_pool_alloc(struct ecore_hwfn *p_hwfn)
47 struct ecore_ptt_pool *p_pool = OSAL_ALLOC(p_hwfn->p_dev,
55 OSAL_LIST_INIT(&p_pool->free_list);
56 for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) {
57 p_pool->ptts[i].idx = i;
58 p_pool->ptts[i].pxp.offset = ECORE_BAR_INVALID_OFFSET;
59 p_pool->ptts[i].pxp.pretend.control = 0;
60 p_pool->ptts[i].hwfn_id = p_hwfn->my_id;
62 /* There are special PTT entries that are taken only by design.
63 * The rest are added ot the list for general usage.
65 if (i >= RESERVED_PTT_MAX)
66 OSAL_LIST_PUSH_HEAD(&p_pool->ptts[i].list_entry,
70 p_hwfn->p_ptt_pool = p_pool;
71 #ifdef CONFIG_ECORE_LOCK_ALLOC
72 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_pool->lock)) {
73 __ecore_ptt_pool_free(p_hwfn);
77 OSAL_SPIN_LOCK_INIT(&p_pool->lock);
81 void ecore_ptt_invalidate(struct ecore_hwfn *p_hwfn)
83 struct ecore_ptt *p_ptt;
86 for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) {
87 p_ptt = &p_hwfn->p_ptt_pool->ptts[i];
88 p_ptt->pxp.offset = ECORE_BAR_INVALID_OFFSET;
92 void ecore_ptt_pool_free(struct ecore_hwfn *p_hwfn)
94 #ifdef CONFIG_ECORE_LOCK_ALLOC
95 if (p_hwfn->p_ptt_pool)
96 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->p_ptt_pool->lock);
98 __ecore_ptt_pool_free(p_hwfn);
101 struct ecore_ptt *ecore_ptt_acquire(struct ecore_hwfn *p_hwfn)
103 struct ecore_ptt *p_ptt;
106 /* Take the free PTT from the list */
107 for (i = 0; i < ECORE_BAR_ACQUIRE_TIMEOUT; i++) {
108 OSAL_SPIN_LOCK(&p_hwfn->p_ptt_pool->lock);
109 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->p_ptt_pool->free_list)) {
110 p_ptt = OSAL_LIST_FIRST_ENTRY(
111 &p_hwfn->p_ptt_pool->free_list,
112 struct ecore_ptt, list_entry);
113 OSAL_LIST_REMOVE_ENTRY(&p_ptt->list_entry,
114 &p_hwfn->p_ptt_pool->free_list);
116 OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);
118 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
119 "allocated ptt %d\n", p_ptt->idx);
124 OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);
128 DP_NOTICE(p_hwfn, true,
129 "PTT acquire timeout - failed to allocate PTT\n");
133 void ecore_ptt_release(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
135 /* This PTT should not be set to pretend if it is being released */
136 /* TODO - add some pretend sanity checks, to make sure pretend
137 * isn't set on this ptt
140 OSAL_SPIN_LOCK(&p_hwfn->p_ptt_pool->lock);
141 OSAL_LIST_PUSH_HEAD(&p_ptt->list_entry, &p_hwfn->p_ptt_pool->free_list);
142 OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);
145 static u32 ecore_ptt_get_hw_addr(struct ecore_ptt *p_ptt)
147 /* The HW is using DWORDS and we need to translate it to Bytes */
148 return OSAL_LE32_TO_CPU(p_ptt->pxp.offset) << 2;
151 static u32 ecore_ptt_config_addr(struct ecore_ptt *p_ptt)
153 return PXP_PF_WINDOW_ADMIN_PER_PF_START +
154 p_ptt->idx * sizeof(struct pxp_ptt_entry);
157 u32 ecore_ptt_get_bar_addr(struct ecore_ptt *p_ptt)
159 return PXP_EXTERNAL_BAR_PF_WINDOW_START +
160 p_ptt->idx * PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE;
163 void ecore_ptt_set_win(struct ecore_hwfn *p_hwfn,
164 struct ecore_ptt *p_ptt, u32 new_hw_addr)
168 prev_hw_addr = ecore_ptt_get_hw_addr(p_ptt);
170 if (new_hw_addr == prev_hw_addr)
173 /* Update PTT entery in admin window */
174 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
175 "Updating PTT entry %d to offset 0x%x\n",
176 p_ptt->idx, new_hw_addr);
178 /* The HW is using DWORDS and the address is in Bytes */
179 p_ptt->pxp.offset = OSAL_CPU_TO_LE32(new_hw_addr >> 2);
182 ecore_ptt_config_addr(p_ptt) +
183 OFFSETOF(struct pxp_ptt_entry, offset),
184 OSAL_LE32_TO_CPU(p_ptt->pxp.offset));
187 static u32 ecore_set_ptt(struct ecore_hwfn *p_hwfn,
188 struct ecore_ptt *p_ptt, u32 hw_addr)
190 u32 win_hw_addr = ecore_ptt_get_hw_addr(p_ptt);
193 offset = hw_addr - win_hw_addr;
195 if (p_ptt->hwfn_id != p_hwfn->my_id)
196 DP_NOTICE(p_hwfn, true,
197 "ptt[%d] of hwfn[%02x] is used by hwfn[%02x]!\n",
198 p_ptt->idx, p_ptt->hwfn_id, p_hwfn->my_id);
200 /* Verify the address is within the window */
201 if (hw_addr < win_hw_addr ||
202 offset >= PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) {
203 ecore_ptt_set_win(p_hwfn, p_ptt, hw_addr);
207 return ecore_ptt_get_bar_addr(p_ptt) + offset;
210 struct ecore_ptt *ecore_get_reserved_ptt(struct ecore_hwfn *p_hwfn,
211 enum reserved_ptts ptt_idx)
213 if (ptt_idx >= RESERVED_PTT_MAX) {
214 DP_NOTICE(p_hwfn, true,
215 "Requested PTT %d is out of range\n", ptt_idx);
219 return &p_hwfn->p_ptt_pool->ptts[ptt_idx];
222 static bool ecore_is_reg_fifo_empty(struct ecore_hwfn *p_hwfn,
223 struct ecore_ptt *p_ptt)
225 bool is_empty = true;
228 if (!p_hwfn->p_dev->chk_reg_fifo)
231 /* ecore_rd() cannot be used here since it calls this function */
232 bar_addr = ecore_set_ptt(p_hwfn, p_ptt, GRC_REG_TRACE_FIFO_VALID_DATA);
233 is_empty = REG_RD(p_hwfn, bar_addr) == 0;
236 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
244 void ecore_wr(struct ecore_hwfn *p_hwfn,
245 struct ecore_ptt *p_ptt, u32 hw_addr, u32 val)
250 prev_fifo_err = !ecore_is_reg_fifo_empty(p_hwfn, p_ptt);
252 bar_addr = ecore_set_ptt(p_hwfn, p_ptt, hw_addr);
253 REG_WR(p_hwfn, bar_addr, val);
254 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
255 "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n",
256 bar_addr, hw_addr, val);
259 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
263 OSAL_WARN(!prev_fifo_err && !ecore_is_reg_fifo_empty(p_hwfn, p_ptt),
264 "reg_fifo err was caused by a call to ecore_wr(0x%x, 0x%x)\n",
268 u32 ecore_rd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 hw_addr)
273 prev_fifo_err = !ecore_is_reg_fifo_empty(p_hwfn, p_ptt);
275 bar_addr = ecore_set_ptt(p_hwfn, p_ptt, hw_addr);
276 val = REG_RD(p_hwfn, bar_addr);
278 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
279 "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n",
280 bar_addr, hw_addr, val);
283 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
287 OSAL_WARN(!prev_fifo_err && !ecore_is_reg_fifo_empty(p_hwfn, p_ptt),
288 "reg_fifo error was caused by a call to ecore_rd(0x%x)\n",
294 static void ecore_memcpy_hw(struct ecore_hwfn *p_hwfn,
295 struct ecore_ptt *p_ptt,
297 u32 hw_addr, osal_size_t n, bool to_device)
299 u32 dw_count, *host_addr, hw_offset;
300 osal_size_t quota, done = 0;
301 u32 OSAL_IOMEM *reg_addr;
304 quota = OSAL_MIN_T(osal_size_t, n - done,
305 PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE);
307 if (IS_PF(p_hwfn->p_dev)) {
308 ecore_ptt_set_win(p_hwfn, p_ptt, hw_addr + done);
309 hw_offset = ecore_ptt_get_bar_addr(p_ptt);
311 hw_offset = hw_addr + done;
314 dw_count = quota / 4;
315 host_addr = (u32 *)((u8 *)addr + done);
316 reg_addr = (u32 OSAL_IOMEM *)OSAL_REG_ADDR(p_hwfn, hw_offset);
320 DIRECT_REG_WR(p_hwfn, reg_addr++, *host_addr++);
323 *host_addr++ = DIRECT_REG_RD(p_hwfn,
330 void ecore_memcpy_from(struct ecore_hwfn *p_hwfn,
331 struct ecore_ptt *p_ptt,
332 void *dest, u32 hw_addr, osal_size_t n)
334 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
335 "hw_addr 0x%x, dest %p hw_addr 0x%x, size %lu\n",
336 hw_addr, dest, hw_addr, (unsigned long)n);
338 ecore_memcpy_hw(p_hwfn, p_ptt, dest, hw_addr, n, false);
341 void ecore_memcpy_to(struct ecore_hwfn *p_hwfn,
342 struct ecore_ptt *p_ptt,
343 u32 hw_addr, void *src, osal_size_t n)
345 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
346 "hw_addr 0x%x, hw_addr 0x%x, src %p size %lu\n",
347 hw_addr, hw_addr, src, (unsigned long)n);
349 ecore_memcpy_hw(p_hwfn, p_ptt, src, hw_addr, n, true);
352 void ecore_fid_pretend(struct ecore_hwfn *p_hwfn,
353 struct ecore_ptt *p_ptt, u16 fid)
357 SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1);
358 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1);
360 /* Every pretend undos prev pretends, including previous port pretend */
362 SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0);
363 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0);
364 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
366 if (!GET_FIELD(fid, PXP_CONCRETE_FID_VFVALID))
367 fid = GET_FIELD(fid, PXP_CONCRETE_FID_PFID);
369 p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
370 p_ptt->pxp.pretend.fid.concrete_fid.fid = OSAL_CPU_TO_LE16(fid);
373 ecore_ptt_config_addr(p_ptt) +
374 OFFSETOF(struct pxp_ptt_entry, pretend),
375 *(u32 *)&p_ptt->pxp.pretend);
378 void ecore_port_pretend(struct ecore_hwfn *p_hwfn,
379 struct ecore_ptt *p_ptt, u8 port_id)
383 SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id);
384 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1);
385 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
386 p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
389 ecore_ptt_config_addr(p_ptt) +
390 OFFSETOF(struct pxp_ptt_entry, pretend),
391 *(u32 *)&p_ptt->pxp.pretend);
394 void ecore_port_unpretend(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
398 SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0);
399 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0);
400 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
402 p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
405 ecore_ptt_config_addr(p_ptt) +
406 OFFSETOF(struct pxp_ptt_entry, pretend),
407 *(u32 *)&p_ptt->pxp.pretend);
410 u32 ecore_vfid_to_concrete(struct ecore_hwfn *p_hwfn, u8 vfid)
412 u32 concrete_fid = 0;
414 SET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID, p_hwfn->rel_pf_id);
415 SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID, vfid);
416 SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID, 1);
424 * Although the implementation is ready, today we don't have any flow that
425 * utliizes said locks - and we want to keep it this way.
426 * If this changes, this needs to be revisted.
432 static void ecore_dmae_opcode(struct ecore_hwfn *p_hwfn,
433 const u8 is_src_type_grc,
434 const u8 is_dst_type_grc,
435 struct ecore_dmae_params *p_params)
440 /* Whether the source is the PCIe or the GRC.
441 * 0- The source is the PCIe
442 * 1- The source is the GRC.
444 opcode |= (is_src_type_grc ? DMAE_CMD_SRC_MASK_GRC
445 : DMAE_CMD_SRC_MASK_PCIE) << DMAE_CMD_SRC_SHIFT;
446 opcode |= (p_hwfn->rel_pf_id & DMAE_CMD_SRC_PF_ID_MASK) <<
447 DMAE_CMD_SRC_PF_ID_SHIFT;
449 /* The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */
450 opcode |= (is_dst_type_grc ? DMAE_CMD_DST_MASK_GRC
451 : DMAE_CMD_DST_MASK_PCIE) << DMAE_CMD_DST_SHIFT;
452 opcode |= (p_hwfn->rel_pf_id & DMAE_CMD_DST_PF_ID_MASK) <<
453 DMAE_CMD_DST_PF_ID_SHIFT;
455 /* DMAE_E4_TODO need to check which value to specifiy here. */
456 /* opcode |= (!b_complete_to_host)<< DMAE_CMD_C_DST_SHIFT; */
458 /* Whether to write a completion word to the completion destination:
459 * 0-Do not write a completion word
460 * 1-Write the completion word
462 opcode |= DMAE_CMD_COMP_WORD_EN_MASK << DMAE_CMD_COMP_WORD_EN_SHIFT;
463 opcode |= DMAE_CMD_SRC_ADDR_RESET_MASK << DMAE_CMD_SRC_ADDR_RESET_SHIFT;
465 if (p_params->flags & ECORE_DMAE_FLAG_COMPLETION_DST)
466 opcode |= 1 << DMAE_CMD_COMP_FUNC_SHIFT;
468 /* swapping mode 3 - big endian there should be a define ifdefed in
469 * the HSI somewhere. Since it is currently
471 opcode |= DMAE_CMD_ENDIANITY << DMAE_CMD_ENDIANITY_MODE_SHIFT;
473 opcode |= p_hwfn->port_id << DMAE_CMD_PORT_ID_SHIFT;
475 /* reset source address in next go */
476 opcode |= DMAE_CMD_SRC_ADDR_RESET_MASK << DMAE_CMD_SRC_ADDR_RESET_SHIFT;
478 /* reset dest address in next go */
479 opcode |= DMAE_CMD_DST_ADDR_RESET_MASK << DMAE_CMD_DST_ADDR_RESET_SHIFT;
481 /* SRC/DST VFID: all 1's - pf, otherwise VF id */
482 if (p_params->flags & ECORE_DMAE_FLAG_VF_SRC) {
483 opcode |= (1 << DMAE_CMD_SRC_VF_ID_VALID_SHIFT);
484 opcode_b |= (p_params->src_vfid << DMAE_CMD_SRC_VF_ID_SHIFT);
486 opcode_b |= (DMAE_CMD_SRC_VF_ID_MASK <<
487 DMAE_CMD_SRC_VF_ID_SHIFT);
489 if (p_params->flags & ECORE_DMAE_FLAG_VF_DST) {
490 opcode |= 1 << DMAE_CMD_DST_VF_ID_VALID_SHIFT;
491 opcode_b |= p_params->dst_vfid << DMAE_CMD_DST_VF_ID_SHIFT;
493 opcode_b |= DMAE_CMD_DST_VF_ID_MASK << DMAE_CMD_DST_VF_ID_SHIFT;
496 p_hwfn->dmae_info.p_dmae_cmd->opcode = OSAL_CPU_TO_LE32(opcode);
497 p_hwfn->dmae_info.p_dmae_cmd->opcode_b = OSAL_CPU_TO_LE16(opcode_b);
500 static u32 ecore_dmae_idx_to_go_cmd(u8 idx)
502 OSAL_BUILD_BUG_ON((DMAE_REG_GO_C31 - DMAE_REG_GO_C0) != 31 * 4);
504 /* All the DMAE 'go' registers form an array in internal memory */
505 return DMAE_REG_GO_C0 + (idx << 2);
508 static enum _ecore_status_t ecore_dmae_post_command(struct ecore_hwfn *p_hwfn,
509 struct ecore_ptt *p_ptt)
511 struct dmae_cmd *p_command = p_hwfn->dmae_info.p_dmae_cmd;
512 u8 idx_cmd = p_hwfn->dmae_info.channel, i;
513 enum _ecore_status_t ecore_status = ECORE_SUCCESS;
515 /* verify address is not OSAL_NULL */
516 if ((((!p_command->dst_addr_lo) && (!p_command->dst_addr_hi)) ||
517 ((!p_command->src_addr_lo) && (!p_command->src_addr_hi)))) {
518 DP_NOTICE(p_hwfn, true,
519 "source or destination address 0 idx_cmd=%d\n"
520 "opcode = [0x%08x,0x%04x] len=0x%x"
521 " src=0x%x:%x dst=0x%x:%x\n",
523 OSAL_LE32_TO_CPU(p_command->opcode),
524 OSAL_LE16_TO_CPU(p_command->opcode_b),
525 OSAL_LE16_TO_CPU(p_command->length_dw),
526 OSAL_LE32_TO_CPU(p_command->src_addr_hi),
527 OSAL_LE32_TO_CPU(p_command->src_addr_lo),
528 OSAL_LE32_TO_CPU(p_command->dst_addr_hi),
529 OSAL_LE32_TO_CPU(p_command->dst_addr_lo));
534 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
535 "Posting DMAE command [idx %d]: opcode = [0x%08x,0x%04x]"
536 "len=0x%x src=0x%x:%x dst=0x%x:%x\n",
538 OSAL_LE32_TO_CPU(p_command->opcode),
539 OSAL_LE16_TO_CPU(p_command->opcode_b),
540 OSAL_LE16_TO_CPU(p_command->length_dw),
541 OSAL_LE32_TO_CPU(p_command->src_addr_hi),
542 OSAL_LE32_TO_CPU(p_command->src_addr_lo),
543 OSAL_LE32_TO_CPU(p_command->dst_addr_hi),
544 OSAL_LE32_TO_CPU(p_command->dst_addr_lo));
546 /* Copy the command to DMAE - need to do it before every call
547 * for source/dest address no reset.
548 * The number of commands have been increased to 16 (previous was 14)
549 * The first 9 DWs are the command registers, the 10 DW is the
551 * the rest are result registers (which are read only by the client).
553 for (i = 0; i < DMAE_CMD_SIZE; i++) {
554 u32 data = (i < DMAE_CMD_SIZE_TO_FILL) ?
555 *(((u32 *)p_command) + i) : 0;
557 ecore_wr(p_hwfn, p_ptt,
559 (idx_cmd * DMAE_CMD_SIZE * sizeof(u32)) +
560 (i * sizeof(u32)), data);
563 ecore_wr(p_hwfn, p_ptt,
564 ecore_dmae_idx_to_go_cmd(idx_cmd), DMAE_GO_VALUE);
569 enum _ecore_status_t ecore_dmae_info_alloc(struct ecore_hwfn *p_hwfn)
571 dma_addr_t *p_addr = &p_hwfn->dmae_info.completion_word_phys_addr;
572 struct dmae_cmd **p_cmd = &p_hwfn->dmae_info.p_dmae_cmd;
573 u32 **p_buff = &p_hwfn->dmae_info.p_intermediate_buffer;
574 u32 **p_comp = &p_hwfn->dmae_info.p_completion_word;
576 *p_comp = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, p_addr, sizeof(u32));
577 if (*p_comp == OSAL_NULL) {
578 DP_NOTICE(p_hwfn, false,
579 "Failed to allocate `p_completion_word'\n");
583 p_addr = &p_hwfn->dmae_info.dmae_cmd_phys_addr;
584 *p_cmd = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, p_addr,
585 sizeof(struct dmae_cmd));
586 if (*p_cmd == OSAL_NULL) {
587 DP_NOTICE(p_hwfn, false,
588 "Failed to allocate `struct dmae_cmd'\n");
592 p_addr = &p_hwfn->dmae_info.intermediate_buffer_phys_addr;
593 *p_buff = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, p_addr,
594 sizeof(u32) * DMAE_MAX_RW_SIZE);
595 if (*p_buff == OSAL_NULL) {
596 DP_NOTICE(p_hwfn, false,
597 "Failed to allocate `intermediate_buffer'\n");
601 p_hwfn->dmae_info.channel = p_hwfn->rel_pf_id;
602 p_hwfn->dmae_info.b_mem_ready = true;
604 return ECORE_SUCCESS;
606 ecore_dmae_info_free(p_hwfn);
610 void ecore_dmae_info_free(struct ecore_hwfn *p_hwfn)
614 OSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);
615 p_hwfn->dmae_info.b_mem_ready = false;
616 OSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);
618 if (p_hwfn->dmae_info.p_completion_word != OSAL_NULL) {
619 p_phys = p_hwfn->dmae_info.completion_word_phys_addr;
620 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
621 p_hwfn->dmae_info.p_completion_word,
622 p_phys, sizeof(u32));
623 p_hwfn->dmae_info.p_completion_word = OSAL_NULL;
626 if (p_hwfn->dmae_info.p_dmae_cmd != OSAL_NULL) {
627 p_phys = p_hwfn->dmae_info.dmae_cmd_phys_addr;
628 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
629 p_hwfn->dmae_info.p_dmae_cmd,
630 p_phys, sizeof(struct dmae_cmd));
631 p_hwfn->dmae_info.p_dmae_cmd = OSAL_NULL;
634 if (p_hwfn->dmae_info.p_intermediate_buffer != OSAL_NULL) {
635 p_phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr;
636 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
637 p_hwfn->dmae_info.p_intermediate_buffer,
638 p_phys, sizeof(u32) * DMAE_MAX_RW_SIZE);
639 p_hwfn->dmae_info.p_intermediate_buffer = OSAL_NULL;
643 static enum _ecore_status_t ecore_dmae_operation_wait(struct ecore_hwfn *p_hwfn)
645 u32 wait_cnt_limit = 10000, wait_cnt = 0;
646 enum _ecore_status_t ecore_status = ECORE_SUCCESS;
649 u32 factor = (CHIP_REV_IS_EMUL(p_hwfn->p_dev) ?
651 (CHIP_REV_IS_FPGA(p_hwfn->p_dev) ?
652 ECORE_FPGA_FACTOR : 1));
654 wait_cnt_limit *= factor;
657 /* DMAE_E4_TODO : TODO check if we have to call any other function
658 * other than BARRIER to sync the completion_word since we are not
659 * using the volatile keyword for this
661 OSAL_BARRIER(p_hwfn->p_dev);
662 while (*p_hwfn->dmae_info.p_completion_word != DMAE_COMPLETION_VAL) {
663 OSAL_UDELAY(DMAE_MIN_WAIT_TIME);
664 if (++wait_cnt > wait_cnt_limit) {
665 DP_NOTICE(p_hwfn->p_dev, ECORE_MSG_HW,
666 "Timed-out waiting for operation to"
667 " complete. Completion word is 0x%08x"
668 " expected 0x%08x.\n",
669 *p_hwfn->dmae_info.p_completion_word,
670 DMAE_COMPLETION_VAL);
671 ecore_status = ECORE_TIMEOUT;
674 /* to sync the completion_word since we are not
675 * using the volatile keyword for p_completion_word
677 OSAL_BARRIER(p_hwfn->p_dev);
680 if (ecore_status == ECORE_SUCCESS)
681 *p_hwfn->dmae_info.p_completion_word = 0;
686 static enum _ecore_status_t
687 ecore_dmae_execute_sub_operation(struct ecore_hwfn *p_hwfn,
688 struct ecore_ptt *p_ptt,
691 u8 src_type, u8 dst_type, u32 length_dw)
693 dma_addr_t phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr;
694 struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd;
695 enum _ecore_status_t ecore_status = ECORE_SUCCESS;
698 case ECORE_DMAE_ADDRESS_GRC:
699 case ECORE_DMAE_ADDRESS_HOST_PHYS:
700 cmd->src_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(src_addr));
701 cmd->src_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(src_addr));
703 /* for virt source addresses we use the intermediate buffer. */
704 case ECORE_DMAE_ADDRESS_HOST_VIRT:
705 cmd->src_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(phys));
706 cmd->src_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(phys));
707 OSAL_MEMCPY(&p_hwfn->dmae_info.p_intermediate_buffer[0],
708 (void *)(osal_uintptr_t)src_addr,
709 length_dw * sizeof(u32));
716 case ECORE_DMAE_ADDRESS_GRC:
717 case ECORE_DMAE_ADDRESS_HOST_PHYS:
718 cmd->dst_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(dst_addr));
719 cmd->dst_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(dst_addr));
721 /* for virt destination address we use the intermediate buff. */
722 case ECORE_DMAE_ADDRESS_HOST_VIRT:
723 cmd->dst_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(phys));
724 cmd->dst_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(phys));
730 cmd->length_dw = OSAL_CPU_TO_LE16((u16)length_dw);
732 if (src_type == ECORE_DMAE_ADDRESS_HOST_VIRT ||
733 src_type == ECORE_DMAE_ADDRESS_HOST_PHYS)
734 OSAL_DMA_SYNC(p_hwfn->p_dev,
735 (void *)HILO_U64(cmd->src_addr_hi,
737 length_dw * sizeof(u32), false);
739 ecore_dmae_post_command(p_hwfn, p_ptt);
741 ecore_status = ecore_dmae_operation_wait(p_hwfn);
743 /* TODO - is it true ? */
744 if (src_type == ECORE_DMAE_ADDRESS_HOST_VIRT ||
745 src_type == ECORE_DMAE_ADDRESS_HOST_PHYS)
746 OSAL_DMA_SYNC(p_hwfn->p_dev,
747 (void *)HILO_U64(cmd->src_addr_hi,
749 length_dw * sizeof(u32), true);
751 if (ecore_status != ECORE_SUCCESS) {
752 DP_NOTICE(p_hwfn, ECORE_MSG_HW,
753 "Wait Failed. source_addr 0x%lx, grc_addr 0x%lx, size_in_dwords 0x%x, intermediate buffer 0x%lx.\n",
754 (unsigned long)src_addr, (unsigned long)dst_addr,
756 (unsigned long)p_hwfn->dmae_info.intermediate_buffer_phys_addr);
760 if (dst_type == ECORE_DMAE_ADDRESS_HOST_VIRT)
761 OSAL_MEMCPY((void *)(osal_uintptr_t)(dst_addr),
762 &p_hwfn->dmae_info.p_intermediate_buffer[0],
763 length_dw * sizeof(u32));
765 return ECORE_SUCCESS;
768 static enum _ecore_status_t
769 ecore_dmae_execute_command(struct ecore_hwfn *p_hwfn,
770 struct ecore_ptt *p_ptt,
776 struct ecore_dmae_params *p_params)
778 dma_addr_t phys = p_hwfn->dmae_info.completion_word_phys_addr;
779 u16 length_cur = 0, i = 0, cnt_split = 0, length_mod = 0;
780 struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd;
781 u64 src_addr_split = 0, dst_addr_split = 0;
782 u16 length_limit = DMAE_MAX_RW_SIZE;
783 enum _ecore_status_t ecore_status = ECORE_SUCCESS;
786 if (!p_hwfn->dmae_info.b_mem_ready) {
787 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
788 "No buffers allocated. Avoid DMAE transaction [{src: addr 0x%lx, type %d}, {dst: addr 0x%lx, type %d}, size %d].\n",
789 (unsigned long)src_addr, src_type,
790 (unsigned long)dst_addr, dst_type,
795 if (p_hwfn->p_dev->recov_in_prog) {
796 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
797 "Recovery is in progress. Avoid DMAE transaction [{src: addr 0x%lx, type %d}, {dst: addr 0x%lx, type %d}, size %d].\n",
798 (unsigned long)src_addr, src_type,
799 (unsigned long)dst_addr, dst_type,
801 /* Return success to let the flow to be completed successfully
802 * w/o any error handling.
804 return ECORE_SUCCESS;
808 DP_NOTICE(p_hwfn, true,
809 "ecore_dmae_execute_sub_operation failed. Invalid state. source_addr 0x%lx, destination addr 0x%lx, size_in_dwords 0x%x\n",
810 (unsigned long)src_addr,
811 (unsigned long)dst_addr,
816 ecore_dmae_opcode(p_hwfn,
817 (src_type == ECORE_DMAE_ADDRESS_GRC),
818 (dst_type == ECORE_DMAE_ADDRESS_GRC), p_params);
820 cmd->comp_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(phys));
821 cmd->comp_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(phys));
822 cmd->comp_val = OSAL_CPU_TO_LE32(DMAE_COMPLETION_VAL);
824 /* Check if the grc_addr is valid like < MAX_GRC_OFFSET */
825 cnt_split = size_in_dwords / length_limit;
826 length_mod = size_in_dwords % length_limit;
828 src_addr_split = src_addr;
829 dst_addr_split = dst_addr;
831 for (i = 0; i <= cnt_split; i++) {
832 offset = length_limit * i;
834 if (!(p_params->flags & ECORE_DMAE_FLAG_RW_REPL_SRC)) {
835 if (src_type == ECORE_DMAE_ADDRESS_GRC)
836 src_addr_split = src_addr + offset;
838 src_addr_split = src_addr + (offset * 4);
841 if (dst_type == ECORE_DMAE_ADDRESS_GRC)
842 dst_addr_split = dst_addr + offset;
844 dst_addr_split = dst_addr + (offset * 4);
846 length_cur = (cnt_split == i) ? length_mod : length_limit;
848 /* might be zero on last iteration */
852 ecore_status = ecore_dmae_execute_sub_operation(p_hwfn,
859 if (ecore_status != ECORE_SUCCESS) {
860 DP_NOTICE(p_hwfn, false,
861 "ecore_dmae_execute_sub_operation Failed"
862 " with error 0x%x. source_addr 0x%lx,"
863 " dest addr 0x%lx, size_in_dwords 0x%x\n",
864 ecore_status, (unsigned long)src_addr,
865 (unsigned long)dst_addr, length_cur);
867 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_DMAE_FAIL);
876 ecore_dmae_host2grc(struct ecore_hwfn *p_hwfn,
877 struct ecore_ptt *p_ptt,
879 u32 grc_addr, u32 size_in_dwords, u32 flags)
881 u32 grc_addr_in_dw = grc_addr / sizeof(u32);
882 struct ecore_dmae_params params;
883 enum _ecore_status_t rc;
885 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_dmae_params));
886 params.flags = flags;
888 OSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);
890 rc = ecore_dmae_execute_command(p_hwfn, p_ptt, source_addr,
892 ECORE_DMAE_ADDRESS_HOST_VIRT,
893 ECORE_DMAE_ADDRESS_GRC,
894 size_in_dwords, ¶ms);
896 OSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);
902 ecore_dmae_grc2host(struct ecore_hwfn *p_hwfn,
903 struct ecore_ptt *p_ptt,
905 dma_addr_t dest_addr, u32 size_in_dwords, u32 flags)
907 u32 grc_addr_in_dw = grc_addr / sizeof(u32);
908 struct ecore_dmae_params params;
909 enum _ecore_status_t rc;
911 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_dmae_params));
912 params.flags = flags;
914 OSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);
916 rc = ecore_dmae_execute_command(p_hwfn, p_ptt, grc_addr_in_dw,
917 dest_addr, ECORE_DMAE_ADDRESS_GRC,
918 ECORE_DMAE_ADDRESS_HOST_VIRT,
919 size_in_dwords, ¶ms);
921 OSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);
927 ecore_dmae_host2host(struct ecore_hwfn *p_hwfn,
928 struct ecore_ptt *p_ptt,
929 dma_addr_t source_addr,
930 dma_addr_t dest_addr,
931 u32 size_in_dwords, struct ecore_dmae_params *p_params)
933 enum _ecore_status_t rc;
935 OSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);
937 rc = ecore_dmae_execute_command(p_hwfn, p_ptt, source_addr,
939 ECORE_DMAE_ADDRESS_HOST_PHYS,
940 ECORE_DMAE_ADDRESS_HOST_PHYS,
941 size_in_dwords, p_params);
943 OSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);
948 void ecore_hw_err_notify(struct ecore_hwfn *p_hwfn,
949 enum ecore_hw_err_type err_type)
951 /* Fan failure cannot be masked by handling of another HW error */
952 if (p_hwfn->p_dev->recov_in_prog && err_type != ECORE_HW_ERR_FAN_FAIL) {
953 DP_VERBOSE(p_hwfn, ECORE_MSG_DRV,
954 "Recovery is in progress."
955 "Avoid notifying about HW error %d.\n",
960 OSAL_HW_ERROR_OCCURRED(p_hwfn, err_type);
963 enum _ecore_status_t ecore_dmae_sanity(struct ecore_hwfn *p_hwfn,
964 struct ecore_ptt *p_ptt,
967 u32 size = OSAL_PAGE_SIZE / 2, val;
968 struct ecore_dmae_params params;
969 enum _ecore_status_t rc = ECORE_SUCCESS;
974 p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, &p_phys, 2 * size);
976 DP_NOTICE(p_hwfn, false,
977 "DMAE sanity [%s]: failed to allocate memory\n",
982 /* Fill the bottom half of the allocated memory with a known pattern */
983 for (p_tmp = (u32 *)p_virt;
984 p_tmp < (u32 *)((u8 *)p_virt + size);
986 /* Save the address itself as the value */
987 val = (u32)(osal_uintptr_t)p_tmp;
991 /* Zero the top half of the allocated memory */
992 OSAL_MEM_ZERO((u8 *)p_virt + size, size);
994 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
995 "DMAE sanity [%s]: src_addr={phys 0x%lx, virt %p}, dst_addr={phys 0x%lx, virt %p}, size 0x%x\n",
996 phase, (unsigned long)p_phys, p_virt,
997 (unsigned long)(p_phys + size),
998 (u8 *)p_virt + size, size);
1000 OSAL_MEMSET(¶ms, 0, sizeof(params));
1001 rc = ecore_dmae_host2host(p_hwfn, p_ptt, p_phys, p_phys + size,
1002 size / 4 /* size_in_dwords */, ¶ms);
1003 if (rc != ECORE_SUCCESS) {
1004 DP_NOTICE(p_hwfn, false,
1005 "DMAE sanity [%s]: ecore_dmae_host2host() failed. rc = %d.\n",
1010 /* Verify that the top half of the allocated memory has the pattern */
1011 for (p_tmp = (u32 *)((u8 *)p_virt + size);
1012 p_tmp < (u32 *)((u8 *)p_virt + (2 * size));
1014 /* The corresponding address in the bottom half */
1015 val = (u32)(osal_uintptr_t)p_tmp - size;
1017 if (*p_tmp != val) {
1018 DP_NOTICE(p_hwfn, false,
1019 "DMAE sanity [%s]: addr={phys 0x%lx, virt %p}, read_val 0x%08x, expected_val 0x%08x\n",
1021 (unsigned long)p_phys +
1022 ((u8 *)p_tmp - (u8 *)p_virt),
1023 p_tmp, *p_tmp, val);
1024 rc = ECORE_UNKNOWN_ERROR;
1030 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, p_virt, p_phys, 2 * size);