2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
10 #include "ecore_hsi_common.h"
11 #include "ecore_status.h"
15 #include "ecore_utils.h"
16 #include "ecore_iov_api.h"
19 #define ECORE_EMUL_FACTOR 2000
20 #define ECORE_FPGA_FACTOR 200
23 #define ECORE_BAR_ACQUIRE_TIMEOUT 1000
26 #define ECORE_BAR_INVALID_OFFSET (OSAL_CPU_TO_LE32(-1))
29 osal_list_entry_t list_entry;
31 struct pxp_ptt_entry pxp;
35 struct ecore_ptt_pool {
36 osal_list_t free_list;
37 osal_spinlock_t lock; /* ptt synchronized access */
38 struct ecore_ptt ptts[PXP_EXTERNAL_BAR_PF_WINDOW_NUM];
41 enum _ecore_status_t ecore_ptt_pool_alloc(struct ecore_hwfn *p_hwfn)
43 struct ecore_ptt_pool *p_pool = OSAL_ALLOC(p_hwfn->p_dev,
51 OSAL_LIST_INIT(&p_pool->free_list);
52 for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) {
53 p_pool->ptts[i].idx = i;
54 p_pool->ptts[i].pxp.offset = ECORE_BAR_INVALID_OFFSET;
55 p_pool->ptts[i].pxp.pretend.control = 0;
56 p_pool->ptts[i].hwfn_id = p_hwfn->my_id;
58 /* There are special PTT entries that are taken only by design.
59 * The rest are added ot the list for general usage.
61 if (i >= RESERVED_PTT_MAX)
62 OSAL_LIST_PUSH_HEAD(&p_pool->ptts[i].list_entry,
66 p_hwfn->p_ptt_pool = p_pool;
67 #ifdef CONFIG_ECORE_LOCK_ALLOC
68 OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_pool->lock);
70 OSAL_SPIN_LOCK_INIT(&p_pool->lock);
75 void ecore_ptt_invalidate(struct ecore_hwfn *p_hwfn)
77 struct ecore_ptt *p_ptt;
80 for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) {
81 p_ptt = &p_hwfn->p_ptt_pool->ptts[i];
82 p_ptt->pxp.offset = ECORE_BAR_INVALID_OFFSET;
86 void ecore_ptt_pool_free(struct ecore_hwfn *p_hwfn)
88 #ifdef CONFIG_ECORE_LOCK_ALLOC
89 if (p_hwfn->p_ptt_pool)
90 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->p_ptt_pool->lock);
92 OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_ptt_pool);
95 struct ecore_ptt *ecore_ptt_acquire(struct ecore_hwfn *p_hwfn)
97 struct ecore_ptt *p_ptt;
100 /* Take the free PTT from the list */
101 for (i = 0; i < ECORE_BAR_ACQUIRE_TIMEOUT; i++) {
102 OSAL_SPIN_LOCK(&p_hwfn->p_ptt_pool->lock);
103 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->p_ptt_pool->free_list)) {
104 p_ptt = OSAL_LIST_FIRST_ENTRY(
105 &p_hwfn->p_ptt_pool->free_list,
106 struct ecore_ptt, list_entry);
107 OSAL_LIST_REMOVE_ENTRY(&p_ptt->list_entry,
108 &p_hwfn->p_ptt_pool->free_list);
110 OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);
112 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
113 "allocated ptt %d\n", p_ptt->idx);
118 OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);
122 DP_NOTICE(p_hwfn, true,
123 "PTT acquire timeout - failed to allocate PTT\n");
127 void ecore_ptt_release(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
129 /* This PTT should not be set to pretend if it is being released */
130 /* TODO - add some pretend sanity checks, to make sure pretend
131 * isn't set on this ptt
134 OSAL_SPIN_LOCK(&p_hwfn->p_ptt_pool->lock);
135 OSAL_LIST_PUSH_HEAD(&p_ptt->list_entry, &p_hwfn->p_ptt_pool->free_list);
136 OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);
139 static u32 ecore_ptt_get_hw_addr(struct ecore_ptt *p_ptt)
141 /* The HW is using DWORDS and we need to translate it to Bytes */
142 return OSAL_LE32_TO_CPU(p_ptt->pxp.offset) << 2;
145 static u32 ecore_ptt_config_addr(struct ecore_ptt *p_ptt)
147 return PXP_PF_WINDOW_ADMIN_PER_PF_START +
148 p_ptt->idx * sizeof(struct pxp_ptt_entry);
151 u32 ecore_ptt_get_bar_addr(struct ecore_ptt *p_ptt)
153 return PXP_EXTERNAL_BAR_PF_WINDOW_START +
154 p_ptt->idx * PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE;
157 void ecore_ptt_set_win(struct ecore_hwfn *p_hwfn,
158 struct ecore_ptt *p_ptt, u32 new_hw_addr)
162 prev_hw_addr = ecore_ptt_get_hw_addr(p_ptt);
164 if (new_hw_addr == prev_hw_addr)
167 /* Update PTT entery in admin window */
168 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
169 "Updating PTT entry %d to offset 0x%x\n",
170 p_ptt->idx, new_hw_addr);
172 /* The HW is using DWORDS and the address is in Bytes */
173 p_ptt->pxp.offset = OSAL_CPU_TO_LE32(new_hw_addr >> 2);
176 ecore_ptt_config_addr(p_ptt) +
177 OFFSETOF(struct pxp_ptt_entry, offset),
178 OSAL_LE32_TO_CPU(p_ptt->pxp.offset));
181 static u32 ecore_set_ptt(struct ecore_hwfn *p_hwfn,
182 struct ecore_ptt *p_ptt, u32 hw_addr)
184 u32 win_hw_addr = ecore_ptt_get_hw_addr(p_ptt);
187 offset = hw_addr - win_hw_addr;
189 if (p_ptt->hwfn_id != p_hwfn->my_id)
190 DP_NOTICE(p_hwfn, true,
191 "ptt[%d] of hwfn[%02x] is used by hwfn[%02x]!\n",
192 p_ptt->idx, p_ptt->hwfn_id, p_hwfn->my_id);
194 /* Verify the address is within the window */
195 if (hw_addr < win_hw_addr ||
196 offset >= PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) {
197 ecore_ptt_set_win(p_hwfn, p_ptt, hw_addr);
201 return ecore_ptt_get_bar_addr(p_ptt) + offset;
204 struct ecore_ptt *ecore_get_reserved_ptt(struct ecore_hwfn *p_hwfn,
205 enum reserved_ptts ptt_idx)
207 if (ptt_idx >= RESERVED_PTT_MAX) {
208 DP_NOTICE(p_hwfn, true,
209 "Requested PTT %d is out of range\n", ptt_idx);
213 return &p_hwfn->p_ptt_pool->ptts[ptt_idx];
216 static bool ecore_is_reg_fifo_empty(struct ecore_hwfn *p_hwfn,
217 struct ecore_ptt *p_ptt)
219 bool is_empty = true;
222 if (!p_hwfn->p_dev->chk_reg_fifo)
225 /* ecore_rd() cannot be used here since it calls this function */
226 bar_addr = ecore_set_ptt(p_hwfn, p_ptt, GRC_REG_TRACE_FIFO_VALID_DATA);
227 is_empty = REG_RD(p_hwfn, bar_addr) == 0;
230 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
238 void ecore_wr(struct ecore_hwfn *p_hwfn,
239 struct ecore_ptt *p_ptt, u32 hw_addr, u32 val)
244 prev_fifo_err = !ecore_is_reg_fifo_empty(p_hwfn, p_ptt);
246 bar_addr = ecore_set_ptt(p_hwfn, p_ptt, hw_addr);
247 REG_WR(p_hwfn, bar_addr, val);
248 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
249 "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n",
250 bar_addr, hw_addr, val);
253 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
257 OSAL_WARN(!prev_fifo_err && !ecore_is_reg_fifo_empty(p_hwfn, p_ptt),
258 "reg_fifo err was caused by a call to ecore_wr(0x%x, 0x%x)\n",
262 u32 ecore_rd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 hw_addr)
267 prev_fifo_err = !ecore_is_reg_fifo_empty(p_hwfn, p_ptt);
269 bar_addr = ecore_set_ptt(p_hwfn, p_ptt, hw_addr);
270 val = REG_RD(p_hwfn, bar_addr);
272 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
273 "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n",
274 bar_addr, hw_addr, val);
277 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
281 OSAL_WARN(!prev_fifo_err && !ecore_is_reg_fifo_empty(p_hwfn, p_ptt),
282 "reg_fifo error was caused by a call to ecore_rd(0x%x)\n",
288 static void ecore_memcpy_hw(struct ecore_hwfn *p_hwfn,
289 struct ecore_ptt *p_ptt,
291 u32 hw_addr, osal_size_t n, bool to_device)
293 u32 dw_count, *host_addr, hw_offset;
294 osal_size_t quota, done = 0;
295 u32 OSAL_IOMEM *reg_addr;
298 quota = OSAL_MIN_T(osal_size_t, n - done,
299 PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE);
301 if (IS_PF(p_hwfn->p_dev)) {
302 ecore_ptt_set_win(p_hwfn, p_ptt, hw_addr + done);
303 hw_offset = ecore_ptt_get_bar_addr(p_ptt);
305 hw_offset = hw_addr + done;
308 dw_count = quota / 4;
309 host_addr = (u32 *)((u8 *)addr + done);
310 reg_addr = (u32 OSAL_IOMEM *)OSAL_REG_ADDR(p_hwfn, hw_offset);
314 DIRECT_REG_WR(p_hwfn, reg_addr++, *host_addr++);
317 *host_addr++ = DIRECT_REG_RD(p_hwfn,
324 void ecore_memcpy_from(struct ecore_hwfn *p_hwfn,
325 struct ecore_ptt *p_ptt,
326 void *dest, u32 hw_addr, osal_size_t n)
328 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
329 "hw_addr 0x%x, dest %p hw_addr 0x%x, size %lu\n",
330 hw_addr, dest, hw_addr, (unsigned long)n);
332 ecore_memcpy_hw(p_hwfn, p_ptt, dest, hw_addr, n, false);
335 void ecore_memcpy_to(struct ecore_hwfn *p_hwfn,
336 struct ecore_ptt *p_ptt,
337 u32 hw_addr, void *src, osal_size_t n)
339 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
340 "hw_addr 0x%x, hw_addr 0x%x, src %p size %lu\n",
341 hw_addr, hw_addr, src, (unsigned long)n);
343 ecore_memcpy_hw(p_hwfn, p_ptt, src, hw_addr, n, true);
346 void ecore_fid_pretend(struct ecore_hwfn *p_hwfn,
347 struct ecore_ptt *p_ptt, u16 fid)
351 SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1);
352 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1);
354 /* Every pretend undos prev pretends, including previous port pretend */
356 SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0);
357 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0);
358 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
360 if (!GET_FIELD(fid, PXP_CONCRETE_FID_VFVALID))
361 fid = GET_FIELD(fid, PXP_CONCRETE_FID_PFID);
363 p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
364 p_ptt->pxp.pretend.fid.concrete_fid.fid = OSAL_CPU_TO_LE16(fid);
367 ecore_ptt_config_addr(p_ptt) +
368 OFFSETOF(struct pxp_ptt_entry, pretend),
369 *(u32 *)&p_ptt->pxp.pretend);
372 void ecore_port_pretend(struct ecore_hwfn *p_hwfn,
373 struct ecore_ptt *p_ptt, u8 port_id)
377 SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id);
378 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1);
379 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
380 p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
383 ecore_ptt_config_addr(p_ptt) +
384 OFFSETOF(struct pxp_ptt_entry, pretend),
385 *(u32 *)&p_ptt->pxp.pretend);
388 void ecore_port_unpretend(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
392 SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0);
393 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0);
394 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
396 p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
399 ecore_ptt_config_addr(p_ptt) +
400 OFFSETOF(struct pxp_ptt_entry, pretend),
401 *(u32 *)&p_ptt->pxp.pretend);
404 u32 ecore_vfid_to_concrete(struct ecore_hwfn *p_hwfn, u8 vfid)
406 u32 concrete_fid = 0;
408 SET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID, p_hwfn->rel_pf_id);
409 SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID, vfid);
410 SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID, 1);
418 * Although the implementation is ready, today we don't have any flow that
419 * utliizes said locks - and we want to keep it this way.
420 * If this changes, this needs to be revisted.
426 static void ecore_dmae_opcode(struct ecore_hwfn *p_hwfn,
427 const u8 is_src_type_grc,
428 const u8 is_dst_type_grc,
429 struct ecore_dmae_params *p_params)
434 /* Whether the source is the PCIe or the GRC.
435 * 0- The source is the PCIe
436 * 1- The source is the GRC.
438 opcode |= (is_src_type_grc ? DMAE_CMD_SRC_MASK_GRC
439 : DMAE_CMD_SRC_MASK_PCIE) << DMAE_CMD_SRC_SHIFT;
440 opcode |= (p_hwfn->rel_pf_id & DMAE_CMD_SRC_PF_ID_MASK) <<
441 DMAE_CMD_SRC_PF_ID_SHIFT;
443 /* The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */
444 opcode |= (is_dst_type_grc ? DMAE_CMD_DST_MASK_GRC
445 : DMAE_CMD_DST_MASK_PCIE) << DMAE_CMD_DST_SHIFT;
446 opcode |= (p_hwfn->rel_pf_id & DMAE_CMD_DST_PF_ID_MASK) <<
447 DMAE_CMD_DST_PF_ID_SHIFT;
449 /* DMAE_E4_TODO need to check which value to specifiy here. */
450 /* opcode |= (!b_complete_to_host)<< DMAE_CMD_C_DST_SHIFT; */
452 /* Whether to write a completion word to the completion destination:
453 * 0-Do not write a completion word
454 * 1-Write the completion word
456 opcode |= DMAE_CMD_COMP_WORD_EN_MASK << DMAE_CMD_COMP_WORD_EN_SHIFT;
457 opcode |= DMAE_CMD_SRC_ADDR_RESET_MASK << DMAE_CMD_SRC_ADDR_RESET_SHIFT;
459 if (p_params->flags & ECORE_DMAE_FLAG_COMPLETION_DST)
460 opcode |= 1 << DMAE_CMD_COMP_FUNC_SHIFT;
462 /* swapping mode 3 - big endian there should be a define ifdefed in
463 * the HSI somewhere. Since it is currently
465 opcode |= DMAE_CMD_ENDIANITY << DMAE_CMD_ENDIANITY_MODE_SHIFT;
467 opcode |= p_hwfn->port_id << DMAE_CMD_PORT_ID_SHIFT;
469 /* reset source address in next go */
470 opcode |= DMAE_CMD_SRC_ADDR_RESET_MASK << DMAE_CMD_SRC_ADDR_RESET_SHIFT;
472 /* reset dest address in next go */
473 opcode |= DMAE_CMD_DST_ADDR_RESET_MASK << DMAE_CMD_DST_ADDR_RESET_SHIFT;
475 /* SRC/DST VFID: all 1's - pf, otherwise VF id */
476 if (p_params->flags & ECORE_DMAE_FLAG_VF_SRC) {
477 opcode |= (1 << DMAE_CMD_SRC_VF_ID_VALID_SHIFT);
478 opcode_b |= (p_params->src_vfid << DMAE_CMD_SRC_VF_ID_SHIFT);
480 opcode_b |= (DMAE_CMD_SRC_VF_ID_MASK <<
481 DMAE_CMD_SRC_VF_ID_SHIFT);
483 if (p_params->flags & ECORE_DMAE_FLAG_VF_DST) {
484 opcode |= 1 << DMAE_CMD_DST_VF_ID_VALID_SHIFT;
485 opcode_b |= p_params->dst_vfid << DMAE_CMD_DST_VF_ID_SHIFT;
487 opcode_b |= DMAE_CMD_DST_VF_ID_MASK << DMAE_CMD_DST_VF_ID_SHIFT;
490 p_hwfn->dmae_info.p_dmae_cmd->opcode = OSAL_CPU_TO_LE32(opcode);
491 p_hwfn->dmae_info.p_dmae_cmd->opcode_b = OSAL_CPU_TO_LE16(opcode_b);
494 static u32 ecore_dmae_idx_to_go_cmd(u8 idx)
496 OSAL_BUILD_BUG_ON((DMAE_REG_GO_C31 - DMAE_REG_GO_C0) != 31 * 4);
498 /* All the DMAE 'go' registers form an array in internal memory */
499 return DMAE_REG_GO_C0 + (idx << 2);
502 static enum _ecore_status_t ecore_dmae_post_command(struct ecore_hwfn *p_hwfn,
503 struct ecore_ptt *p_ptt)
505 struct dmae_cmd *p_command = p_hwfn->dmae_info.p_dmae_cmd;
506 u8 idx_cmd = p_hwfn->dmae_info.channel, i;
507 enum _ecore_status_t ecore_status = ECORE_SUCCESS;
509 /* verify address is not OSAL_NULL */
510 if ((((!p_command->dst_addr_lo) && (!p_command->dst_addr_hi)) ||
511 ((!p_command->src_addr_lo) && (!p_command->src_addr_hi)))) {
512 DP_NOTICE(p_hwfn, true,
513 "source or destination address 0 idx_cmd=%d\n"
514 "opcode = [0x%08x,0x%04x] len=0x%x"
515 " src=0x%x:%x dst=0x%x:%x\n",
517 OSAL_LE32_TO_CPU(p_command->opcode),
518 OSAL_LE16_TO_CPU(p_command->opcode_b),
519 OSAL_LE16_TO_CPU(p_command->length_dw),
520 OSAL_LE32_TO_CPU(p_command->src_addr_hi),
521 OSAL_LE32_TO_CPU(p_command->src_addr_lo),
522 OSAL_LE32_TO_CPU(p_command->dst_addr_hi),
523 OSAL_LE32_TO_CPU(p_command->dst_addr_lo));
528 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
529 "Posting DMAE command [idx %d]: opcode = [0x%08x,0x%04x]"
530 "len=0x%x src=0x%x:%x dst=0x%x:%x\n",
532 OSAL_LE32_TO_CPU(p_command->opcode),
533 OSAL_LE16_TO_CPU(p_command->opcode_b),
534 OSAL_LE16_TO_CPU(p_command->length_dw),
535 OSAL_LE32_TO_CPU(p_command->src_addr_hi),
536 OSAL_LE32_TO_CPU(p_command->src_addr_lo),
537 OSAL_LE32_TO_CPU(p_command->dst_addr_hi),
538 OSAL_LE32_TO_CPU(p_command->dst_addr_lo));
540 /* Copy the command to DMAE - need to do it before every call
541 * for source/dest address no reset.
542 * The number of commands have been increased to 16 (previous was 14)
543 * The first 9 DWs are the command registers, the 10 DW is the
545 * the rest are result registers (which are read only by the client).
547 for (i = 0; i < DMAE_CMD_SIZE; i++) {
548 u32 data = (i < DMAE_CMD_SIZE_TO_FILL) ?
549 *(((u32 *)p_command) + i) : 0;
551 ecore_wr(p_hwfn, p_ptt,
553 (idx_cmd * DMAE_CMD_SIZE * sizeof(u32)) +
554 (i * sizeof(u32)), data);
557 ecore_wr(p_hwfn, p_ptt,
558 ecore_dmae_idx_to_go_cmd(idx_cmd), DMAE_GO_VALUE);
563 enum _ecore_status_t ecore_dmae_info_alloc(struct ecore_hwfn *p_hwfn)
565 dma_addr_t *p_addr = &p_hwfn->dmae_info.completion_word_phys_addr;
566 struct dmae_cmd **p_cmd = &p_hwfn->dmae_info.p_dmae_cmd;
567 u32 **p_buff = &p_hwfn->dmae_info.p_intermediate_buffer;
568 u32 **p_comp = &p_hwfn->dmae_info.p_completion_word;
570 *p_comp = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, p_addr, sizeof(u32));
571 if (*p_comp == OSAL_NULL) {
572 DP_NOTICE(p_hwfn, true,
573 "Failed to allocate `p_completion_word'\n");
577 p_addr = &p_hwfn->dmae_info.dmae_cmd_phys_addr;
578 *p_cmd = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, p_addr,
579 sizeof(struct dmae_cmd));
580 if (*p_cmd == OSAL_NULL) {
581 DP_NOTICE(p_hwfn, true,
582 "Failed to allocate `struct dmae_cmd'\n");
586 p_addr = &p_hwfn->dmae_info.intermediate_buffer_phys_addr;
587 *p_buff = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, p_addr,
588 sizeof(u32) * DMAE_MAX_RW_SIZE);
589 if (*p_buff == OSAL_NULL) {
590 DP_NOTICE(p_hwfn, true,
591 "Failed to allocate `intermediate_buffer'\n");
595 p_hwfn->dmae_info.channel = p_hwfn->rel_pf_id;
596 p_hwfn->dmae_info.b_mem_ready = true;
598 return ECORE_SUCCESS;
600 ecore_dmae_info_free(p_hwfn);
604 void ecore_dmae_info_free(struct ecore_hwfn *p_hwfn)
608 OSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);
609 p_hwfn->dmae_info.b_mem_ready = false;
610 OSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);
612 if (p_hwfn->dmae_info.p_completion_word != OSAL_NULL) {
613 p_phys = p_hwfn->dmae_info.completion_word_phys_addr;
614 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
615 p_hwfn->dmae_info.p_completion_word,
616 p_phys, sizeof(u32));
617 p_hwfn->dmae_info.p_completion_word = OSAL_NULL;
620 if (p_hwfn->dmae_info.p_dmae_cmd != OSAL_NULL) {
621 p_phys = p_hwfn->dmae_info.dmae_cmd_phys_addr;
622 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
623 p_hwfn->dmae_info.p_dmae_cmd,
624 p_phys, sizeof(struct dmae_cmd));
625 p_hwfn->dmae_info.p_dmae_cmd = OSAL_NULL;
628 if (p_hwfn->dmae_info.p_intermediate_buffer != OSAL_NULL) {
629 p_phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr;
630 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
631 p_hwfn->dmae_info.p_intermediate_buffer,
632 p_phys, sizeof(u32) * DMAE_MAX_RW_SIZE);
633 p_hwfn->dmae_info.p_intermediate_buffer = OSAL_NULL;
637 static enum _ecore_status_t ecore_dmae_operation_wait(struct ecore_hwfn *p_hwfn)
639 u32 wait_cnt_limit = 10000, wait_cnt = 0;
640 enum _ecore_status_t ecore_status = ECORE_SUCCESS;
643 u32 factor = (CHIP_REV_IS_EMUL(p_hwfn->p_dev) ?
645 (CHIP_REV_IS_FPGA(p_hwfn->p_dev) ?
646 ECORE_FPGA_FACTOR : 1));
648 wait_cnt_limit *= factor;
651 /* DMAE_E4_TODO : TODO check if we have to call any other function
652 * other than BARRIER to sync the completion_word since we are not
653 * using the volatile keyword for this
655 OSAL_BARRIER(p_hwfn->p_dev);
656 while (*p_hwfn->dmae_info.p_completion_word != DMAE_COMPLETION_VAL) {
657 OSAL_UDELAY(DMAE_MIN_WAIT_TIME);
658 if (++wait_cnt > wait_cnt_limit) {
659 DP_NOTICE(p_hwfn->p_dev, ECORE_MSG_HW,
660 "Timed-out waiting for operation to"
661 " complete. Completion word is 0x%08x"
662 " expected 0x%08x.\n",
663 *p_hwfn->dmae_info.p_completion_word,
664 DMAE_COMPLETION_VAL);
665 ecore_status = ECORE_TIMEOUT;
668 /* to sync the completion_word since we are not
669 * using the volatile keyword for p_completion_word
671 OSAL_BARRIER(p_hwfn->p_dev);
674 if (ecore_status == ECORE_SUCCESS)
675 *p_hwfn->dmae_info.p_completion_word = 0;
680 static enum _ecore_status_t
681 ecore_dmae_execute_sub_operation(struct ecore_hwfn *p_hwfn,
682 struct ecore_ptt *p_ptt,
685 u8 src_type, u8 dst_type, u32 length_dw)
687 dma_addr_t phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr;
688 struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd;
689 enum _ecore_status_t ecore_status = ECORE_SUCCESS;
692 case ECORE_DMAE_ADDRESS_GRC:
693 case ECORE_DMAE_ADDRESS_HOST_PHYS:
694 cmd->src_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(src_addr));
695 cmd->src_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(src_addr));
697 /* for virt source addresses we use the intermediate buffer. */
698 case ECORE_DMAE_ADDRESS_HOST_VIRT:
699 cmd->src_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(phys));
700 cmd->src_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(phys));
701 OSAL_MEMCPY(&p_hwfn->dmae_info.p_intermediate_buffer[0],
702 (void *)(osal_uintptr_t)src_addr,
703 length_dw * sizeof(u32));
710 case ECORE_DMAE_ADDRESS_GRC:
711 case ECORE_DMAE_ADDRESS_HOST_PHYS:
712 cmd->dst_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(dst_addr));
713 cmd->dst_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(dst_addr));
715 /* for virt destination address we use the intermediate buff. */
716 case ECORE_DMAE_ADDRESS_HOST_VIRT:
717 cmd->dst_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(phys));
718 cmd->dst_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(phys));
724 cmd->length_dw = OSAL_CPU_TO_LE16((u16)length_dw);
726 if (src_type == ECORE_DMAE_ADDRESS_HOST_VIRT ||
727 src_type == ECORE_DMAE_ADDRESS_HOST_PHYS)
728 OSAL_DMA_SYNC(p_hwfn->p_dev,
729 (void *)HILO_U64(cmd->src_addr_hi,
731 length_dw * sizeof(u32), false);
733 ecore_dmae_post_command(p_hwfn, p_ptt);
735 ecore_status = ecore_dmae_operation_wait(p_hwfn);
737 /* TODO - is it true ? */
738 if (src_type == ECORE_DMAE_ADDRESS_HOST_VIRT ||
739 src_type == ECORE_DMAE_ADDRESS_HOST_PHYS)
740 OSAL_DMA_SYNC(p_hwfn->p_dev,
741 (void *)HILO_U64(cmd->src_addr_hi,
743 length_dw * sizeof(u32), true);
745 if (ecore_status != ECORE_SUCCESS) {
746 DP_NOTICE(p_hwfn, ECORE_MSG_HW,
747 "Wait Failed. source_addr 0x%lx, grc_addr 0x%lx, size_in_dwords 0x%x, intermediate buffer 0x%lx.\n",
748 (unsigned long)src_addr, (unsigned long)dst_addr,
750 (unsigned long)p_hwfn->dmae_info.intermediate_buffer_phys_addr);
754 if (dst_type == ECORE_DMAE_ADDRESS_HOST_VIRT)
755 OSAL_MEMCPY((void *)(osal_uintptr_t)(dst_addr),
756 &p_hwfn->dmae_info.p_intermediate_buffer[0],
757 length_dw * sizeof(u32));
759 return ECORE_SUCCESS;
762 static enum _ecore_status_t
763 ecore_dmae_execute_command(struct ecore_hwfn *p_hwfn,
764 struct ecore_ptt *p_ptt,
770 struct ecore_dmae_params *p_params)
772 dma_addr_t phys = p_hwfn->dmae_info.completion_word_phys_addr;
773 u16 length_cur = 0, i = 0, cnt_split = 0, length_mod = 0;
774 struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd;
775 u64 src_addr_split = 0, dst_addr_split = 0;
776 u16 length_limit = DMAE_MAX_RW_SIZE;
777 enum _ecore_status_t ecore_status = ECORE_SUCCESS;
780 if (!p_hwfn->dmae_info.b_mem_ready) {
781 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
782 "No buffers allocated. Avoid DMAE transaction [{src: addr 0x%lx, type %d}, {dst: addr 0x%lx, type %d}, size %d].\n",
783 (unsigned long)src_addr, src_type,
784 (unsigned long)dst_addr, dst_type,
789 if (p_hwfn->p_dev->recov_in_prog) {
790 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
791 "Recovery is in progress. Avoid DMAE transaction [{src: addr 0x%lx, type %d}, {dst: addr 0x%lx, type %d}, size %d].\n",
792 (unsigned long)src_addr, src_type,
793 (unsigned long)dst_addr, dst_type,
795 /* Return success to let the flow to be completed successfully
796 * w/o any error handling.
798 return ECORE_SUCCESS;
802 DP_NOTICE(p_hwfn, true,
803 "ecore_dmae_execute_sub_operation failed. Invalid state. source_addr 0x%lx, destination addr 0x%lx, size_in_dwords 0x%x\n",
804 (unsigned long)src_addr,
805 (unsigned long)dst_addr,
810 ecore_dmae_opcode(p_hwfn,
811 (src_type == ECORE_DMAE_ADDRESS_GRC),
812 (dst_type == ECORE_DMAE_ADDRESS_GRC), p_params);
814 cmd->comp_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(phys));
815 cmd->comp_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(phys));
816 cmd->comp_val = OSAL_CPU_TO_LE32(DMAE_COMPLETION_VAL);
818 /* Check if the grc_addr is valid like < MAX_GRC_OFFSET */
819 cnt_split = size_in_dwords / length_limit;
820 length_mod = size_in_dwords % length_limit;
822 src_addr_split = src_addr;
823 dst_addr_split = dst_addr;
825 for (i = 0; i <= cnt_split; i++) {
826 offset = length_limit * i;
828 if (!(p_params->flags & ECORE_DMAE_FLAG_RW_REPL_SRC)) {
829 if (src_type == ECORE_DMAE_ADDRESS_GRC)
830 src_addr_split = src_addr + offset;
832 src_addr_split = src_addr + (offset * 4);
835 if (dst_type == ECORE_DMAE_ADDRESS_GRC)
836 dst_addr_split = dst_addr + offset;
838 dst_addr_split = dst_addr + (offset * 4);
840 length_cur = (cnt_split == i) ? length_mod : length_limit;
842 /* might be zero on last iteration */
846 ecore_status = ecore_dmae_execute_sub_operation(p_hwfn,
853 if (ecore_status != ECORE_SUCCESS) {
854 DP_NOTICE(p_hwfn, false,
855 "ecore_dmae_execute_sub_operation Failed"
856 " with error 0x%x. source_addr 0x%lx,"
857 " dest addr 0x%lx, size_in_dwords 0x%x\n",
858 ecore_status, (unsigned long)src_addr,
859 (unsigned long)dst_addr, length_cur);
861 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_DMAE_FAIL);
870 ecore_dmae_host2grc(struct ecore_hwfn *p_hwfn,
871 struct ecore_ptt *p_ptt,
873 u32 grc_addr, u32 size_in_dwords, u32 flags)
875 u32 grc_addr_in_dw = grc_addr / sizeof(u32);
876 struct ecore_dmae_params params;
877 enum _ecore_status_t rc;
879 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_dmae_params));
880 params.flags = flags;
882 OSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);
884 rc = ecore_dmae_execute_command(p_hwfn, p_ptt, source_addr,
886 ECORE_DMAE_ADDRESS_HOST_VIRT,
887 ECORE_DMAE_ADDRESS_GRC,
888 size_in_dwords, ¶ms);
890 OSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);
896 ecore_dmae_grc2host(struct ecore_hwfn *p_hwfn,
897 struct ecore_ptt *p_ptt,
899 dma_addr_t dest_addr, u32 size_in_dwords, u32 flags)
901 u32 grc_addr_in_dw = grc_addr / sizeof(u32);
902 struct ecore_dmae_params params;
903 enum _ecore_status_t rc;
905 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_dmae_params));
906 params.flags = flags;
908 OSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);
910 rc = ecore_dmae_execute_command(p_hwfn, p_ptt, grc_addr_in_dw,
911 dest_addr, ECORE_DMAE_ADDRESS_GRC,
912 ECORE_DMAE_ADDRESS_HOST_VIRT,
913 size_in_dwords, ¶ms);
915 OSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);
921 ecore_dmae_host2host(struct ecore_hwfn *p_hwfn,
922 struct ecore_ptt *p_ptt,
923 dma_addr_t source_addr,
924 dma_addr_t dest_addr,
925 u32 size_in_dwords, struct ecore_dmae_params *p_params)
927 enum _ecore_status_t rc;
929 OSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);
931 rc = ecore_dmae_execute_command(p_hwfn, p_ptt, source_addr,
933 ECORE_DMAE_ADDRESS_HOST_PHYS,
934 ECORE_DMAE_ADDRESS_HOST_PHYS,
935 size_in_dwords, p_params);
937 OSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);
942 void ecore_hw_err_notify(struct ecore_hwfn *p_hwfn,
943 enum ecore_hw_err_type err_type)
945 /* Fan failure cannot be masked by handling of another HW error */
946 if (p_hwfn->p_dev->recov_in_prog && err_type != ECORE_HW_ERR_FAN_FAIL) {
947 DP_VERBOSE(p_hwfn, ECORE_MSG_DRV,
948 "Recovery is in progress."
949 "Avoid notifying about HW error %d.\n",
954 OSAL_HW_ERROR_OCCURRED(p_hwfn, err_type);
957 enum _ecore_status_t ecore_dmae_sanity(struct ecore_hwfn *p_hwfn,
958 struct ecore_ptt *p_ptt,
961 u32 size = OSAL_PAGE_SIZE / 2, val;
962 struct ecore_dmae_params params;
963 enum _ecore_status_t rc = ECORE_SUCCESS;
968 p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, &p_phys, 2 * size);
970 DP_NOTICE(p_hwfn, false,
971 "DMAE sanity [%s]: failed to allocate memory\n",
976 /* Fill the bottom half of the allocated memory with a known pattern */
977 for (p_tmp = (u32 *)p_virt;
978 p_tmp < (u32 *)((u8 *)p_virt + size);
980 /* Save the address itself as the value */
981 val = (u32)(osal_uintptr_t)p_tmp;
985 /* Zero the top half of the allocated memory */
986 OSAL_MEM_ZERO((u8 *)p_virt + size, size);
988 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
989 "DMAE sanity [%s]: src_addr={phys 0x%lx, virt %p}, dst_addr={phys 0x%lx, virt %p}, size 0x%x\n",
990 phase, (unsigned long)p_phys, p_virt,
991 (unsigned long)(p_phys + size),
992 (u8 *)p_virt + size, size);
994 OSAL_MEMSET(¶ms, 0, sizeof(params));
995 rc = ecore_dmae_host2host(p_hwfn, p_ptt, p_phys, p_phys + size,
996 size / 4 /* size_in_dwords */, ¶ms);
997 if (rc != ECORE_SUCCESS) {
998 DP_NOTICE(p_hwfn, false,
999 "DMAE sanity [%s]: ecore_dmae_host2host() failed. rc = %d.\n",
1004 /* Verify that the top half of the allocated memory has the pattern */
1005 for (p_tmp = (u32 *)((u8 *)p_virt + size);
1006 p_tmp < (u32 *)((u8 *)p_virt + (2 * size));
1008 /* The corresponding address in the bottom half */
1009 val = (u32)(osal_uintptr_t)p_tmp - size;
1011 if (*p_tmp != val) {
1012 DP_NOTICE(p_hwfn, false,
1013 "DMAE sanity [%s]: addr={phys 0x%lx, virt %p}, read_val 0x%08x, expected_val 0x%08x\n",
1015 (unsigned long)p_phys +
1016 ((u8 *)p_tmp - (u8 *)p_virt),
1017 p_tmp, *p_tmp, val);
1018 rc = ECORE_UNKNOWN_ERROR;
1024 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, p_virt, p_phys, 2 * size);