1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
8 #include "ecore_hsi_common.h"
9 #include "ecore_status.h"
13 #include "ecore_utils.h"
14 #include "ecore_iov_api.h"
17 #define ECORE_EMUL_FACTOR 2000
18 #define ECORE_FPGA_FACTOR 200
21 #define ECORE_BAR_ACQUIRE_TIMEOUT 1000
24 #define ECORE_BAR_INVALID_OFFSET (OSAL_CPU_TO_LE32(-1))
27 osal_list_entry_t list_entry;
29 struct pxp_ptt_entry pxp;
33 struct ecore_ptt_pool {
34 osal_list_t free_list;
35 osal_spinlock_t lock; /* ptt synchronized access */
36 struct ecore_ptt ptts[PXP_EXTERNAL_BAR_PF_WINDOW_NUM];
39 void __ecore_ptt_pool_free(struct ecore_hwfn *p_hwfn)
41 OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_ptt_pool);
42 p_hwfn->p_ptt_pool = OSAL_NULL;
45 enum _ecore_status_t ecore_ptt_pool_alloc(struct ecore_hwfn *p_hwfn)
47 struct ecore_ptt_pool *p_pool = OSAL_ALLOC(p_hwfn->p_dev,
55 OSAL_LIST_INIT(&p_pool->free_list);
56 for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) {
57 p_pool->ptts[i].idx = i;
58 p_pool->ptts[i].pxp.offset = ECORE_BAR_INVALID_OFFSET;
59 p_pool->ptts[i].pxp.pretend.control = 0;
60 p_pool->ptts[i].hwfn_id = p_hwfn->my_id;
62 /* There are special PTT entries that are taken only by design.
63 * The rest are added ot the list for general usage.
65 if (i >= RESERVED_PTT_MAX)
66 OSAL_LIST_PUSH_HEAD(&p_pool->ptts[i].list_entry,
70 p_hwfn->p_ptt_pool = p_pool;
71 #ifdef CONFIG_ECORE_LOCK_ALLOC
72 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_pool->lock)) {
73 __ecore_ptt_pool_free(p_hwfn);
77 OSAL_SPIN_LOCK_INIT(&p_pool->lock);
81 void ecore_ptt_invalidate(struct ecore_hwfn *p_hwfn)
83 struct ecore_ptt *p_ptt;
86 for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) {
87 p_ptt = &p_hwfn->p_ptt_pool->ptts[i];
88 p_ptt->pxp.offset = ECORE_BAR_INVALID_OFFSET;
92 void ecore_ptt_pool_free(struct ecore_hwfn *p_hwfn)
94 #ifdef CONFIG_ECORE_LOCK_ALLOC
95 if (p_hwfn->p_ptt_pool)
96 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->p_ptt_pool->lock);
98 __ecore_ptt_pool_free(p_hwfn);
101 struct ecore_ptt *ecore_ptt_acquire(struct ecore_hwfn *p_hwfn)
103 struct ecore_ptt *p_ptt;
106 /* Take the free PTT from the list */
107 for (i = 0; i < ECORE_BAR_ACQUIRE_TIMEOUT; i++) {
108 OSAL_SPIN_LOCK(&p_hwfn->p_ptt_pool->lock);
109 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->p_ptt_pool->free_list)) {
110 p_ptt = OSAL_LIST_FIRST_ENTRY(
111 &p_hwfn->p_ptt_pool->free_list,
112 struct ecore_ptt, list_entry);
113 OSAL_LIST_REMOVE_ENTRY(&p_ptt->list_entry,
114 &p_hwfn->p_ptt_pool->free_list);
116 OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);
118 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
119 "allocated ptt %d\n", p_ptt->idx);
124 OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);
128 DP_NOTICE(p_hwfn, true,
129 "PTT acquire timeout - failed to allocate PTT\n");
133 void ecore_ptt_release(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
135 /* This PTT should not be set to pretend if it is being released */
136 /* TODO - add some pretend sanity checks, to make sure pretend
137 * isn't set on this ptt
140 OSAL_SPIN_LOCK(&p_hwfn->p_ptt_pool->lock);
141 OSAL_LIST_PUSH_HEAD(&p_ptt->list_entry, &p_hwfn->p_ptt_pool->free_list);
142 OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);
145 static u32 ecore_ptt_get_hw_addr(struct ecore_ptt *p_ptt)
147 /* The HW is using DWORDS and we need to translate it to Bytes */
148 return OSAL_LE32_TO_CPU(p_ptt->pxp.offset) << 2;
151 static u32 ecore_ptt_config_addr(struct ecore_ptt *p_ptt)
153 return PXP_PF_WINDOW_ADMIN_PER_PF_START +
154 p_ptt->idx * sizeof(struct pxp_ptt_entry);
157 u32 ecore_ptt_get_bar_addr(struct ecore_ptt *p_ptt)
159 return PXP_EXTERNAL_BAR_PF_WINDOW_START +
160 p_ptt->idx * PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE;
163 void ecore_ptt_set_win(struct ecore_hwfn *p_hwfn,
164 struct ecore_ptt *p_ptt, u32 new_hw_addr)
168 prev_hw_addr = ecore_ptt_get_hw_addr(p_ptt);
170 if (new_hw_addr == prev_hw_addr)
173 /* Update PTT entery in admin window */
174 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
175 "Updating PTT entry %d to offset 0x%x\n",
176 p_ptt->idx, new_hw_addr);
178 /* The HW is using DWORDS and the address is in Bytes */
179 p_ptt->pxp.offset = OSAL_CPU_TO_LE32(new_hw_addr >> 2);
182 ecore_ptt_config_addr(p_ptt) +
183 OFFSETOF(struct pxp_ptt_entry, offset),
184 OSAL_LE32_TO_CPU(p_ptt->pxp.offset));
187 static u32 ecore_set_ptt(struct ecore_hwfn *p_hwfn,
188 struct ecore_ptt *p_ptt, u32 hw_addr)
190 u32 win_hw_addr = ecore_ptt_get_hw_addr(p_ptt);
193 offset = hw_addr - win_hw_addr;
195 if (p_ptt->hwfn_id != p_hwfn->my_id)
196 DP_NOTICE(p_hwfn, true,
197 "ptt[%d] of hwfn[%02x] is used by hwfn[%02x]!\n",
198 p_ptt->idx, p_ptt->hwfn_id, p_hwfn->my_id);
200 /* Verify the address is within the window */
201 if (hw_addr < win_hw_addr ||
202 offset >= PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) {
203 ecore_ptt_set_win(p_hwfn, p_ptt, hw_addr);
207 return ecore_ptt_get_bar_addr(p_ptt) + offset;
210 struct ecore_ptt *ecore_get_reserved_ptt(struct ecore_hwfn *p_hwfn,
211 enum reserved_ptts ptt_idx)
213 if (ptt_idx >= RESERVED_PTT_MAX) {
214 DP_NOTICE(p_hwfn, true,
215 "Requested PTT %d is out of range\n", ptt_idx);
219 return &p_hwfn->p_ptt_pool->ptts[ptt_idx];
222 static bool ecore_is_reg_fifo_empty(struct ecore_hwfn *p_hwfn,
223 struct ecore_ptt *p_ptt)
225 bool is_empty = true;
228 if (!p_hwfn->p_dev->chk_reg_fifo)
231 /* ecore_rd() cannot be used here since it calls this function */
232 bar_addr = ecore_set_ptt(p_hwfn, p_ptt, GRC_REG_TRACE_FIFO_VALID_DATA);
233 is_empty = REG_RD(p_hwfn, bar_addr) == 0;
236 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
244 void ecore_wr(struct ecore_hwfn *p_hwfn,
245 struct ecore_ptt *p_ptt, u32 hw_addr, u32 val)
250 prev_fifo_err = !ecore_is_reg_fifo_empty(p_hwfn, p_ptt);
252 bar_addr = ecore_set_ptt(p_hwfn, p_ptt, hw_addr);
253 REG_WR(p_hwfn, bar_addr, val);
254 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
255 "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n",
256 bar_addr, hw_addr, val);
259 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
263 OSAL_WARN(!prev_fifo_err && !ecore_is_reg_fifo_empty(p_hwfn, p_ptt),
264 "reg_fifo err was caused by a call to ecore_wr(0x%x, 0x%x)\n",
268 u32 ecore_rd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 hw_addr)
273 prev_fifo_err = !ecore_is_reg_fifo_empty(p_hwfn, p_ptt);
275 bar_addr = ecore_set_ptt(p_hwfn, p_ptt, hw_addr);
276 val = REG_RD(p_hwfn, bar_addr);
278 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
279 "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n",
280 bar_addr, hw_addr, val);
283 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
287 OSAL_WARN(!prev_fifo_err && !ecore_is_reg_fifo_empty(p_hwfn, p_ptt),
288 "reg_fifo error was caused by a call to ecore_rd(0x%x)\n",
294 static void ecore_memcpy_hw(struct ecore_hwfn *p_hwfn,
295 struct ecore_ptt *p_ptt,
297 u32 hw_addr, osal_size_t n, bool to_device)
299 u32 dw_count, *host_addr, hw_offset;
300 osal_size_t quota, done = 0;
301 u32 OSAL_IOMEM *reg_addr;
304 quota = OSAL_MIN_T(osal_size_t, n - done,
305 PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE);
307 if (IS_PF(p_hwfn->p_dev)) {
308 ecore_ptt_set_win(p_hwfn, p_ptt, hw_addr + done);
309 hw_offset = ecore_ptt_get_bar_addr(p_ptt);
311 hw_offset = hw_addr + done;
314 dw_count = quota / 4;
315 host_addr = (u32 *)((u8 *)addr + done);
316 reg_addr = (u32 OSAL_IOMEM *)OSAL_REG_ADDR(p_hwfn, hw_offset);
320 DIRECT_REG_WR(p_hwfn, reg_addr++, *host_addr++);
323 *host_addr++ = DIRECT_REG_RD(p_hwfn,
330 void ecore_memcpy_from(struct ecore_hwfn *p_hwfn,
331 struct ecore_ptt *p_ptt,
332 void *dest, u32 hw_addr, osal_size_t n)
334 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
335 "hw_addr 0x%x, dest %p hw_addr 0x%x, size %lu\n",
336 hw_addr, dest, hw_addr, (unsigned long)n);
338 ecore_memcpy_hw(p_hwfn, p_ptt, dest, hw_addr, n, false);
341 void ecore_memcpy_to(struct ecore_hwfn *p_hwfn,
342 struct ecore_ptt *p_ptt,
343 u32 hw_addr, void *src, osal_size_t n)
345 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
346 "hw_addr 0x%x, hw_addr 0x%x, src %p size %lu\n",
347 hw_addr, hw_addr, src, (unsigned long)n);
349 ecore_memcpy_hw(p_hwfn, p_ptt, src, hw_addr, n, true);
352 void ecore_fid_pretend(struct ecore_hwfn *p_hwfn,
353 struct ecore_ptt *p_ptt, u16 fid)
357 SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1);
358 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1);
360 /* Every pretend undos prev pretends, including previous port pretend */
362 SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0);
363 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0);
364 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
366 if (!GET_FIELD(fid, PXP_CONCRETE_FID_VFVALID))
367 fid = GET_FIELD(fid, PXP_CONCRETE_FID_PFID);
369 p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
370 p_ptt->pxp.pretend.fid.concrete_fid.fid = OSAL_CPU_TO_LE16(fid);
373 ecore_ptt_config_addr(p_ptt) +
374 OFFSETOF(struct pxp_ptt_entry, pretend),
375 *(u32 *)&p_ptt->pxp.pretend);
378 void ecore_port_pretend(struct ecore_hwfn *p_hwfn,
379 struct ecore_ptt *p_ptt, u8 port_id)
383 SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id);
384 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1);
385 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
386 p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
389 ecore_ptt_config_addr(p_ptt) +
390 OFFSETOF(struct pxp_ptt_entry, pretend),
391 *(u32 *)&p_ptt->pxp.pretend);
394 void ecore_port_unpretend(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
398 SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0);
399 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0);
400 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
402 p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
405 ecore_ptt_config_addr(p_ptt) +
406 OFFSETOF(struct pxp_ptt_entry, pretend),
407 *(u32 *)&p_ptt->pxp.pretend);
410 void ecore_port_fid_pretend(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
415 SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id);
416 SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1);
417 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
419 SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1);
420 SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1);
422 if (!GET_FIELD(fid, PXP_CONCRETE_FID_VFVALID))
423 fid = GET_FIELD(fid, PXP_CONCRETE_FID_PFID);
425 p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
426 p_ptt->pxp.pretend.fid.concrete_fid.fid = OSAL_CPU_TO_LE16(fid);
429 ecore_ptt_config_addr(p_ptt) +
430 OFFSETOF(struct pxp_ptt_entry, pretend),
431 *(u32 *)&p_ptt->pxp.pretend);
434 u32 ecore_vfid_to_concrete(struct ecore_hwfn *p_hwfn, u8 vfid)
436 u32 concrete_fid = 0;
438 SET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID, p_hwfn->rel_pf_id);
439 SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID, vfid);
440 SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID, 1);
448 * Although the implementation is ready, today we don't have any flow that
449 * utliizes said locks - and we want to keep it this way.
450 * If this changes, this needs to be revisted.
455 #define ECORE_DMAE_FLAGS_IS_SET(params, flag) \
456 ((params) != OSAL_NULL && \
457 GET_FIELD((params)->flags, DMAE_PARAMS_##flag))
459 static void ecore_dmae_opcode(struct ecore_hwfn *p_hwfn,
460 const u8 is_src_type_grc,
461 const u8 is_dst_type_grc,
462 struct dmae_params *p_params)
464 u8 src_pf_id, dst_pf_id, port_id;
468 /* Whether the source is the PCIe or the GRC.
469 * 0- The source is the PCIe
470 * 1- The source is the GRC.
472 opcode |= (is_src_type_grc ? dmae_cmd_src_grc : dmae_cmd_src_pcie) <<
474 src_pf_id = ECORE_DMAE_FLAGS_IS_SET(p_params, SRC_PF_VALID) ?
475 p_params->src_pf_id : p_hwfn->rel_pf_id;
476 opcode |= (src_pf_id & DMAE_CMD_SRC_PF_ID_MASK) <<
477 DMAE_CMD_SRC_PF_ID_SHIFT;
479 /* The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */
480 opcode |= (is_dst_type_grc ? dmae_cmd_dst_grc : dmae_cmd_dst_pcie) <<
482 dst_pf_id = ECORE_DMAE_FLAGS_IS_SET(p_params, DST_PF_VALID) ?
483 p_params->dst_pf_id : p_hwfn->rel_pf_id;
484 opcode |= (dst_pf_id & DMAE_CMD_DST_PF_ID_MASK) <<
485 DMAE_CMD_DST_PF_ID_SHIFT;
487 /* DMAE_E4_TODO need to check which value to specify here. */
488 /* opcode |= (!b_complete_to_host)<< DMAE_CMD_C_DST_SHIFT; */
490 /* Whether to write a completion word to the completion destination:
491 * 0-Do not write a completion word
492 * 1-Write the completion word
494 opcode |= DMAE_CMD_COMP_WORD_EN_MASK << DMAE_CMD_COMP_WORD_EN_SHIFT;
495 opcode |= DMAE_CMD_SRC_ADDR_RESET_MASK << DMAE_CMD_SRC_ADDR_RESET_SHIFT;
497 if (ECORE_DMAE_FLAGS_IS_SET(p_params, COMPLETION_DST))
498 opcode |= 1 << DMAE_CMD_COMP_FUNC_SHIFT;
500 /* swapping mode 3 - big endian there should be a define ifdefed in
501 * the HSI somewhere. Since it is currently
503 opcode |= DMAE_CMD_ENDIANITY << DMAE_CMD_ENDIANITY_MODE_SHIFT;
505 port_id = (ECORE_DMAE_FLAGS_IS_SET(p_params, PORT_VALID)) ?
506 p_params->port_id : p_hwfn->port_id;
507 opcode |= port_id << DMAE_CMD_PORT_ID_SHIFT;
509 /* reset source address in next go */
510 opcode |= DMAE_CMD_SRC_ADDR_RESET_MASK << DMAE_CMD_SRC_ADDR_RESET_SHIFT;
512 /* reset dest address in next go */
513 opcode |= DMAE_CMD_DST_ADDR_RESET_MASK << DMAE_CMD_DST_ADDR_RESET_SHIFT;
515 /* SRC/DST VFID: all 1's - pf, otherwise VF id */
516 if (ECORE_DMAE_FLAGS_IS_SET(p_params, SRC_VF_VALID)) {
517 opcode |= (1 << DMAE_CMD_SRC_VF_ID_VALID_SHIFT);
518 opcode_b |= (p_params->src_vf_id << DMAE_CMD_SRC_VF_ID_SHIFT);
520 opcode_b |= (DMAE_CMD_SRC_VF_ID_MASK <<
521 DMAE_CMD_SRC_VF_ID_SHIFT);
523 if (ECORE_DMAE_FLAGS_IS_SET(p_params, DST_VF_VALID)) {
524 opcode |= 1 << DMAE_CMD_DST_VF_ID_VALID_SHIFT;
525 opcode_b |= p_params->dst_vf_id << DMAE_CMD_DST_VF_ID_SHIFT;
527 opcode_b |= DMAE_CMD_DST_VF_ID_MASK << DMAE_CMD_DST_VF_ID_SHIFT;
530 p_hwfn->dmae_info.p_dmae_cmd->opcode = OSAL_CPU_TO_LE32(opcode);
531 p_hwfn->dmae_info.p_dmae_cmd->opcode_b = OSAL_CPU_TO_LE16(opcode_b);
534 static u32 ecore_dmae_idx_to_go_cmd(u8 idx)
536 OSAL_BUILD_BUG_ON((DMAE_REG_GO_C31 - DMAE_REG_GO_C0) != 31 * 4);
538 /* All the DMAE 'go' registers form an array in internal memory */
539 return DMAE_REG_GO_C0 + (idx << 2);
542 static enum _ecore_status_t ecore_dmae_post_command(struct ecore_hwfn *p_hwfn,
543 struct ecore_ptt *p_ptt)
545 struct dmae_cmd *p_command = p_hwfn->dmae_info.p_dmae_cmd;
546 u8 idx_cmd = p_hwfn->dmae_info.channel, i;
547 enum _ecore_status_t ecore_status = ECORE_SUCCESS;
549 /* verify address is not OSAL_NULL */
550 if ((((!p_command->dst_addr_lo) && (!p_command->dst_addr_hi)) ||
551 ((!p_command->src_addr_lo) && (!p_command->src_addr_hi)))) {
552 DP_NOTICE(p_hwfn, true,
553 "source or destination address 0 idx_cmd=%d\n"
554 "opcode = [0x%08x,0x%04x] len=0x%x"
555 " src=0x%x:%x dst=0x%x:%x\n",
557 OSAL_LE32_TO_CPU(p_command->opcode),
558 OSAL_LE16_TO_CPU(p_command->opcode_b),
559 OSAL_LE16_TO_CPU(p_command->length_dw),
560 OSAL_LE32_TO_CPU(p_command->src_addr_hi),
561 OSAL_LE32_TO_CPU(p_command->src_addr_lo),
562 OSAL_LE32_TO_CPU(p_command->dst_addr_hi),
563 OSAL_LE32_TO_CPU(p_command->dst_addr_lo));
568 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
569 "Posting DMAE command [idx %d]: opcode = [0x%08x,0x%04x]"
570 "len=0x%x src=0x%x:%x dst=0x%x:%x\n",
572 OSAL_LE32_TO_CPU(p_command->opcode),
573 OSAL_LE16_TO_CPU(p_command->opcode_b),
574 OSAL_LE16_TO_CPU(p_command->length_dw),
575 OSAL_LE32_TO_CPU(p_command->src_addr_hi),
576 OSAL_LE32_TO_CPU(p_command->src_addr_lo),
577 OSAL_LE32_TO_CPU(p_command->dst_addr_hi),
578 OSAL_LE32_TO_CPU(p_command->dst_addr_lo));
580 /* Copy the command to DMAE - need to do it before every call
581 * for source/dest address no reset.
582 * The number of commands have been increased to 16 (previous was 14)
583 * The first 9 DWs are the command registers, the 10 DW is the
585 * the rest are result registers (which are read only by the client).
587 for (i = 0; i < DMAE_CMD_SIZE; i++) {
588 u32 data = (i < DMAE_CMD_SIZE_TO_FILL) ?
589 *(((u32 *)p_command) + i) : 0;
591 ecore_wr(p_hwfn, p_ptt,
593 (idx_cmd * DMAE_CMD_SIZE * sizeof(u32)) +
594 (i * sizeof(u32)), data);
597 ecore_wr(p_hwfn, p_ptt,
598 ecore_dmae_idx_to_go_cmd(idx_cmd), DMAE_GO_VALUE);
603 enum _ecore_status_t ecore_dmae_info_alloc(struct ecore_hwfn *p_hwfn)
605 dma_addr_t *p_addr = &p_hwfn->dmae_info.completion_word_phys_addr;
606 struct dmae_cmd **p_cmd = &p_hwfn->dmae_info.p_dmae_cmd;
607 u32 **p_buff = &p_hwfn->dmae_info.p_intermediate_buffer;
608 u32 **p_comp = &p_hwfn->dmae_info.p_completion_word;
610 *p_comp = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, p_addr, sizeof(u32));
611 if (*p_comp == OSAL_NULL) {
612 DP_NOTICE(p_hwfn, false,
613 "Failed to allocate `p_completion_word'\n");
617 p_addr = &p_hwfn->dmae_info.dmae_cmd_phys_addr;
618 *p_cmd = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, p_addr,
619 sizeof(struct dmae_cmd));
620 if (*p_cmd == OSAL_NULL) {
621 DP_NOTICE(p_hwfn, false,
622 "Failed to allocate `struct dmae_cmd'\n");
626 p_addr = &p_hwfn->dmae_info.intermediate_buffer_phys_addr;
627 *p_buff = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, p_addr,
628 sizeof(u32) * DMAE_MAX_RW_SIZE);
629 if (*p_buff == OSAL_NULL) {
630 DP_NOTICE(p_hwfn, false,
631 "Failed to allocate `intermediate_buffer'\n");
635 p_hwfn->dmae_info.channel = p_hwfn->rel_pf_id;
636 p_hwfn->dmae_info.b_mem_ready = true;
638 return ECORE_SUCCESS;
640 ecore_dmae_info_free(p_hwfn);
644 void ecore_dmae_info_free(struct ecore_hwfn *p_hwfn)
648 OSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);
649 p_hwfn->dmae_info.b_mem_ready = false;
650 OSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);
652 if (p_hwfn->dmae_info.p_completion_word != OSAL_NULL) {
653 p_phys = p_hwfn->dmae_info.completion_word_phys_addr;
654 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
655 p_hwfn->dmae_info.p_completion_word,
656 p_phys, sizeof(u32));
657 p_hwfn->dmae_info.p_completion_word = OSAL_NULL;
660 if (p_hwfn->dmae_info.p_dmae_cmd != OSAL_NULL) {
661 p_phys = p_hwfn->dmae_info.dmae_cmd_phys_addr;
662 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
663 p_hwfn->dmae_info.p_dmae_cmd,
664 p_phys, sizeof(struct dmae_cmd));
665 p_hwfn->dmae_info.p_dmae_cmd = OSAL_NULL;
668 if (p_hwfn->dmae_info.p_intermediate_buffer != OSAL_NULL) {
669 p_phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr;
670 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
671 p_hwfn->dmae_info.p_intermediate_buffer,
672 p_phys, sizeof(u32) * DMAE_MAX_RW_SIZE);
673 p_hwfn->dmae_info.p_intermediate_buffer = OSAL_NULL;
677 static enum _ecore_status_t ecore_dmae_operation_wait(struct ecore_hwfn *p_hwfn)
679 u32 wait_cnt_limit = 10000, wait_cnt = 0;
680 enum _ecore_status_t ecore_status = ECORE_SUCCESS;
683 u32 factor = (CHIP_REV_IS_EMUL(p_hwfn->p_dev) ?
685 (CHIP_REV_IS_FPGA(p_hwfn->p_dev) ?
686 ECORE_FPGA_FACTOR : 1));
688 wait_cnt_limit *= factor;
691 /* DMAE_E4_TODO : TODO check if we have to call any other function
692 * other than BARRIER to sync the completion_word since we are not
693 * using the volatile keyword for this
695 OSAL_BARRIER(p_hwfn->p_dev);
696 while (*p_hwfn->dmae_info.p_completion_word != DMAE_COMPLETION_VAL) {
697 OSAL_UDELAY(DMAE_MIN_WAIT_TIME);
698 if (++wait_cnt > wait_cnt_limit) {
699 DP_NOTICE(p_hwfn->p_dev, ECORE_MSG_HW,
700 "Timed-out waiting for operation to"
701 " complete. Completion word is 0x%08x"
702 " expected 0x%08x.\n",
703 *p_hwfn->dmae_info.p_completion_word,
704 DMAE_COMPLETION_VAL);
705 ecore_status = ECORE_TIMEOUT;
708 /* to sync the completion_word since we are not
709 * using the volatile keyword for p_completion_word
711 OSAL_BARRIER(p_hwfn->p_dev);
714 if (ecore_status == ECORE_SUCCESS)
715 *p_hwfn->dmae_info.p_completion_word = 0;
720 enum ecore_dmae_address_type {
721 ECORE_DMAE_ADDRESS_HOST_VIRT,
722 ECORE_DMAE_ADDRESS_HOST_PHYS,
723 ECORE_DMAE_ADDRESS_GRC
726 static enum _ecore_status_t
727 ecore_dmae_execute_sub_operation(struct ecore_hwfn *p_hwfn,
728 struct ecore_ptt *p_ptt,
731 u8 src_type, u8 dst_type, u32 length_dw)
733 dma_addr_t phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr;
734 struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd;
735 enum _ecore_status_t ecore_status = ECORE_SUCCESS;
738 case ECORE_DMAE_ADDRESS_GRC:
739 case ECORE_DMAE_ADDRESS_HOST_PHYS:
740 cmd->src_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(src_addr));
741 cmd->src_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(src_addr));
743 /* for virt source addresses we use the intermediate buffer. */
744 case ECORE_DMAE_ADDRESS_HOST_VIRT:
745 cmd->src_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(phys));
746 cmd->src_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(phys));
747 OSAL_MEMCPY(&p_hwfn->dmae_info.p_intermediate_buffer[0],
748 (void *)(osal_uintptr_t)src_addr,
749 length_dw * sizeof(u32));
756 case ECORE_DMAE_ADDRESS_GRC:
757 case ECORE_DMAE_ADDRESS_HOST_PHYS:
758 cmd->dst_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(dst_addr));
759 cmd->dst_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(dst_addr));
761 /* for virt destination address we use the intermediate buff. */
762 case ECORE_DMAE_ADDRESS_HOST_VIRT:
763 cmd->dst_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(phys));
764 cmd->dst_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(phys));
770 cmd->length_dw = OSAL_CPU_TO_LE16((u16)length_dw);
772 if (src_type == ECORE_DMAE_ADDRESS_HOST_VIRT ||
773 src_type == ECORE_DMAE_ADDRESS_HOST_PHYS)
774 OSAL_DMA_SYNC(p_hwfn->p_dev,
775 (void *)HILO_U64(cmd->src_addr_hi,
777 length_dw * sizeof(u32), false);
779 ecore_dmae_post_command(p_hwfn, p_ptt);
781 ecore_status = ecore_dmae_operation_wait(p_hwfn);
783 /* TODO - is it true ? */
784 if (src_type == ECORE_DMAE_ADDRESS_HOST_VIRT ||
785 src_type == ECORE_DMAE_ADDRESS_HOST_PHYS)
786 OSAL_DMA_SYNC(p_hwfn->p_dev,
787 (void *)HILO_U64(cmd->src_addr_hi,
789 length_dw * sizeof(u32), true);
791 if (ecore_status != ECORE_SUCCESS) {
792 DP_NOTICE(p_hwfn, ECORE_MSG_HW,
793 "Wait Failed. source_addr 0x%lx, grc_addr 0x%lx, size_in_dwords 0x%x, intermediate buffer 0x%lx.\n",
794 (unsigned long)src_addr, (unsigned long)dst_addr,
796 (unsigned long)p_hwfn->dmae_info.intermediate_buffer_phys_addr);
800 if (dst_type == ECORE_DMAE_ADDRESS_HOST_VIRT)
801 OSAL_MEMCPY((void *)(osal_uintptr_t)(dst_addr),
802 &p_hwfn->dmae_info.p_intermediate_buffer[0],
803 length_dw * sizeof(u32));
805 return ECORE_SUCCESS;
808 static enum _ecore_status_t
809 ecore_dmae_execute_command(struct ecore_hwfn *p_hwfn,
810 struct ecore_ptt *p_ptt,
816 struct dmae_params *p_params)
818 dma_addr_t phys = p_hwfn->dmae_info.completion_word_phys_addr;
819 u16 length_cur = 0, i = 0, cnt_split = 0, length_mod = 0;
820 struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd;
821 u64 src_addr_split = 0, dst_addr_split = 0;
822 u16 length_limit = DMAE_MAX_RW_SIZE;
823 enum _ecore_status_t ecore_status = ECORE_SUCCESS;
826 if (!p_hwfn->dmae_info.b_mem_ready) {
827 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
828 "No buffers allocated. Avoid DMAE transaction [{src: addr 0x%lx, type %d}, {dst: addr 0x%lx, type %d}, size %d].\n",
829 (unsigned long)src_addr, src_type,
830 (unsigned long)dst_addr, dst_type,
835 if (p_hwfn->p_dev->recov_in_prog) {
836 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
837 "Recovery is in progress. Avoid DMAE transaction [{src: addr 0x%lx, type %d}, {dst: addr 0x%lx, type %d}, size %d].\n",
838 (unsigned long)src_addr, src_type,
839 (unsigned long)dst_addr, dst_type,
841 /* Return success to let the flow to be completed successfully
842 * w/o any error handling.
844 return ECORE_SUCCESS;
848 DP_NOTICE(p_hwfn, true,
849 "ecore_dmae_execute_sub_operation failed. Invalid state. source_addr 0x%lx, destination addr 0x%lx, size_in_dwords 0x%x\n",
850 (unsigned long)src_addr,
851 (unsigned long)dst_addr,
856 ecore_dmae_opcode(p_hwfn,
857 (src_type == ECORE_DMAE_ADDRESS_GRC),
858 (dst_type == ECORE_DMAE_ADDRESS_GRC), p_params);
860 cmd->comp_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(phys));
861 cmd->comp_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(phys));
862 cmd->comp_val = OSAL_CPU_TO_LE32(DMAE_COMPLETION_VAL);
864 /* Check if the grc_addr is valid like < MAX_GRC_OFFSET */
865 cnt_split = size_in_dwords / length_limit;
866 length_mod = size_in_dwords % length_limit;
868 src_addr_split = src_addr;
869 dst_addr_split = dst_addr;
871 for (i = 0; i <= cnt_split; i++) {
872 offset = length_limit * i;
874 if (!ECORE_DMAE_FLAGS_IS_SET(p_params, RW_REPL_SRC)) {
875 if (src_type == ECORE_DMAE_ADDRESS_GRC)
876 src_addr_split = src_addr + offset;
878 src_addr_split = src_addr + (offset * 4);
881 if (dst_type == ECORE_DMAE_ADDRESS_GRC)
882 dst_addr_split = dst_addr + offset;
884 dst_addr_split = dst_addr + (offset * 4);
886 length_cur = (cnt_split == i) ? length_mod : length_limit;
888 /* might be zero on last iteration */
892 ecore_status = ecore_dmae_execute_sub_operation(p_hwfn,
899 if (ecore_status != ECORE_SUCCESS) {
900 DP_NOTICE(p_hwfn, false,
901 "ecore_dmae_execute_sub_operation Failed"
902 " with error 0x%x. source_addr 0x%lx,"
903 " dest addr 0x%lx, size_in_dwords 0x%x\n",
904 ecore_status, (unsigned long)src_addr,
905 (unsigned long)dst_addr, length_cur);
907 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_DMAE_FAIL);
915 enum _ecore_status_t ecore_dmae_host2grc(struct ecore_hwfn *p_hwfn,
916 struct ecore_ptt *p_ptt,
920 struct dmae_params *p_params)
922 u32 grc_addr_in_dw = grc_addr / sizeof(u32);
923 enum _ecore_status_t rc;
925 OSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);
927 rc = ecore_dmae_execute_command(p_hwfn, p_ptt, source_addr,
929 ECORE_DMAE_ADDRESS_HOST_VIRT,
930 ECORE_DMAE_ADDRESS_GRC,
931 size_in_dwords, p_params);
933 OSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);
938 enum _ecore_status_t ecore_dmae_grc2host(struct ecore_hwfn *p_hwfn,
939 struct ecore_ptt *p_ptt,
941 dma_addr_t dest_addr,
943 struct dmae_params *p_params)
945 u32 grc_addr_in_dw = grc_addr / sizeof(u32);
946 enum _ecore_status_t rc;
948 OSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);
950 rc = ecore_dmae_execute_command(p_hwfn, p_ptt, grc_addr_in_dw,
951 dest_addr, ECORE_DMAE_ADDRESS_GRC,
952 ECORE_DMAE_ADDRESS_HOST_VIRT,
953 size_in_dwords, p_params);
955 OSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);
961 ecore_dmae_host2host(struct ecore_hwfn *p_hwfn,
962 struct ecore_ptt *p_ptt,
963 dma_addr_t source_addr,
964 dma_addr_t dest_addr,
966 struct dmae_params *p_params)
968 enum _ecore_status_t rc;
970 OSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);
972 rc = ecore_dmae_execute_command(p_hwfn, p_ptt, source_addr,
974 ECORE_DMAE_ADDRESS_HOST_PHYS,
975 ECORE_DMAE_ADDRESS_HOST_PHYS,
976 size_in_dwords, p_params);
978 OSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);
983 void ecore_hw_err_notify(struct ecore_hwfn *p_hwfn,
984 enum ecore_hw_err_type err_type)
986 /* Fan failure cannot be masked by handling of another HW error */
987 if (p_hwfn->p_dev->recov_in_prog && err_type != ECORE_HW_ERR_FAN_FAIL) {
988 DP_VERBOSE(p_hwfn, ECORE_MSG_DRV,
989 "Recovery is in progress."
990 "Avoid notifying about HW error %d.\n",
995 OSAL_HW_ERROR_OCCURRED(p_hwfn, err_type);
998 enum _ecore_status_t ecore_dmae_sanity(struct ecore_hwfn *p_hwfn,
999 struct ecore_ptt *p_ptt,
1002 u32 size = OSAL_PAGE_SIZE / 2, val;
1003 enum _ecore_status_t rc = ECORE_SUCCESS;
1008 p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, &p_phys, 2 * size);
1010 DP_NOTICE(p_hwfn, false,
1011 "DMAE sanity [%s]: failed to allocate memory\n",
1016 /* Fill the bottom half of the allocated memory with a known pattern */
1017 for (p_tmp = (u32 *)p_virt;
1018 p_tmp < (u32 *)((u8 *)p_virt + size);
1020 /* Save the address itself as the value */
1021 val = (u32)(osal_uintptr_t)p_tmp;
1025 /* Zero the top half of the allocated memory */
1026 OSAL_MEM_ZERO((u8 *)p_virt + size, size);
1028 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1029 "DMAE sanity [%s]: src_addr={phys 0x%lx, virt %p}, dst_addr={phys 0x%lx, virt %p}, size 0x%x\n",
1030 phase, (unsigned long)p_phys, p_virt,
1031 (unsigned long)(p_phys + size),
1032 (u8 *)p_virt + size, size);
1034 rc = ecore_dmae_host2host(p_hwfn, p_ptt, p_phys, p_phys + size,
1035 size / 4 /* size_in_dwords */,
1036 OSAL_NULL /* default parameters */);
1037 if (rc != ECORE_SUCCESS) {
1038 DP_NOTICE(p_hwfn, false,
1039 "DMAE sanity [%s]: ecore_dmae_host2host() failed. rc = %d.\n",
1044 /* Verify that the top half of the allocated memory has the pattern */
1045 for (p_tmp = (u32 *)((u8 *)p_virt + size);
1046 p_tmp < (u32 *)((u8 *)p_virt + (2 * size));
1048 /* The corresponding address in the bottom half */
1049 val = (u32)(osal_uintptr_t)p_tmp - size;
1051 if (*p_tmp != val) {
1052 DP_NOTICE(p_hwfn, false,
1053 "DMAE sanity [%s]: addr={phys 0x%lx, virt %p}, read_val 0x%08x, expected_val 0x%08x\n",
1055 (unsigned long)p_phys +
1056 ((u8 *)p_tmp - (u8 *)p_virt),
1057 p_tmp, *p_tmp, val);
1058 rc = ECORE_UNKNOWN_ERROR;
1064 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, p_virt, p_phys, 2 * size);
1068 void ecore_ppfid_wr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1069 u8 abs_ppfid, u32 hw_addr, u32 val)
1071 u8 pfid = ECORE_PFID_BY_PPFID(p_hwfn, abs_ppfid);
1073 ecore_fid_pretend(p_hwfn, p_ptt,
1074 pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
1075 ecore_wr(p_hwfn, p_ptt, hw_addr, val);
1076 ecore_fid_pretend(p_hwfn, p_ptt,
1077 p_hwfn->rel_pf_id <<
1078 PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
1081 u32 ecore_ppfid_rd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1082 u8 abs_ppfid, u32 hw_addr)
1084 u8 pfid = ECORE_PFID_BY_PPFID(p_hwfn, abs_ppfid);
1087 ecore_fid_pretend(p_hwfn, p_ptt,
1088 pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
1089 val = ecore_rd(p_hwfn, p_ptt, hw_addr);
1090 ecore_fid_pretend(p_hwfn, p_ptt,
1091 p_hwfn->rel_pf_id <<
1092 PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);