2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #ifndef _ECORE_IGU_DEF_H_
10 #define _ECORE_IGU_DEF_H_
12 /* Fields of IGU PF CONFIGRATION REGISTER */
14 #define IGU_PF_CONF_FUNC_EN (0x1 << 0)
16 #define IGU_PF_CONF_MSI_MSIX_EN (0x1 << 1)
18 #define IGU_PF_CONF_INT_LINE_EN (0x1 << 2)
19 /* attention enable */
20 #define IGU_PF_CONF_ATTN_BIT_EN (0x1 << 3)
21 /* single ISR mode enable */
22 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4)
23 /* simd all ones mode */
24 #define IGU_PF_CONF_SIMD_MODE (0x1 << 5)
26 /* Fields of IGU VF CONFIGRATION REGISTER */
28 #define IGU_VF_CONF_FUNC_EN (0x1 << 0)
30 #define IGU_VF_CONF_MSI_MSIX_EN (0x1 << 1)
31 /* single ISR mode enable */
32 #define IGU_VF_CONF_SINGLE_ISR_EN (0x1 << 4)
34 #define IGU_VF_CONF_PARENT_MASK (0xF)
36 #define IGU_VF_CONF_PARENT_SHIFT 5
38 /* Igu control commands
46 /* Control register for the IGU command register
50 #define IGU_CTRL_REG_FID_MASK 0xFFFF /* Opaque_FID */
51 #define IGU_CTRL_REG_FID_SHIFT 0
52 #define IGU_CTRL_REG_PXP_ADDR_MASK 0xFFF /* Command address */
53 #define IGU_CTRL_REG_PXP_ADDR_SHIFT 16
54 #define IGU_CTRL_REG_RESERVED_MASK 0x1
55 #define IGU_CTRL_REG_RESERVED_SHIFT 28
56 #define IGU_CTRL_REG_TYPE_MASK 0x1 /* use enum igu_ctrl_cmd */
57 #define IGU_CTRL_REG_TYPE_SHIFT 31