2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #ifndef _ECORE_IGU_DEF_H_
10 #define _ECORE_IGU_DEF_H_
12 /* Fields of IGU PF CONFIGRATION REGISTER */
13 #define IGU_PF_CONF_FUNC_EN (0x1 << 0) /* function enable */
14 #define IGU_PF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */
15 #define IGU_PF_CONF_INT_LINE_EN (0x1 << 2) /* INT enable */
16 #define IGU_PF_CONF_ATTN_BIT_EN (0x1 << 3) /* attention enable */
17 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */
18 #define IGU_PF_CONF_SIMD_MODE (0x1 << 5) /* simd all ones mode */
20 /* Fields of IGU VF CONFIGRATION REGISTER */
21 #define IGU_VF_CONF_FUNC_EN (0x1 << 0) /* function enable */
22 #define IGU_VF_CONF_MSI_MSIX_EN (0x1 << 1) /* MSI/MSIX enable */
23 #define IGU_VF_CONF_SINGLE_ISR_EN (0x1 << 4) /* single ISR mode enable */
24 #define IGU_VF_CONF_PARENT_MASK (0xF) /* Parent PF */
25 #define IGU_VF_CONF_PARENT_SHIFT 5 /* Parent PF */
27 /* Igu control commands
35 /* Control register for the IGU command register
39 #define IGU_CTRL_REG_FID_MASK 0xFFFF /* Opaque_FID */
40 #define IGU_CTRL_REG_FID_SHIFT 0
41 #define IGU_CTRL_REG_PXP_ADDR_MASK 0xFFF /* Command address */
42 #define IGU_CTRL_REG_PXP_ADDR_SHIFT 16
43 #define IGU_CTRL_REG_RESERVED_MASK 0x1
44 #define IGU_CTRL_REG_RESERVED_SHIFT 28
45 #define IGU_CTRL_REG_TYPE_MASK 0x1 /* use enum igu_ctrl_cmd */
46 #define IGU_CTRL_REG_TYPE_SHIFT 31