2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_init_ops.h"
13 #include "ecore_rt_defs.h"
14 #include "ecore_hsi_common.h"
15 #include "ecore_hsi_init_func.h"
16 #include "ecore_hsi_eth.h"
17 #include "ecore_hsi_init_tool.h"
18 #include "ecore_iro.h"
19 #include "ecore_init_fw_funcs.h"
21 #define CDU_VALIDATION_DEFAULT_CFG 61
23 static u16 con_region_offsets[3][E4_NUM_OF_CONNECTION_TYPES] = {
24 { 400, 336, 352, 304, 304, 384, 416, 352}, /* region 3 offsets */
25 { 528, 496, 416, 448, 448, 512, 544, 480}, /* region 4 offsets */
26 { 608, 544, 496, 512, 576, 592, 624, 560} /* region 5 offsets */
28 static u16 task_region_offsets[1][E4_NUM_OF_CONNECTION_TYPES] = {
29 { 240, 240, 112, 0, 0, 0, 0, 96} /* region 1 offsets */
32 /* General constants */
33 #define QM_PQ_MEM_4KB(pq_size) (pq_size ? DIV_ROUND_UP((pq_size + 1) * \
34 QM_PQ_ELEMENT_SIZE, 0x1000) : 0)
35 #define QM_PQ_SIZE_256B(pq_size) (pq_size ? DIV_ROUND_UP(pq_size, 0x100) - 1 : \
37 #define QM_INVALID_PQ_ID 0xffff
40 #define QM_BYPASS_EN 1
41 #define QM_BYTE_CRD_EN 1
43 /* Other PQ constants */
44 #define QM_OTHER_PQS_PER_PF 4
48 /* Upper bound in MB, 10 * burst size of 1ms in 50Gbps */
49 #define QM_WFQ_UPPER_BOUND 62500000
51 /* Bit of VOQ in WFQ VP PQ map */
52 #define QM_WFQ_VP_PQ_VOQ_SHIFT 0
54 /* Bit of PF in WFQ VP PQ map */
55 #define QM_WFQ_VP_PQ_PF_SHIFT 5
57 /* 0x9000 = 4*9*1024 */
58 #define QM_WFQ_INC_VAL(weight) ((weight) * 0x9000)
60 /* 0.7 * upper bound (62500000) */
61 #define QM_WFQ_MAX_INC_VAL 43750000
65 /* Upper bound is set to 10 * burst size of 1ms in 50Gbps */
66 #define QM_RL_UPPER_BOUND 62500000
69 #define QM_RL_PERIOD 5
71 /* Period in 25MHz cycles */
72 #define QM_RL_PERIOD_CLK_25M (25 * QM_RL_PERIOD)
74 /* 0.7 * upper bound (62500000) */
75 #define QM_RL_MAX_INC_VAL 43750000
77 /* RL increment value - rate is specified in mbps. the factor of 1.01 was
78 * added after seeing only 99% factor reached in a 25Gbps port with DPDK RFC
79 * 2544 test. In this scenario the PF RL was reducing the line rate to 99%
80 * although the credit increment value was the correct one and FW calculated
81 * correct packet sizes. The reason for the inaccuracy of the RL is unknown at
84 #define QM_RL_INC_VAL(rate) OSAL_MAX_T(u32, (u32)(((rate ? rate : 1000000) * \
85 QM_RL_PERIOD * 101) / (8 * 100)), 1)
87 /* AFullOprtnstcCrdMask constants */
88 #define QM_OPPOR_LINE_VOQ_DEF 1
89 #define QM_OPPOR_FW_STOP_DEF 0
90 #define QM_OPPOR_PQ_EMPTY_DEF 1
92 /* Command Queue constants: */
94 /* Pure LB CmdQ lines (+spare) */
95 #define PBF_CMDQ_PURE_LB_LINES 150
97 #define PBF_CMDQ_LINES_RT_OFFSET(voq) \
98 (PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET + voq * \
99 (PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET - \
100 PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET))
102 #define PBF_BTB_GUARANTEED_RT_OFFSET(voq) \
103 (PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET + voq * \
104 (PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET - \
105 PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET))
107 #define QM_VOQ_LINE_CRD(pbf_cmd_lines) \
108 ((((pbf_cmd_lines) - 4) * 2) | QM_LINE_CRD_REG_SIGN_BIT)
110 /* BTB: blocks constants (block size = 256B) */
112 /* 256B blocks in 9700B packet */
113 #define BTB_JUMBO_PKT_BLOCKS 38
115 /* Headroom per-port */
116 #define BTB_HEADROOM_BLOCKS BTB_JUMBO_PKT_BLOCKS
117 #define BTB_PURE_LB_FACTOR 10
119 /* Factored (hence really 0.7) */
120 #define BTB_PURE_LB_RATIO 7
122 /* QM stop command constants */
123 #define QM_STOP_PQ_MASK_WIDTH 32
124 #define QM_STOP_CMD_ADDR 2
125 #define QM_STOP_CMD_STRUCT_SIZE 2
126 #define QM_STOP_CMD_PAUSE_MASK_OFFSET 0
127 #define QM_STOP_CMD_PAUSE_MASK_SHIFT 0
128 #define QM_STOP_CMD_PAUSE_MASK_MASK 0xffffffff /* @DPDK */
129 #define QM_STOP_CMD_GROUP_ID_OFFSET 1
130 #define QM_STOP_CMD_GROUP_ID_SHIFT 16
131 #define QM_STOP_CMD_GROUP_ID_MASK 15
132 #define QM_STOP_CMD_PQ_TYPE_OFFSET 1
133 #define QM_STOP_CMD_PQ_TYPE_SHIFT 24
134 #define QM_STOP_CMD_PQ_TYPE_MASK 1
135 #define QM_STOP_CMD_MAX_POLL_COUNT 100
136 #define QM_STOP_CMD_POLL_PERIOD_US 500
138 /* QM command macros */
139 #define QM_CMD_STRUCT_SIZE(cmd) cmd##_STRUCT_SIZE
140 #define QM_CMD_SET_FIELD(var, cmd, field, value) \
141 SET_FIELD(var[cmd##_##field##_OFFSET], cmd##_##field, value)
144 #define PHYS_VOQ(port, tc, max_phys_tcs_per_port) \
145 ((port) * (max_phys_tcs_per_port) + (tc))
146 #define LB_VOQ(port) (MAX_PHYS_VOQS + (port))
147 #define VOQ(port, tc, max_phys_tcs_per_port) \
148 ((tc) < LB_TC ? PHYS_VOQ(port, tc, max_phys_tcs_per_port) : \
152 /******************** INTERNAL IMPLEMENTATION *********************/
154 /* Prepare PF RL enable/disable runtime init values */
155 static void ecore_enable_pf_rl(struct ecore_hwfn *p_hwfn, bool pf_rl_en)
157 STORE_RT_REG(p_hwfn, QM_REG_RLPFENABLE_RT_OFFSET, pf_rl_en ? 1 : 0);
159 /* Enable RLs for all VOQs */
160 STORE_RT_REG(p_hwfn, QM_REG_RLPFVOQENABLE_RT_OFFSET,
161 (1 << MAX_NUM_VOQS) - 1);
163 /* Write RL period */
164 STORE_RT_REG(p_hwfn, QM_REG_RLPFPERIOD_RT_OFFSET,
165 QM_RL_PERIOD_CLK_25M);
166 STORE_RT_REG(p_hwfn, QM_REG_RLPFPERIODTIMER_RT_OFFSET,
167 QM_RL_PERIOD_CLK_25M);
169 /* Set credit threshold for QM bypass flow */
171 STORE_RT_REG(p_hwfn, QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET,
176 /* Prepare PF WFQ enable/disable runtime init values */
177 static void ecore_enable_pf_wfq(struct ecore_hwfn *p_hwfn, bool pf_wfq_en)
179 STORE_RT_REG(p_hwfn, QM_REG_WFQPFENABLE_RT_OFFSET, pf_wfq_en ? 1 : 0);
181 /* Set credit threshold for QM bypass flow */
182 if (pf_wfq_en && QM_BYPASS_EN)
183 STORE_RT_REG(p_hwfn, QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET,
187 /* Prepare VPORT RL enable/disable runtime init values */
188 static void ecore_enable_vport_rl(struct ecore_hwfn *p_hwfn, bool vport_rl_en)
190 STORE_RT_REG(p_hwfn, QM_REG_RLGLBLENABLE_RT_OFFSET,
191 vport_rl_en ? 1 : 0);
193 /* Write RL period (use timer 0 only) */
194 STORE_RT_REG(p_hwfn, QM_REG_RLGLBLPERIOD_0_RT_OFFSET,
195 QM_RL_PERIOD_CLK_25M);
196 STORE_RT_REG(p_hwfn, QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET,
197 QM_RL_PERIOD_CLK_25M);
199 /* Set credit threshold for QM bypass flow */
202 QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET,
207 /* Prepare VPORT WFQ enable/disable runtime init values */
208 static void ecore_enable_vport_wfq(struct ecore_hwfn *p_hwfn, bool vport_wfq_en)
210 STORE_RT_REG(p_hwfn, QM_REG_WFQVPENABLE_RT_OFFSET,
211 vport_wfq_en ? 1 : 0);
213 /* Set credit threshold for QM bypass flow */
214 if (vport_wfq_en && QM_BYPASS_EN)
215 STORE_RT_REG(p_hwfn, QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET,
219 /* Prepare runtime init values to allocate PBF command queue lines for
222 static void ecore_cmdq_lines_voq_rt_init(struct ecore_hwfn *p_hwfn,
223 u8 voq, u16 cmdq_lines)
227 qm_line_crd = QM_VOQ_LINE_CRD(cmdq_lines);
229 OVERWRITE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(voq),
231 STORE_RT_REG(p_hwfn, QM_REG_VOQCRDLINE_RT_OFFSET + voq, qm_line_crd);
232 STORE_RT_REG(p_hwfn, QM_REG_VOQINITCRDLINE_RT_OFFSET + voq,
236 /* Prepare runtime init values to allocate PBF command queue lines. */
237 static void ecore_cmdq_lines_rt_init(struct ecore_hwfn *p_hwfn,
238 u8 max_ports_per_engine,
239 u8 max_phys_tcs_per_port,
240 struct init_qm_port_params
241 port_params[MAX_NUM_PORTS])
243 u8 tc, voq, port_id, num_tcs_in_port;
245 /* Clear PBF lines for all VOQs */
246 for (voq = 0; voq < MAX_NUM_VOQS; voq++)
247 STORE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(voq), 0);
249 for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
250 u16 phys_lines, phys_lines_per_tc;
252 if (!port_params[port_id].active)
255 /* Find #lines to divide between the active physical TCs */
256 phys_lines = port_params[port_id].num_pbf_cmd_lines -
257 PBF_CMDQ_PURE_LB_LINES;
259 /* Find #lines per active physical TC */
261 for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++)
262 if (((port_params[port_id].active_phys_tcs >> tc) &
265 phys_lines_per_tc = phys_lines / num_tcs_in_port;
267 /* Init registers per active TC */
268 for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
269 if (((port_params[port_id].active_phys_tcs >> tc) &
271 voq = PHYS_VOQ(port_id, tc,
272 max_phys_tcs_per_port);
273 ecore_cmdq_lines_voq_rt_init(p_hwfn, voq,
278 /* Init registers for pure LB TC */
279 ecore_cmdq_lines_voq_rt_init(p_hwfn, LB_VOQ(port_id),
280 PBF_CMDQ_PURE_LB_LINES);
285 * Prepare runtime init values to allocate guaranteed BTB blocks for the
286 * specified port. The guaranteed BTB space is divided between the TCs as
287 * follows (shared space Is currently not used):
289 * B BTB blocks for this port
290 * C Number of physical TCs for this port
292 * a. 38 blocks (9700B jumbo frame) are allocated for global per port
294 * b. B = B 38 (remainder after global headroom allocation)
295 * c. MAX(38,B/(C+0.7)) blocks are allocated for the pure LB VOQ.
296 * d. B = B MAX(38, B/(C+0.7)) (remainder after pure LB allocation).
297 * e. B/C blocks are allocated for each physical TC.
299 * - MTU is up to 9700 bytes (38 blocks)
300 * - All TCs are considered symmetrical (same rate and packet size)
301 * - No optimization for lossy TC (all are considered lossless). Shared space is
302 * not enabled and allocated for each TC.
304 static void ecore_btb_blocks_rt_init(struct ecore_hwfn *p_hwfn,
305 u8 max_ports_per_engine,
306 u8 max_phys_tcs_per_port,
307 struct init_qm_port_params
308 port_params[MAX_NUM_PORTS])
310 u32 usable_blocks, pure_lb_blocks, phys_blocks;
311 u8 tc, voq, port_id, num_tcs_in_port;
313 for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
314 if (!port_params[port_id].active)
317 /* Subtract headroom blocks */
318 usable_blocks = port_params[port_id].num_btb_blocks -
321 /* Find blocks per physical TC. use factor to avoid floating
325 for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++)
326 if (((port_params[port_id].active_phys_tcs >> tc) &
330 pure_lb_blocks = (usable_blocks * BTB_PURE_LB_FACTOR) /
331 (num_tcs_in_port * BTB_PURE_LB_FACTOR +
333 pure_lb_blocks = OSAL_MAX_T(u32, BTB_JUMBO_PKT_BLOCKS,
336 phys_blocks = (usable_blocks - pure_lb_blocks) /
339 /* Init physical TCs */
340 for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
341 if (((port_params[port_id].active_phys_tcs >> tc) &
343 voq = PHYS_VOQ(port_id, tc,
344 max_phys_tcs_per_port);
346 PBF_BTB_GUARANTEED_RT_OFFSET(voq),
351 /* Init pure LB TC */
353 PBF_BTB_GUARANTEED_RT_OFFSET(LB_VOQ(port_id)),
358 /* Prepare Tx PQ mapping runtime init values for the specified PF */
359 static void ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn,
360 struct ecore_ptt *p_ptt,
363 u8 max_phys_tcs_per_port,
371 u32 base_mem_addr_4kb,
372 struct init_qm_pq_params *pq_params,
373 struct init_qm_vport_params *vport_params)
375 /* A bit per Tx PQ indicating if the PQ is associated with a VF */
376 u32 tx_pq_vf_mask[MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE] = { 0 };
377 u32 num_tx_pq_vf_masks = MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE;
378 u16 num_pqs, first_pq_group, last_pq_group, i, pq_id, pq_group;
379 u32 pq_mem_4kb, vport_pq_mem_4kb, mem_addr_4kb;
381 num_pqs = num_pf_pqs + num_vf_pqs;
383 first_pq_group = start_pq / QM_PF_QUEUE_GROUP_SIZE;
384 last_pq_group = (start_pq + num_pqs - 1) / QM_PF_QUEUE_GROUP_SIZE;
386 pq_mem_4kb = QM_PQ_MEM_4KB(num_pf_cids);
387 vport_pq_mem_4kb = QM_PQ_MEM_4KB(num_vf_cids);
388 mem_addr_4kb = base_mem_addr_4kb;
390 /* Set mapping from PQ group to PF */
391 for (pq_group = first_pq_group; pq_group <= last_pq_group; pq_group++)
392 STORE_RT_REG(p_hwfn, QM_REG_PQTX2PF_0_RT_OFFSET + pq_group,
396 STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_0_RT_OFFSET,
397 QM_PQ_SIZE_256B(num_pf_cids));
398 STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_1_RT_OFFSET,
399 QM_PQ_SIZE_256B(num_vf_cids));
401 /* Go over all Tx PQs */
402 for (i = 0, pq_id = start_pq; i < num_pqs; i++, pq_id++) {
403 u32 max_qm_global_rls = MAX_QM_GLOBAL_RLS;
404 struct qm_rf_pq_map tx_pq_map;
405 bool is_vf_pq, rl_valid;
406 u8 voq, vport_id_in_pf;
409 voq = VOQ(port_id, pq_params[i].tc_id, max_phys_tcs_per_port);
410 is_vf_pq = (i >= num_pf_pqs);
411 rl_valid = pq_params[i].rl_valid && pq_params[i].vport_id <
414 /* Update first Tx PQ of VPORT/TC */
415 vport_id_in_pf = pq_params[i].vport_id - start_vport;
417 vport_params[vport_id_in_pf].first_tx_pq_id[pq_params[i].tc_id];
418 if (first_tx_pq_id == QM_INVALID_PQ_ID) {
419 /* Create new VP PQ */
420 vport_params[vport_id_in_pf].
421 first_tx_pq_id[pq_params[i].tc_id] = pq_id;
422 first_tx_pq_id = pq_id;
424 /* Map VP PQ to VOQ and PF */
426 QM_REG_WFQVPMAP_RT_OFFSET + first_tx_pq_id,
427 (voq << QM_WFQ_VP_PQ_VOQ_SHIFT) | (pf_id <<
428 QM_WFQ_VP_PQ_PF_SHIFT));
432 if (pq_params[i].rl_valid && pq_params[i].vport_id >=
434 DP_NOTICE(p_hwfn, true,
435 "Invalid VPORT ID for rate limiter config\n");
437 /* Fill PQ map entry */
438 OSAL_MEMSET(&tx_pq_map, 0, sizeof(tx_pq_map));
439 SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_PQ_VALID, 1);
440 SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_RL_VALID,
442 SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_VP_PQ_ID, first_tx_pq_id);
443 SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_RL_ID,
444 rl_valid ? pq_params[i].vport_id : 0);
445 SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_VOQ, voq);
446 SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_WRR_WEIGHT_GROUP,
447 pq_params[i].wrr_group);
449 /* Write PQ map entry to CAM */
450 STORE_RT_REG(p_hwfn, QM_REG_TXPQMAP_RT_OFFSET + pq_id,
451 *((u32 *)&tx_pq_map));
453 /* Set base address */
454 STORE_RT_REG(p_hwfn, QM_REG_BASEADDRTXPQ_RT_OFFSET + pq_id,
457 /* If VF PQ, add indication to PQ VF mask */
459 tx_pq_vf_mask[pq_id / QM_PF_QUEUE_GROUP_SIZE] |=
460 (1 << (pq_id % QM_PF_QUEUE_GROUP_SIZE));
461 mem_addr_4kb += vport_pq_mem_4kb;
463 mem_addr_4kb += pq_mem_4kb;
467 /* Store Tx PQ VF mask to size select register */
468 for (i = 0; i < num_tx_pq_vf_masks; i++)
469 if (tx_pq_vf_mask[i])
470 STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET +
471 i, tx_pq_vf_mask[i]);
474 /* Prepare Other PQ mapping runtime init values for the specified PF */
475 static void ecore_other_pq_map_rt_init(struct ecore_hwfn *p_hwfn,
479 u32 num_tids, u32 base_mem_addr_4kb)
481 u32 pq_size, pq_mem_4kb, mem_addr_4kb;
482 u16 i, pq_id, pq_group;
484 /* A single other PQ group is used in each PF, where PQ group i is used
488 pq_size = num_pf_cids + num_tids;
489 pq_mem_4kb = QM_PQ_MEM_4KB(pq_size);
490 mem_addr_4kb = base_mem_addr_4kb;
492 /* Map PQ group to PF */
493 STORE_RT_REG(p_hwfn, QM_REG_PQOTHER2PF_0_RT_OFFSET + pq_group,
497 STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_2_RT_OFFSET,
498 QM_PQ_SIZE_256B(pq_size));
500 /* Set base address */
501 for (i = 0, pq_id = pf_id * QM_PF_QUEUE_GROUP_SIZE;
502 i < QM_OTHER_PQS_PER_PF; i++, pq_id++) {
503 STORE_RT_REG(p_hwfn, QM_REG_BASEADDROTHERPQ_RT_OFFSET + pq_id,
505 mem_addr_4kb += pq_mem_4kb;
509 /* Prepare PF WFQ runtime init values for the specified PF.
510 * Return -1 on error.
512 static int ecore_pf_wfq_rt_init(struct ecore_hwfn *p_hwfn,
516 u8 max_phys_tcs_per_port,
518 struct init_qm_pq_params *pq_params)
520 u32 inc_val, crd_reg_offset;
524 crd_reg_offset = (pf_id < MAX_NUM_PFS_BB ? QM_REG_WFQPFCRD_RT_OFFSET :
525 QM_REG_WFQPFCRD_MSB_RT_OFFSET) +
526 (pf_id % MAX_NUM_PFS_BB);
528 inc_val = QM_WFQ_INC_VAL(pf_wfq);
529 if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
530 DP_NOTICE(p_hwfn, true,
531 "Invalid PF WFQ weight configuration\n");
535 for (i = 0; i < num_tx_pqs; i++) {
536 voq = VOQ(port_id, pq_params[i].tc_id, max_phys_tcs_per_port);
537 OVERWRITE_RT_REG(p_hwfn, crd_reg_offset + voq * MAX_NUM_PFS_BB,
538 (u32)QM_WFQ_CRD_REG_SIGN_BIT);
541 STORE_RT_REG(p_hwfn, QM_REG_WFQPFUPPERBOUND_RT_OFFSET + pf_id,
542 QM_WFQ_UPPER_BOUND | (u32)QM_WFQ_CRD_REG_SIGN_BIT);
543 STORE_RT_REG(p_hwfn, QM_REG_WFQPFWEIGHT_RT_OFFSET + pf_id, inc_val);
547 /* Prepare PF RL runtime init values for the specified PF.
548 * Return -1 on error.
550 static int ecore_pf_rl_rt_init(struct ecore_hwfn *p_hwfn, u8 pf_id, u32 pf_rl)
554 inc_val = QM_RL_INC_VAL(pf_rl);
555 if (inc_val > QM_RL_MAX_INC_VAL) {
556 DP_NOTICE(p_hwfn, true,
557 "Invalid PF rate limit configuration\n");
561 STORE_RT_REG(p_hwfn, QM_REG_RLPFCRD_RT_OFFSET + pf_id,
562 (u32)QM_RL_CRD_REG_SIGN_BIT);
563 STORE_RT_REG(p_hwfn, QM_REG_RLPFUPPERBOUND_RT_OFFSET + pf_id,
564 QM_RL_UPPER_BOUND | (u32)QM_RL_CRD_REG_SIGN_BIT);
565 STORE_RT_REG(p_hwfn, QM_REG_RLPFINCVAL_RT_OFFSET + pf_id, inc_val);
570 /* Prepare VPORT WFQ runtime init values for the specified VPORTs.
571 * Return -1 on error.
573 static int ecore_vp_wfq_rt_init(struct ecore_hwfn *p_hwfn,
575 struct init_qm_vport_params *vport_params)
581 /* Go over all PF VPORTs */
582 for (i = 0; i < num_vports; i++) {
583 if (!vport_params[i].vport_wfq)
586 inc_val = QM_WFQ_INC_VAL(vport_params[i].vport_wfq);
587 if (inc_val > QM_WFQ_MAX_INC_VAL) {
588 DP_NOTICE(p_hwfn, true,
589 "Invalid VPORT WFQ weight configuration\n");
593 /* Each VPORT can have several VPORT PQ IDs for various TCs */
594 for (tc = 0; tc < NUM_OF_TCS; tc++) {
595 vport_pq_id = vport_params[i].first_tx_pq_id[tc];
596 if (vport_pq_id != QM_INVALID_PQ_ID) {
597 STORE_RT_REG(p_hwfn, QM_REG_WFQVPCRD_RT_OFFSET +
599 (u32)QM_WFQ_CRD_REG_SIGN_BIT);
601 QM_REG_WFQVPWEIGHT_RT_OFFSET +
602 vport_pq_id, inc_val);
609 /* Prepare VPORT RL runtime init values for the specified VPORTs.
610 * Return -1 on error.
612 static int ecore_vport_rl_rt_init(struct ecore_hwfn *p_hwfn,
615 struct init_qm_vport_params *vport_params)
620 if (start_vport + num_vports >= MAX_QM_GLOBAL_RLS) {
621 DP_NOTICE(p_hwfn, true,
622 "Invalid VPORT ID for rate limiter configuration\n");
626 /* Go over all PF VPORTs */
627 for (i = 0, vport_id = start_vport; i < num_vports; i++, vport_id++) {
628 u32 inc_val = QM_RL_INC_VAL(vport_params[i].vport_rl);
629 if (inc_val > QM_RL_MAX_INC_VAL) {
630 DP_NOTICE(p_hwfn, true,
631 "Invalid VPORT rate-limit configuration\n");
635 STORE_RT_REG(p_hwfn, QM_REG_RLGLBLCRD_RT_OFFSET + vport_id,
636 (u32)QM_RL_CRD_REG_SIGN_BIT);
638 QM_REG_RLGLBLUPPERBOUND_RT_OFFSET + vport_id,
639 QM_RL_UPPER_BOUND | (u32)QM_RL_CRD_REG_SIGN_BIT);
640 STORE_RT_REG(p_hwfn, QM_REG_RLGLBLINCVAL_RT_OFFSET + vport_id,
647 static bool ecore_poll_on_qm_cmd_ready(struct ecore_hwfn *p_hwfn,
648 struct ecore_ptt *p_ptt)
652 for (i = 0, reg_val = 0; i < QM_STOP_CMD_MAX_POLL_COUNT && !reg_val;
654 OSAL_UDELAY(QM_STOP_CMD_POLL_PERIOD_US);
655 reg_val = ecore_rd(p_hwfn, p_ptt, QM_REG_SDMCMDREADY);
658 /* Check if timeout while waiting for SDM command ready */
659 if (i == QM_STOP_CMD_MAX_POLL_COUNT) {
660 DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG,
661 "Timeout waiting for QM SDM cmd ready signal\n");
668 static bool ecore_send_qm_cmd(struct ecore_hwfn *p_hwfn,
669 struct ecore_ptt *p_ptt,
670 u32 cmd_addr, u32 cmd_data_lsb, u32 cmd_data_msb)
672 if (!ecore_poll_on_qm_cmd_ready(p_hwfn, p_ptt))
675 ecore_wr(p_hwfn, p_ptt, QM_REG_SDMCMDADDR, cmd_addr);
676 ecore_wr(p_hwfn, p_ptt, QM_REG_SDMCMDDATALSB, cmd_data_lsb);
677 ecore_wr(p_hwfn, p_ptt, QM_REG_SDMCMDDATAMSB, cmd_data_msb);
678 ecore_wr(p_hwfn, p_ptt, QM_REG_SDMCMDGO, 1);
679 ecore_wr(p_hwfn, p_ptt, QM_REG_SDMCMDGO, 0);
681 return ecore_poll_on_qm_cmd_ready(p_hwfn, p_ptt);
685 /******************** INTERFACE IMPLEMENTATION *********************/
687 u32 ecore_qm_pf_mem_size(u8 pf_id,
690 u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs)
692 return QM_PQ_MEM_4KB(num_pf_cids) * num_pf_pqs +
693 QM_PQ_MEM_4KB(num_vf_cids) * num_vf_pqs +
694 QM_PQ_MEM_4KB(num_pf_cids + num_tids) * QM_OTHER_PQS_PER_PF;
697 int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn,
698 u8 max_ports_per_engine,
699 u8 max_phys_tcs_per_port,
704 struct init_qm_port_params
705 port_params[MAX_NUM_PORTS])
709 /* Init AFullOprtnstcCrdMask */
710 mask = (QM_OPPOR_LINE_VOQ_DEF <<
711 QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT) |
712 (QM_BYTE_CRD_EN << QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT) |
713 (pf_wfq_en << QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT) |
714 (vport_wfq_en << QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT) |
715 (pf_rl_en << QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT) |
716 (vport_rl_en << QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT) |
717 (QM_OPPOR_FW_STOP_DEF <<
718 QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT) |
719 (QM_OPPOR_PQ_EMPTY_DEF <<
720 QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT);
721 STORE_RT_REG(p_hwfn, QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET, mask);
723 /* Enable/disable PF RL */
724 ecore_enable_pf_rl(p_hwfn, pf_rl_en);
726 /* Enable/disable PF WFQ */
727 ecore_enable_pf_wfq(p_hwfn, pf_wfq_en);
729 /* Enable/disable VPORT RL */
730 ecore_enable_vport_rl(p_hwfn, vport_rl_en);
732 /* Enable/disable VPORT WFQ */
733 ecore_enable_vport_wfq(p_hwfn, vport_wfq_en);
735 /* Init PBF CMDQ line credit */
736 ecore_cmdq_lines_rt_init(p_hwfn, max_ports_per_engine,
737 max_phys_tcs_per_port, port_params);
739 /* Init BTB blocks in PBF */
740 ecore_btb_blocks_rt_init(p_hwfn, max_ports_per_engine,
741 max_phys_tcs_per_port, port_params);
746 int ecore_qm_pf_rt_init(struct ecore_hwfn *p_hwfn,
747 struct ecore_ptt *p_ptt,
750 u8 max_phys_tcs_per_port,
762 struct init_qm_pq_params *pq_params,
763 struct init_qm_vport_params *vport_params)
765 u32 other_mem_size_4kb;
768 other_mem_size_4kb = QM_PQ_MEM_4KB(num_pf_cids + num_tids) *
771 /* Clear first Tx PQ ID array for each VPORT */
772 for (i = 0; i < num_vports; i++)
773 for (tc = 0; tc < NUM_OF_TCS; tc++)
774 vport_params[i].first_tx_pq_id[tc] = QM_INVALID_PQ_ID;
776 /* Map Other PQs (if any) */
777 #if QM_OTHER_PQS_PER_PF > 0
778 ecore_other_pq_map_rt_init(p_hwfn, port_id, pf_id, num_pf_cids,
783 ecore_tx_pq_map_rt_init(p_hwfn, p_ptt, port_id, pf_id,
784 max_phys_tcs_per_port, is_first_pf, num_pf_cids,
785 num_vf_cids, start_pq, num_pf_pqs, num_vf_pqs,
786 start_vport, other_mem_size_4kb, pq_params,
791 if (ecore_pf_wfq_rt_init
792 (p_hwfn, port_id, pf_id, pf_wfq, max_phys_tcs_per_port,
793 num_pf_pqs + num_vf_pqs, pq_params))
797 if (ecore_pf_rl_rt_init(p_hwfn, pf_id, pf_rl))
801 if (ecore_vp_wfq_rt_init(p_hwfn, num_vports, vport_params))
805 if (ecore_vport_rl_rt_init
806 (p_hwfn, start_vport, num_vports, vport_params))
812 int ecore_init_pf_wfq(struct ecore_hwfn *p_hwfn,
813 struct ecore_ptt *p_ptt, u8 pf_id, u16 pf_wfq)
817 inc_val = QM_WFQ_INC_VAL(pf_wfq);
818 if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
819 DP_NOTICE(p_hwfn, true,
820 "Invalid PF WFQ weight configuration\n");
824 ecore_wr(p_hwfn, p_ptt, QM_REG_WFQPFWEIGHT + pf_id * 4, inc_val);
829 int ecore_init_pf_rl(struct ecore_hwfn *p_hwfn,
830 struct ecore_ptt *p_ptt, u8 pf_id, u32 pf_rl)
834 inc_val = QM_RL_INC_VAL(pf_rl);
835 if (inc_val > QM_RL_MAX_INC_VAL) {
836 DP_NOTICE(p_hwfn, true,
837 "Invalid PF rate limit configuration\n");
841 ecore_wr(p_hwfn, p_ptt, QM_REG_RLPFCRD + pf_id * 4,
842 (u32)QM_RL_CRD_REG_SIGN_BIT);
843 ecore_wr(p_hwfn, p_ptt, QM_REG_RLPFINCVAL + pf_id * 4, inc_val);
848 int ecore_init_vport_wfq(struct ecore_hwfn *p_hwfn,
849 struct ecore_ptt *p_ptt,
850 u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq)
856 inc_val = QM_WFQ_INC_VAL(vport_wfq);
857 if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
858 DP_NOTICE(p_hwfn, true,
859 "Invalid VPORT WFQ weight configuration\n");
863 for (tc = 0; tc < NUM_OF_TCS; tc++) {
864 vport_pq_id = first_tx_pq_id[tc];
865 if (vport_pq_id != QM_INVALID_PQ_ID) {
866 ecore_wr(p_hwfn, p_ptt,
867 QM_REG_WFQVPWEIGHT + vport_pq_id * 4, inc_val);
874 int ecore_init_vport_rl(struct ecore_hwfn *p_hwfn,
875 struct ecore_ptt *p_ptt, u8 vport_id, u32 vport_rl)
877 u32 inc_val, max_qm_global_rls = MAX_QM_GLOBAL_RLS;
879 if (vport_id >= max_qm_global_rls) {
880 DP_NOTICE(p_hwfn, true,
881 "Invalid VPORT ID for rate limiter configuration\n");
885 inc_val = QM_RL_INC_VAL(vport_rl);
886 if (inc_val > QM_RL_MAX_INC_VAL) {
887 DP_NOTICE(p_hwfn, true,
888 "Invalid VPORT rate-limit configuration\n");
892 ecore_wr(p_hwfn, p_ptt, QM_REG_RLGLBLCRD + vport_id * 4,
893 (u32)QM_RL_CRD_REG_SIGN_BIT);
894 ecore_wr(p_hwfn, p_ptt, QM_REG_RLGLBLINCVAL + vport_id * 4, inc_val);
899 bool ecore_send_qm_stop_cmd(struct ecore_hwfn *p_hwfn,
900 struct ecore_ptt *p_ptt,
902 bool is_tx_pq, u16 start_pq, u16 num_pqs)
904 u32 cmd_arr[QM_CMD_STRUCT_SIZE(QM_STOP_CMD)] = { 0 };
905 u32 pq_mask = 0, last_pq, pq_id;
907 last_pq = start_pq + num_pqs - 1;
909 /* Set command's PQ type */
910 QM_CMD_SET_FIELD(cmd_arr, QM_STOP_CMD, PQ_TYPE, is_tx_pq ? 0 : 1);
912 /* Go over requested PQs */
913 for (pq_id = start_pq; pq_id <= last_pq; pq_id++) {
914 /* Set PQ bit in mask (stop command only) */
916 pq_mask |= (1 << (pq_id % QM_STOP_PQ_MASK_WIDTH));
918 /* If last PQ or end of PQ mask, write command */
919 if ((pq_id == last_pq) ||
920 (pq_id % QM_STOP_PQ_MASK_WIDTH ==
921 (QM_STOP_PQ_MASK_WIDTH - 1))) {
922 QM_CMD_SET_FIELD(cmd_arr, QM_STOP_CMD, PAUSE_MASK,
924 QM_CMD_SET_FIELD(cmd_arr, QM_STOP_CMD, GROUP_ID,
925 pq_id / QM_STOP_PQ_MASK_WIDTH);
926 if (!ecore_send_qm_cmd
927 (p_hwfn, p_ptt, QM_STOP_CMD_ADDR, cmd_arr[0],
938 /* NIG: ETS configuration constants */
939 #define NIG_TX_ETS_CLIENT_OFFSET 4
940 #define NIG_LB_ETS_CLIENT_OFFSET 1
941 #define NIG_ETS_MIN_WFQ_BYTES 1600
943 /* NIG: ETS constants */
944 #define NIG_ETS_UP_BOUND(weight, mtu) \
945 (2 * ((weight) > (mtu) ? (weight) : (mtu)))
947 /* NIG: RL constants */
949 /* Byte base type value */
950 #define NIG_RL_BASE_TYPE 1
953 #define NIG_RL_PERIOD 1
955 /* Period in 25MHz cycles */
956 #define NIG_RL_PERIOD_CLK_25M (25 * NIG_RL_PERIOD)
959 #define NIG_RL_INC_VAL(rate) (((rate) * NIG_RL_PERIOD) / 8)
961 #define NIG_RL_MAX_VAL(inc_val, mtu) \
962 (2 * ((inc_val) > (mtu) ? (inc_val) : (mtu)))
964 /* NIG: packet prioritry configuration constants */
965 #define NIG_PRIORITY_MAP_TC_BITS 4
968 void ecore_init_nig_ets(struct ecore_hwfn *p_hwfn,
969 struct ecore_ptt *p_ptt,
970 struct init_ets_req *req, bool is_lb)
972 u32 min_weight, tc_weight_base_addr, tc_weight_addr_diff;
973 u32 tc_bound_base_addr, tc_bound_addr_diff;
974 u8 sp_tc_map = 0, wfq_tc_map = 0;
975 u8 tc, num_tc, tc_client_offset;
977 num_tc = is_lb ? NUM_OF_TCS : NUM_OF_PHYS_TCS;
978 tc_client_offset = is_lb ? NIG_LB_ETS_CLIENT_OFFSET :
979 NIG_TX_ETS_CLIENT_OFFSET;
980 min_weight = 0xffffffff;
981 tc_weight_base_addr = is_lb ? NIG_REG_LB_ARB_CREDIT_WEIGHT_0 :
982 NIG_REG_TX_ARB_CREDIT_WEIGHT_0;
983 tc_weight_addr_diff = is_lb ? NIG_REG_LB_ARB_CREDIT_WEIGHT_1 -
984 NIG_REG_LB_ARB_CREDIT_WEIGHT_0 :
985 NIG_REG_TX_ARB_CREDIT_WEIGHT_1 -
986 NIG_REG_TX_ARB_CREDIT_WEIGHT_0;
987 tc_bound_base_addr = is_lb ? NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_0 :
988 NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_0;
989 tc_bound_addr_diff = is_lb ? NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_1 -
990 NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_0 :
991 NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_1 -
992 NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_0;
994 for (tc = 0; tc < num_tc; tc++) {
995 struct init_ets_tc_req *tc_req = &req->tc_req[tc];
999 sp_tc_map |= (1 << tc);
1001 if (!tc_req->use_wfq)
1004 /* Update WFQ map */
1005 wfq_tc_map |= (1 << tc);
1007 /* Find minimal weight */
1008 if (tc_req->weight < min_weight)
1009 min_weight = tc_req->weight;
1013 ecore_wr(p_hwfn, p_ptt,
1014 is_lb ? NIG_REG_LB_ARB_CLIENT_IS_STRICT :
1015 NIG_REG_TX_ARB_CLIENT_IS_STRICT,
1016 (sp_tc_map << tc_client_offset));
1019 ecore_wr(p_hwfn, p_ptt,
1020 is_lb ? NIG_REG_LB_ARB_CLIENT_IS_SUBJECT2WFQ :
1021 NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
1022 (wfq_tc_map << tc_client_offset));
1023 /* write WFQ weights */
1024 for (tc = 0; tc < num_tc; tc++, tc_client_offset++) {
1025 struct init_ets_tc_req *tc_req = &req->tc_req[tc];
1028 if (!tc_req->use_wfq)
1031 /* Translate weight to bytes */
1032 byte_weight = (NIG_ETS_MIN_WFQ_BYTES * tc_req->weight) /
1035 /* Write WFQ weight */
1036 ecore_wr(p_hwfn, p_ptt, tc_weight_base_addr +
1037 tc_weight_addr_diff * tc_client_offset, byte_weight);
1039 /* Write WFQ upper bound */
1040 ecore_wr(p_hwfn, p_ptt, tc_bound_base_addr +
1041 tc_bound_addr_diff * tc_client_offset,
1042 NIG_ETS_UP_BOUND(byte_weight, req->mtu));
1046 void ecore_init_nig_lb_rl(struct ecore_hwfn *p_hwfn,
1047 struct ecore_ptt *p_ptt,
1048 struct init_nig_lb_rl_req *req)
1050 u32 ctrl, inc_val, reg_offset;
1053 /* Disable global MAC+LB RL */
1056 NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_BASE_TYPE_SHIFT;
1057 ecore_wr(p_hwfn, p_ptt, NIG_REG_TX_LB_GLBRATELIMIT_CTRL, ctrl);
1059 /* Configure and enable global MAC+LB RL */
1060 if (req->lb_mac_rate) {
1062 ecore_wr(p_hwfn, p_ptt, NIG_REG_TX_LB_GLBRATELIMIT_INC_PERIOD,
1063 NIG_RL_PERIOD_CLK_25M);
1064 inc_val = NIG_RL_INC_VAL(req->lb_mac_rate);
1065 ecore_wr(p_hwfn, p_ptt, NIG_REG_TX_LB_GLBRATELIMIT_INC_VALUE,
1067 ecore_wr(p_hwfn, p_ptt, NIG_REG_TX_LB_GLBRATELIMIT_MAX_VALUE,
1068 NIG_RL_MAX_VAL(inc_val, req->mtu));
1073 NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_EN_SHIFT;
1074 ecore_wr(p_hwfn, p_ptt, NIG_REG_TX_LB_GLBRATELIMIT_CTRL, ctrl);
1077 /* Disable global LB-only RL */
1080 NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_BASE_TYPE_SHIFT;
1081 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_BRBRATELIMIT_CTRL, ctrl);
1083 /* Configure and enable global LB-only RL */
1086 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_BRBRATELIMIT_INC_PERIOD,
1087 NIG_RL_PERIOD_CLK_25M);
1088 inc_val = NIG_RL_INC_VAL(req->lb_rate);
1089 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_BRBRATELIMIT_INC_VALUE,
1091 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_BRBRATELIMIT_MAX_VALUE,
1092 NIG_RL_MAX_VAL(inc_val, req->mtu));
1096 1 << NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_EN_SHIFT;
1097 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_BRBRATELIMIT_CTRL, ctrl);
1101 for (tc = 0, reg_offset = 0; tc < NUM_OF_PHYS_TCS;
1102 tc++, reg_offset += 4) {
1106 NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_BASE_TYPE_0_SHIFT;
1107 ecore_wr(p_hwfn, p_ptt,
1108 NIG_REG_LB_TCRATELIMIT_CTRL_0 + reg_offset, ctrl);
1110 /* Configure and enable TC RL */
1111 if (!req->tc_rate[tc])
1115 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_INC_PERIOD_0 +
1116 reg_offset, NIG_RL_PERIOD_CLK_25M);
1117 inc_val = NIG_RL_INC_VAL(req->tc_rate[tc]);
1118 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_INC_VALUE_0 +
1119 reg_offset, inc_val);
1120 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_MAX_VALUE_0 +
1121 reg_offset, NIG_RL_MAX_VAL(inc_val, req->mtu));
1125 NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_EN_0_SHIFT;
1126 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_CTRL_0 +
1131 void ecore_init_nig_pri_tc_map(struct ecore_hwfn *p_hwfn,
1132 struct ecore_ptt *p_ptt,
1133 struct init_nig_pri_tc_map_req *req)
1135 u8 tc_pri_mask[NUM_OF_PHYS_TCS] = { 0 };
1136 u32 pri_tc_mask = 0;
1139 for (pri = 0; pri < NUM_OF_VLAN_PRIORITIES; pri++) {
1140 if (!req->pri[pri].valid)
1143 pri_tc_mask |= (req->pri[pri].tc_id <<
1144 (pri * NIG_PRIORITY_MAP_TC_BITS));
1145 tc_pri_mask[req->pri[pri].tc_id] |= (1 << pri);
1148 /* Write priority -> TC mask */
1149 ecore_wr(p_hwfn, p_ptt, NIG_REG_PKT_PRIORITY_TO_TC, pri_tc_mask);
1151 /* Write TC -> priority mask */
1152 for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
1153 ecore_wr(p_hwfn, p_ptt, NIG_REG_PRIORITY_FOR_TC_0 + tc * 4,
1155 ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_TC0_PRIORITY_MASK + tc * 4,
1161 /* PRS: ETS configuration constants */
1162 #define PRS_ETS_MIN_WFQ_BYTES 1600
1163 #define PRS_ETS_UP_BOUND(weight, mtu) \
1164 (2 * ((weight) > (mtu) ? (weight) : (mtu)))
1167 void ecore_init_prs_ets(struct ecore_hwfn *p_hwfn,
1168 struct ecore_ptt *p_ptt, struct init_ets_req *req)
1170 u32 tc_weight_addr_diff, tc_bound_addr_diff, min_weight = 0xffffffff;
1171 u8 tc, sp_tc_map = 0, wfq_tc_map = 0;
1173 tc_weight_addr_diff = PRS_REG_ETS_ARB_CREDIT_WEIGHT_1 -
1174 PRS_REG_ETS_ARB_CREDIT_WEIGHT_0;
1175 tc_bound_addr_diff = PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_1 -
1176 PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_0;
1178 for (tc = 0; tc < NUM_OF_TCS; tc++) {
1179 struct init_ets_tc_req *tc_req = &req->tc_req[tc];
1183 sp_tc_map |= (1 << tc);
1185 if (!tc_req->use_wfq)
1188 /* Update WFQ map */
1189 wfq_tc_map |= (1 << tc);
1191 /* Find minimal weight */
1192 if (tc_req->weight < min_weight)
1193 min_weight = tc_req->weight;
1197 ecore_wr(p_hwfn, p_ptt, PRS_REG_ETS_ARB_CLIENT_IS_STRICT, sp_tc_map);
1200 ecore_wr(p_hwfn, p_ptt, PRS_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ,
1203 /* write WFQ weights */
1204 for (tc = 0; tc < NUM_OF_TCS; tc++) {
1205 struct init_ets_tc_req *tc_req = &req->tc_req[tc];
1208 if (!tc_req->use_wfq)
1211 /* Translate weight to bytes */
1212 byte_weight = (PRS_ETS_MIN_WFQ_BYTES * tc_req->weight) /
1215 /* Write WFQ weight */
1216 ecore_wr(p_hwfn, p_ptt, PRS_REG_ETS_ARB_CREDIT_WEIGHT_0 + tc *
1217 tc_weight_addr_diff, byte_weight);
1219 /* Write WFQ upper bound */
1220 ecore_wr(p_hwfn, p_ptt, PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_0 +
1221 tc * tc_bound_addr_diff, PRS_ETS_UP_BOUND(byte_weight,
1227 /* BRB: RAM configuration constants */
1228 #define BRB_TOTAL_RAM_BLOCKS_BB 4800
1229 #define BRB_TOTAL_RAM_BLOCKS_K2 5632
1230 #define BRB_BLOCK_SIZE 128
1231 #define BRB_MIN_BLOCKS_PER_TC 9
1232 #define BRB_HYST_BYTES 10240
1233 #define BRB_HYST_BLOCKS (BRB_HYST_BYTES / BRB_BLOCK_SIZE)
1235 /* Temporary big RAM allocation - should be updated */
1236 void ecore_init_brb_ram(struct ecore_hwfn *p_hwfn,
1237 struct ecore_ptt *p_ptt, struct init_brb_ram_req *req)
1239 u32 tc_headroom_blocks, min_pkt_size_blocks, total_blocks;
1240 u32 active_port_blocks, reg_offset = 0;
1241 u8 port, active_ports = 0;
1243 tc_headroom_blocks = (u32)DIV_ROUND_UP(req->headroom_per_tc,
1245 min_pkt_size_blocks = (u32)DIV_ROUND_UP(req->min_pkt_size,
1247 total_blocks = ECORE_IS_K2(p_hwfn->p_dev) ? BRB_TOTAL_RAM_BLOCKS_K2 :
1248 BRB_TOTAL_RAM_BLOCKS_BB;
1250 /* Find number of active ports */
1251 for (port = 0; port < MAX_NUM_PORTS; port++)
1252 if (req->num_active_tcs[port])
1255 active_port_blocks = (u32)(total_blocks / active_ports);
1257 for (port = 0; port < req->max_ports_per_engine; port++) {
1258 u32 port_blocks, port_shared_blocks, port_guaranteed_blocks;
1259 u32 full_xoff_th, full_xon_th, pause_xoff_th, pause_xon_th;
1260 u32 tc_guaranteed_blocks;
1263 /* Calculate per-port sizes */
1264 tc_guaranteed_blocks = (u32)DIV_ROUND_UP(req->guranteed_per_tc,
1266 port_blocks = req->num_active_tcs[port] ? active_port_blocks :
1268 port_guaranteed_blocks = req->num_active_tcs[port] *
1269 tc_guaranteed_blocks;
1270 port_shared_blocks = port_blocks - port_guaranteed_blocks;
1271 full_xoff_th = req->num_active_tcs[port] *
1272 BRB_MIN_BLOCKS_PER_TC;
1273 full_xon_th = full_xoff_th + min_pkt_size_blocks;
1274 pause_xoff_th = tc_headroom_blocks;
1275 pause_xon_th = pause_xoff_th + min_pkt_size_blocks;
1277 /* Init total size per port */
1278 ecore_wr(p_hwfn, p_ptt, BRB_REG_TOTAL_MAC_SIZE + port * 4,
1281 /* Init shared size per port */
1282 ecore_wr(p_hwfn, p_ptt, BRB_REG_SHARED_HR_AREA + port * 4,
1283 port_shared_blocks);
1285 for (tc = 0; tc < NUM_OF_TCS; tc++, reg_offset += 4) {
1286 /* Clear init values for non-active TCs */
1287 if (tc == req->num_active_tcs[port]) {
1288 tc_guaranteed_blocks = 0;
1295 /* Init guaranteed size per TC */
1296 ecore_wr(p_hwfn, p_ptt,
1297 BRB_REG_TC_GUARANTIED_0 + reg_offset,
1298 tc_guaranteed_blocks);
1299 ecore_wr(p_hwfn, p_ptt,
1300 BRB_REG_MAIN_TC_GUARANTIED_HYST_0 + reg_offset,
1303 /* Init pause/full thresholds per physical TC - for
1306 ecore_wr(p_hwfn, p_ptt,
1307 BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_0 +
1308 reg_offset, full_xoff_th);
1309 ecore_wr(p_hwfn, p_ptt,
1310 BRB_REG_LB_TC_FULL_XON_THRESHOLD_0 +
1311 reg_offset, full_xon_th);
1312 ecore_wr(p_hwfn, p_ptt,
1313 BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_0 +
1314 reg_offset, pause_xoff_th);
1315 ecore_wr(p_hwfn, p_ptt,
1316 BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_0 +
1317 reg_offset, pause_xon_th);
1319 /* Init pause/full thresholds per physical TC - for
1322 ecore_wr(p_hwfn, p_ptt,
1323 BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_0 +
1324 reg_offset, full_xoff_th);
1325 ecore_wr(p_hwfn, p_ptt,
1326 BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_0 +
1327 reg_offset, full_xon_th);
1328 ecore_wr(p_hwfn, p_ptt,
1329 BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_0 +
1330 reg_offset, pause_xoff_th);
1331 ecore_wr(p_hwfn, p_ptt,
1332 BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_0 +
1333 reg_offset, pause_xon_th);
1338 /* In MF should be called once per engine to set EtherType of OuterTag */
1339 void ecore_set_engine_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn,
1340 struct ecore_ptt *p_ptt, u32 ethType)
1342 /* Update PRS register */
1343 STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET, ethType);
1345 /* Update NIG register */
1346 STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET, ethType);
1348 /* Update PBF register */
1349 STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET, ethType);
1352 /* In MF should be called once per port to set EtherType of OuterTag */
1353 void ecore_set_port_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn,
1354 struct ecore_ptt *p_ptt, u32 ethType)
1356 /* Update DORQ register */
1357 STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET, ethType);
1360 #define SET_TUNNEL_TYPE_ENABLE_BIT(var, offset, enable) \
1361 (var = ((var) & ~(1 << (offset))) | ((enable) ? (1 << (offset)) : 0))
1362 #define PRS_ETH_TUNN_FIC_FORMAT -188897008
1363 void ecore_set_vxlan_dest_port(struct ecore_hwfn *p_hwfn,
1364 struct ecore_ptt *p_ptt, u16 dest_port)
1366 /* Update PRS register */
1367 ecore_wr(p_hwfn, p_ptt, PRS_REG_VXLAN_PORT, dest_port);
1369 /* Update NIG register */
1370 ecore_wr(p_hwfn, p_ptt, NIG_REG_VXLAN_CTRL, dest_port);
1372 /* Update PBF register */
1373 ecore_wr(p_hwfn, p_ptt, PBF_REG_VXLAN_PORT, dest_port);
1376 void ecore_set_vxlan_enable(struct ecore_hwfn *p_hwfn,
1377 struct ecore_ptt *p_ptt, bool vxlan_enable)
1381 /* Update PRS register */
1382 reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
1383 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val,
1384 PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT,
1386 ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
1388 ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
1389 (u32)PRS_ETH_TUNN_FIC_FORMAT);
1392 /* Update NIG register */
1393 reg_val = ecore_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
1394 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val,
1395 NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT,
1397 ecore_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val);
1399 /* Update DORQ register */
1400 ecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN,
1401 vxlan_enable ? 1 : 0);
1404 void ecore_set_gre_enable(struct ecore_hwfn *p_hwfn,
1405 struct ecore_ptt *p_ptt,
1406 bool eth_gre_enable, bool ip_gre_enable)
1410 /* Update PRS register */
1411 reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
1412 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val,
1413 PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT,
1415 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val,
1416 PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT,
1418 ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
1420 ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
1421 (u32)PRS_ETH_TUNN_FIC_FORMAT);
1424 /* Update NIG register */
1425 reg_val = ecore_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
1426 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val,
1427 NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT,
1429 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val,
1430 NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT,
1432 ecore_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val);
1434 /* Update DORQ registers */
1435 ecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN,
1436 eth_gre_enable ? 1 : 0);
1437 ecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN,
1438 ip_gre_enable ? 1 : 0);
1441 void ecore_set_geneve_dest_port(struct ecore_hwfn *p_hwfn,
1442 struct ecore_ptt *p_ptt, u16 dest_port)
1444 /* Update PRS register */
1445 ecore_wr(p_hwfn, p_ptt, PRS_REG_NGE_PORT, dest_port);
1447 /* Update NIG register */
1448 ecore_wr(p_hwfn, p_ptt, NIG_REG_NGE_PORT, dest_port);
1450 /* Update PBF register */
1451 ecore_wr(p_hwfn, p_ptt, PBF_REG_NGE_PORT, dest_port);
1454 void ecore_set_geneve_enable(struct ecore_hwfn *p_hwfn,
1455 struct ecore_ptt *p_ptt,
1456 bool eth_geneve_enable, bool ip_geneve_enable)
1460 /* Update PRS register */
1461 reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
1462 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val,
1463 PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT,
1465 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val,
1466 PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT,
1468 ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
1470 ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
1471 (u32)PRS_ETH_TUNN_FIC_FORMAT);
1474 /* Update NIG register */
1475 ecore_wr(p_hwfn, p_ptt, NIG_REG_NGE_ETH_ENABLE,
1476 eth_geneve_enable ? 1 : 0);
1477 ecore_wr(p_hwfn, p_ptt, NIG_REG_NGE_IP_ENABLE,
1478 ip_geneve_enable ? 1 : 0);
1480 /* EDPM with geneve tunnel not supported in BB */
1481 if (ECORE_IS_BB_B0(p_hwfn->p_dev))
1484 /* Update DORQ registers */
1485 ecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5,
1486 eth_geneve_enable ? 1 : 0);
1487 ecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5,
1488 ip_geneve_enable ? 1 : 0);
1492 #define T_ETH_PACKET_ACTION_GFT_EVENTID 23
1493 #define PARSER_ETH_CONN_GFT_ACTION_CM_HDR 272
1494 #define T_ETH_PACKET_MATCH_RFS_EVENTID 25
1495 #define PARSER_ETH_CONN_CM_HDR 0
1496 #define CAM_LINE_SIZE sizeof(u32)
1497 #define RAM_LINE_SIZE sizeof(u64)
1498 #define REG_SIZE sizeof(u32)
1501 void ecore_set_gft_event_id_cm_hdr(struct ecore_hwfn *p_hwfn,
1502 struct ecore_ptt *p_ptt)
1504 u32 rfs_cm_hdr_event_id;
1506 /* Set RFS event ID to be awakened i Tstorm By Prs */
1507 rfs_cm_hdr_event_id = ecore_rd(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT);
1508 rfs_cm_hdr_event_id |= T_ETH_PACKET_ACTION_GFT_EVENTID <<
1509 PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT;
1510 rfs_cm_hdr_event_id |= PARSER_ETH_CONN_GFT_ACTION_CM_HDR <<
1511 PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT;
1512 ecore_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, rfs_cm_hdr_event_id);
1515 void ecore_set_rfs_mode_enable(struct ecore_hwfn *p_hwfn,
1516 struct ecore_ptt *p_ptt,
1523 u32 rfs_cm_hdr_event_id = ecore_rd(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT);
1524 union gft_cam_line_union camLine;
1525 struct gft_ram_line ramLine;
1526 u32 *ramLinePointer = (u32 *)&ramLine;
1530 DP_NOTICE(p_hwfn, true,
1531 "set_rfs_mode_enable: must accept at "
1532 "least on of - ipv4 or ipv6");
1535 DP_NOTICE(p_hwfn, true,
1536 "set_rfs_mode_enable: must accept at "
1537 "least on of - udp or tcp");
1539 /* Set RFS event ID to be awakened i Tstorm By Prs */
1540 rfs_cm_hdr_event_id |= T_ETH_PACKET_MATCH_RFS_EVENTID <<
1541 PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT;
1542 rfs_cm_hdr_event_id |= PARSER_ETH_CONN_CM_HDR <<
1543 PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT;
1544 ecore_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, rfs_cm_hdr_event_id);
1546 /* Configure Registers for RFS mode */
1548 /* Enable gft search */
1549 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 1);
1550 ecore_wr(p_hwfn, p_ptt, PRS_REG_LOAD_L2_FILTER, 0); /* do not load
1554 camLine.cam_line_mapped.camline = 0;
1556 /* Cam line is now valid!! */
1557 SET_FIELD(camLine.cam_line_mapped.camline,
1558 GFT_CAM_LINE_MAPPED_VALID, 1);
1560 /* Filters are per PF!! */
1561 SET_FIELD(camLine.cam_line_mapped.camline,
1562 GFT_CAM_LINE_MAPPED_PF_ID_MASK, 1);
1563 SET_FIELD(camLine.cam_line_mapped.camline,
1564 GFT_CAM_LINE_MAPPED_PF_ID, pf_id);
1566 if (!(tcp && udp)) {
1567 SET_FIELD(camLine.cam_line_mapped.camline,
1568 GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK,
1569 GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK);
1571 SET_FIELD(camLine.cam_line_mapped.camline,
1572 GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE,
1573 GFT_PROFILE_TCP_PROTOCOL);
1575 SET_FIELD(camLine.cam_line_mapped.camline,
1576 GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE,
1577 GFT_PROFILE_UDP_PROTOCOL);
1580 if (!(ipv4 && ipv6)) {
1581 SET_FIELD(camLine.cam_line_mapped.camline,
1582 GFT_CAM_LINE_MAPPED_IP_VERSION_MASK, 1);
1584 SET_FIELD(camLine.cam_line_mapped.camline,
1585 GFT_CAM_LINE_MAPPED_IP_VERSION,
1588 SET_FIELD(camLine.cam_line_mapped.camline,
1589 GFT_CAM_LINE_MAPPED_IP_VERSION,
1593 /* Write characteristics to cam */
1594 ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id,
1595 camLine.cam_line_mapped.camline);
1596 camLine.cam_line_mapped.camline =
1597 ecore_rd(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id);
1599 /* Write line to RAM - compare to filter 4 tuple */
1602 SET_FIELD(ramLine.hi, GFT_RAM_LINE_DST_IP, 1);
1603 SET_FIELD(ramLine.hi, GFT_RAM_LINE_SRC_IP, 1);
1604 SET_FIELD(ramLine.hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1);
1605 SET_FIELD(ramLine.lo, GFT_RAM_LINE_ETHERTYPE, 1);
1606 SET_FIELD(ramLine.lo, GFT_RAM_LINE_SRC_PORT, 1);
1607 SET_FIELD(ramLine.lo, GFT_RAM_LINE_DST_PORT, 1);
1609 /* Each iteration write to reg */
1610 for (i = 0; i < RAM_LINE_SIZE / REG_SIZE; i++)
1611 ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM +
1612 RAM_LINE_SIZE * pf_id +
1613 i * REG_SIZE, *(ramLinePointer + i));
1615 /* Set default profile so that no filter match will happen */
1616 ramLine.lo = 0xffff;
1617 ramLine.hi = 0xffff;
1618 for (i = 0; i < RAM_LINE_SIZE / REG_SIZE; i++)
1619 ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM +
1620 RAM_LINE_SIZE * PRS_GFT_CAM_LINES_NO_MATCH +
1621 i * REG_SIZE, *(ramLinePointer + i));
1624 /* Configure VF zone size mode */
1625 void ecore_config_vf_zone_size_mode(struct ecore_hwfn *p_hwfn,
1626 struct ecore_ptt *p_ptt, u16 mode,
1629 u32 msdm_vf_size_log = MSTORM_VF_ZONE_DEFAULT_SIZE_LOG;
1630 u32 msdm_vf_offset_mask;
1632 if (mode == VF_ZONE_SIZE_MODE_DOUBLE)
1633 msdm_vf_size_log += 1;
1634 else if (mode == VF_ZONE_SIZE_MODE_QUAD)
1635 msdm_vf_size_log += 2;
1637 msdm_vf_offset_mask = (1 << msdm_vf_size_log) - 1;
1640 STORE_RT_REG(p_hwfn,
1641 PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET,
1643 STORE_RT_REG(p_hwfn,
1644 PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET,
1645 msdm_vf_offset_mask);
1647 ecore_wr(p_hwfn, p_ptt,
1648 PGLUE_B_REG_MSDM_VF_SHIFT_B, msdm_vf_size_log);
1649 ecore_wr(p_hwfn, p_ptt,
1650 PGLUE_B_REG_MSDM_OFFSET_MASK_B, msdm_vf_offset_mask);
1654 /* Get mstorm statistics for offset by VF zone size mode */
1655 u32 ecore_get_mstorm_queue_stat_offset(struct ecore_hwfn *p_hwfn,
1657 u16 vf_zone_size_mode)
1659 u32 offset = MSTORM_QUEUE_STAT_OFFSET(stat_cnt_id);
1661 if ((vf_zone_size_mode != VF_ZONE_SIZE_MODE_DEFAULT) &&
1662 (stat_cnt_id > MAX_NUM_PFS)) {
1663 if (vf_zone_size_mode == VF_ZONE_SIZE_MODE_DOUBLE)
1664 offset += (1 << MSTORM_VF_ZONE_DEFAULT_SIZE_LOG) *
1665 (stat_cnt_id - MAX_NUM_PFS);
1666 else if (vf_zone_size_mode == VF_ZONE_SIZE_MODE_QUAD)
1667 offset += 3 * (1 << MSTORM_VF_ZONE_DEFAULT_SIZE_LOG) *
1668 (stat_cnt_id - MAX_NUM_PFS);
1674 /* Get mstorm VF producer offset by VF zone size mode */
1675 u32 ecore_get_mstorm_eth_vf_prods_offset(struct ecore_hwfn *p_hwfn,
1678 u16 vf_zone_size_mode)
1680 u32 offset = MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id);
1682 if (vf_zone_size_mode != VF_ZONE_SIZE_MODE_DEFAULT) {
1683 if (vf_zone_size_mode == VF_ZONE_SIZE_MODE_DOUBLE)
1684 offset += (1 << MSTORM_VF_ZONE_DEFAULT_SIZE_LOG) *
1686 else if (vf_zone_size_mode == VF_ZONE_SIZE_MODE_QUAD)
1687 offset += 3 * (1 << MSTORM_VF_ZONE_DEFAULT_SIZE_LOG) *
1694 /* Calculate CRC8 of first 4 bytes in buf */
1695 static u8 ecore_calc_crc8(const u8 *buf)
1697 u32 i, j, crc = 0xff << 8;
1699 /* CRC-8 polynomial */
1702 for (j = 0; j < 4; j++, buf++) {
1704 for (i = 0; i < 8; i++) {
1712 return (u8)(crc >> 8);
1715 /* Calculate and return CDU validation byte per conneciton type / region /
1718 static u8 ecore_calc_cdu_validation_byte(u8 conn_type, u8 region,
1721 const u8 validation_cfg = CDU_VALIDATION_DEFAULT_CFG;
1722 u8 crc, validation_byte = 0;
1723 u32 validation_string = 0;
1724 const u8 *data_to_crc_rev;
1727 data_to_crc_rev = (const u8 *)&validation_string;
1730 * The CRC is calculated on the String-to-compress:
1731 * [31:8] = {CID[31:20],CID[11:0]}
1735 if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_CID) & 1)
1736 validation_string |= (cid & 0xFFF00000) | ((cid & 0xFFF) << 8);
1738 if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_REGION) & 1)
1739 validation_string |= ((region & 0xF) << 4);
1741 if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_TYPE) & 1)
1742 validation_string |= (conn_type & 0xF);
1744 /* Convert to big-endian (ntoh())*/
1745 data_to_crc[0] = data_to_crc_rev[3];
1746 data_to_crc[1] = data_to_crc_rev[2];
1747 data_to_crc[2] = data_to_crc_rev[1];
1748 data_to_crc[3] = data_to_crc_rev[0];
1750 crc = ecore_calc_crc8(data_to_crc);
1752 validation_byte |= ((validation_cfg >>
1753 CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE) & 1) << 7;
1755 if ((validation_cfg >>
1756 CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT) & 1)
1757 validation_byte |= ((conn_type & 0xF) << 3) | (crc & 0x7);
1759 validation_byte |= crc & 0x7F;
1761 return validation_byte;
1764 /* Calcualte and set validation bytes for session context */
1765 void ecore_calc_session_ctx_validation(void *p_ctx_mem, u16 ctx_size,
1766 u8 ctx_type, u32 cid)
1768 u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx;
1770 p_ctx = (u8 *)p_ctx_mem;
1771 x_val_ptr = &p_ctx[con_region_offsets[0][ctx_type]];
1772 t_val_ptr = &p_ctx[con_region_offsets[1][ctx_type]];
1773 u_val_ptr = &p_ctx[con_region_offsets[2][ctx_type]];
1775 OSAL_MEMSET(p_ctx, 0, ctx_size);
1777 *x_val_ptr = ecore_calc_cdu_validation_byte(ctx_type, 3, cid);
1778 *t_val_ptr = ecore_calc_cdu_validation_byte(ctx_type, 4, cid);
1779 *u_val_ptr = ecore_calc_cdu_validation_byte(ctx_type, 5, cid);
1782 /* Calcualte and set validation bytes for task context */
1783 void ecore_calc_task_ctx_validation(void *p_ctx_mem, u16 ctx_size,
1784 u8 ctx_type, u32 tid)
1786 u8 *p_ctx, *region1_val_ptr;
1788 p_ctx = (u8 *)p_ctx_mem;
1789 region1_val_ptr = &p_ctx[task_region_offsets[0][ctx_type]];
1791 OSAL_MEMSET(p_ctx, 0, ctx_size);
1793 *region1_val_ptr = ecore_calc_cdu_validation_byte(ctx_type, 1, tid);
1796 /* Memset session context to 0 while preserving validation bytes */
1797 void ecore_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type)
1799 u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx;
1800 u8 x_val, t_val, u_val;
1802 p_ctx = (u8 *)p_ctx_mem;
1803 x_val_ptr = &p_ctx[con_region_offsets[0][ctx_type]];
1804 t_val_ptr = &p_ctx[con_region_offsets[1][ctx_type]];
1805 u_val_ptr = &p_ctx[con_region_offsets[2][ctx_type]];
1811 OSAL_MEMSET(p_ctx, 0, ctx_size);
1818 /* Memset task context to 0 while preserving validation bytes */
1819 void ecore_memset_task_ctx(void *p_ctx_mem, const u32 ctx_size,
1822 u8 *p_ctx, *region1_val_ptr;
1825 p_ctx = (u8 *)p_ctx_mem;
1826 region1_val_ptr = &p_ctx[task_region_offsets[0][ctx_type]];
1828 region1_val = *region1_val_ptr;
1830 OSAL_MEMSET(p_ctx, 0, ctx_size);
1832 *region1_val_ptr = region1_val;
1835 /* Enable and configure context validation */
1836 void ecore_enable_context_validation(struct ecore_hwfn *p_hwfn,
1837 struct ecore_ptt *p_ptt)
1841 /* Enable validation for connection region 3 - bits [31:24] */
1842 ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 24;
1843 ecore_wr(p_hwfn, p_ptt, CDU_REG_CCFC_CTX_VALID0, ctx_validation);
1845 /* Enable validation for connection region 5 - bits [15: 8] */
1846 ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 8;
1847 ecore_wr(p_hwfn, p_ptt, CDU_REG_CCFC_CTX_VALID1, ctx_validation);
1849 /* Enable validation for connection region 1 - bits [15: 8] */
1850 ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 8;
1851 ecore_wr(p_hwfn, p_ptt, CDU_REG_TCFC_CTX_VALID0, ctx_validation);