1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
7 #ifndef _INIT_FW_FUNCS_H
8 #define _INIT_FW_FUNCS_H
9 #include "ecore_hsi_common.h"
10 #include "ecore_hsi_eth.h"
12 /* Returns the VOQ based on port and TC */
13 #define VOQ(port, tc, max_phys_tcs_per_port) \
14 ((tc) == PURE_LB_TC ? NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB + (port) : \
15 (port) * (max_phys_tcs_per_port) + (tc))
17 struct init_qm_pq_params;
20 * @brief ecore_qm_pf_mem_size - Prepare QM ILT sizes
22 * Returns the required host memory size in 4KB units.
23 * Must be called before all QM init HSI functions.
25 * @param p_hwfn - HW device data
26 * @param num_pf_cids - number of connections used by this PF
27 * @param num_vf_cids - number of connections used by VFs of this PF
28 * @param num_tids - number of tasks used by this PF
29 * @param num_pf_pqs - number of PQs used by this PF
30 * @param num_vf_pqs - number of PQs used by VFs of this PF
32 * @return The required host memory size in 4KB units.
34 u32 ecore_qm_pf_mem_size(struct ecore_hwfn *p_hwfn,
42 * @brief ecore_qm_common_rt_init - Prepare QM runtime init values for engine
46 * @param max_ports_per_engine - max number of ports per engine in HW
47 * @param max_phys_tcs_per_port - max number of physical TCs per port in HW
48 * @param pf_rl_en - enable per-PF rate limiters
49 * @param pf_wfq_en - enable per-PF WFQ
50 * @param global_rl_en - enable global rate limiters
51 * @param vport_wfq_en - enable per-VPORT WFQ
52 * @param port_params - array with parameters for each port.
53 * @param global_rl_params - array with parameters for each global RL.
54 * If OSAL_NULL, global RLs are not configured.
56 * @return 0 on success, -1 on error.
58 int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn,
59 u8 max_ports_per_engine,
60 u8 max_phys_tcs_per_port,
65 struct init_qm_port_params port_params[MAX_NUM_PORTS],
66 struct init_qm_global_rl_params
67 global_rl_params[COMMON_MAX_QM_GLOBAL_RLS]);
70 * @brief ecore_qm_pf_rt_init Prepare QM runtime init values for the PF phase
73 * @param p_ptt - ptt window used for writing the registers
74 * @param pf_id - PF ID
75 * @param max_phys_tcs_per_port - max number of physical TCs per port in HW
76 * @param is_pf_loading - indicates if the PF is currently loading,
77 * i.e. it has no allocated QM resources.
78 * @param num_pf_cids - number of connections used by this PF
79 * @param num_vf_cids - number of connections used by VFs of this PF
80 * @param num_tids - number of tasks used by this PF
81 * @param start_pq - first Tx PQ ID associated with this PF
82 * @param num_pf_pqs - number of Tx PQs associated with this PF
84 * @param num_vf_pqs - number of Tx PQs associated with a VF
85 * @param start_vport - first VPORT ID associated with this PF
86 * @param num_vports - number of VPORTs associated with this PF
87 * @param pf_wfq - WFQ weight. if PF WFQ is globally disabled, the weight must
88 * be 0. otherwise, the weight must be non-zero.
89 * @param pf_rl - rate limit in Mb/sec units. a value of 0 means don't
90 * configure. ignored if PF RL is globally disabled.
91 * @param pq_params - array of size (num_pf_pqs+num_vf_pqs) with parameters for
92 * each Tx PQ associated with the specified PF.
93 * @param vport_params - array of size num_vports with parameters for each
96 * @return 0 on success, -1 on error.
98 int ecore_qm_pf_rt_init(struct ecore_hwfn *p_hwfn,
99 struct ecore_ptt *p_ptt,
101 u8 max_phys_tcs_per_port,
113 struct init_qm_pq_params *pq_params,
114 struct init_qm_vport_params *vport_params);
117 * @brief ecore_init_pf_wfq Initializes the WFQ weight of the specified PF
120 * @param p_ptt - ptt window used for writing the registers
121 * @param pf_id - PF ID
122 * @param pf_wfq - WFQ weight. Must be non-zero.
124 * @return 0 on success, -1 on error.
126 int ecore_init_pf_wfq(struct ecore_hwfn *p_hwfn,
127 struct ecore_ptt *p_ptt,
132 * @brief ecore_init_pf_rl - Initializes the rate limit of the specified PF
135 * @param p_ptt - ptt window used for writing the registers
136 * @param pf_id - PF ID
137 * @param pf_rl - rate limit in Mb/sec units
139 * @return 0 on success, -1 on error.
141 int ecore_init_pf_rl(struct ecore_hwfn *p_hwfn,
142 struct ecore_ptt *p_ptt,
147 * @brief ecore_init_vport_wfq Initializes the WFQ weight of specified VPORT
150 * @param p_ptt - ptt window used for writing the registers
151 * @param first_tx_pq_id- An array containing the first Tx PQ ID associated
152 * with the VPORT for each TC. This array is filled by
153 * ecore_qm_pf_rt_init
154 * @param wfq - WFQ weight. Must be non-zero.
156 * @return 0 on success, -1 on error.
158 int ecore_init_vport_wfq(struct ecore_hwfn *p_hwfn,
159 struct ecore_ptt *p_ptt,
160 u16 first_tx_pq_id[NUM_OF_TCS],
164 * @brief ecore_init_global_rl - Initializes the rate limit of the specified
167 * @param p_hwfn - HW device data
168 * @param p_ptt - ptt window used for writing the registers
169 * @param rl_id - RL ID
170 * @param rate_limit - rate limit in Mb/sec units
172 * @return 0 on success, -1 on error.
174 int ecore_init_global_rl(struct ecore_hwfn *p_hwfn,
175 struct ecore_ptt *p_ptt,
180 * @brief ecore_init_vport_rl - Initializes the rate limit of the specified
183 * @param p_hwfn - HW device data
184 * @param p_ptt - ptt window used for writing the registers
185 * @param vport_id - VPORT ID
186 * @param vport_rl - rate limit in Mb/sec units
187 * @param link_speed - link speed in Mbps.
189 * @return 0 on success, -1 on error.
191 int ecore_init_vport_rl(struct ecore_hwfn *p_hwfn,
192 struct ecore_ptt *p_ptt,
198 * @brief ecore_send_qm_stop_cmd Sends a stop command to the QM
201 * @param p_ptt - ptt window used for writing the registers
202 * @param is_release_cmd - true for release, false for stop.
203 * @param is_tx_pq - true for Tx PQs, false for Other PQs.
204 * @param start_pq - first PQ ID to stop
205 * @param num_pqs - Number of PQs to stop, starting from start_pq.
207 * @return bool, true if successful, false if timeout occurred while waiting
208 * for QM command done.
210 bool ecore_send_qm_stop_cmd(struct ecore_hwfn *p_hwfn,
211 struct ecore_ptt *p_ptt,
216 #ifndef UNUSED_HSI_FUNC
219 * @brief ecore_init_nig_ets - initializes the NIG ETS arbiter
221 * Based on weight/priority requirements per-TC.
223 * @param p_ptt - ptt window used for writing the registers.
224 * @param req - the NIG ETS initialization requirements.
225 * @param is_lb - if set, the loopback port arbiter is initialized, otherwise
226 * the physical port arbiter is initialized. The pure-LB TC
227 * requirements are ignored when is_lb is cleared.
229 void ecore_init_nig_ets(struct ecore_hwfn *p_hwfn,
230 struct ecore_ptt *p_ptt,
231 struct init_ets_req *req,
235 * @brief ecore_init_nig_lb_rl - initializes the NIG LB RLs
237 * Based on global and per-TC rate requirements
239 * @param p_ptt - ptt window used for writing the registers.
240 * @param req - the NIG LB RLs initialization requirements.
242 void ecore_init_nig_lb_rl(struct ecore_hwfn *p_hwfn,
243 struct ecore_ptt *p_ptt,
244 struct init_nig_lb_rl_req *req);
245 #endif /* UNUSED_HSI_FUNC */
248 * @brief ecore_init_nig_pri_tc_map - initializes the NIG priority to TC map.
250 * Assumes valid arguments.
252 * @param p_ptt - ptt window used for writing the registers.
253 * @param req - required mapping from prioirties to TCs.
255 void ecore_init_nig_pri_tc_map(struct ecore_hwfn *p_hwfn,
256 struct ecore_ptt *p_ptt,
257 struct init_nig_pri_tc_map_req *req);
259 #ifndef UNUSED_HSI_FUNC
261 * @brief ecore_init_prs_ets - initializes the PRS Rx ETS arbiter
263 * Based on weight/priority requirements per-TC.
265 * @param p_ptt - ptt window used for writing the registers.
266 * @param req - the PRS ETS initialization requirements.
268 void ecore_init_prs_ets(struct ecore_hwfn *p_hwfn,
269 struct ecore_ptt *p_ptt,
270 struct init_ets_req *req);
271 #endif /* UNUSED_HSI_FUNC */
273 #ifndef UNUSED_HSI_FUNC
275 * @brief ecore_init_brb_ram - initializes BRB RAM sizes per TC
277 * Based on weight/priority requirements per-TC.
279 * @param p_ptt - ptt window used for writing the registers.
280 * @param req - the BRB RAM initialization requirements.
282 void ecore_init_brb_ram(struct ecore_hwfn *p_hwfn,
283 struct ecore_ptt *p_ptt,
284 struct init_brb_ram_req *req);
285 #endif /* UNUSED_HSI_FUNC */
288 * @brief ecore_set_vxlan_no_l2_enable - enable or disable VXLAN no L2 parsing
290 * @param p_ptt - ptt window used for writing the registers.
291 * @param enable - VXLAN no L2 enable flag.
293 void ecore_set_vxlan_no_l2_enable(struct ecore_hwfn *p_hwfn,
294 struct ecore_ptt *p_ptt,
297 #ifndef UNUSED_HSI_FUNC
299 * @brief ecore_set_port_mf_ovlan_eth_type - initializes DORQ ethType Regs to
300 * input ethType should Be called
303 * @param p_hwfn - HW device data
304 * @param ethType - etherType to configure
306 void ecore_set_port_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn,
308 #endif /* UNUSED_HSI_FUNC */
311 * @brief ecore_set_vxlan_dest_port - initializes vxlan tunnel destination udp
314 * @param p_hwfn - HW device data
315 * @param p_ptt - ptt window used for writing the registers.
316 * @param dest_port - vxlan destination udp port.
318 void ecore_set_vxlan_dest_port(struct ecore_hwfn *p_hwfn,
319 struct ecore_ptt *p_ptt,
323 * @brief ecore_set_vxlan_enable - enable or disable VXLAN tunnel in HW
325 * @param p_hwfn - HW device data
326 * @param p_ptt - ptt window used for writing the registers.
327 * @param vxlan_enable - vxlan enable flag.
329 void ecore_set_vxlan_enable(struct ecore_hwfn *p_hwfn,
330 struct ecore_ptt *p_ptt,
334 * @brief ecore_set_gre_enable - enable or disable GRE tunnel in HW
336 * @param p_hwfn - HW device data
337 * @param p_ptt - ptt window used for writing the registers.
338 * @param eth_gre_enable - eth GRE enable enable flag.
339 * @param ip_gre_enable - IP GRE enable enable flag.
341 void ecore_set_gre_enable(struct ecore_hwfn *p_hwfn,
342 struct ecore_ptt *p_ptt,
347 * @brief ecore_set_geneve_dest_port - initializes geneve tunnel destination
350 * @param p_hwfn - HW device data
351 * @param p_ptt - ptt window used for writing the registers.
352 * @param dest_port - geneve destination udp port.
354 void ecore_set_geneve_dest_port(struct ecore_hwfn *p_hwfn,
355 struct ecore_ptt *p_ptt,
359 * @brief ecore_set_geneve_enable - enable or disable GRE tunnel in HW
361 * @param p_hwfn - HW device data
362 * @param p_ptt - ptt window used for writing the registers.
363 * @param eth_geneve_enable - eth GENEVE enable enable flag.
364 * @param ip_geneve_enable - IP GENEVE enable enable flag.
366 void ecore_set_geneve_enable(struct ecore_hwfn *p_hwfn,
367 struct ecore_ptt *p_ptt,
368 bool eth_geneve_enable,
369 bool ip_geneve_enable);
370 #ifndef UNUSED_HSI_FUNC
373 * @brief ecore_set_gft_event_id_cm_hdr - configure GFT event id and cm header
375 * @param p_ptt - ptt window used for writing the registers.
377 void ecore_set_gft_event_id_cm_hdr(struct ecore_hwfn *p_hwfn,
378 struct ecore_ptt *p_ptt);
381 * @brief ecore_gft_disable - Disable GFT
383 * @param p_hwfn - HW device data
384 * @param p_ptt - ptt window used for writing the registers.
385 * @param pf_id - pf on which to disable GFT.
387 void ecore_gft_disable(struct ecore_hwfn *p_hwfn,
388 struct ecore_ptt *p_ptt,
392 * @brief ecore_gft_config - Enable and configure HW for GFT
394 * @param p_hwfn - HW device data
395 * @param p_ptt - ptt window used for writing the registers.
396 * @param pf_id - pf on which to enable GFT.
397 * @param tcp - set profile tcp packets.
398 * @param udp - set profile udp packet.
399 * @param ipv4 - set profile ipv4 packet.
400 * @param ipv6 - set profile ipv6 packet.
401 * @param profile_type - define packet same fields. Use enum gft_profile_type.
403 void ecore_gft_config(struct ecore_hwfn *p_hwfn,
404 struct ecore_ptt *p_ptt,
410 enum gft_profile_type profile_type);
411 #endif /* UNUSED_HSI_FUNC */
414 * @brief ecore_config_vf_zone_size_mode - Configure VF zone size mode. Must be
415 * used before first ETH queue started.
417 * @param p_hwfn - HW device data
418 * @param p_ptt - ptt window used for writing the registers. Don't care
419 * if runtime_init used.
420 * @param mode - VF zone size mode. Use enum vf_zone_size_mode.
421 * @param runtime_init - Set 1 to init runtime registers in engine phase.
422 * Set 0 if VF zone size mode configured after engine
425 void ecore_config_vf_zone_size_mode(struct ecore_hwfn *p_hwfn, struct ecore_ptt
426 *p_ptt, u16 mode, bool runtime_init);
429 * @brief ecore_get_mstorm_queue_stat_offset - Get mstorm statistics offset by
432 * @param p_hwfn - HW device data
433 * @param stat_cnt_id - statistic counter id
434 * @param vf_zone_size_mode - VF zone size mode. Use enum vf_zone_size_mode.
436 u32 ecore_get_mstorm_queue_stat_offset(struct ecore_hwfn *p_hwfn,
437 u16 stat_cnt_id, u16 vf_zone_size_mode);
440 * @brief ecore_get_mstorm_eth_vf_prods_offset - VF producer offset by VF zone
443 * @param p_hwfn - HW device data
444 * @param vf_id - vf id.
445 * @param vf_queue_id - per VF rx queue id.
446 * @param vf_zone_size_mode - vf zone size mode. Use enum vf_zone_size_mode.
448 u32 ecore_get_mstorm_eth_vf_prods_offset(struct ecore_hwfn *p_hwfn, u8 vf_id, u8
449 vf_queue_id, u16 vf_zone_size_mode);
451 * @brief ecore_enable_context_validation - Enable and configure context
454 * @param p_hwfn - HW device data
455 * @param p_ptt - ptt window used for writing the registers.
457 void ecore_enable_context_validation(struct ecore_hwfn *p_hwfn,
458 struct ecore_ptt *p_ptt);
460 * @brief ecore_calc_session_ctx_validation - Calcualte validation byte for
463 * @param p_hwfn - HW device data
464 * @param p_ctx_mem - pointer to context memory.
465 * @param ctx_size - context size.
466 * @param ctx_type - context type.
467 * @param cid - context cid.
469 void ecore_calc_session_ctx_validation(struct ecore_hwfn *p_hwfn,
476 * @brief ecore_calc_task_ctx_validation - Calcualte validation byte for task
479 * @param p_hwfn - HW device data
480 * @param p_ctx_mem - pointer to context memory.
481 * @param ctx_size - context size.
482 * @param ctx_type - context type.
483 * @param tid - context tid.
485 void ecore_calc_task_ctx_validation(struct ecore_hwfn *p_hwfn,
492 * @brief ecore_memset_session_ctx - Memset session context to 0 while
493 * preserving validation bytes.
495 * @param p_hwfn - HW device data
496 * @param p_ctx_mem - pointer to context memory.
497 * @param ctx_size - size to initialzie.
498 * @param ctx_type - context type.
500 void ecore_memset_session_ctx(struct ecore_hwfn *p_hwfn,
506 * @brief ecore_memset_task_ctx - Memset task context to 0 while preserving
509 * @param p_hwfn - HW device data
510 * @param p_ctx_mem - pointer to context memory.
511 * @param ctx_size - size to initialzie.
512 * @param ctx_type - context type.
514 void ecore_memset_task_ctx(struct ecore_hwfn *p_hwfn,
520 /*******************************************************************************
521 * File name : rdma_init.h
522 * Author : Michael Shteinbok
523 *******************************************************************************
524 *******************************************************************************
526 * RDMA HSI functions header
528 *******************************************************************************
529 * Notes: This is the input to the auto generated file drv_init_fw_funcs.h
531 *******************************************************************************
538 * @brief ecore_set_rdma_error_level - Sets the RDMA assert level.
539 * If the severity of the error will be
540 * above the level, the FW will assert.
541 * @param p_hwfn - HW device data
542 * @param p_ptt - ptt window used for writing the registers
543 * @param assert_level - An array of assert levels for each storm.
545 void ecore_set_rdma_error_level(struct ecore_hwfn *p_hwfn,
546 struct ecore_ptt *p_ptt,
547 u8 assert_level[NUM_STORMS]);
550 * @brief ecore_fw_overlay_mem_alloc - Allocates and fills the FW overlay memory
552 * @param p_hwfn - HW device data
553 * @param fw_overlay_in_buf - the input FW overlay buffer.
554 * @param buf_size - the size of the input FW overlay buffer in bytes.
555 * must be aligned to dwords.
556 * @param fw_overlay_out_mem - OUT: a pointer to the allocated overlays memory.
558 * @return a pointer to the allocated overlays memory, or OSAL_NULL in case of
561 struct phys_mem_desc *ecore_fw_overlay_mem_alloc(struct ecore_hwfn *p_hwfn,
562 const u32 *const fw_overlay_in_buf,
563 u32 buf_size_in_bytes);
566 * @brief ecore_fw_overlay_init_ram - Initializes the FW overlay RAM.
568 * @param p_hwfn - HW device data.
569 * @param p_ptt - ptt window used for writing the registers.
570 * @param fw_overlay_mem - the allocated FW overlay memory.
572 void ecore_fw_overlay_init_ram(struct ecore_hwfn *p_hwfn,
573 struct ecore_ptt *p_ptt,
574 struct phys_mem_desc *fw_overlay_mem);
577 * @brief ecore_fw_overlay_mem_free - Frees the FW overlay memory.
579 * @param p_hwfn - HW device data.
580 * @param fw_overlay_mem - the allocated FW overlay memory to free.
582 void ecore_fw_overlay_mem_free(struct ecore_hwfn *p_hwfn,
583 struct phys_mem_desc *fw_overlay_mem);