drivers/net/qede/base/ecore_init_fw_funcs.h

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #ifndef _INIT_FW_FUNCS_H
  10 #define _INIT_FW_FUNCS_H
  11 /* forward declarations */
  12 struct init_qm_pq_params;
  13 /**
  14  * @brief ecore_qm_pf_mem_size - prepare QM ILT sizes
  15  *
  16  * Returns the required host memory size in 4KB units.
  17  * Must be called before all QM init HSI functions.
  18  *
  19  * @param pf_id                 - physical function ID
  20  * @param num_pf_cids   - number of connections used by this PF
  21  * @param num_vf_cids   - number of connections used by VFs of this PF
  22  * @param num_tids              - number of tasks used by this PF
  23  * @param num_pf_pqs    - number of PQs used by this PF
  24  * @param num_vf_pqs    - number of PQs used by VFs of this PF
  25  *
  26  * @return The required host memory size in 4KB units.
  27  */
  28 u32 ecore_qm_pf_mem_size(u8 pf_id,
  29                                                  u32 num_pf_cids,
  30                                                  u32 num_vf_cids,
  31                          u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs);
  32 /**
  33  * @brief ecore_qm_common_rt_init -
  34  * Prepare QM runtime init values for the engine phase
  35  *
  36  * @param p_hwfn
  37  * @param max_ports_per_engine  - max number of ports per engine in HW
  38  * @param max_phys_tcs_per_port - max number of physical TCs per port in HW
  39  * @param pf_rl_en                              - enable per-PF rate limiters
  40  * @param pf_wfq_en                             - enable per-PF WFQ
  41  * @param vport_rl_en                   - enable per-VPORT rate limiters
  42  * @param vport_wfq_en                  - enable per-VPORT WFQ
  43  * @param port_params - array of size MAX_NUM_PORTS with params for each port
  44  *
  45  * @return 0 on success, -1 on error.
  46  */
  47 int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn,
  48                          u8 max_ports_per_engine,
  49                          u8 max_phys_tcs_per_port,
  50                          bool pf_rl_en,
  51                          bool pf_wfq_en,
  52                          bool vport_rl_en,
  53                          bool vport_wfq_en,
  54                             struct init_qm_port_params
  55                             port_params[MAX_NUM_PORTS]);
  56
  57 int ecore_qm_pf_rt_init(struct ecore_hwfn *p_hwfn,
  58                                 struct ecore_ptt *p_ptt,
  59                                 u8 port_id,
  60                                 u8 pf_id,
  61                                 u8 max_phys_tcs_per_port,
  62                                 bool is_first_pf,
  63                                 u32 num_pf_cids,
  64                                 u32 num_vf_cids,
  65                                 u32 num_tids,
  66                                 u16 start_pq,
  67                                 u16 num_pf_pqs,
  68                                 u16 num_vf_pqs,
  69                                 u8 start_vport,
  70                                 u8 num_vports,
  71                                 u16 pf_wfq,
  72                                 u32 pf_rl,
  73                                 struct init_qm_pq_params *pq_params,
  74                                 struct init_qm_vport_params *vport_params);
  75 /**
  76  * @brief ecore_init_pf_wfq  Initializes the WFQ weight of the specified PF
  77  *
  78  * @param p_hwfn
  79  * @param p_ptt         - ptt window used for writing the registers
  80  * @param pf_id         - PF ID
  81  * @param pf_wfq        - WFQ weight. Must be non-zero.
  82  *
  83  * @return 0 on success, -1 on error.
  84  */
  85 int ecore_init_pf_wfq(struct ecore_hwfn *p_hwfn,
  86                                           struct ecore_ptt *p_ptt,
  87                                           u8 pf_id,
  88                                           u16 pf_wfq);
  89 /**
  90  * @brief ecore_init_pf_rl  Initializes the rate limit of the specified PF
  91  *
  92  * @param p_hwfn
  93  * @param p_ptt - ptt window used for writing the registers
  94  * @param pf_id - PF ID
  95  * @param pf_rl - rate limit in Mb/sec units
  96  *
  97  * @return 0 on success, -1 on error.
  98  */
  99 int ecore_init_pf_rl(struct ecore_hwfn *p_hwfn,
 100                                          struct ecore_ptt *p_ptt,
 101                                          u8 pf_id,
 102                                          u32 pf_rl);
 103 /**
 104  * @brief ecore_init_vport_wfq  Initializes the WFQ weight of specified VPORT
 105  *
 106  * @param p_hwfn
 107  * @param p_ptt                 - ptt window used for writing the registers
 108  * @param first_tx_pq_id- An array containing the first Tx PQ ID associated
 109  *                        with the VPORT for each TC. This array is filled by
 110  *                        ecore_qm_pf_rt_init
 111  * @param vport_wfq             - WFQ weight. Must be non-zero.
 112  *
 113  * @return 0 on success, -1 on error.
 114  */
 115 int ecore_init_vport_wfq(struct ecore_hwfn *p_hwfn,
 116                                                  struct ecore_ptt *p_ptt,
 117                                                  u16 first_tx_pq_id[NUM_OF_TCS],
 118                                                  u16 vport_wfq);
 119 /**
 120  * @brief ecore_init_vport_rl  Initializes the rate limit of the specified VPORT
 121  *
 122  * @param p_hwfn
 123  * @param p_ptt         - ptt window used for writing the registers
 124  * @param vport_id      - VPORT ID
 125  * @param vport_rl      - rate limit in Mb/sec units
 126  *
 127  * @return 0 on success, -1 on error.
 128  */
 129 int ecore_init_vport_rl(struct ecore_hwfn *p_hwfn,
 130                                                 struct ecore_ptt *p_ptt,
 131                                                 u8 vport_id,
 132                                                 u32 vport_rl);
 133 /**
 134  * @brief ecore_send_qm_stop_cmd  Sends a stop command to the QM
 135  *
 136  * @param p_hwfn
 137  * @param p_ptt          - ptt window used for writing the registers
 138  * @param is_release_cmd - true for release, false for stop.
 139  * @param is_tx_pq       - true for Tx PQs, false for Other PQs.
 140  * @param start_pq       - first PQ ID to stop
 141  * @param num_pqs        - Number of PQs to stop, starting from start_pq.
 142  *
 143  * @return bool, true if successful, false if timeout occurred while waiting
 144  *  for QM command done.
 145  */
 146 bool ecore_send_qm_stop_cmd(struct ecore_hwfn *p_hwfn,
 147                                                         struct ecore_ptt *p_ptt,
 148                                                         bool is_release_cmd,
 149                                                         bool is_tx_pq,
 150                                                         u16 start_pq,
 151                                                         u16 num_pqs);
 152 #ifndef UNUSED_HSI_FUNC
 153 /**
 154  * @brief ecore_init_nig_ets - initializes the NIG ETS arbiter
 155  *
 156  * Based on weight/priority requirements per-TC.
 157  *
 158  * @param p_ptt - ptt window used for writing the registers.
 159  * @param req   - the NIG ETS initialization requirements.
 160  * @param is_lb - if set, the loopback port arbiter is initialized, otherwise
 161  *                the physical port arbiter is initialized. The pure-LB TC
 162  *                requirements are ignored when is_lb is cleared.
 163  */
 164 void ecore_init_nig_ets(struct ecore_hwfn *p_hwfn,
 165                                                 struct ecore_ptt *p_ptt,
 166                                                 struct init_ets_req *req,
 167                                                 bool is_lb);
 168 /**
 169  * @brief ecore_init_nig_lb_rl - initializes the NIG LB RLs
 170  *
 171  * Based on global and per-TC rate requirements
 172  *
 173  * @param p_ptt - ptt window used for writing the registers.
 174  * @param req   - the NIG LB RLs initialization requirements.
 175  */
 176 void ecore_init_nig_lb_rl(struct ecore_hwfn *p_hwfn,
 177                                   struct ecore_ptt *p_ptt,
 178                                   struct init_nig_lb_rl_req *req);
 179 #endif /* UNUSED_HSI_FUNC */
 180 /**
 181  * @brief ecore_init_nig_pri_tc_map - initializes the NIG priority to TC map.
 182  *
 183  * Assumes valid arguments.
 184  *
 185  * @param p_ptt - ptt window used for writing the registers.
 186  * @param req   - required mapping from prioirties to TCs.
 187  */
 188 void ecore_init_nig_pri_tc_map(struct ecore_hwfn *p_hwfn,
 189                                            struct ecore_ptt *p_ptt,
 190                                            struct init_nig_pri_tc_map_req *req);
 191 #ifndef UNUSED_HSI_FUNC
 192 /**
 193  * @brief ecore_init_prs_ets - initializes the PRS Rx ETS arbiter
 194  *
 195  * Based on weight/priority requirements per-TC.
 196  *
 197  * @param p_ptt - ptt window used for writing the registers.
 198  * @param req   - the PRS ETS initialization requirements.
 199  */
 200 void ecore_init_prs_ets(struct ecore_hwfn *p_hwfn,
 201                                                 struct ecore_ptt *p_ptt,
 202                                                 struct init_ets_req *req);
 203 #endif /* UNUSED_HSI_FUNC */
 204 #ifndef UNUSED_HSI_FUNC
 205 /**
 206  * @brief ecore_init_brb_ram - initializes BRB RAM sizes per TC
 207  *
 208  * Based on weight/priority requirements per-TC.
 209  *
 210  * @param p_ptt - ptt window used for writing the registers.
 211  * @param req   - the BRB RAM initialization requirements.
 212  */
 213 void ecore_init_brb_ram(struct ecore_hwfn *p_hwfn,
 214                                                 struct ecore_ptt *p_ptt,
 215                                                 struct init_brb_ram_req *req);
 216 #endif /* UNUSED_HSI_FUNC */
 217 #ifndef UNUSED_HSI_FUNC
 218 /**
 219  * @brief ecore_set_engine_mf_ovlan_eth_type - initializes Nig,Prs,Pbf and llh
 220  *                                             ethType Regs to  input ethType
 221  *                                             should Be called once per engine
 222  *                                             if engine
 223  *  is in BD mode.
 224  *
 225  * @param p_ptt    - ptt window used for writing the registers.
 226  * @param ethType - etherType to configure
 227  */
 228 void ecore_set_engine_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn,
 229                         struct ecore_ptt *p_ptt, u32 ethType);
 230 /**
 231  * @brief ecore_set_port_mf_ovlan_eth_type - initializes DORQ ethType Regs to
 232  *                                           input ethType should Be called
 233  *                                           once per port.
 234  *
 235  * @param p_ptt    - ptt window used for writing the registers.
 236  * @param ethType - etherType to configure
 237  */
 238 void ecore_set_port_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn,
 239                         struct ecore_ptt *p_ptt, u32 ethType);
 240 #endif /* UNUSED_HSI_FUNC */
 241 /**
 242  * @brief ecore_set_vxlan_dest_port - initializes vxlan tunnel destination udp
 243  *                                    port
 244  *
 245  * @param p_ptt     - ptt window used for writing the registers.
 246  * @param dest_port - vxlan destination udp port.
 247  */
 248 void ecore_set_vxlan_dest_port(struct ecore_hwfn *p_hwfn,
 249                                struct ecore_ptt *p_ptt,
 250                                u16 dest_port);
 251 /**
 252  * @brief ecore_set_vxlan_enable - enable or disable VXLAN tunnel in HW
 253  *
 254  * @param p_ptt - ptt window used for writing the registers.
 255  * @param vxlan_enable - vxlan enable flag.
 256  */
 257 void ecore_set_vxlan_enable(struct ecore_hwfn *p_hwfn,
 258                             struct ecore_ptt *p_ptt,
 259                             bool vxlan_enable);
 260 /**
 261  * @brief ecore_set_gre_enable - enable or disable GRE tunnel in HW
 262  *
 263  * @param p_ptt          - ptt window used for writing the registers.
 264  * @param eth_gre_enable - eth GRE enable enable flag.
 265  * @param ip_gre_enable  - IP GRE enable enable flag.
 266  */
 267 void ecore_set_gre_enable(struct ecore_hwfn *p_hwfn,
 268                           struct ecore_ptt *p_ptt,
 269                           bool eth_gre_enable,
 270                           bool ip_gre_enable);
 271 /**
 272  * @brief ecore_set_geneve_dest_port - initializes geneve tunnel destination
 273  *                                     udp port
 274  *
 275  * @param p_ptt     - ptt window used for writing the registers.
 276  * @param dest_port - geneve destination udp port.
 277  */
 278 void ecore_set_geneve_dest_port(struct ecore_hwfn *p_hwfn,
 279                                 struct ecore_ptt *p_ptt,
 280                                 u16 dest_port);
 281 /**
 282  * @brief ecore_set_gre_enable - enable or disable GRE tunnel in HW
 283  *
 284  * @param p_ptt             - ptt window used for writing the registers.
 285  * @param eth_geneve_enable - eth GENEVE enable enable flag.
 286  * @param ip_geneve_enable  - IP GENEVE enable enable flag.
 287   */
 288 void ecore_set_geneve_enable(struct ecore_hwfn *p_hwfn,
 289                              struct ecore_ptt *p_ptt,
 290                              bool eth_geneve_enable, bool ip_geneve_enable);
 291 #endif