1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
7 #ifndef _INIT_FW_FUNCS_H
8 #define _INIT_FW_FUNCS_H
9 #include "ecore_hsi_common.h"
10 #include "ecore_hsi_eth.h"
12 /* Physical memory descriptor */
13 struct phys_mem_desc {
16 u32 size; /* In bytes */
19 /* Returns the VOQ based on port and TC */
20 #define VOQ(port, tc, max_phys_tcs_per_port) \
21 ((tc) == PURE_LB_TC ? NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB + (port) : \
22 (port) * (max_phys_tcs_per_port) + (tc))
24 struct init_qm_pq_params;
27 * @brief ecore_qm_pf_mem_size - Prepare QM ILT sizes
29 * Returns the required host memory size in 4KB units.
30 * Must be called before all QM init HSI functions.
32 * @param p_hwfn - HW device data
33 * @param num_pf_cids - number of connections used by this PF
34 * @param num_vf_cids - number of connections used by VFs of this PF
35 * @param num_tids - number of tasks used by this PF
36 * @param num_pf_pqs - number of PQs used by this PF
37 * @param num_vf_pqs - number of PQs used by VFs of this PF
39 * @return The required host memory size in 4KB units.
41 u32 ecore_qm_pf_mem_size(struct ecore_hwfn *p_hwfn,
49 * @brief ecore_qm_common_rt_init - Prepare QM runtime init values for engine
53 * @param max_ports_per_engine - max number of ports per engine in HW
54 * @param max_phys_tcs_per_port - max number of physical TCs per port in HW
55 * @param pf_rl_en - enable per-PF rate limiters
56 * @param pf_wfq_en - enable per-PF WFQ
57 * @param global_rl_en - enable global rate limiters
58 * @param vport_wfq_en - enable per-VPORT WFQ
59 * @param port_params - array with parameters for each port.
60 * @param global_rl_params - array with parameters for each global RL.
61 * If OSAL_NULL, global RLs are not configured.
63 * @return 0 on success, -1 on error.
65 int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn,
66 u8 max_ports_per_engine,
67 u8 max_phys_tcs_per_port,
72 struct init_qm_port_params port_params[MAX_NUM_PORTS],
73 struct init_qm_global_rl_params
74 global_rl_params[COMMON_MAX_QM_GLOBAL_RLS]);
77 * @brief ecore_qm_pf_rt_init Prepare QM runtime init values for the PF phase
80 * @param p_ptt - ptt window used for writing the registers
81 * @param pf_id - PF ID
82 * @param max_phys_tcs_per_port - max number of physical TCs per port in HW
83 * @param is_pf_loading - indicates if the PF is currently loading,
84 * i.e. it has no allocated QM resources.
85 * @param num_pf_cids - number of connections used by this PF
86 * @param num_vf_cids - number of connections used by VFs of this PF
87 * @param num_tids - number of tasks used by this PF
88 * @param start_pq - first Tx PQ ID associated with this PF
89 * @param num_pf_pqs - number of Tx PQs associated with this PF
91 * @param num_vf_pqs - number of Tx PQs associated with a VF
92 * @param start_vport - first VPORT ID associated with this PF
93 * @param num_vports - number of VPORTs associated with this PF
94 * @param pf_wfq - WFQ weight. if PF WFQ is globally disabled, the weight must
95 * be 0. otherwise, the weight must be non-zero.
96 * @param pf_rl - rate limit in Mb/sec units. a value of 0 means don't
97 * configure. ignored if PF RL is globally disabled.
98 * @param pq_params - array of size (num_pf_pqs+num_vf_pqs) with parameters for
99 * each Tx PQ associated with the specified PF.
100 * @param vport_params - array of size num_vports with parameters for each
103 * @return 0 on success, -1 on error.
105 int ecore_qm_pf_rt_init(struct ecore_hwfn *p_hwfn,
106 struct ecore_ptt *p_ptt,
108 u8 max_phys_tcs_per_port,
120 struct init_qm_pq_params *pq_params,
121 struct init_qm_vport_params *vport_params);
124 * @brief ecore_init_pf_wfq Initializes the WFQ weight of the specified PF
127 * @param p_ptt - ptt window used for writing the registers
128 * @param pf_id - PF ID
129 * @param pf_wfq - WFQ weight. Must be non-zero.
131 * @return 0 on success, -1 on error.
133 int ecore_init_pf_wfq(struct ecore_hwfn *p_hwfn,
134 struct ecore_ptt *p_ptt,
139 * @brief ecore_init_pf_rl - Initializes the rate limit of the specified PF
142 * @param p_ptt - ptt window used for writing the registers
143 * @param pf_id - PF ID
144 * @param pf_rl - rate limit in Mb/sec units
146 * @return 0 on success, -1 on error.
148 int ecore_init_pf_rl(struct ecore_hwfn *p_hwfn,
149 struct ecore_ptt *p_ptt,
154 * @brief ecore_init_vport_wfq Initializes the WFQ weight of specified VPORT
157 * @param p_ptt - ptt window used for writing the registers
158 * @param first_tx_pq_id- An array containing the first Tx PQ ID associated
159 * with the VPORT for each TC. This array is filled by
160 * ecore_qm_pf_rt_init
161 * @param wfq - WFQ weight. Must be non-zero.
163 * @return 0 on success, -1 on error.
165 int ecore_init_vport_wfq(struct ecore_hwfn *p_hwfn,
166 struct ecore_ptt *p_ptt,
167 u16 first_tx_pq_id[NUM_OF_TCS],
171 * @brief ecore_init_global_rl - Initializes the rate limit of the specified
174 * @param p_hwfn - HW device data
175 * @param p_ptt - ptt window used for writing the registers
176 * @param rl_id - RL ID
177 * @param rate_limit - rate limit in Mb/sec units
179 * @return 0 on success, -1 on error.
181 int ecore_init_global_rl(struct ecore_hwfn *p_hwfn,
182 struct ecore_ptt *p_ptt,
187 * @brief ecore_init_vport_rl - Initializes the rate limit of the specified
190 * @param p_hwfn - HW device data
191 * @param p_ptt - ptt window used for writing the registers
192 * @param vport_id - VPORT ID
193 * @param vport_rl - rate limit in Mb/sec units
194 * @param link_speed - link speed in Mbps.
196 * @return 0 on success, -1 on error.
198 int ecore_init_vport_rl(struct ecore_hwfn *p_hwfn,
199 struct ecore_ptt *p_ptt,
205 * @brief ecore_send_qm_stop_cmd Sends a stop command to the QM
208 * @param p_ptt - ptt window used for writing the registers
209 * @param is_release_cmd - true for release, false for stop.
210 * @param is_tx_pq - true for Tx PQs, false for Other PQs.
211 * @param start_pq - first PQ ID to stop
212 * @param num_pqs - Number of PQs to stop, starting from start_pq.
214 * @return bool, true if successful, false if timeout occurred while waiting
215 * for QM command done.
217 bool ecore_send_qm_stop_cmd(struct ecore_hwfn *p_hwfn,
218 struct ecore_ptt *p_ptt,
223 #ifndef UNUSED_HSI_FUNC
226 * @brief ecore_init_nig_ets - initializes the NIG ETS arbiter
228 * Based on weight/priority requirements per-TC.
230 * @param p_ptt - ptt window used for writing the registers.
231 * @param req - the NIG ETS initialization requirements.
232 * @param is_lb - if set, the loopback port arbiter is initialized, otherwise
233 * the physical port arbiter is initialized. The pure-LB TC
234 * requirements are ignored when is_lb is cleared.
236 void ecore_init_nig_ets(struct ecore_hwfn *p_hwfn,
237 struct ecore_ptt *p_ptt,
238 struct init_ets_req *req,
242 * @brief ecore_init_nig_lb_rl - initializes the NIG LB RLs
244 * Based on global and per-TC rate requirements
246 * @param p_ptt - ptt window used for writing the registers.
247 * @param req - the NIG LB RLs initialization requirements.
249 void ecore_init_nig_lb_rl(struct ecore_hwfn *p_hwfn,
250 struct ecore_ptt *p_ptt,
251 struct init_nig_lb_rl_req *req);
252 #endif /* UNUSED_HSI_FUNC */
255 * @brief ecore_init_nig_pri_tc_map - initializes the NIG priority to TC map.
257 * Assumes valid arguments.
259 * @param p_ptt - ptt window used for writing the registers.
260 * @param req - required mapping from prioirties to TCs.
262 void ecore_init_nig_pri_tc_map(struct ecore_hwfn *p_hwfn,
263 struct ecore_ptt *p_ptt,
264 struct init_nig_pri_tc_map_req *req);
266 #ifndef UNUSED_HSI_FUNC
268 * @brief ecore_init_prs_ets - initializes the PRS Rx ETS arbiter
270 * Based on weight/priority requirements per-TC.
272 * @param p_ptt - ptt window used for writing the registers.
273 * @param req - the PRS ETS initialization requirements.
275 void ecore_init_prs_ets(struct ecore_hwfn *p_hwfn,
276 struct ecore_ptt *p_ptt,
277 struct init_ets_req *req);
278 #endif /* UNUSED_HSI_FUNC */
280 #ifndef UNUSED_HSI_FUNC
282 * @brief ecore_init_brb_ram - initializes BRB RAM sizes per TC
284 * Based on weight/priority requirements per-TC.
286 * @param p_ptt - ptt window used for writing the registers.
287 * @param req - the BRB RAM initialization requirements.
289 void ecore_init_brb_ram(struct ecore_hwfn *p_hwfn,
290 struct ecore_ptt *p_ptt,
291 struct init_brb_ram_req *req);
292 #endif /* UNUSED_HSI_FUNC */
295 * @brief ecore_set_vxlan_no_l2_enable - enable or disable VXLAN no L2 parsing
297 * @param p_ptt - ptt window used for writing the registers.
298 * @param enable - VXLAN no L2 enable flag.
300 void ecore_set_vxlan_no_l2_enable(struct ecore_hwfn *p_hwfn,
301 struct ecore_ptt *p_ptt,
304 #ifndef UNUSED_HSI_FUNC
306 * @brief ecore_set_port_mf_ovlan_eth_type - initializes DORQ ethType Regs to
307 * input ethType should Be called
310 * @param p_hwfn - HW device data
311 * @param ethType - etherType to configure
313 void ecore_set_port_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn,
315 #endif /* UNUSED_HSI_FUNC */
318 * @brief ecore_set_vxlan_dest_port - initializes vxlan tunnel destination udp
321 * @param p_hwfn - HW device data
322 * @param p_ptt - ptt window used for writing the registers.
323 * @param dest_port - vxlan destination udp port.
325 void ecore_set_vxlan_dest_port(struct ecore_hwfn *p_hwfn,
326 struct ecore_ptt *p_ptt,
330 * @brief ecore_set_vxlan_enable - enable or disable VXLAN tunnel in HW
332 * @param p_hwfn - HW device data
333 * @param p_ptt - ptt window used for writing the registers.
334 * @param vxlan_enable - vxlan enable flag.
336 void ecore_set_vxlan_enable(struct ecore_hwfn *p_hwfn,
337 struct ecore_ptt *p_ptt,
341 * @brief ecore_set_gre_enable - enable or disable GRE tunnel in HW
343 * @param p_hwfn - HW device data
344 * @param p_ptt - ptt window used for writing the registers.
345 * @param eth_gre_enable - eth GRE enable enable flag.
346 * @param ip_gre_enable - IP GRE enable enable flag.
348 void ecore_set_gre_enable(struct ecore_hwfn *p_hwfn,
349 struct ecore_ptt *p_ptt,
354 * @brief ecore_set_geneve_dest_port - initializes geneve tunnel destination
357 * @param p_hwfn - HW device data
358 * @param p_ptt - ptt window used for writing the registers.
359 * @param dest_port - geneve destination udp port.
361 void ecore_set_geneve_dest_port(struct ecore_hwfn *p_hwfn,
362 struct ecore_ptt *p_ptt,
366 * @brief ecore_set_geneve_enable - enable or disable GRE tunnel in HW
368 * @param p_hwfn - HW device data
369 * @param p_ptt - ptt window used for writing the registers.
370 * @param eth_geneve_enable - eth GENEVE enable enable flag.
371 * @param ip_geneve_enable - IP GENEVE enable enable flag.
373 void ecore_set_geneve_enable(struct ecore_hwfn *p_hwfn,
374 struct ecore_ptt *p_ptt,
375 bool eth_geneve_enable,
376 bool ip_geneve_enable);
377 #ifndef UNUSED_HSI_FUNC
380 * @brief ecore_set_gft_event_id_cm_hdr - configure GFT event id and cm header
382 * @param p_ptt - ptt window used for writing the registers.
384 void ecore_set_gft_event_id_cm_hdr(struct ecore_hwfn *p_hwfn,
385 struct ecore_ptt *p_ptt);
388 * @brief ecore_gft_disable - Disable GFT
390 * @param p_hwfn - HW device data
391 * @param p_ptt - ptt window used for writing the registers.
392 * @param pf_id - pf on which to disable GFT.
394 void ecore_gft_disable(struct ecore_hwfn *p_hwfn,
395 struct ecore_ptt *p_ptt,
399 * @brief ecore_gft_config - Enable and configure HW for GFT
401 * @param p_hwfn - HW device data
402 * @param p_ptt - ptt window used for writing the registers.
403 * @param pf_id - pf on which to enable GFT.
404 * @param tcp - set profile tcp packets.
405 * @param udp - set profile udp packet.
406 * @param ipv4 - set profile ipv4 packet.
407 * @param ipv6 - set profile ipv6 packet.
408 * @param profile_type - define packet same fields. Use enum gft_profile_type.
410 void ecore_gft_config(struct ecore_hwfn *p_hwfn,
411 struct ecore_ptt *p_ptt,
417 enum gft_profile_type profile_type);
418 #endif /* UNUSED_HSI_FUNC */
421 * @brief ecore_config_vf_zone_size_mode - Configure VF zone size mode. Must be
422 * used before first ETH queue started.
424 * @param p_hwfn - HW device data
425 * @param p_ptt - ptt window used for writing the registers. Don't care
426 * if runtime_init used.
427 * @param mode - VF zone size mode. Use enum vf_zone_size_mode.
428 * @param runtime_init - Set 1 to init runtime registers in engine phase.
429 * Set 0 if VF zone size mode configured after engine
432 void ecore_config_vf_zone_size_mode(struct ecore_hwfn *p_hwfn, struct ecore_ptt
433 *p_ptt, u16 mode, bool runtime_init);
436 * @brief ecore_get_mstorm_queue_stat_offset - Get mstorm statistics offset by
439 * @param p_hwfn - HW device data
440 * @param stat_cnt_id - statistic counter id
441 * @param vf_zone_size_mode - VF zone size mode. Use enum vf_zone_size_mode.
443 u32 ecore_get_mstorm_queue_stat_offset(struct ecore_hwfn *p_hwfn,
444 u16 stat_cnt_id, u16 vf_zone_size_mode);
447 * @brief ecore_get_mstorm_eth_vf_prods_offset - VF producer offset by VF zone
450 * @param p_hwfn - HW device data
451 * @param vf_id - vf id.
452 * @param vf_queue_id - per VF rx queue id.
453 * @param vf_zone_size_mode - vf zone size mode. Use enum vf_zone_size_mode.
455 u32 ecore_get_mstorm_eth_vf_prods_offset(struct ecore_hwfn *p_hwfn, u8 vf_id, u8
456 vf_queue_id, u16 vf_zone_size_mode);
458 * @brief ecore_enable_context_validation - Enable and configure context
461 * @param p_hwfn - HW device data
462 * @param p_ptt - ptt window used for writing the registers.
464 void ecore_enable_context_validation(struct ecore_hwfn *p_hwfn,
465 struct ecore_ptt *p_ptt);
467 * @brief ecore_calc_session_ctx_validation - Calcualte validation byte for
470 * @param p_hwfn - HW device data
471 * @param p_ctx_mem - pointer to context memory.
472 * @param ctx_size - context size.
473 * @param ctx_type - context type.
474 * @param cid - context cid.
476 void ecore_calc_session_ctx_validation(struct ecore_hwfn *p_hwfn,
483 * @brief ecore_calc_task_ctx_validation - Calcualte validation byte for task
486 * @param p_hwfn - HW device data
487 * @param p_ctx_mem - pointer to context memory.
488 * @param ctx_size - context size.
489 * @param ctx_type - context type.
490 * @param tid - context tid.
492 void ecore_calc_task_ctx_validation(struct ecore_hwfn *p_hwfn,
499 * @brief ecore_memset_session_ctx - Memset session context to 0 while
500 * preserving validation bytes.
502 * @param p_hwfn - HW device data
503 * @param p_ctx_mem - pointer to context memory.
504 * @param ctx_size - size to initialzie.
505 * @param ctx_type - context type.
507 void ecore_memset_session_ctx(struct ecore_hwfn *p_hwfn,
513 * @brief ecore_memset_task_ctx - Memset task context to 0 while preserving
516 * @param p_hwfn - HW device data
517 * @param p_ctx_mem - pointer to context memory.
518 * @param ctx_size - size to initialzie.
519 * @param ctx_type - context type.
521 void ecore_memset_task_ctx(struct ecore_hwfn *p_hwfn,
527 /*******************************************************************************
528 * File name : rdma_init.h
529 * Author : Michael Shteinbok
530 *******************************************************************************
531 *******************************************************************************
533 * RDMA HSI functions header
535 *******************************************************************************
536 * Notes: This is the input to the auto generated file drv_init_fw_funcs.h
538 *******************************************************************************
545 * @brief ecore_set_rdma_error_level - Sets the RDMA assert level.
546 * If the severity of the error will be
547 * above the level, the FW will assert.
548 * @param p_hwfn - HW device data
549 * @param p_ptt - ptt window used for writing the registers
550 * @param assert_level - An array of assert levels for each storm.
552 void ecore_set_rdma_error_level(struct ecore_hwfn *p_hwfn,
553 struct ecore_ptt *p_ptt,
554 u8 assert_level[NUM_STORMS]);