2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #ifndef _INIT_FW_FUNCS_H
10 #define _INIT_FW_FUNCS_H
11 /* forward declarations */
12 struct init_qm_pq_params;
14 * @brief ecore_qm_pf_mem_size - prepare QM ILT sizes
16 * Returns the required host memory size in 4KB units.
17 * Must be called before all QM init HSI functions.
19 * @param pf_id - physical function ID
20 * @param num_pf_cids - number of connections used by this PF
21 * @param num_vf_cids - number of connections used by VFs of this PF
22 * @param num_tids - number of tasks used by this PF
23 * @param num_pf_pqs - number of PQs used by this PF
24 * @param num_vf_pqs - number of PQs used by VFs of this PF
26 * @return The required host memory size in 4KB units.
28 u32 ecore_qm_pf_mem_size(u8 pf_id,
31 u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs);
33 * @brief ecore_qm_common_rt_init -
34 * Prepare QM runtime init values for the engine phase
37 * @param max_ports_per_engine - max number of ports per engine in HW
38 * @param max_phys_tcs_per_port - max number of physical TCs per port in HW
39 * @param pf_rl_en - enable per-PF rate limiters
40 * @param pf_wfq_en - enable per-PF WFQ
41 * @param vport_rl_en - enable per-VPORT rate limiters
42 * @param vport_wfq_en - enable per-VPORT WFQ
43 * @param port_params- array of size MAX_NUM_PORTS with parameters for each port
45 * @return 0 on success, -1 on error.
47 int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn,
48 u8 max_ports_per_engine,
49 u8 max_phys_tcs_per_port,
54 struct init_qm_port_params
55 port_params[MAX_NUM_PORTS]);
57 int ecore_qm_pf_rt_init(struct ecore_hwfn *p_hwfn,
58 struct ecore_ptt *p_ptt,
61 u8 max_phys_tcs_per_port,
73 struct init_qm_pq_params *pq_params,
74 struct init_qm_vport_params *vport_params);
76 * @brief ecore_init_pf_wfq Initializes the WFQ weight of the specified PF
79 * @param p_ptt - ptt window used for writing the registers
80 * @param pf_id - PF ID
81 * @param pf_wfq - WFQ weight. Must be non-zero.
83 * @return 0 on success, -1 on error.
85 int ecore_init_pf_wfq(struct ecore_hwfn *p_hwfn,
86 struct ecore_ptt *p_ptt, u8 pf_id, u16 pf_wfq);
88 * @brief ecore_init_pf_rl Initializes the rate limit of the specified PF
91 * @param p_ptt - ptt window used for writing the registers
92 * @param pf_id - PF ID
93 * @param pf_rl - rate limit in Mb/sec units
95 * @return 0 on success, -1 on error.
97 int ecore_init_pf_rl(struct ecore_hwfn *p_hwfn,
98 struct ecore_ptt *p_ptt, u8 pf_id, u32 pf_rl);
100 * @brief ecore_init_vport_wfq Initializes the WFQ weight of the specified VPORT
103 * @param p_ptt - ptt window used for writing the registers
104 * @param first_tx_pq_id- An array containing the first Tx PQ ID associated
105 * with the VPORT for each TC. This array is filled by
106 * ecore_qm_pf_rt_init
107 * @param vport_wfq - WFQ weight. Must be non-zero.
109 * @return 0 on success, -1 on error.
111 int ecore_init_vport_wfq(struct ecore_hwfn *p_hwfn,
112 struct ecore_ptt *p_ptt,
113 u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq);
115 * @brief ecore_init_vport_rl Initializes the rate limit of the specified VPORT
118 * @param p_ptt - ptt window used for writing the registers
119 * @param vport_id - VPORT ID
120 * @param vport_rl - rate limit in Mb/sec units
122 * @return 0 on success, -1 on error.
124 int ecore_init_vport_rl(struct ecore_hwfn *p_hwfn,
125 struct ecore_ptt *p_ptt, u8 vport_id, u32 vport_rl);
127 * @brief ecore_send_qm_stop_cmd Sends a stop command to the QM
130 * @param p_ptt - ptt window used for writing the registers
131 * @param is_release_cmd - true for release, false for stop.
132 * @param is_tx_pq - true for Tx PQs, false for Other PQs.
133 * @param start_pq - first PQ ID to stop
134 * @param num_pqs - Number of PQs to stop, starting from start_pq.
136 * @return bool, true if successful, false if timeout occurred while
137 * waiting for QM command done.
139 bool ecore_send_qm_stop_cmd(struct ecore_hwfn *p_hwfn,
140 struct ecore_ptt *p_ptt,
142 bool is_tx_pq, u16 start_pq, u16 num_pqs);
144 * @brief ecore_init_nig_ets - initializes the NIG ETS arbiter
146 * Based on weight/priority requirements per-TC.
148 * @param p_ptt - ptt window used for writing the registers.
149 * @param req - the NIG ETS initialization requirements.
150 * @param is_lb - if set, the loopback port arbiter is initialized, otherwise
151 * the physical port arbiter is initialized. The pure-LB TC
152 * requirements are ignored when is_lb is cleared.
154 void ecore_init_nig_ets(struct ecore_hwfn *p_hwfn,
155 struct ecore_ptt *p_ptt,
156 struct init_ets_req *req, bool is_lb);
158 * @brief ecore_init_nig_lb_rl - initializes the NIG LB RLs
160 * Based on global and per-TC rate requirements
162 * @param p_ptt - ptt window used for writing the registers.
163 * @param req - the NIG LB RLs initialization requirements.
165 void ecore_init_nig_lb_rl(struct ecore_hwfn *p_hwfn,
166 struct ecore_ptt *p_ptt,
167 struct init_nig_lb_rl_req *req);
169 * @brief ecore_init_nig_pri_tc_map - initializes the NIG priority to TC map.
171 * Assumes valid arguments.
173 * @param p_ptt - ptt window used for writing the registers.
174 * @param req - required mapping from prioirties to TCs.
176 void ecore_init_nig_pri_tc_map(struct ecore_hwfn *p_hwfn,
177 struct ecore_ptt *p_ptt,
178 struct init_nig_pri_tc_map_req *req);
180 * @brief ecore_init_prs_ets - initializes the PRS Rx ETS arbiter
182 * Based on weight/priority requirements per-TC.
184 * @param p_ptt - ptt window used for writing the registers.
185 * @param req - the PRS ETS initialization requirements.
187 void ecore_init_prs_ets(struct ecore_hwfn *p_hwfn,
188 struct ecore_ptt *p_ptt, struct init_ets_req *req);
190 * @brief ecore_init_brb_ram - initializes BRB RAM sizes per TC
192 * Based on weight/priority requirements per-TC.
194 * @param p_ptt - ptt window used for writing the registers.
195 * @param req - the BRB RAM initialization requirements.
197 void ecore_init_brb_ram(struct ecore_hwfn *p_hwfn,
198 struct ecore_ptt *p_ptt, struct init_brb_ram_req *req);
200 * @brief ecore_set_engine_mf_ovlan_eth_type - initializes Nig,Prs,Pbf
201 * and llh ethType Regs to input ethType
202 * should Be called once per engine if engine is in BD mode.
204 * @param p_ptt - ptt window used for writing the registers.
205 * @param ethType - etherType to configure
207 void ecore_set_engine_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn,
208 struct ecore_ptt *p_ptt, u32 eth_type);
210 * @brief ecore_set_port_mf_ovlan_eth_type - initializes DORQ ethType Regs
212 * should Be called once per port.
214 * @param p_ptt - ptt window used for writing the registers.
215 * @param ethType - etherType to configure
217 void ecore_set_port_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn,
218 struct ecore_ptt *p_ptt, u32 eth_type);
220 * @brief ecore_set_vxlan_dest_port - init vxlan tunnel destination udp port
222 * @param p_ptt - ptt window used for writing the registers.
223 * @param dest_port - vxlan destination udp port.
225 void ecore_set_vxlan_dest_port(struct ecore_hwfn *p_hwfn,
226 struct ecore_ptt *p_ptt, u16 dest_port);
228 * @brief ecore_set_vxlan_enable - enable or disable VXLAN tunnel in HW
230 * @param p_ptt - ptt window used for writing the registers.
231 * @param vxlan_enable - vxlan enable flag.
233 void ecore_set_vxlan_enable(struct ecore_hwfn *p_hwfn,
234 struct ecore_ptt *p_ptt, bool vxlan_enable);
236 * @brief ecore_set_gre_enable - enable or disable GRE tunnel in HW
238 * @param p_ptt - ptt window used for writing the registers.
239 * @param eth_gre_enable - eth GRE enable enable flag.
240 * @param ip_gre_enable - IP GRE enable enable flag.
242 void ecore_set_gre_enable(struct ecore_hwfn *p_hwfn,
243 struct ecore_ptt *p_ptt,
244 bool eth_gre_enable, bool ip_gre_enable);
246 * @brief ecore_set_geneve_dest_port - init geneve tunnel destination udp port
248 * @param p_ptt - ptt window used for writing the registers.
249 * @param dest_port - geneve destination udp port.
251 void ecore_set_geneve_dest_port(struct ecore_hwfn *p_hwfn,
252 struct ecore_ptt *p_ptt, u16 dest_port);
254 * @brief ecore_set_gre_enable - enable or disable GRE tunnel in HW
256 * @param p_ptt - ptt window used for writing the registers.
257 * @param eth_geneve_enable - eth GENEVE enable enable flag.
258 * @param ip_geneve_enable - IP GENEVE enable enable flag.
260 void ecore_set_geneve_enable(struct ecore_hwfn *p_hwfn,
261 struct ecore_ptt *p_ptt,
262 bool eth_geneve_enable, bool ip_geneve_enable);