2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 /* include the precompiled configuration values - only once */
11 #include "ecore_hsi_common.h"
14 #include "ecore_status.h"
15 #include "ecore_rt_defs.h"
16 #include "ecore_init_fw_funcs.h"
18 #include "ecore_iro_values.h"
19 #include "ecore_gtt_values.h"
21 #include "ecore_init_ops.h"
23 #define ECORE_INIT_MAX_POLL_COUNT 100
24 #define ECORE_INIT_POLL_PERIOD_US 500
26 void ecore_init_iro_array(struct ecore_dev *p_dev)
28 p_dev->iro_arr = iro_arr;
31 /* Runtime configuration helpers */
32 void ecore_init_clear_rt_data(struct ecore_hwfn *p_hwfn)
36 for (i = 0; i < RUNTIME_ARRAY_SIZE; i++)
37 p_hwfn->rt_data.b_valid[i] = false;
40 void ecore_init_store_rt_reg(struct ecore_hwfn *p_hwfn, u32 rt_offset, u32 val)
42 p_hwfn->rt_data.init_val[rt_offset] = val;
43 p_hwfn->rt_data.b_valid[rt_offset] = true;
46 void ecore_init_store_rt_agg(struct ecore_hwfn *p_hwfn,
47 u32 rt_offset, u32 *p_val, osal_size_t size)
51 for (i = 0; i < size / sizeof(u32); i++) {
52 p_hwfn->rt_data.init_val[rt_offset + i] = p_val[i];
53 p_hwfn->rt_data.b_valid[rt_offset + i] = true;
57 static enum _ecore_status_t ecore_init_rt(struct ecore_hwfn *p_hwfn,
58 struct ecore_ptt *p_ptt,
61 u16 size, bool b_must_dmae)
63 u32 *p_init_val = &p_hwfn->rt_data.init_val[rt_offset];
64 bool *p_valid = &p_hwfn->rt_data.b_valid[rt_offset];
65 enum _ecore_status_t rc = ECORE_SUCCESS;
68 /* Since not all RT entries are initialized, go over the RT and
69 * for each segment of initialized values use DMA.
71 for (i = 0; i < size; i++) {
75 /* In case there isn't any wide-bus configuration here,
76 * simply write the data instead of using dmae.
79 ecore_wr(p_hwfn, p_ptt, addr + (i << 2), p_init_val[i]);
83 /* Start of a new segment */
84 for (segment = 1; i + segment < size; segment++)
85 if (!p_valid[i + segment])
88 rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
89 (osal_uintptr_t)(p_init_val + i),
90 addr + (i << 2), segment, 0);
91 if (rc != ECORE_SUCCESS)
94 /* Jump over the entire segment, including invalid entry */
101 enum _ecore_status_t ecore_init_alloc(struct ecore_hwfn *p_hwfn)
103 struct ecore_rt_data *rt_data = &p_hwfn->rt_data;
105 rt_data->b_valid = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
106 sizeof(bool) * RUNTIME_ARRAY_SIZE);
107 if (!rt_data->b_valid)
110 rt_data->init_val = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
111 sizeof(u32) * RUNTIME_ARRAY_SIZE);
112 if (!rt_data->init_val) {
113 OSAL_FREE(p_hwfn->p_dev, rt_data->b_valid);
117 return ECORE_SUCCESS;
120 void ecore_init_free(struct ecore_hwfn *p_hwfn)
122 OSAL_FREE(p_hwfn->p_dev, p_hwfn->rt_data.init_val);
123 OSAL_FREE(p_hwfn->p_dev, p_hwfn->rt_data.b_valid);
126 static enum _ecore_status_t ecore_init_array_dmae(struct ecore_hwfn *p_hwfn,
127 struct ecore_ptt *p_ptt,
129 u32 dmae_data_offset,
130 u32 size, const u32 *p_buf,
134 enum _ecore_status_t rc = ECORE_SUCCESS;
136 /* Perform DMAE only for lengthy enough sections or for wide-bus */
138 if ((CHIP_REV_IS_SLOW(p_hwfn->p_dev) && (size < 16)) ||
139 !b_can_dmae || (!b_must_dmae && (size < 16))) {
141 if (!b_can_dmae || (!b_must_dmae && (size < 16))) {
143 const u32 *data = p_buf + dmae_data_offset;
146 for (i = 0; i < size; i++)
147 ecore_wr(p_hwfn, p_ptt, addr + (i << 2), data[i]);
149 rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
150 (osal_uintptr_t)(p_buf +
158 static enum _ecore_status_t ecore_init_fill_dmae(struct ecore_hwfn *p_hwfn,
159 struct ecore_ptt *p_ptt,
163 static u32 zero_buffer[DMAE_MAX_RW_SIZE];
165 OSAL_MEMSET(zero_buffer, 0, sizeof(u32) * DMAE_MAX_RW_SIZE);
167 return ecore_dmae_host2grc(p_hwfn, p_ptt,
168 (osal_uintptr_t)&zero_buffer[0],
170 ECORE_DMAE_FLAG_RW_REPL_SRC);
173 static void ecore_init_fill(struct ecore_hwfn *p_hwfn,
174 struct ecore_ptt *p_ptt,
175 u32 addr, u32 fill, u32 fill_count)
179 for (i = 0; i < fill_count; i++, addr += sizeof(u32))
180 ecore_wr(p_hwfn, p_ptt, addr, fill);
183 static enum _ecore_status_t ecore_init_cmd_array(struct ecore_hwfn *p_hwfn,
184 struct ecore_ptt *p_ptt,
185 struct init_write_op *cmd,
189 #ifdef CONFIG_ECORE_ZIPPED_FW
190 u32 offset, output_len, input_len, max_size;
192 u32 dmae_array_offset = OSAL_LE32_TO_CPU(cmd->args.array_offset);
193 struct ecore_dev *p_dev = p_hwfn->p_dev;
194 enum _ecore_status_t rc = ECORE_SUCCESS;
195 union init_array_hdr *hdr;
196 const u32 *array_data;
197 u32 size, addr, data;
199 array_data = p_dev->fw_data->arr_data;
200 data = OSAL_LE32_TO_CPU(cmd->data);
201 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2;
203 hdr = (union init_array_hdr *)
204 (uintptr_t)(array_data + dmae_array_offset);
205 data = OSAL_LE32_TO_CPU(hdr->raw.data);
206 switch (GET_FIELD(data, INIT_ARRAY_RAW_HDR_TYPE)) {
207 case INIT_ARR_ZIPPED:
208 #ifdef CONFIG_ECORE_ZIPPED_FW
209 offset = dmae_array_offset + 1;
210 input_len = GET_FIELD(data, INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE);
211 max_size = MAX_ZIPPED_SIZE * 4;
212 OSAL_MEMSET(p_hwfn->unzip_buf, 0, max_size);
214 output_len = OSAL_UNZIP_DATA(p_hwfn, input_len,
215 (u8 *)(uintptr_t)&array_data[offset],
217 (u8 *)p_hwfn->unzip_buf);
219 rc = ecore_init_array_dmae(p_hwfn, p_ptt, addr, 0,
222 b_must_dmae, b_can_dmae);
224 DP_NOTICE(p_hwfn, true, "Failed to unzip dmae data\n");
228 DP_NOTICE(p_hwfn, true,
229 "Using zipped firmware without config enabled\n");
233 case INIT_ARR_PATTERN:
235 u32 repeats = GET_FIELD(data,
236 INIT_ARRAY_PATTERN_HDR_REPETITIONS);
239 size = GET_FIELD(data,
240 INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE);
242 for (i = 0; i < repeats; i++, addr += size << 2) {
243 rc = ecore_init_array_dmae(p_hwfn, p_ptt, addr,
253 case INIT_ARR_STANDARD:
254 size = GET_FIELD(data, INIT_ARRAY_STANDARD_HDR_SIZE);
255 rc = ecore_init_array_dmae(p_hwfn, p_ptt, addr,
256 dmae_array_offset + 1,
258 b_must_dmae, b_can_dmae);
265 /* init_ops write command */
266 static enum _ecore_status_t ecore_init_cmd_wr(struct ecore_hwfn *p_hwfn,
267 struct ecore_ptt *p_ptt,
268 struct init_write_op *p_cmd,
271 enum _ecore_status_t rc = ECORE_SUCCESS;
275 data = OSAL_LE32_TO_CPU(p_cmd->data);
276 b_must_dmae = GET_FIELD(data, INIT_WRITE_OP_WIDE_BUS);
277 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2;
280 if (b_must_dmae && !b_can_dmae) {
281 DP_NOTICE(p_hwfn, true,
282 "Need to write to %08x for Wide-bus but DMAE isn't"
288 switch (GET_FIELD(data, INIT_WRITE_OP_SOURCE)) {
289 case INIT_SRC_INLINE:
290 data = OSAL_LE32_TO_CPU(p_cmd->args.inline_val);
291 ecore_wr(p_hwfn, p_ptt, addr, data);
294 data = OSAL_LE32_TO_CPU(p_cmd->args.zeros_count);
295 if (b_must_dmae || (b_can_dmae && (data >= 64)))
296 rc = ecore_init_fill_dmae(p_hwfn, p_ptt, addr, 0, data);
298 ecore_init_fill(p_hwfn, p_ptt, addr, 0, data);
301 rc = ecore_init_cmd_array(p_hwfn, p_ptt, p_cmd,
302 b_must_dmae, b_can_dmae);
304 case INIT_SRC_RUNTIME:
305 ecore_init_rt(p_hwfn, p_ptt, addr,
306 OSAL_LE16_TO_CPU(p_cmd->args.runtime.offset),
307 OSAL_LE16_TO_CPU(p_cmd->args.runtime.size),
315 static OSAL_INLINE bool comp_eq(u32 val, u32 expected_val)
317 return (val == expected_val);
320 static OSAL_INLINE bool comp_and(u32 val, u32 expected_val)
322 return (val & expected_val) == expected_val;
325 static OSAL_INLINE bool comp_or(u32 val, u32 expected_val)
327 return (val | expected_val) > 0;
330 /* init_ops read/poll commands */
331 static void ecore_init_cmd_rd(struct ecore_hwfn *p_hwfn,
332 struct ecore_ptt *p_ptt, struct init_read_op *cmd)
334 bool (*comp_check)(u32 val, u32 expected_val);
335 u32 delay = ECORE_INIT_POLL_PERIOD_US, val;
336 u32 data, addr, poll;
339 data = OSAL_LE32_TO_CPU(cmd->op_data);
340 addr = GET_FIELD(data, INIT_READ_OP_ADDRESS) << 2;
341 poll = GET_FIELD(data, INIT_READ_OP_POLL_TYPE);
344 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
348 val = ecore_rd(p_hwfn, p_ptt, addr);
350 if (poll == INIT_POLL_NONE)
355 comp_check = comp_eq;
358 comp_check = comp_or;
361 comp_check = comp_and;
364 DP_ERR(p_hwfn, "Invalid poll comparison type %08x\n",
369 data = OSAL_LE32_TO_CPU(cmd->expected_val);
371 i < ECORE_INIT_MAX_POLL_COUNT && !comp_check(val, data); i++) {
373 val = ecore_rd(p_hwfn, p_ptt, addr);
376 if (i == ECORE_INIT_MAX_POLL_COUNT)
378 "Timeout when polling reg: 0x%08x [ Waiting-for: %08x"
379 " Got: %08x (comparsion %08x)]\n",
380 addr, OSAL_LE32_TO_CPU(cmd->expected_val), val,
381 OSAL_LE32_TO_CPU(cmd->op_data));
384 /* init_ops callbacks entry point */
385 static void ecore_init_cmd_cb(struct ecore_hwfn *p_hwfn,
386 struct ecore_ptt *p_ptt,
387 struct init_callback_op *p_cmd)
389 DP_NOTICE(p_hwfn, true,
390 "Currently init values have no need of callbacks\n");
393 static u8 ecore_init_cmd_mode_match(struct ecore_hwfn *p_hwfn,
394 u16 *p_offset, int modes)
396 struct ecore_dev *p_dev = p_hwfn->p_dev;
397 const u8 *modes_tree_buf;
398 u8 arg1, arg2, tree_val;
400 modes_tree_buf = p_dev->fw_data->modes_tree_buf;
401 tree_val = modes_tree_buf[(*p_offset)++];
403 case INIT_MODE_OP_NOT:
404 return ecore_init_cmd_mode_match(p_hwfn, p_offset, modes) ^ 1;
405 case INIT_MODE_OP_OR:
406 arg1 = ecore_init_cmd_mode_match(p_hwfn, p_offset, modes);
407 arg2 = ecore_init_cmd_mode_match(p_hwfn, p_offset, modes);
409 case INIT_MODE_OP_AND:
410 arg1 = ecore_init_cmd_mode_match(p_hwfn, p_offset, modes);
411 arg2 = ecore_init_cmd_mode_match(p_hwfn, p_offset, modes);
414 tree_val -= MAX_INIT_MODE_OPS;
415 return (modes & (1 << tree_val)) ? 1 : 0;
419 static u32 ecore_init_cmd_mode(struct ecore_hwfn *p_hwfn,
420 struct init_if_mode_op *p_cmd, int modes)
422 u16 offset = OSAL_LE16_TO_CPU(p_cmd->modes_buf_offset);
424 if (ecore_init_cmd_mode_match(p_hwfn, &offset, modes))
427 return GET_FIELD(OSAL_LE32_TO_CPU(p_cmd->op_data),
428 INIT_IF_MODE_OP_CMD_OFFSET);
431 static u32 ecore_init_cmd_phase(struct ecore_hwfn *p_hwfn,
432 struct init_if_phase_op *p_cmd,
433 u32 phase, u32 phase_id)
435 u32 data = OSAL_LE32_TO_CPU(p_cmd->phase_data);
437 if (!(GET_FIELD(data, INIT_IF_PHASE_OP_PHASE) == phase &&
438 (GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == ANY_PHASE_ID ||
439 GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == phase_id)))
440 return GET_FIELD(OSAL_LE32_TO_CPU(p_cmd->op_data),
441 INIT_IF_PHASE_OP_CMD_OFFSET);
446 enum _ecore_status_t ecore_init_run(struct ecore_hwfn *p_hwfn,
447 struct ecore_ptt *p_ptt,
448 int phase, int phase_id, int modes)
450 struct ecore_dev *p_dev = p_hwfn->p_dev;
451 enum _ecore_status_t rc = ECORE_SUCCESS;
452 u32 cmd_num, num_init_ops;
453 union init_op *init_ops;
456 num_init_ops = p_dev->fw_data->init_ops_size;
457 init_ops = p_dev->fw_data->init_ops;
459 #ifdef CONFIG_ECORE_ZIPPED_FW
460 p_hwfn->unzip_buf = OSAL_ZALLOC(p_hwfn->p_dev, GFP_ATOMIC,
461 MAX_ZIPPED_SIZE * 4);
462 if (!p_hwfn->unzip_buf) {
463 DP_NOTICE(p_hwfn, true, "Failed to allocate unzip buffer\n");
468 for (cmd_num = 0; cmd_num < num_init_ops; cmd_num++) {
469 union init_op *cmd = &init_ops[cmd_num];
470 u32 data = OSAL_LE32_TO_CPU(cmd->raw.op_data);
472 switch (GET_FIELD(data, INIT_CALLBACK_OP_OP)) {
474 rc = ecore_init_cmd_wr(p_hwfn, p_ptt, &cmd->write,
479 ecore_init_cmd_rd(p_hwfn, p_ptt, &cmd->read);
482 case INIT_OP_IF_MODE:
483 cmd_num += ecore_init_cmd_mode(p_hwfn, &cmd->if_mode,
486 case INIT_OP_IF_PHASE:
487 cmd_num += ecore_init_cmd_phase(p_hwfn, &cmd->if_phase,
489 b_dmae = GET_FIELD(data, INIT_IF_PHASE_OP_DMAE_ENABLE);
492 /* ecore_init_run is always invoked from
495 OSAL_UDELAY(cmd->delay.delay);
498 case INIT_OP_CALLBACK:
499 ecore_init_cmd_cb(p_hwfn, p_ptt, &cmd->callback);
506 #ifdef CONFIG_ECORE_ZIPPED_FW
507 OSAL_FREE(p_hwfn->p_dev, p_hwfn->unzip_buf);
512 void ecore_gtt_init(struct ecore_hwfn *p_hwfn)
518 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
519 /* This is done by MFW on ASIC; regardless, this should only
520 * be done once per chip [i.e., common]. Implementation is
521 * not too bright, but it should work on the simple FPGA/EMUL
524 bool initialized = false; /* @DPDK */
528 /* initialize PTT/GTT (poll for completion) */
530 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
531 PGLUE_B_REG_START_INIT_PTT_GTT, 1);
536 /* ptt might be overrided by HW until this is done */
538 ecore_ptt_invalidate(p_hwfn);
539 val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
540 PGLUE_B_REG_INIT_DONE_PTT_GTT);
541 } while ((val != 1) && --poll_cnt);
545 "PGLUE_B_REG_INIT_DONE didn't complete\n");
549 /* Set the global windows */
550 gtt_base = PXP_PF_WINDOW_ADMIN_START + PXP_PF_WINDOW_ADMIN_GLOBAL_START;
552 for (i = 0; i < OSAL_ARRAY_SIZE(pxp_global_win); i++)
553 if (pxp_global_win[i])
554 REG_WR(p_hwfn, gtt_base + i * PXP_GLOBAL_ENTRY_SIZE,
558 enum _ecore_status_t ecore_init_fw_data(struct ecore_dev *p_dev,
561 struct ecore_fw_data *fw = p_dev->fw_data;
563 #ifdef CONFIG_ECORE_BINARY_FW
564 struct bin_buffer_hdr *buf_hdr;
568 DP_NOTICE(p_dev, true, "Invalid fw data\n");
572 buf_hdr = (struct bin_buffer_hdr *)(uintptr_t)data;
574 offset = buf_hdr[BIN_BUF_FW_VER_INFO].offset;
575 fw->fw_ver_info = (struct fw_ver_info *)((uintptr_t)(data + offset));
577 offset = buf_hdr[BIN_BUF_INIT_CMD].offset;
578 fw->init_ops = (union init_op *)((uintptr_t)(data + offset));
580 offset = buf_hdr[BIN_BUF_INIT_VAL].offset;
581 fw->arr_data = (u32 *)((uintptr_t)(data + offset));
583 offset = buf_hdr[BIN_BUF_INIT_MODE_TREE].offset;
584 fw->modes_tree_buf = (u8 *)((uintptr_t)(data + offset));
585 len = buf_hdr[BIN_BUF_INIT_CMD].length;
586 fw->init_ops_size = len / sizeof(struct init_raw_op);
588 fw->init_ops = (union init_op *)init_ops;
589 fw->arr_data = (u32 *)init_val;
590 fw->modes_tree_buf = (u8 *)modes_tree_buf;
591 fw->init_ops_size = init_ops_size;
594 return ECORE_SUCCESS;