drivers/net/qede/base/ecore_init_ops.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 /* include the precompiled configuration values - only once */
  10 #include "bcm_osal.h"
  11 #include "ecore_hsi_common.h"
  12 #include "ecore.h"
  13 #include "ecore_hw.h"
  14 #include "ecore_status.h"
  15 #include "ecore_rt_defs.h"
  16 #include "ecore_init_fw_funcs.h"
  17
  18 #include "ecore_iro_values.h"
  19 #include "ecore_sriov.h"
  20 #include "ecore_gtt_values.h"
  21 #include "reg_addr.h"
  22 #include "ecore_init_ops.h"
  23
  24 #define ECORE_INIT_MAX_POLL_COUNT       100
  25 #define ECORE_INIT_POLL_PERIOD_US       500
  26
  27 void ecore_init_iro_array(struct ecore_dev *p_dev)
  28 {
  29         p_dev->iro_arr = iro_arr;
  30 }
  31
  32 /* Runtime configuration helpers */
  33 void ecore_init_clear_rt_data(struct ecore_hwfn *p_hwfn)
  34 {
  35         int i;
  36
  37         for (i = 0; i < RUNTIME_ARRAY_SIZE; i++)
  38                 p_hwfn->rt_data.b_valid[i] = false;
  39 }
  40
  41 void ecore_init_store_rt_reg(struct ecore_hwfn *p_hwfn, u32 rt_offset, u32 val)
  42 {
  43         if (rt_offset >= RUNTIME_ARRAY_SIZE) {
  44                 DP_ERR(p_hwfn,
  45                        "Avoid storing %u in rt_data at index %u since RUNTIME_ARRAY_SIZE is %u!\n",
  46                        val, rt_offset, RUNTIME_ARRAY_SIZE);
  47                 return;
  48         }
  49
  50         p_hwfn->rt_data.init_val[rt_offset] = val;
  51         p_hwfn->rt_data.b_valid[rt_offset] = true;
  52 }
  53
  54 void ecore_init_store_rt_agg(struct ecore_hwfn *p_hwfn,
  55                              u32 rt_offset, u32 *p_val, osal_size_t size)
  56 {
  57         osal_size_t i;
  58
  59         if ((rt_offset + size - 1) >= RUNTIME_ARRAY_SIZE) {
  60                 DP_ERR(p_hwfn,
  61                        "Avoid storing values in rt_data at indices %u-%u since RUNTIME_ARRAY_SIZE is %u!\n",
  62                        rt_offset, (u32)(rt_offset + size - 1),
  63                        RUNTIME_ARRAY_SIZE);
  64                 return;
  65         }
  66
  67         for (i = 0; i < size / sizeof(u32); i++) {
  68                 p_hwfn->rt_data.init_val[rt_offset + i] = p_val[i];
  69                 p_hwfn->rt_data.b_valid[rt_offset + i] = true;
  70         }
  71 }
  72
  73 static enum _ecore_status_t ecore_init_rt(struct ecore_hwfn *p_hwfn,
  74                                           struct ecore_ptt *p_ptt,
  75                                           u32 addr,
  76                                           u16 rt_offset,
  77                                           u16 size, bool b_must_dmae)
  78 {
  79         u32 *p_init_val = &p_hwfn->rt_data.init_val[rt_offset];
  80         bool *p_valid = &p_hwfn->rt_data.b_valid[rt_offset];
  81         u16 i, segment;
  82         enum _ecore_status_t rc = ECORE_SUCCESS;
  83
  84         /* Since not all RT entries are initialized, go over the RT and
  85          * for each segment of initialized values use DMA.
  86          */
  87         for (i = 0; i < size; i++) {
  88                 if (!p_valid[i])
  89                         continue;
  90
  91                 /* In case there isn't any wide-bus configuration here,
  92                  * simply write the data instead of using dmae.
  93                  */
  94                 if (!b_must_dmae) {
  95                         ecore_wr(p_hwfn, p_ptt, addr + (i << 2), p_init_val[i]);
  96                         continue;
  97                 }
  98
  99                 /* Start of a new segment */
 100                 for (segment = 1; i + segment < size; segment++)
 101                         if (!p_valid[i + segment])
 102                                 break;
 103
 104                 rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
 105                                          (osal_uintptr_t)(p_init_val + i),
 106                                          addr + (i << 2), segment, 0);
 107                 if (rc != ECORE_SUCCESS)
 108                         return rc;
 109
 110                 /* Jump over the entire segment, including invalid entry */
 111                 i += segment;
 112         }
 113
 114         return rc;
 115 }
 116
 117 enum _ecore_status_t ecore_init_alloc(struct ecore_hwfn *p_hwfn)
 118 {
 119         struct ecore_rt_data *rt_data = &p_hwfn->rt_data;
 120
 121         if (IS_VF(p_hwfn->p_dev))
 122                 return ECORE_SUCCESS;
 123
 124         rt_data->b_valid = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 125                                        sizeof(bool) * RUNTIME_ARRAY_SIZE);
 126         if (!rt_data->b_valid)
 127                 return ECORE_NOMEM;
 128
 129         rt_data->init_val = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 130                                         sizeof(u32) * RUNTIME_ARRAY_SIZE);
 131         if (!rt_data->init_val) {
 132                 OSAL_FREE(p_hwfn->p_dev, rt_data->b_valid);
 133                 return ECORE_NOMEM;
 134         }
 135
 136         return ECORE_SUCCESS;
 137 }
 138
 139 void ecore_init_free(struct ecore_hwfn *p_hwfn)
 140 {
 141         OSAL_FREE(p_hwfn->p_dev, p_hwfn->rt_data.init_val);
 142         OSAL_FREE(p_hwfn->p_dev, p_hwfn->rt_data.b_valid);
 143 }
 144
 145 static enum _ecore_status_t ecore_init_array_dmae(struct ecore_hwfn *p_hwfn,
 146                                                   struct ecore_ptt *p_ptt,
 147                                                   u32 addr,
 148                                                   u32 dmae_data_offset,
 149                                                   u32 size, const u32 *p_buf,
 150                                                   bool b_must_dmae,
 151                                                   bool b_can_dmae)
 152 {
 153         enum _ecore_status_t rc = ECORE_SUCCESS;
 154
 155         /* Perform DMAE only for lengthy enough sections or for wide-bus */
 156 #ifndef ASIC_ONLY
 157         if ((CHIP_REV_IS_SLOW(p_hwfn->p_dev) && (size < 16)) ||
 158             !b_can_dmae || (!b_must_dmae && (size < 16))) {
 159 #else
 160         if (!b_can_dmae || (!b_must_dmae && (size < 16))) {
 161 #endif
 162                 const u32 *data = p_buf + dmae_data_offset;
 163                 u32 i;
 164
 165                 for (i = 0; i < size; i++)
 166                         ecore_wr(p_hwfn, p_ptt, addr + (i << 2), data[i]);
 167         } else {
 168                 rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
 169                                          (osal_uintptr_t)(p_buf +
 170                                                            dmae_data_offset),
 171                                          addr, size, 0);
 172         }
 173
 174         return rc;
 175 }
 176
 177 static enum _ecore_status_t ecore_init_fill_dmae(struct ecore_hwfn *p_hwfn,
 178                                                  struct ecore_ptt *p_ptt,
 179                                                  u32 addr, u32 fill,
 180                                                  u32 fill_count)
 181 {
 182         static u32 zero_buffer[DMAE_MAX_RW_SIZE];
 183
 184         OSAL_MEMSET(zero_buffer, 0, sizeof(u32) * DMAE_MAX_RW_SIZE);
 185
 186         return ecore_dmae_host2grc(p_hwfn, p_ptt,
 187                                    (osal_uintptr_t)&zero_buffer[0],
 188                                    addr, fill_count,
 189                                    ECORE_DMAE_FLAG_RW_REPL_SRC);
 190 }
 191
 192 static void ecore_init_fill(struct ecore_hwfn *p_hwfn,
 193                             struct ecore_ptt *p_ptt,
 194                             u32 addr, u32 fill, u32 fill_count)
 195 {
 196         u32 i;
 197
 198         for (i = 0; i < fill_count; i++, addr += sizeof(u32))
 199                 ecore_wr(p_hwfn, p_ptt, addr, fill);
 200 }
 201
 202 static enum _ecore_status_t ecore_init_cmd_array(struct ecore_hwfn *p_hwfn,
 203                                                  struct ecore_ptt *p_ptt,
 204                                                  struct init_write_op *cmd,
 205                                                  bool b_must_dmae,
 206                                                  bool b_can_dmae)
 207 {
 208         u32 dmae_array_offset = OSAL_LE32_TO_CPU(cmd->args.array_offset);
 209         u32 data = OSAL_LE32_TO_CPU(cmd->data);
 210         u32 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2;
 211 #ifdef CONFIG_ECORE_ZIPPED_FW
 212         u32 offset, output_len, input_len, max_size;
 213 #endif
 214         struct ecore_dev *p_dev = p_hwfn->p_dev;
 215         union init_array_hdr *hdr;
 216         const u32 *array_data;
 217         enum _ecore_status_t rc = ECORE_SUCCESS;
 218         u32 size;
 219
 220         array_data = p_dev->fw_data->arr_data;
 221
 222         hdr = (union init_array_hdr *)
 223                 (uintptr_t)(array_data + dmae_array_offset);
 224         data = OSAL_LE32_TO_CPU(hdr->raw.data);
 225         switch (GET_FIELD(data, INIT_ARRAY_RAW_HDR_TYPE)) {
 226         case INIT_ARR_ZIPPED:
 227 #ifdef CONFIG_ECORE_ZIPPED_FW
 228                 offset = dmae_array_offset + 1;
 229                 input_len = GET_FIELD(data, INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE);
 230                 max_size = MAX_ZIPPED_SIZE * 4;
 231                 OSAL_MEMSET(p_hwfn->unzip_buf, 0, max_size);
 232
 233                 output_len = OSAL_UNZIP_DATA(p_hwfn, input_len,
 234                                 (u8 *)(uintptr_t)&array_data[offset],
 235                                 max_size,
 236                                 (u8 *)p_hwfn->unzip_buf);
 237                 if (output_len) {
 238                         rc = ecore_init_array_dmae(p_hwfn, p_ptt, addr, 0,
 239                                                    output_len,
 240                                                    p_hwfn->unzip_buf,
 241                                                    b_must_dmae, b_can_dmae);
 242                 } else {
 243                         DP_NOTICE(p_hwfn, true, "Failed to unzip dmae data\n");
 244                         rc = ECORE_INVAL;
 245                 }
 246 #else
 247                 DP_NOTICE(p_hwfn, true,
 248                           "Using zipped firmware without config enabled\n");
 249                 rc = ECORE_INVAL;
 250 #endif
 251                 break;
 252         case INIT_ARR_PATTERN:
 253                 {
 254                         u32 repeats = GET_FIELD(data,
 255                                         INIT_ARRAY_PATTERN_HDR_REPETITIONS);
 256                         u32 i;
 257
 258                         size = GET_FIELD(data,
 259                                          INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE);
 260
 261                         for (i = 0; i < repeats; i++, addr += size << 2) {
 262                                 rc = ecore_init_array_dmae(p_hwfn, p_ptt, addr,
 263                                                            dmae_array_offset +
 264                                                            1, size, array_data,
 265                                                            b_must_dmae,
 266                                                            b_can_dmae);
 267                                 if (rc)
 268                                         break;
 269                 }
 270                 break;
 271         }
 272         case INIT_ARR_STANDARD:
 273                 size = GET_FIELD(data, INIT_ARRAY_STANDARD_HDR_SIZE);
 274                 rc = ecore_init_array_dmae(p_hwfn, p_ptt, addr,
 275                                            dmae_array_offset + 1,
 276                                            size, array_data,
 277                                            b_must_dmae, b_can_dmae);
 278                 break;
 279         }
 280
 281         return rc;
 282 }
 283
 284 /* init_ops write command */
 285 static enum _ecore_status_t ecore_init_cmd_wr(struct ecore_hwfn *p_hwfn,
 286                                               struct ecore_ptt *p_ptt,
 287                                               struct init_write_op *p_cmd,
 288                                               bool b_can_dmae)
 289 {
 290         u32 data = OSAL_LE32_TO_CPU(p_cmd->data);
 291         bool b_must_dmae = GET_FIELD(data, INIT_WRITE_OP_WIDE_BUS);
 292         u32 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2;
 293         enum _ecore_status_t rc = ECORE_SUCCESS;
 294
 295         /* Sanitize */
 296         if (b_must_dmae && !b_can_dmae) {
 297                 DP_NOTICE(p_hwfn, true,
 298                           "Need to write to %08x for Wide-bus but DMAE isn't"
 299                           " allowed\n",
 300                           addr);
 301                 return ECORE_INVAL;
 302         }
 303
 304         switch (GET_FIELD(data, INIT_WRITE_OP_SOURCE)) {
 305         case INIT_SRC_INLINE:
 306                 data = OSAL_LE32_TO_CPU(p_cmd->args.inline_val);
 307                 ecore_wr(p_hwfn, p_ptt, addr, data);
 308                 break;
 309         case INIT_SRC_ZEROS:
 310                 data = OSAL_LE32_TO_CPU(p_cmd->args.zeros_count);
 311                 if (b_must_dmae || (b_can_dmae && (data >= 64)))
 312                         rc = ecore_init_fill_dmae(p_hwfn, p_ptt, addr, 0, data);
 313                 else
 314                         ecore_init_fill(p_hwfn, p_ptt, addr, 0, data);
 315                 break;
 316         case INIT_SRC_ARRAY:
 317                 rc = ecore_init_cmd_array(p_hwfn, p_ptt, p_cmd,
 318                                           b_must_dmae, b_can_dmae);
 319                 break;
 320         case INIT_SRC_RUNTIME:
 321                 ecore_init_rt(p_hwfn, p_ptt, addr,
 322                               OSAL_LE16_TO_CPU(p_cmd->args.runtime.offset),
 323                               OSAL_LE16_TO_CPU(p_cmd->args.runtime.size),
 324                               b_must_dmae);
 325                 break;
 326         }
 327
 328         return rc;
 329 }
 330
 331 static OSAL_INLINE bool comp_eq(u32 val, u32 expected_val)
 332 {
 333         return (val == expected_val);
 334 }
 335
 336 static OSAL_INLINE bool comp_and(u32 val, u32 expected_val)
 337 {
 338         return (val & expected_val) == expected_val;
 339 }
 340
 341 static OSAL_INLINE bool comp_or(u32 val, u32 expected_val)
 342 {
 343         return (val | expected_val) > 0;
 344 }
 345
 346 /* init_ops read/poll commands */
 347 static void ecore_init_cmd_rd(struct ecore_hwfn *p_hwfn,
 348                               struct ecore_ptt *p_ptt, struct init_read_op *cmd)
 349 {
 350         bool (*comp_check)(u32 val, u32 expected_val);
 351         u32 delay = ECORE_INIT_POLL_PERIOD_US, val;
 352         u32 data, addr, poll;
 353         int i;
 354
 355         data = OSAL_LE32_TO_CPU(cmd->op_data);
 356         addr = GET_FIELD(data, INIT_READ_OP_ADDRESS) << 2;
 357         poll = GET_FIELD(data, INIT_READ_OP_POLL_TYPE);
 358
 359 #ifndef ASIC_ONLY
 360         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 361                 delay *= 100;
 362 #endif
 363
 364         val = ecore_rd(p_hwfn, p_ptt, addr);
 365
 366         if (poll == INIT_POLL_NONE)
 367                 return;
 368
 369         switch (poll) {
 370         case INIT_POLL_EQ:
 371                 comp_check = comp_eq;
 372                 break;
 373         case INIT_POLL_OR:
 374                 comp_check = comp_or;
 375                 break;
 376         case INIT_POLL_AND:
 377                 comp_check = comp_and;
 378                 break;
 379         default:
 380                 DP_ERR(p_hwfn, "Invalid poll comparison type %08x\n",
 381                        cmd->op_data);
 382                 return;
 383         }
 384
 385         data = OSAL_LE32_TO_CPU(cmd->expected_val);
 386         for (i = 0;
 387              i < ECORE_INIT_MAX_POLL_COUNT && !comp_check(val, data); i++) {
 388                 OSAL_UDELAY(delay);
 389                 val = ecore_rd(p_hwfn, p_ptt, addr);
 390         }
 391
 392         if (i == ECORE_INIT_MAX_POLL_COUNT)
 393                 DP_ERR(p_hwfn,
 394                        "Timeout when polling reg: 0x%08x [ Waiting-for: %08x"
 395                        " Got: %08x (comparsion %08x)]\n",
 396                        addr, OSAL_LE32_TO_CPU(cmd->expected_val), val,
 397                        OSAL_LE32_TO_CPU(cmd->op_data));
 398 }
 399
 400 /* init_ops callbacks entry point */
 401 static void ecore_init_cmd_cb(struct ecore_hwfn *p_hwfn,
 402                               struct ecore_ptt *p_ptt,
 403                               struct init_callback_op *p_cmd)
 404 {
 405         DP_NOTICE(p_hwfn, true,
 406                   "Currently init values have no need of callbacks\n");
 407 }
 408
 409 static u8 ecore_init_cmd_mode_match(struct ecore_hwfn *p_hwfn,
 410                                     u16 *p_offset, int modes)
 411 {
 412         struct ecore_dev *p_dev = p_hwfn->p_dev;
 413         const u8 *modes_tree_buf;
 414         u8 arg1, arg2, tree_val;
 415
 416         modes_tree_buf = p_dev->fw_data->modes_tree_buf;
 417         tree_val = modes_tree_buf[(*p_offset)++];
 418         switch (tree_val) {
 419         case INIT_MODE_OP_NOT:
 420                 return ecore_init_cmd_mode_match(p_hwfn, p_offset, modes) ^ 1;
 421         case INIT_MODE_OP_OR:
 422                 arg1 = ecore_init_cmd_mode_match(p_hwfn, p_offset, modes);
 423                 arg2 = ecore_init_cmd_mode_match(p_hwfn, p_offset, modes);
 424                 return arg1 | arg2;
 425         case INIT_MODE_OP_AND:
 426                 arg1 = ecore_init_cmd_mode_match(p_hwfn, p_offset, modes);
 427                 arg2 = ecore_init_cmd_mode_match(p_hwfn, p_offset, modes);
 428                 return arg1 & arg2;
 429         default:
 430                 tree_val -= MAX_INIT_MODE_OPS;
 431                 return (modes & (1 << tree_val)) ? 1 : 0;
 432         }
 433 }
 434
 435 static u32 ecore_init_cmd_mode(struct ecore_hwfn *p_hwfn,
 436                                struct init_if_mode_op *p_cmd, int modes)
 437 {
 438         u16 offset = OSAL_LE16_TO_CPU(p_cmd->modes_buf_offset);
 439
 440         if (ecore_init_cmd_mode_match(p_hwfn, &offset, modes))
 441                 return 0;
 442         else
 443                 return GET_FIELD(OSAL_LE32_TO_CPU(p_cmd->op_data),
 444                                  INIT_IF_MODE_OP_CMD_OFFSET);
 445 }
 446
 447 static u32 ecore_init_cmd_phase(struct ecore_hwfn *p_hwfn,
 448                                 struct init_if_phase_op *p_cmd,
 449                                 u32 phase, u32 phase_id)
 450 {
 451         u32 data = OSAL_LE32_TO_CPU(p_cmd->phase_data);
 452
 453         if (!(GET_FIELD(data, INIT_IF_PHASE_OP_PHASE) == phase &&
 454               (GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == ANY_PHASE_ID ||
 455                GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == phase_id)))
 456                 return GET_FIELD(OSAL_LE32_TO_CPU(p_cmd->op_data),
 457                                  INIT_IF_PHASE_OP_CMD_OFFSET);
 458         else
 459                 return 0;
 460 }
 461
 462 enum _ecore_status_t ecore_init_run(struct ecore_hwfn *p_hwfn,
 463                                     struct ecore_ptt *p_ptt,
 464                                     int phase, int phase_id, int modes)
 465 {
 466         struct ecore_dev *p_dev = p_hwfn->p_dev;
 467         u32 cmd_num, num_init_ops;
 468         union init_op *init_ops;
 469         bool b_dmae = false;
 470         enum _ecore_status_t rc = ECORE_SUCCESS;
 471
 472         num_init_ops = p_dev->fw_data->init_ops_size;
 473         init_ops = p_dev->fw_data->init_ops;
 474
 475 #ifdef CONFIG_ECORE_ZIPPED_FW
 476         p_hwfn->unzip_buf = OSAL_ZALLOC(p_hwfn->p_dev, GFP_ATOMIC,
 477                                         MAX_ZIPPED_SIZE * 4);
 478         if (!p_hwfn->unzip_buf) {
 479                 DP_NOTICE(p_hwfn, true, "Failed to allocate unzip buffer\n");
 480                 return ECORE_NOMEM;
 481         }
 482 #endif
 483
 484         for (cmd_num = 0; cmd_num < num_init_ops; cmd_num++) {
 485                 union init_op *cmd = &init_ops[cmd_num];
 486                 u32 data = OSAL_LE32_TO_CPU(cmd->raw.op_data);
 487
 488                 switch (GET_FIELD(data, INIT_CALLBACK_OP_OP)) {
 489                 case INIT_OP_WRITE:
 490                         rc = ecore_init_cmd_wr(p_hwfn, p_ptt, &cmd->write,
 491                                                b_dmae);
 492                         break;
 493
 494                 case INIT_OP_READ:
 495                         ecore_init_cmd_rd(p_hwfn, p_ptt, &cmd->read);
 496                         break;
 497
 498                 case INIT_OP_IF_MODE:
 499                         cmd_num += ecore_init_cmd_mode(p_hwfn, &cmd->if_mode,
 500                                                        modes);
 501                         break;
 502                 case INIT_OP_IF_PHASE:
 503                         cmd_num += ecore_init_cmd_phase(p_hwfn, &cmd->if_phase,
 504                                                         phase, phase_id);
 505                         b_dmae = GET_FIELD(data, INIT_IF_PHASE_OP_DMAE_ENABLE);
 506                         break;
 507                 case INIT_OP_DELAY:
 508                         /* ecore_init_run is always invoked from
 509                          * sleep-able context
 510                          */
 511                         OSAL_UDELAY(cmd->delay.delay);
 512                         break;
 513
 514                 case INIT_OP_CALLBACK:
 515                         ecore_init_cmd_cb(p_hwfn, p_ptt, &cmd->callback);
 516                         break;
 517                 }
 518
 519                 if (rc)
 520                         break;
 521         }
 522 #ifdef CONFIG_ECORE_ZIPPED_FW
 523         OSAL_FREE(p_hwfn->p_dev, p_hwfn->unzip_buf);
 524 #endif
 525         return rc;
 526 }
 527
 528 void ecore_gtt_init(struct ecore_hwfn *p_hwfn,
 529                     struct ecore_ptt *p_ptt)
 530 {
 531         u32 gtt_base;
 532         u32 i;
 533
 534 #ifndef ASIC_ONLY
 535         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 536                 /* This is done by MFW on ASIC; regardless, this should only
 537                  * be done once per chip [i.e., common]. Implementation is
 538                  * not too bright, but it should work on the simple FPGA/EMUL
 539                  * scenarios.
 540                  */
 541                 static bool initialized;
 542                 int poll_cnt = 500;
 543                 u32 val;
 544
 545                 /* initialize PTT/GTT (poll for completion) */
 546                 if (!initialized) {
 547                         ecore_wr(p_hwfn, p_ptt,
 548                                  PGLUE_B_REG_START_INIT_PTT_GTT, 1);
 549                         initialized = true;
 550                 }
 551
 552                 do {
 553                         /* ptt might be overrided by HW until this is done */
 554                         OSAL_UDELAY(10);
 555                         ecore_ptt_invalidate(p_hwfn);
 556                         val = ecore_rd(p_hwfn, p_ptt,
 557                                        PGLUE_B_REG_INIT_DONE_PTT_GTT);
 558                 } while ((val != 1) && --poll_cnt);
 559
 560                 if (!poll_cnt)
 561                         DP_ERR(p_hwfn,
 562                                "PGLUE_B_REG_INIT_DONE didn't complete\n");
 563         }
 564 #endif
 565
 566         /* Set the global windows */
 567         gtt_base = PXP_PF_WINDOW_ADMIN_START + PXP_PF_WINDOW_ADMIN_GLOBAL_START;
 568
 569         for (i = 0; i < OSAL_ARRAY_SIZE(pxp_global_win); i++)
 570                 if (pxp_global_win[i])
 571                         REG_WR(p_hwfn, gtt_base + i * PXP_GLOBAL_ENTRY_SIZE,
 572                                pxp_global_win[i]);
 573 }
 574
 575 enum _ecore_status_t ecore_init_fw_data(struct ecore_dev *p_dev,
 576                                         const u8 *data)
 577 {
 578         struct ecore_fw_data *fw = p_dev->fw_data;
 579
 580 #ifdef CONFIG_ECORE_BINARY_FW
 581         struct bin_buffer_hdr *buf_hdr;
 582         u32 offset, len;
 583
 584         if (!data) {
 585                 DP_NOTICE(p_dev, true, "Invalid fw data\n");
 586                 return ECORE_INVAL;
 587         }
 588
 589         buf_hdr = (struct bin_buffer_hdr *)(uintptr_t)data;
 590
 591         offset = buf_hdr[BIN_BUF_INIT_FW_VER_INFO].offset;
 592         fw->fw_ver_info = (struct fw_ver_info *)((uintptr_t)(data + offset));
 593
 594         offset = buf_hdr[BIN_BUF_INIT_CMD].offset;
 595         fw->init_ops = (union init_op *)((uintptr_t)(data + offset));
 596
 597         offset = buf_hdr[BIN_BUF_INIT_VAL].offset;
 598         fw->arr_data = (u32 *)((uintptr_t)(data + offset));
 599
 600         offset = buf_hdr[BIN_BUF_INIT_MODE_TREE].offset;
 601         fw->modes_tree_buf = (u8 *)((uintptr_t)(data + offset));
 602         len = buf_hdr[BIN_BUF_INIT_CMD].length;
 603         fw->init_ops_size = len / sizeof(struct init_raw_op);
 604 #else
 605         fw->init_ops = (union init_op *)init_ops;
 606         fw->arr_data = (u32 *)init_val;
 607         fw->modes_tree_buf = (u8 *)modes_tree_buf;
 608         fw->init_ops_size = init_ops_size;
 609 #endif
 610
 611         return ECORE_SUCCESS;
 612 }