2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 /* include the precompiled configuration values - only once */
11 #include "ecore_hsi_common.h"
14 #include "ecore_status.h"
15 #include "ecore_rt_defs.h"
16 #include "ecore_init_fw_funcs.h"
18 #include "ecore_iro_values.h"
19 #include "ecore_sriov.h"
20 #include "ecore_gtt_values.h"
22 #include "ecore_init_ops.h"
24 #define ECORE_INIT_MAX_POLL_COUNT 100
25 #define ECORE_INIT_POLL_PERIOD_US 500
27 void ecore_init_iro_array(struct ecore_dev *p_dev)
29 p_dev->iro_arr = iro_arr;
32 /* Runtime configuration helpers */
33 void ecore_init_clear_rt_data(struct ecore_hwfn *p_hwfn)
37 for (i = 0; i < RUNTIME_ARRAY_SIZE; i++)
38 p_hwfn->rt_data.b_valid[i] = false;
41 void ecore_init_store_rt_reg(struct ecore_hwfn *p_hwfn, u32 rt_offset, u32 val)
43 p_hwfn->rt_data.init_val[rt_offset] = val;
44 p_hwfn->rt_data.b_valid[rt_offset] = true;
47 void ecore_init_store_rt_agg(struct ecore_hwfn *p_hwfn,
48 u32 rt_offset, u32 *p_val, osal_size_t size)
52 for (i = 0; i < size / sizeof(u32); i++) {
53 p_hwfn->rt_data.init_val[rt_offset + i] = p_val[i];
54 p_hwfn->rt_data.b_valid[rt_offset + i] = true;
58 static enum _ecore_status_t ecore_init_rt(struct ecore_hwfn *p_hwfn,
59 struct ecore_ptt *p_ptt,
62 u16 size, bool b_must_dmae)
64 u32 *p_init_val = &p_hwfn->rt_data.init_val[rt_offset];
65 bool *p_valid = &p_hwfn->rt_data.b_valid[rt_offset];
66 enum _ecore_status_t rc = ECORE_SUCCESS;
69 /* Since not all RT entries are initialized, go over the RT and
70 * for each segment of initialized values use DMA.
72 for (i = 0; i < size; i++) {
76 /* In case there isn't any wide-bus configuration here,
77 * simply write the data instead of using dmae.
80 ecore_wr(p_hwfn, p_ptt, addr + (i << 2), p_init_val[i]);
84 /* Start of a new segment */
85 for (segment = 1; i + segment < size; segment++)
86 if (!p_valid[i + segment])
89 rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
90 (osal_uintptr_t)(p_init_val + i),
91 addr + (i << 2), segment, 0);
92 if (rc != ECORE_SUCCESS)
95 /* Jump over the entire segment, including invalid entry */
102 enum _ecore_status_t ecore_init_alloc(struct ecore_hwfn *p_hwfn)
104 struct ecore_rt_data *rt_data = &p_hwfn->rt_data;
106 if (IS_VF(p_hwfn->p_dev))
107 return ECORE_SUCCESS;
109 rt_data->b_valid = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
110 sizeof(bool) * RUNTIME_ARRAY_SIZE);
111 if (!rt_data->b_valid)
114 rt_data->init_val = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
115 sizeof(u32) * RUNTIME_ARRAY_SIZE);
116 if (!rt_data->init_val) {
117 OSAL_FREE(p_hwfn->p_dev, rt_data->b_valid);
121 return ECORE_SUCCESS;
124 void ecore_init_free(struct ecore_hwfn *p_hwfn)
126 OSAL_FREE(p_hwfn->p_dev, p_hwfn->rt_data.init_val);
127 OSAL_FREE(p_hwfn->p_dev, p_hwfn->rt_data.b_valid);
130 static enum _ecore_status_t ecore_init_array_dmae(struct ecore_hwfn *p_hwfn,
131 struct ecore_ptt *p_ptt,
133 u32 dmae_data_offset,
134 u32 size, const u32 *p_buf,
138 enum _ecore_status_t rc = ECORE_SUCCESS;
140 /* Perform DMAE only for lengthy enough sections or for wide-bus */
142 if ((CHIP_REV_IS_SLOW(p_hwfn->p_dev) && (size < 16)) ||
143 !b_can_dmae || (!b_must_dmae && (size < 16))) {
145 if (!b_can_dmae || (!b_must_dmae && (size < 16))) {
147 const u32 *data = p_buf + dmae_data_offset;
150 for (i = 0; i < size; i++)
151 ecore_wr(p_hwfn, p_ptt, addr + (i << 2), data[i]);
153 rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
154 (osal_uintptr_t)(p_buf +
162 static enum _ecore_status_t ecore_init_fill_dmae(struct ecore_hwfn *p_hwfn,
163 struct ecore_ptt *p_ptt,
167 static u32 zero_buffer[DMAE_MAX_RW_SIZE];
169 OSAL_MEMSET(zero_buffer, 0, sizeof(u32) * DMAE_MAX_RW_SIZE);
171 return ecore_dmae_host2grc(p_hwfn, p_ptt,
172 (osal_uintptr_t)&zero_buffer[0],
174 ECORE_DMAE_FLAG_RW_REPL_SRC);
177 static void ecore_init_fill(struct ecore_hwfn *p_hwfn,
178 struct ecore_ptt *p_ptt,
179 u32 addr, u32 fill, u32 fill_count)
183 for (i = 0; i < fill_count; i++, addr += sizeof(u32))
184 ecore_wr(p_hwfn, p_ptt, addr, fill);
187 static enum _ecore_status_t ecore_init_cmd_array(struct ecore_hwfn *p_hwfn,
188 struct ecore_ptt *p_ptt,
189 struct init_write_op *cmd,
193 #ifdef CONFIG_ECORE_ZIPPED_FW
194 u32 offset, output_len, input_len, max_size;
196 u32 dmae_array_offset = OSAL_LE32_TO_CPU(cmd->args.array_offset);
197 struct ecore_dev *p_dev = p_hwfn->p_dev;
198 enum _ecore_status_t rc = ECORE_SUCCESS;
199 union init_array_hdr *hdr;
200 const u32 *array_data;
201 u32 size, addr, data;
203 array_data = p_dev->fw_data->arr_data;
204 data = OSAL_LE32_TO_CPU(cmd->data);
205 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2;
207 hdr = (union init_array_hdr *)
208 (uintptr_t)(array_data + dmae_array_offset);
209 data = OSAL_LE32_TO_CPU(hdr->raw.data);
210 switch (GET_FIELD(data, INIT_ARRAY_RAW_HDR_TYPE)) {
211 case INIT_ARR_ZIPPED:
212 #ifdef CONFIG_ECORE_ZIPPED_FW
213 offset = dmae_array_offset + 1;
214 input_len = GET_FIELD(data, INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE);
215 max_size = MAX_ZIPPED_SIZE * 4;
216 OSAL_MEMSET(p_hwfn->unzip_buf, 0, max_size);
218 output_len = OSAL_UNZIP_DATA(p_hwfn, input_len,
219 (u8 *)(uintptr_t)&array_data[offset],
221 (u8 *)p_hwfn->unzip_buf);
223 rc = ecore_init_array_dmae(p_hwfn, p_ptt, addr, 0,
226 b_must_dmae, b_can_dmae);
228 DP_NOTICE(p_hwfn, true, "Failed to unzip dmae data\n");
232 DP_NOTICE(p_hwfn, true,
233 "Using zipped firmware without config enabled\n");
237 case INIT_ARR_PATTERN:
239 u32 repeats = GET_FIELD(data,
240 INIT_ARRAY_PATTERN_HDR_REPETITIONS);
243 size = GET_FIELD(data,
244 INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE);
246 for (i = 0; i < repeats; i++, addr += size << 2) {
247 rc = ecore_init_array_dmae(p_hwfn, p_ptt, addr,
257 case INIT_ARR_STANDARD:
258 size = GET_FIELD(data, INIT_ARRAY_STANDARD_HDR_SIZE);
259 rc = ecore_init_array_dmae(p_hwfn, p_ptt, addr,
260 dmae_array_offset + 1,
262 b_must_dmae, b_can_dmae);
269 /* init_ops write command */
270 static enum _ecore_status_t ecore_init_cmd_wr(struct ecore_hwfn *p_hwfn,
271 struct ecore_ptt *p_ptt,
272 struct init_write_op *p_cmd,
275 enum _ecore_status_t rc = ECORE_SUCCESS;
279 data = OSAL_LE32_TO_CPU(p_cmd->data);
280 b_must_dmae = GET_FIELD(data, INIT_WRITE_OP_WIDE_BUS);
281 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2;
284 if (b_must_dmae && !b_can_dmae) {
285 DP_NOTICE(p_hwfn, true,
286 "Need to write to %08x for Wide-bus but DMAE isn't"
292 switch (GET_FIELD(data, INIT_WRITE_OP_SOURCE)) {
293 case INIT_SRC_INLINE:
294 data = OSAL_LE32_TO_CPU(p_cmd->args.inline_val);
295 ecore_wr(p_hwfn, p_ptt, addr, data);
298 data = OSAL_LE32_TO_CPU(p_cmd->args.zeros_count);
299 if (b_must_dmae || (b_can_dmae && (data >= 64)))
300 rc = ecore_init_fill_dmae(p_hwfn, p_ptt, addr, 0, data);
302 ecore_init_fill(p_hwfn, p_ptt, addr, 0, data);
305 rc = ecore_init_cmd_array(p_hwfn, p_ptt, p_cmd,
306 b_must_dmae, b_can_dmae);
308 case INIT_SRC_RUNTIME:
309 ecore_init_rt(p_hwfn, p_ptt, addr,
310 OSAL_LE16_TO_CPU(p_cmd->args.runtime.offset),
311 OSAL_LE16_TO_CPU(p_cmd->args.runtime.size),
319 static OSAL_INLINE bool comp_eq(u32 val, u32 expected_val)
321 return (val == expected_val);
324 static OSAL_INLINE bool comp_and(u32 val, u32 expected_val)
326 return (val & expected_val) == expected_val;
329 static OSAL_INLINE bool comp_or(u32 val, u32 expected_val)
331 return (val | expected_val) > 0;
334 /* init_ops read/poll commands */
335 static void ecore_init_cmd_rd(struct ecore_hwfn *p_hwfn,
336 struct ecore_ptt *p_ptt, struct init_read_op *cmd)
338 bool (*comp_check)(u32 val, u32 expected_val);
339 u32 delay = ECORE_INIT_POLL_PERIOD_US, val;
340 u32 data, addr, poll;
343 data = OSAL_LE32_TO_CPU(cmd->op_data);
344 addr = GET_FIELD(data, INIT_READ_OP_ADDRESS) << 2;
345 poll = GET_FIELD(data, INIT_READ_OP_POLL_TYPE);
348 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
352 val = ecore_rd(p_hwfn, p_ptt, addr);
354 if (poll == INIT_POLL_NONE)
359 comp_check = comp_eq;
362 comp_check = comp_or;
365 comp_check = comp_and;
368 DP_ERR(p_hwfn, "Invalid poll comparison type %08x\n",
373 data = OSAL_LE32_TO_CPU(cmd->expected_val);
375 i < ECORE_INIT_MAX_POLL_COUNT && !comp_check(val, data); i++) {
377 val = ecore_rd(p_hwfn, p_ptt, addr);
380 if (i == ECORE_INIT_MAX_POLL_COUNT)
382 "Timeout when polling reg: 0x%08x [ Waiting-for: %08x"
383 " Got: %08x (comparsion %08x)]\n",
384 addr, OSAL_LE32_TO_CPU(cmd->expected_val), val,
385 OSAL_LE32_TO_CPU(cmd->op_data));
388 /* init_ops callbacks entry point */
389 static void ecore_init_cmd_cb(struct ecore_hwfn *p_hwfn,
390 struct ecore_ptt *p_ptt,
391 struct init_callback_op *p_cmd)
393 DP_NOTICE(p_hwfn, true,
394 "Currently init values have no need of callbacks\n");
397 static u8 ecore_init_cmd_mode_match(struct ecore_hwfn *p_hwfn,
398 u16 *p_offset, int modes)
400 struct ecore_dev *p_dev = p_hwfn->p_dev;
401 const u8 *modes_tree_buf;
402 u8 arg1, arg2, tree_val;
404 modes_tree_buf = p_dev->fw_data->modes_tree_buf;
405 tree_val = modes_tree_buf[(*p_offset)++];
407 case INIT_MODE_OP_NOT:
408 return ecore_init_cmd_mode_match(p_hwfn, p_offset, modes) ^ 1;
409 case INIT_MODE_OP_OR:
410 arg1 = ecore_init_cmd_mode_match(p_hwfn, p_offset, modes);
411 arg2 = ecore_init_cmd_mode_match(p_hwfn, p_offset, modes);
413 case INIT_MODE_OP_AND:
414 arg1 = ecore_init_cmd_mode_match(p_hwfn, p_offset, modes);
415 arg2 = ecore_init_cmd_mode_match(p_hwfn, p_offset, modes);
418 tree_val -= MAX_INIT_MODE_OPS;
419 return (modes & (1 << tree_val)) ? 1 : 0;
423 static u32 ecore_init_cmd_mode(struct ecore_hwfn *p_hwfn,
424 struct init_if_mode_op *p_cmd, int modes)
426 u16 offset = OSAL_LE16_TO_CPU(p_cmd->modes_buf_offset);
428 if (ecore_init_cmd_mode_match(p_hwfn, &offset, modes))
431 return GET_FIELD(OSAL_LE32_TO_CPU(p_cmd->op_data),
432 INIT_IF_MODE_OP_CMD_OFFSET);
435 static u32 ecore_init_cmd_phase(struct ecore_hwfn *p_hwfn,
436 struct init_if_phase_op *p_cmd,
437 u32 phase, u32 phase_id)
439 u32 data = OSAL_LE32_TO_CPU(p_cmd->phase_data);
441 if (!(GET_FIELD(data, INIT_IF_PHASE_OP_PHASE) == phase &&
442 (GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == ANY_PHASE_ID ||
443 GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == phase_id)))
444 return GET_FIELD(OSAL_LE32_TO_CPU(p_cmd->op_data),
445 INIT_IF_PHASE_OP_CMD_OFFSET);
450 enum _ecore_status_t ecore_init_run(struct ecore_hwfn *p_hwfn,
451 struct ecore_ptt *p_ptt,
452 int phase, int phase_id, int modes)
454 struct ecore_dev *p_dev = p_hwfn->p_dev;
455 enum _ecore_status_t rc = ECORE_SUCCESS;
456 u32 cmd_num, num_init_ops;
457 union init_op *init_ops;
460 num_init_ops = p_dev->fw_data->init_ops_size;
461 init_ops = p_dev->fw_data->init_ops;
463 #ifdef CONFIG_ECORE_ZIPPED_FW
464 p_hwfn->unzip_buf = OSAL_ZALLOC(p_hwfn->p_dev, GFP_ATOMIC,
465 MAX_ZIPPED_SIZE * 4);
466 if (!p_hwfn->unzip_buf) {
467 DP_NOTICE(p_hwfn, true, "Failed to allocate unzip buffer\n");
472 for (cmd_num = 0; cmd_num < num_init_ops; cmd_num++) {
473 union init_op *cmd = &init_ops[cmd_num];
474 u32 data = OSAL_LE32_TO_CPU(cmd->raw.op_data);
476 switch (GET_FIELD(data, INIT_CALLBACK_OP_OP)) {
478 rc = ecore_init_cmd_wr(p_hwfn, p_ptt, &cmd->write,
483 ecore_init_cmd_rd(p_hwfn, p_ptt, &cmd->read);
486 case INIT_OP_IF_MODE:
487 cmd_num += ecore_init_cmd_mode(p_hwfn, &cmd->if_mode,
490 case INIT_OP_IF_PHASE:
491 cmd_num += ecore_init_cmd_phase(p_hwfn, &cmd->if_phase,
493 b_dmae = GET_FIELD(data, INIT_IF_PHASE_OP_DMAE_ENABLE);
496 /* ecore_init_run is always invoked from
499 OSAL_UDELAY(cmd->delay.delay);
502 case INIT_OP_CALLBACK:
503 ecore_init_cmd_cb(p_hwfn, p_ptt, &cmd->callback);
510 #ifdef CONFIG_ECORE_ZIPPED_FW
511 OSAL_FREE(p_hwfn->p_dev, p_hwfn->unzip_buf);
516 void ecore_gtt_init(struct ecore_hwfn *p_hwfn)
522 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
523 /* This is done by MFW on ASIC; regardless, this should only
524 * be done once per chip [i.e., common]. Implementation is
525 * not too bright, but it should work on the simple FPGA/EMUL
528 static bool initialized;
532 /* initialize PTT/GTT (poll for completion) */
534 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
535 PGLUE_B_REG_START_INIT_PTT_GTT, 1);
540 /* ptt might be overrided by HW until this is done */
542 ecore_ptt_invalidate(p_hwfn);
543 val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
544 PGLUE_B_REG_INIT_DONE_PTT_GTT);
545 } while ((val != 1) && --poll_cnt);
549 "PGLUE_B_REG_INIT_DONE didn't complete\n");
553 /* Set the global windows */
554 gtt_base = PXP_PF_WINDOW_ADMIN_START + PXP_PF_WINDOW_ADMIN_GLOBAL_START;
556 for (i = 0; i < OSAL_ARRAY_SIZE(pxp_global_win); i++)
557 if (pxp_global_win[i])
558 REG_WR(p_hwfn, gtt_base + i * PXP_GLOBAL_ENTRY_SIZE,
562 enum _ecore_status_t ecore_init_fw_data(struct ecore_dev *p_dev,
565 struct ecore_fw_data *fw = p_dev->fw_data;
567 #ifdef CONFIG_ECORE_BINARY_FW
568 struct bin_buffer_hdr *buf_hdr;
572 DP_NOTICE(p_dev, true, "Invalid fw data\n");
576 buf_hdr = (struct bin_buffer_hdr *)(uintptr_t)data;
578 offset = buf_hdr[BIN_BUF_INIT_FW_VER_INFO].offset;
579 fw->fw_ver_info = (struct fw_ver_info *)((uintptr_t)(data + offset));
581 offset = buf_hdr[BIN_BUF_INIT_CMD].offset;
582 fw->init_ops = (union init_op *)((uintptr_t)(data + offset));
584 offset = buf_hdr[BIN_BUF_INIT_VAL].offset;
585 fw->arr_data = (u32 *)((uintptr_t)(data + offset));
587 offset = buf_hdr[BIN_BUF_INIT_MODE_TREE].offset;
588 fw->modes_tree_buf = (u8 *)((uintptr_t)(data + offset));
589 len = buf_hdr[BIN_BUF_INIT_CMD].length;
590 fw->init_ops_size = len / sizeof(struct init_raw_op);
592 fw->init_ops = (union init_op *)init_ops;
593 fw->arr_data = (u32 *)init_val;
594 fw->modes_tree_buf = (u8 *)modes_tree_buf;
595 fw->init_ops_size = init_ops_size;
598 return ECORE_SUCCESS;