1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
7 #ifndef __ECORE_INIT_OPS__
8 #define __ECORE_INIT_OPS__
13 * @brief ecore_init_iro_array - init iro_arr.
18 void ecore_init_iro_array(struct ecore_dev *p_dev);
21 * @brief ecore_init_run - Run the init-sequence.
29 * @return _ecore_status_t
31 enum _ecore_status_t ecore_init_run(struct ecore_hwfn *p_hwfn,
32 struct ecore_ptt *p_ptt,
38 * @brief ecore_init_hwfn_allocate - Allocate RT array, Store 'values' ptrs.
43 * @return _ecore_status_t
45 enum _ecore_status_t ecore_init_alloc(struct ecore_hwfn *p_hwfn);
48 * @brief ecore_init_hwfn_deallocate
53 void ecore_init_free(struct ecore_hwfn *p_hwfn);
57 * @brief ecore_init_clear_rt_data - Clears the runtime init array.
62 void ecore_init_clear_rt_data(struct ecore_hwfn *p_hwfn);
65 * @brief ecore_init_store_rt_reg - Store a configuration value in the RT array.
72 void ecore_init_store_rt_reg(struct ecore_hwfn *p_hwfn,
76 #define STORE_RT_REG(hwfn, offset, val) \
77 ecore_init_store_rt_reg(hwfn, offset, val)
79 #define OVERWRITE_RT_REG(hwfn, offset, val) \
80 ecore_init_store_rt_reg(hwfn, offset, val)
92 void ecore_init_store_rt_agg(struct ecore_hwfn *p_hwfn,
97 #define STORE_RT_REG_AGG(hwfn, offset, val) \
98 ecore_init_store_rt_agg(hwfn, offset, (u32 *)&val, sizeof(val))
100 #endif /* __ECORE_INIT_OPS__ */