2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_spq.h"
12 #include "ecore_gtt_reg_addr.h"
13 #include "ecore_init_ops.h"
14 #include "ecore_rt_defs.h"
15 #include "ecore_int.h"
18 #include "ecore_sriov.h"
20 #include "ecore_hw_defs.h"
21 #include "ecore_hsi_common.h"
22 #include "ecore_mcp.h"
24 struct ecore_pi_info {
25 ecore_int_comp_cb_t comp_cb;
26 void *cookie; /* Will be sent to the compl cb function */
29 struct ecore_sb_sp_info {
30 struct ecore_sb_info sb_info;
31 /* per protocol index data */
32 struct ecore_pi_info pi_info_arr[PIS_PER_SB_E4];
35 enum ecore_attention_type {
37 ECORE_ATTN_TYPE_PARITY,
40 #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
41 ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
43 struct aeu_invert_reg_bit {
46 #define ATTENTION_PARITY (1 << 0)
48 #define ATTENTION_LENGTH_MASK (0x00000ff0)
49 #define ATTENTION_LENGTH_SHIFT (4)
50 #define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \
51 ATTENTION_LENGTH_SHIFT)
52 #define ATTENTION_SINGLE (1 << ATTENTION_LENGTH_SHIFT)
53 #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY)
54 #define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \
57 /* Multiple bits start with this offset */
58 #define ATTENTION_OFFSET_MASK (0x000ff000)
59 #define ATTENTION_OFFSET_SHIFT (12)
61 #define ATTENTION_BB_MASK (0x00700000)
62 #define ATTENTION_BB_SHIFT (20)
63 #define ATTENTION_BB(value) ((value) << ATTENTION_BB_SHIFT)
64 #define ATTENTION_BB_DIFFERENT (1 << 23)
66 #define ATTENTION_CLEAR_ENABLE (1 << 28)
69 /* Callback to call if attention will be triggered */
70 enum _ecore_status_t (*cb)(struct ecore_hwfn *p_hwfn);
72 enum block_id block_index;
75 struct aeu_invert_reg {
76 struct aeu_invert_reg_bit bits[32];
79 #define MAX_ATTN_GRPS (8)
80 #define NUM_ATTN_REGS (9)
82 static enum _ecore_status_t ecore_mcp_attn_cb(struct ecore_hwfn *p_hwfn)
84 u32 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE);
86 DP_INFO(p_hwfn->p_dev, "MCP_REG_CPU_STATE: %08x - Masking...\n", tmp);
87 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 0xffffffff);
92 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK (0x3c000)
93 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT (14)
94 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK (0x03fc0)
95 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT (6)
96 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK (0x00020)
97 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT (5)
98 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK (0x0001e)
99 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT (1)
100 #define ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK (0x1)
101 #define ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT (0)
102 #define ECORE_PSWHST_ATTENTION_VF_DISABLED (0x1)
103 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1)
104 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1)
105 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0)
106 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0x1e)
107 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1)
108 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x20)
109 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5)
110 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0x3fc0)
111 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6)
112 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0x3c000)
113 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14)
114 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0x3fc0000)
115 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18)
116 static enum _ecore_status_t ecore_pswhst_attn_cb(struct ecore_hwfn *p_hwfn)
119 ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
120 PSWHST_REG_VF_DISABLED_ERROR_VALID);
122 /* Disabled VF access */
123 if (tmp & ECORE_PSWHST_ATTENTION_VF_DISABLED) {
126 addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
127 PSWHST_REG_VF_DISABLED_ERROR_ADDRESS);
128 data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
129 PSWHST_REG_VF_DISABLED_ERROR_DATA);
130 DP_INFO(p_hwfn->p_dev,
131 "PF[0x%02x] VF [0x%02x] [Valid 0x%02x] Client [0x%02x]"
132 " Write [0x%02x] Addr [0x%08x]\n",
133 (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK)
134 >> ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT),
135 (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK)
136 >> ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT),
138 ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK) >>
139 ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT),
141 ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK) >>
142 ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT),
144 ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK) >>
145 ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT),
149 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
150 PSWHST_REG_INCORRECT_ACCESS_VALID);
151 if (tmp & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS) {
152 u32 addr, data, length;
154 addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
155 PSWHST_REG_INCORRECT_ACCESS_ADDRESS);
156 data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
157 PSWHST_REG_INCORRECT_ACCESS_DATA);
158 length = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
159 PSWHST_REG_INCORRECT_ACCESS_LENGTH);
161 DP_INFO(p_hwfn->p_dev,
162 "Incorrect access to %08x of length %08x - PF [%02x]"
163 " VF [%04x] [valid %02x] client [%02x] write [%02x]"
164 " Byte-Enable [%04x] [%08x]\n",
167 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK) >>
168 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT),
170 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK) >>
171 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT),
173 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK) >>
174 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT),
176 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK) >>
177 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT),
179 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK) >>
180 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT),
182 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK) >>
183 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT),
187 /* TODO - We know 'some' of these are legal due to virtualization,
188 * but is it true for all of them?
190 return ECORE_SUCCESS;
193 #define ECORE_GRC_ATTENTION_VALID_BIT (1 << 0)
194 #define ECORE_GRC_ATTENTION_ADDRESS_MASK (0x7fffff << 0)
195 #define ECORE_GRC_ATTENTION_RDWR_BIT (1 << 23)
196 #define ECORE_GRC_ATTENTION_MASTER_MASK (0xf << 24)
197 #define ECORE_GRC_ATTENTION_MASTER_SHIFT (24)
198 #define ECORE_GRC_ATTENTION_PF_MASK (0xf)
199 #define ECORE_GRC_ATTENTION_VF_MASK (0xff << 4)
200 #define ECORE_GRC_ATTENTION_VF_SHIFT (4)
201 #define ECORE_GRC_ATTENTION_PRIV_MASK (0x3 << 14)
202 #define ECORE_GRC_ATTENTION_PRIV_SHIFT (14)
203 #define ECORE_GRC_ATTENTION_PRIV_VF (0)
204 static const char *grc_timeout_attn_master_to_str(u8 master)
232 static enum _ecore_status_t ecore_grc_attn_cb(struct ecore_hwfn *p_hwfn)
236 /* We've already cleared the timeout interrupt register, so we learn
237 * of interrupts via the validity register
239 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
240 GRC_REG_TIMEOUT_ATTN_ACCESS_VALID);
241 if (!(tmp & ECORE_GRC_ATTENTION_VALID_BIT))
244 /* Read the GRC timeout information */
245 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
246 GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0);
247 tmp2 = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
248 GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1);
250 DP_NOTICE(p_hwfn->p_dev, false,
251 "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n",
253 (tmp & ECORE_GRC_ATTENTION_RDWR_BIT) ? "Write to"
255 (tmp & ECORE_GRC_ATTENTION_ADDRESS_MASK) << 2,
256 grc_timeout_attn_master_to_str(
257 (tmp & ECORE_GRC_ATTENTION_MASTER_MASK) >>
258 ECORE_GRC_ATTENTION_MASTER_SHIFT),
259 (tmp2 & ECORE_GRC_ATTENTION_PF_MASK),
260 (((tmp2 & ECORE_GRC_ATTENTION_PRIV_MASK) >>
261 ECORE_GRC_ATTENTION_PRIV_SHIFT) ==
262 ECORE_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant:)",
263 (tmp2 & ECORE_GRC_ATTENTION_VF_MASK) >>
264 ECORE_GRC_ATTENTION_VF_SHIFT);
267 /* Regardles of anything else, clean the validity bit */
268 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
269 GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0);
270 return ECORE_SUCCESS;
273 #define ECORE_PGLUE_ATTENTION_VALID (1 << 29)
274 #define ECORE_PGLUE_ATTENTION_RD_VALID (1 << 26)
275 #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf << 20)
276 #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20)
277 #define ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID (1 << 19)
278 #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff << 24)
279 #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24)
280 #define ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR (1 << 21)
281 #define ECORE_PGLUE_ATTENTION_DETAILS2_BME (1 << 22)
282 #define ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN (1 << 23)
283 #define ECORE_PGLUE_ATTENTION_ICPL_VALID (1 << 23)
284 #define ECORE_PGLUE_ATTENTION_ZLR_VALID (1 << 25)
285 #define ECORE_PGLUE_ATTENTION_ILT_VALID (1 << 23)
287 enum _ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn *p_hwfn,
288 struct ecore_ptt *p_ptt)
292 tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS2);
293 if (tmp & ECORE_PGLUE_ATTENTION_VALID) {
294 u32 addr_lo, addr_hi, details;
296 addr_lo = ecore_rd(p_hwfn, p_ptt,
297 PGLUE_B_REG_TX_ERR_WR_ADD_31_0);
298 addr_hi = ecore_rd(p_hwfn, p_ptt,
299 PGLUE_B_REG_TX_ERR_WR_ADD_63_32);
300 details = ecore_rd(p_hwfn, p_ptt,
301 PGLUE_B_REG_TX_ERR_WR_DETAILS);
303 DP_NOTICE(p_hwfn, false,
304 "Illegal write by chip to [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
305 addr_hi, addr_lo, details,
307 ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>
308 ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
310 ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >>
311 ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
313 ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0),
315 (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ?
317 (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ?
319 (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ?
323 tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS2);
324 if (tmp & ECORE_PGLUE_ATTENTION_RD_VALID) {
325 u32 addr_lo, addr_hi, details;
327 addr_lo = ecore_rd(p_hwfn, p_ptt,
328 PGLUE_B_REG_TX_ERR_RD_ADD_31_0);
329 addr_hi = ecore_rd(p_hwfn, p_ptt,
330 PGLUE_B_REG_TX_ERR_RD_ADD_63_32);
331 details = ecore_rd(p_hwfn, p_ptt,
332 PGLUE_B_REG_TX_ERR_RD_DETAILS);
334 DP_NOTICE(p_hwfn, false,
335 "Illegal read by chip from [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
336 addr_hi, addr_lo, details,
338 ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>
339 ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
341 ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >>
342 ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
344 ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0),
346 (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ?
348 (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ?
350 (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ?
354 tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL);
355 if (tmp & ECORE_PGLUE_ATTENTION_ICPL_VALID)
356 DP_NOTICE(p_hwfn, false, "ICPL erorr - %08x\n", tmp);
358 tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS);
359 if (tmp & ECORE_PGLUE_ATTENTION_ZLR_VALID) {
360 u32 addr_hi, addr_lo;
362 addr_lo = ecore_rd(p_hwfn, p_ptt,
363 PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0);
364 addr_hi = ecore_rd(p_hwfn, p_ptt,
365 PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32);
367 DP_NOTICE(p_hwfn, false,
368 "ICPL erorr - %08x [Address %08x:%08x]\n",
369 tmp, addr_hi, addr_lo);
372 tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_DETAILS2);
373 if (tmp & ECORE_PGLUE_ATTENTION_ILT_VALID) {
374 u32 addr_hi, addr_lo, details;
376 addr_lo = ecore_rd(p_hwfn, p_ptt,
377 PGLUE_B_REG_VF_ILT_ERR_ADD_31_0);
378 addr_hi = ecore_rd(p_hwfn, p_ptt,
379 PGLUE_B_REG_VF_ILT_ERR_ADD_63_32);
380 details = ecore_rd(p_hwfn, p_ptt,
381 PGLUE_B_REG_VF_ILT_ERR_DETAILS);
383 DP_NOTICE(p_hwfn, false,
384 "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n",
385 details, tmp, addr_hi, addr_lo);
388 /* Clear the indications */
389 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2));
391 return ECORE_SUCCESS;
394 static enum _ecore_status_t ecore_pglueb_rbc_attn_cb(struct ecore_hwfn *p_hwfn)
396 return ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt);
399 static enum _ecore_status_t ecore_fw_assertion(struct ecore_hwfn *p_hwfn)
401 DP_NOTICE(p_hwfn, false, "FW assertion!\n");
403 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FW_ASSERT);
408 static enum _ecore_status_t
409 ecore_general_attention_35(struct ecore_hwfn *p_hwfn)
411 DP_INFO(p_hwfn, "General attention 35!\n");
413 return ECORE_SUCCESS;
416 #define ECORE_DORQ_ATTENTION_REASON_MASK (0xfffff)
417 #define ECORE_DORQ_ATTENTION_OPAQUE_MASK (0xffff)
418 #define ECORE_DORQ_ATTENTION_OPAQUE_SHIFT (0x0)
419 #define ECORE_DORQ_ATTENTION_SIZE_MASK (0x7f)
420 #define ECORE_DORQ_ATTENTION_SIZE_SHIFT (16)
422 #define ECORE_DB_REC_COUNT 10
423 #define ECORE_DB_REC_INTERVAL 100
425 /* assumes sticky overflow indication was set for this PF */
426 static enum _ecore_status_t ecore_db_rec_attn(struct ecore_hwfn *p_hwfn,
427 struct ecore_ptt *p_ptt)
429 u8 count = ECORE_DB_REC_COUNT;
432 /* wait for usage to zero or count to run out. This is necessary since
433 * EDPM doorbell transactions can take multiple 64b cycles, and as such
434 * can "split" over the pci. Possibly, the doorbell drop can happen with
435 * half an EDPM in the queue and other half dropped. Another EDPM
436 * doorbell to the same address (from doorbell recovery mechanism or
437 * from the doorbelling entity) could have first half dropped and second
438 * half interperted as continuation of the first. To prevent such
439 * malformed doorbells from reaching the device, flush the queue before
440 * releaseing the overflow sticky indication.
442 while (count-- && usage) {
443 usage = ecore_rd(p_hwfn, p_ptt, DORQ_REG_PF_USAGE_CNT);
444 OSAL_UDELAY(ECORE_DB_REC_INTERVAL);
447 /* should have been depleted by now */
449 DP_NOTICE(p_hwfn->p_dev, false,
450 "DB recovery: doorbell usage failed to zero after %d usec. usage was %x\n",
451 ECORE_DB_REC_INTERVAL * ECORE_DB_REC_COUNT, usage);
452 return ECORE_TIMEOUT;
455 /* flush any pedning (e)dpm as they may never arrive */
456 ecore_wr(p_hwfn, p_ptt, DORQ_REG_DPM_FORCE_ABORT, 0x1);
458 /* release overflow sticky indication (stop silently dropping
461 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0);
463 /* repeat all last doorbells (doorbell drop recovery) */
464 ecore_db_recovery_execute(p_hwfn, DB_REC_REAL_DEAL);
466 return ECORE_SUCCESS;
469 static enum _ecore_status_t ecore_dorq_attn_cb(struct ecore_hwfn *p_hwfn)
471 u32 int_sts, first_drop_reason, details, address, overflow,
473 struct ecore_ptt *p_ptt = p_hwfn->p_dpc_ptt;
474 enum _ecore_status_t rc;
476 int_sts = ecore_rd(p_hwfn, p_ptt, DORQ_REG_INT_STS);
477 DP_NOTICE(p_hwfn->p_dev, false, "DORQ attention. int_sts was %x\n",
480 /* int_sts may be zero since all PFs were interrupted for doorbell
481 * overflow but another one already handled it. Can abort here. If
482 * This PF also requires overflow recovery we will be interrupted again
485 return ECORE_SUCCESS;
487 /* check if db_drop or overflow happened */
488 if (int_sts & (DORQ_REG_INT_STS_DB_DROP |
489 DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR)) {
490 /* obtain data about db drop/overflow */
491 first_drop_reason = ecore_rd(p_hwfn, p_ptt,
492 DORQ_REG_DB_DROP_REASON) &
493 ECORE_DORQ_ATTENTION_REASON_MASK;
494 details = ecore_rd(p_hwfn, p_ptt,
495 DORQ_REG_DB_DROP_DETAILS);
496 address = ecore_rd(p_hwfn, p_ptt,
497 DORQ_REG_DB_DROP_DETAILS_ADDRESS);
498 overflow = ecore_rd(p_hwfn, p_ptt,
499 DORQ_REG_PF_OVFL_STICKY);
500 all_drops_reason = ecore_rd(p_hwfn, p_ptt,
501 DORQ_REG_DB_DROP_DETAILS_REASON);
504 DP_NOTICE(p_hwfn->p_dev, false,
505 "Doorbell drop occurred\n"
506 "Address\t\t0x%08x\t(second BAR address)\n"
507 "FID\t\t0x%04x\t\t(Opaque FID)\n"
508 "Size\t\t0x%04x\t\t(in bytes)\n"
509 "1st drop reason\t0x%08x\t(details on first drop since last handling)\n"
510 "Sticky reasons\t0x%08x\t(all drop reasons since last handling)\n"
511 "Overflow\t0x%x\t\t(a per PF indication)\n",
513 GET_FIELD(details, ECORE_DORQ_ATTENTION_OPAQUE),
514 GET_FIELD(details, ECORE_DORQ_ATTENTION_SIZE) * 4,
515 first_drop_reason, all_drops_reason, overflow);
517 /* if this PF caused overflow, initiate recovery */
519 rc = ecore_db_rec_attn(p_hwfn, p_ptt);
520 if (rc != ECORE_SUCCESS)
524 /* clear the doorbell drop details and prepare for next drop */
525 ecore_wr(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS_REL, 0);
527 /* mark interrupt as handeld (note: even if drop was due to a
528 * different reason than overflow we mark as handled)
530 ecore_wr(p_hwfn, p_ptt, DORQ_REG_INT_STS_WR,
531 DORQ_REG_INT_STS_DB_DROP |
532 DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR);
534 /* if there are no indications otherthan drop indications,
537 if ((int_sts & ~(DORQ_REG_INT_STS_DB_DROP |
538 DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR |
539 DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) == 0)
540 return ECORE_SUCCESS;
543 /* some other indication was present - non recoverable */
544 DP_INFO(p_hwfn, "DORQ fatal attention\n");
549 static enum _ecore_status_t ecore_tm_attn_cb(struct ecore_hwfn *p_hwfn)
552 if (CHIP_REV_IS_EMUL_B0(p_hwfn->p_dev)) {
553 u32 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
556 if (val & ~(TM_REG_INT_STS_1_PEND_TASK_SCAN |
557 TM_REG_INT_STS_1_PEND_CONN_SCAN))
560 if (val & (TM_REG_INT_STS_1_PEND_TASK_SCAN |
561 TM_REG_INT_STS_1_PEND_CONN_SCAN))
563 "TM attention on emulation - most likely"
564 " results of clock-ratios\n");
565 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1);
566 val |= TM_REG_INT_MASK_1_PEND_CONN_SCAN |
567 TM_REG_INT_MASK_1_PEND_TASK_SCAN;
568 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1, val);
570 return ECORE_SUCCESS;
577 /* Instead of major changes to the data-structure, we have a some 'special'
578 * identifiers for sources that changed meaning between adapters.
580 enum aeu_invert_reg_special_type {
581 AEU_INVERT_REG_SPECIAL_CNIG_0,
582 AEU_INVERT_REG_SPECIAL_CNIG_1,
583 AEU_INVERT_REG_SPECIAL_CNIG_2,
584 AEU_INVERT_REG_SPECIAL_CNIG_3,
585 AEU_INVERT_REG_SPECIAL_MAX,
588 static struct aeu_invert_reg_bit
589 aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = {
590 {"CNIG port 0", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
591 {"CNIG port 1", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
592 {"CNIG port 2", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
593 {"CNIG port 3", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
596 /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */
597 static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = {
599 { /* After Invert 1 */
600 {"GPIO0 function%d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
606 { /* After Invert 2 */
607 {"PGLUE config_space", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
608 {"PGLUE misc_flr", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
609 {"PGLUE B RBC", ATTENTION_PAR_INT, ecore_pglueb_rbc_attn_cb,
611 {"PGLUE misc_mctp", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
612 {"Flash event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
613 {"SMB event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
614 {"Main Power", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
616 (8 << ATTENTION_LENGTH_SHIFT) | (1 << ATTENTION_OFFSET_SHIFT),
617 OSAL_NULL, MAX_BLOCK_ID},
618 {"PCIE glue/PXP VPD %d", (16 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
624 { /* After Invert 3 */
625 {"General Attention %d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
631 { /* After Invert 4 */
632 {"General Attention 32", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE,
633 ecore_fw_assertion, MAX_BLOCK_ID},
634 {"General Attention %d",
635 (2 << ATTENTION_LENGTH_SHIFT) | (33 << ATTENTION_OFFSET_SHIFT),
636 OSAL_NULL, MAX_BLOCK_ID},
637 {"General Attention 35", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE,
638 ecore_general_attention_35, MAX_BLOCK_ID},
639 {"NWS Parity", ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
640 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0),
641 OSAL_NULL, BLOCK_NWS},
642 {"NWS Interrupt", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
643 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1),
644 OSAL_NULL, BLOCK_NWS},
645 {"NWM Parity", ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
646 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2),
647 OSAL_NULL, BLOCK_NWM},
648 {"NWM Interrupt", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
649 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3),
650 OSAL_NULL, BLOCK_NWM},
651 {"MCP CPU", ATTENTION_SINGLE, ecore_mcp_attn_cb, MAX_BLOCK_ID},
652 {"MCP Watchdog timer", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
653 {"MCP M2P", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
654 {"AVS stop status ready", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
655 {"MSTAT", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
656 {"MSTAT per-path", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
657 {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
659 {"NIG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NIG},
660 {"BMB/OPTE/MCP", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BMB},
661 {"BTB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BTB},
662 {"BRB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BRB},
663 {"PRS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRS},
668 { /* After Invert 5 */
669 {"SRC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_SRC},
670 {"PB Client1", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB1},
671 {"PB Client2", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB2},
672 {"RPB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RPB},
673 {"PBF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF},
674 {"QM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_QM},
675 {"TM", ATTENTION_PAR_INT, ecore_tm_attn_cb, BLOCK_TM},
676 {"MCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MCM},
677 {"MSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSDM},
678 {"MSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSEM},
679 {"PCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PCM},
680 {"PSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSDM},
681 {"PSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSEM},
682 {"TCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCM},
683 {"TSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSDM},
684 {"TSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSEM},
689 { /* After Invert 6 */
690 {"UCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_UCM},
691 {"USDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USDM},
692 {"USEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USEM},
693 {"XCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XCM},
694 {"XSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSDM},
695 {"XSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSEM},
696 {"YCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YCM},
697 {"YSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSDM},
698 {"YSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSEM},
699 {"XYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XYLD},
700 {"TMLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TMLD},
701 {"MYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MULD},
702 {"YULD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YULD},
703 {"DORQ", ATTENTION_PAR_INT, ecore_dorq_attn_cb, BLOCK_DORQ},
704 {"DBG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DBG},
705 {"IPC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IPC},
710 { /* After Invert 7 */
711 {"CCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CCFC},
712 {"CDU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CDU},
713 {"DMAE", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DMAE},
714 {"IGU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IGU},
715 {"ATC", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
716 {"CAU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CAU},
717 {"PTU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PTU},
718 {"PRM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRM},
719 {"TCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCFC},
720 {"RDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RDIF},
721 {"TDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TDIF},
722 {"RSS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RSS},
723 {"MISC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISC},
724 {"MISCS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISCS},
725 {"PCIE", ATTENTION_PAR, OSAL_NULL, BLOCK_PCIE},
726 {"Vaux PCI core", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
727 {"PSWRQ", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ},
732 { /* After Invert 8 */
733 {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ2},
734 {"PSWWR", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR},
735 {"PSWWR (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR2},
736 {"PSWRD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD},
737 {"PSWRD (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD2},
738 {"PSWHST", ATTENTION_PAR_INT, ecore_pswhst_attn_cb, BLOCK_PSWHST},
739 {"PSWHST (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWHST2},
740 {"GRC", ATTENTION_PAR_INT, ecore_grc_attn_cb, BLOCK_GRC},
741 {"CPMU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CPMU},
742 {"NCSI", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NCSI},
743 {"MSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
744 {"PSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
745 {"TSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
746 {"USEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
747 {"XSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
748 {"YSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
749 {"pxp_misc_mps", ATTENTION_PAR, OSAL_NULL, BLOCK_PGLCS},
750 {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
751 {"PERST_B assertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
752 {"PERST_B deassertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
753 {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
759 { /* After Invert 9 */
760 {"MCP Latched memory", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
761 {"MCP Latched scratchpad cache", ATTENTION_SINGLE, OSAL_NULL,
763 {"MCP Latched ump_tx", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
764 {"MCP Latched scratchpad", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
765 {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
772 static struct aeu_invert_reg_bit *
773 ecore_int_aeu_translate(struct ecore_hwfn *p_hwfn,
774 struct aeu_invert_reg_bit *p_bit)
776 if (!ECORE_IS_BB(p_hwfn->p_dev))
779 if (!(p_bit->flags & ATTENTION_BB_DIFFERENT))
782 return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >>
786 static bool ecore_int_is_parity_flag(struct ecore_hwfn *p_hwfn,
787 struct aeu_invert_reg_bit *p_bit)
789 return !!(ecore_int_aeu_translate(p_hwfn, p_bit)->flags &
793 #define ATTN_STATE_BITS (0xfff)
794 #define ATTN_BITS_MASKABLE (0x3ff)
795 struct ecore_sb_attn_info {
796 /* Virtual & Physical address of the SB */
797 struct atten_status_block *sb_attn;
800 /* Last seen running index */
803 /* A mask of the AEU bits resulting in a parity error */
804 u32 parity_mask[NUM_ATTN_REGS];
806 /* A pointer to the attention description structure */
807 struct aeu_invert_reg *p_aeu_desc;
809 /* Previously asserted attentions, which are still unasserted */
812 /* Cleanup address for the link's general hw attention */
816 static u16 ecore_attn_update_idx(struct ecore_hwfn *p_hwfn,
817 struct ecore_sb_attn_info *p_sb_desc)
821 OSAL_MMIOWB(p_hwfn->p_dev);
823 index = OSAL_LE16_TO_CPU(p_sb_desc->sb_attn->sb_index);
824 if (p_sb_desc->index != index) {
825 p_sb_desc->index = index;
826 rc = ECORE_SB_ATT_IDX;
829 OSAL_MMIOWB(p_hwfn->p_dev);
835 * @brief ecore_int_assertion - handles asserted attention bits
838 * @param asserted_bits newly asserted bits
839 * @return enum _ecore_status_t
841 static enum _ecore_status_t ecore_int_assertion(struct ecore_hwfn *p_hwfn,
844 struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
847 /* Mask the source of the attention in the IGU */
848 igu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
849 IGU_REG_ATTENTION_ENABLE);
850 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n",
851 igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE));
852 igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE);
853 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);
855 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
856 "inner known ATTN state: 0x%04x --> 0x%04x\n",
857 sb_attn_sw->known_attn,
858 sb_attn_sw->known_attn | asserted_bits);
859 sb_attn_sw->known_attn |= asserted_bits;
861 /* Handle MCP events */
862 if (asserted_bits & 0x100) {
863 ecore_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt);
864 /* Clean the MCP attention */
865 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
866 sb_attn_sw->mfw_attn_addr, 0);
869 /* FIXME - this will change once we'll have GOOD gtt definitions */
870 DIRECT_REG_WR(p_hwfn,
871 (u8 OSAL_IOMEM *) p_hwfn->regview +
872 GTT_BAR0_MAP_REG_IGU_CMD +
873 ((IGU_CMD_ATTN_BIT_SET_UPPER -
874 IGU_CMD_INT_ACK_BASE) << 3), (u32)asserted_bits);
876 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "set cmd IGU: 0x%04x\n",
879 return ECORE_SUCCESS;
882 static void ecore_int_attn_print(struct ecore_hwfn *p_hwfn,
883 enum block_id id, enum dbg_attn_type type,
887 DP_NOTICE(p_hwfn->p_dev, false, "[block_id %d type %d]\n", id, type);
891 * @brief ecore_int_deassertion_aeu_bit - handles the effects of a single
892 * cause of the attention
895 * @param p_aeu - descriptor of an AEU bit which caused the attention
896 * @param aeu_en_reg - register offset of the AEU enable reg. which configured
897 * this bit to this group.
898 * @param bit_index - index of this bit in the aeu_en_reg
900 * @return enum _ecore_status_t
902 static enum _ecore_status_t
903 ecore_int_deassertion_aeu_bit(struct ecore_hwfn *p_hwfn,
904 struct aeu_invert_reg_bit *p_aeu,
906 const char *p_bit_name,
909 enum _ecore_status_t rc = ECORE_INVAL;
910 bool b_fatal = false;
912 DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n",
913 p_bit_name, bitmask);
915 /* Call callback before clearing the interrupt status */
917 DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n",
919 rc = p_aeu->cb(p_hwfn);
922 if (rc != ECORE_SUCCESS)
925 /* Print HW block interrupt registers */
926 if (p_aeu->block_index != MAX_BLOCK_ID) {
927 ecore_int_attn_print(p_hwfn, p_aeu->block_index,
928 ATTN_TYPE_INTERRUPT, !b_fatal);
932 /* Reach assertion if attention is fatal */
933 if (b_fatal || (strcmp(p_bit_name, "PGLUE B RBC") == 0)) {
934 DP_NOTICE(p_hwfn, true, "`%s': Fatal attention\n",
937 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
940 /* Prevent this Attention from being asserted in the future */
941 if (p_aeu->flags & ATTENTION_CLEAR_ENABLE ||
942 p_hwfn->p_dev->attn_clr_en) {
945 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
946 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & mask));
947 DP_ERR(p_hwfn, "`%s' - Disabled future attentions\n",
955 * @brief ecore_int_deassertion_parity - handle a single parity AEU source
958 * @param p_aeu - descriptor of an AEU bit which caused the parity
959 * @param aeu_en_reg - address of the AEU enable register
962 static void ecore_int_deassertion_parity(struct ecore_hwfn *p_hwfn,
963 struct aeu_invert_reg_bit *p_aeu,
964 u32 aeu_en_reg, u8 bit_index)
966 u32 block_id = p_aeu->block_index, mask, val;
968 DP_NOTICE(p_hwfn->p_dev, false,
969 "%s parity attention is set [address 0x%08x, bit %d]\n",
970 p_aeu->bit_name, aeu_en_reg, bit_index);
972 if (block_id != MAX_BLOCK_ID) {
973 ecore_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false);
975 /* In A0, there's a single parity bit for several blocks */
976 if (block_id == BLOCK_BTB) {
977 ecore_int_attn_print(p_hwfn, BLOCK_OPTE,
978 ATTN_TYPE_PARITY, false);
979 ecore_int_attn_print(p_hwfn, BLOCK_MCP,
980 ATTN_TYPE_PARITY, false);
984 /* Prevent this parity error from being re-asserted */
985 mask = ~(0x1 << bit_index);
986 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
987 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask);
988 DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n",
993 * @brief - handles deassertion of previously asserted attentions.
996 * @param deasserted_bits - newly deasserted bits
997 * @return enum _ecore_status_t
1000 static enum _ecore_status_t ecore_int_deassertion(struct ecore_hwfn *p_hwfn,
1001 u16 deasserted_bits)
1003 struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
1004 u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en;
1005 u8 i, j, k, bit_idx;
1006 enum _ecore_status_t rc = ECORE_SUCCESS;
1008 /* Read the attention registers in the AEU */
1009 for (i = 0; i < NUM_ATTN_REGS; i++) {
1010 aeu_inv_arr[i] = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1011 MISC_REG_AEU_AFTER_INVERT_1_IGU +
1013 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1014 "Deasserted bits [%d]: %08x\n", i, aeu_inv_arr[i]);
1017 /* Handle parity attentions first */
1018 for (i = 0; i < NUM_ATTN_REGS; i++) {
1019 struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i];
1022 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32);
1023 en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
1024 parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en;
1026 /* Skip register in which no parity bit is currently set */
1030 for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
1031 struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j];
1033 if (ecore_int_is_parity_flag(p_hwfn, p_bit) &&
1034 !!(parities & (1 << bit_idx)))
1035 ecore_int_deassertion_parity(p_hwfn, p_bit,
1038 bit_idx += ATTENTION_LENGTH(p_bit->flags);
1042 /* Find non-parity cause for attention and act */
1043 for (k = 0; k < MAX_ATTN_GRPS; k++) {
1044 struct aeu_invert_reg_bit *p_aeu;
1046 /* Handle only groups whose attention is currently deasserted */
1047 if (!(deasserted_bits & (1 << k)))
1050 for (i = 0; i < NUM_ATTN_REGS; i++) {
1053 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
1055 k * sizeof(u32) * NUM_ATTN_REGS;
1056 en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
1057 bits = aeu_inv_arr[i] & en;
1059 /* Skip if no bit from this group is currently set */
1063 /* Find all set bits from current register which belong
1064 * to current group, making them responsible for the
1065 * previous assertion.
1067 for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
1068 unsigned long int bitmask;
1071 /* Need to account bits with changed meaning */
1072 p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j];
1075 bit_len = ATTENTION_LENGTH(p_aeu->flags);
1076 if (ecore_int_is_parity_flag(p_hwfn, p_aeu)) {
1082 /* Find the bits relating to HW-block, then
1083 * shift so they'll become LSB.
1085 bitmask = bits & (((1 << bit_len) - 1) << bit);
1089 u32 flags = p_aeu->flags;
1093 num = (u8)OSAL_FIND_FIRST_BIT(&bitmask,
1096 /* Some bits represent more than a
1097 * a single interrupt. Correctly print
1100 if (ATTENTION_LENGTH(flags) > 2 ||
1101 ((flags & ATTENTION_PAR_INT) &&
1102 ATTENTION_LENGTH(flags) > 1))
1103 OSAL_SNPRINTF(bit_name, 30,
1107 OSAL_STRNCPY(bit_name,
1111 /* We now need to pass bitmask in its
1116 /* Handle source of the attention */
1117 ecore_int_deassertion_aeu_bit(p_hwfn,
1124 bit_idx += ATTENTION_LENGTH(p_aeu->flags);
1129 /* Clear IGU indication for the deasserted bits */
1130 /* FIXME - this will change once we'll have GOOD gtt definitions */
1131 DIRECT_REG_WR(p_hwfn,
1132 (u8 OSAL_IOMEM *) p_hwfn->regview +
1133 GTT_BAR0_MAP_REG_IGU_CMD +
1134 ((IGU_CMD_ATTN_BIT_CLR_UPPER -
1135 IGU_CMD_INT_ACK_BASE) << 3), ~((u32)deasserted_bits));
1137 /* Unmask deasserted attentions in IGU */
1138 aeu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1139 IGU_REG_ATTENTION_ENABLE);
1140 aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE);
1141 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);
1143 /* Clear deassertion from inner state */
1144 sb_attn_sw->known_attn &= ~deasserted_bits;
1149 static enum _ecore_status_t ecore_int_attentions(struct ecore_hwfn *p_hwfn)
1151 struct ecore_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn;
1152 struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn;
1153 u16 index = 0, asserted_bits, deasserted_bits;
1154 u32 attn_bits = 0, attn_acks = 0;
1155 enum _ecore_status_t rc = ECORE_SUCCESS;
1157 /* Read current attention bits/acks - safeguard against attentions
1158 * by guaranting work on a synchronized timeframe
1161 index = OSAL_LE16_TO_CPU(p_sb_attn->sb_index);
1162 attn_bits = OSAL_LE32_TO_CPU(p_sb_attn->atten_bits);
1163 attn_acks = OSAL_LE32_TO_CPU(p_sb_attn->atten_ack);
1164 } while (index != OSAL_LE16_TO_CPU(p_sb_attn->sb_index));
1165 p_sb_attn->sb_index = index;
1167 /* Attention / Deassertion are meaningful (and in correct state)
1168 * only when they differ and consistent with known state - deassertion
1169 * when previous attention & current ack, and assertion when current
1170 * attention with no previous attention
1172 asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) &
1173 ~p_sb_attn_sw->known_attn;
1174 deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) &
1175 p_sb_attn_sw->known_attn;
1177 if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100))
1179 "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n",
1180 index, attn_bits, attn_acks, asserted_bits,
1181 deasserted_bits, p_sb_attn_sw->known_attn);
1182 else if (asserted_bits == 0x100)
1183 DP_INFO(p_hwfn, "MFW indication via attention\n");
1185 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1186 "MFW indication [deassertion]\n");
1188 if (asserted_bits) {
1189 rc = ecore_int_assertion(p_hwfn, asserted_bits);
1194 if (deasserted_bits)
1195 rc = ecore_int_deassertion(p_hwfn, deasserted_bits);
1200 static void ecore_sb_ack_attn(struct ecore_hwfn *p_hwfn,
1201 void OSAL_IOMEM *igu_addr, u32 ack_cons)
1203 struct igu_prod_cons_update igu_ack = { 0 };
1205 igu_ack.sb_id_and_flags =
1206 ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1207 (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1208 (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1209 (IGU_SEG_ACCESS_ATTN <<
1210 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1212 DIRECT_REG_WR(p_hwfn, igu_addr, igu_ack.sb_id_and_flags);
1214 /* Both segments (interrupts & acks) are written to same place address;
1215 * Need to guarantee all commands will be received (in-order) by HW.
1217 OSAL_MMIOWB(p_hwfn->p_dev);
1218 OSAL_BARRIER(p_hwfn->p_dev);
1221 void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie)
1223 struct ecore_hwfn *p_hwfn = (struct ecore_hwfn *)hwfn_cookie;
1224 struct ecore_pi_info *pi_info = OSAL_NULL;
1225 struct ecore_sb_attn_info *sb_attn;
1226 struct ecore_sb_info *sb_info;
1233 if (!p_hwfn->p_sp_sb) {
1234 DP_ERR(p_hwfn->p_dev, "DPC called - no p_sp_sb\n");
1238 sb_info = &p_hwfn->p_sp_sb->sb_info;
1239 arr_size = OSAL_ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr);
1241 DP_ERR(p_hwfn->p_dev,
1242 "Status block is NULL - cannot ack interrupts\n");
1246 if (!p_hwfn->p_sb_attn) {
1247 DP_ERR(p_hwfn->p_dev, "DPC called - no p_sb_attn");
1250 sb_attn = p_hwfn->p_sb_attn;
1252 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "DPC Called! (hwfn %p %d)\n",
1253 p_hwfn, p_hwfn->my_id);
1255 /* Disable ack for def status block. Required both for msix +
1256 * inta in non-mask mode, in inta does no harm.
1258 ecore_sb_ack(sb_info, IGU_INT_DISABLE, 0);
1260 /* Gather Interrupts/Attentions information */
1261 if (!sb_info->sb_virt) {
1262 DP_ERR(p_hwfn->p_dev,
1263 "Interrupt Status block is NULL -"
1264 " cannot check for new interrupts!\n");
1266 u32 tmp_index = sb_info->sb_ack;
1267 rc = ecore_sb_update_sb_idx(sb_info);
1268 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR,
1269 "Interrupt indices: 0x%08x --> 0x%08x\n",
1270 tmp_index, sb_info->sb_ack);
1273 if (!sb_attn || !sb_attn->sb_attn) {
1274 DP_ERR(p_hwfn->p_dev,
1275 "Attentions Status block is NULL -"
1276 " cannot check for new attentions!\n");
1278 u16 tmp_index = sb_attn->index;
1280 rc |= ecore_attn_update_idx(p_hwfn, sb_attn);
1281 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR,
1282 "Attention indices: 0x%08x --> 0x%08x\n",
1283 tmp_index, sb_attn->index);
1286 /* Check if we expect interrupts at this time. if not just ack them */
1287 if (!(rc & ECORE_SB_EVENT_MASK)) {
1288 ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1292 /* Check the validity of the DPC ptt. If not ack interrupts and fail */
1294 if (!p_hwfn->p_dpc_ptt) {
1295 DP_NOTICE(p_hwfn->p_dev, true, "Failed to allocate PTT\n");
1296 ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1300 if (rc & ECORE_SB_ATT_IDX)
1301 ecore_int_attentions(p_hwfn);
1303 if (rc & ECORE_SB_IDX) {
1306 /* Since we only looked at the SB index, it's possible more
1307 * than a single protocol-index on the SB incremented.
1308 * Iterate over all configured protocol indices and check
1309 * whether something happened for each.
1311 for (pi = 0; pi < arr_size; pi++) {
1312 pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi];
1313 if (pi_info->comp_cb != OSAL_NULL)
1314 pi_info->comp_cb(p_hwfn, pi_info->cookie);
1318 if (sb_attn && (rc & ECORE_SB_ATT_IDX)) {
1319 /* This should be done before the interrupts are enabled,
1320 * since otherwise a new attention will be generated.
1322 ecore_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index);
1325 ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1328 static void ecore_int_sb_attn_free(struct ecore_hwfn *p_hwfn)
1330 struct ecore_sb_attn_info *p_sb = p_hwfn->p_sb_attn;
1335 if (p_sb->sb_attn) {
1336 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, p_sb->sb_attn,
1338 SB_ATTN_ALIGNED_SIZE(p_hwfn));
1340 OSAL_FREE(p_hwfn->p_dev, p_sb);
1343 static void ecore_int_sb_attn_setup(struct ecore_hwfn *p_hwfn,
1344 struct ecore_ptt *p_ptt)
1346 struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1348 OSAL_MEMSET(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn));
1351 sb_info->known_attn = 0;
1353 /* Configure Attention Status Block in IGU */
1354 ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,
1355 DMA_LO(p_hwfn->p_sb_attn->sb_phys));
1356 ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,
1357 DMA_HI(p_hwfn->p_sb_attn->sb_phys));
1360 static void ecore_int_sb_attn_init(struct ecore_hwfn *p_hwfn,
1361 struct ecore_ptt *p_ptt,
1362 void *sb_virt_addr, dma_addr_t sb_phy_addr)
1364 struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1367 sb_info->sb_attn = sb_virt_addr;
1368 sb_info->sb_phys = sb_phy_addr;
1370 /* Set the pointer to the AEU descriptors */
1371 sb_info->p_aeu_desc = aeu_descs;
1373 /* Calculate Parity Masks */
1374 OSAL_MEMSET(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS);
1375 for (i = 0; i < NUM_ATTN_REGS; i++) {
1376 /* j is array index, k is bit index */
1377 for (j = 0, k = 0; k < 32; j++) {
1378 struct aeu_invert_reg_bit *p_aeu;
1380 p_aeu = &aeu_descs[i].bits[j];
1381 if (ecore_int_is_parity_flag(p_hwfn, p_aeu))
1382 sb_info->parity_mask[i] |= 1 << k;
1384 k += ATTENTION_LENGTH(p_aeu->flags);
1386 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1387 "Attn Mask [Reg %d]: 0x%08x\n",
1388 i, sb_info->parity_mask[i]);
1391 /* Set the address of cleanup for the mcp attention */
1392 sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) +
1393 MISC_REG_AEU_GENERAL_ATTN_0;
1395 ecore_int_sb_attn_setup(p_hwfn, p_ptt);
1398 static enum _ecore_status_t ecore_int_sb_attn_alloc(struct ecore_hwfn *p_hwfn,
1399 struct ecore_ptt *p_ptt)
1401 struct ecore_dev *p_dev = p_hwfn->p_dev;
1402 struct ecore_sb_attn_info *p_sb;
1403 dma_addr_t p_phys = 0;
1407 p_sb = OSAL_ALLOC(p_dev, GFP_KERNEL, sizeof(*p_sb));
1409 DP_NOTICE(p_dev, true,
1410 "Failed to allocate `struct ecore_sb_attn_info'\n");
1415 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
1416 SB_ATTN_ALIGNED_SIZE(p_hwfn));
1418 DP_NOTICE(p_dev, true,
1419 "Failed to allocate status block (attentions)\n");
1420 OSAL_FREE(p_dev, p_sb);
1424 /* Attention setup */
1425 p_hwfn->p_sb_attn = p_sb;
1426 ecore_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys);
1428 return ECORE_SUCCESS;
1431 /* coalescing timeout = timeset << (timer_res + 1) */
1432 #define ECORE_CAU_DEF_RX_USECS 24
1433 #define ECORE_CAU_DEF_TX_USECS 48
1435 void ecore_init_cau_sb_entry(struct ecore_hwfn *p_hwfn,
1436 struct cau_sb_entry *p_sb_entry,
1437 u8 pf_id, u16 vf_number, u8 vf_valid)
1439 struct ecore_dev *p_dev = p_hwfn->p_dev;
1443 OSAL_MEMSET(p_sb_entry, 0, sizeof(*p_sb_entry));
1445 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id);
1446 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number);
1447 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid);
1448 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F);
1449 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F);
1451 cau_state = CAU_HC_DISABLE_STATE;
1453 if (p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
1454 cau_state = CAU_HC_ENABLE_STATE;
1455 if (!p_dev->rx_coalesce_usecs)
1456 p_dev->rx_coalesce_usecs = ECORE_CAU_DEF_RX_USECS;
1457 if (!p_dev->tx_coalesce_usecs)
1458 p_dev->tx_coalesce_usecs = ECORE_CAU_DEF_TX_USECS;
1461 /* Coalesce = (timeset << timer-res), timeset is 7bit wide */
1462 if (p_dev->rx_coalesce_usecs <= 0x7F)
1464 else if (p_dev->rx_coalesce_usecs <= 0xFF)
1468 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
1470 if (p_dev->tx_coalesce_usecs <= 0x7F)
1472 else if (p_dev->tx_coalesce_usecs <= 0xFF)
1476 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
1478 SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state);
1479 SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
1482 static void _ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
1483 struct ecore_ptt *p_ptt,
1484 u16 igu_sb_id, u32 pi_index,
1485 enum ecore_coalescing_fsm coalescing_fsm,
1488 struct cau_pi_entry pi_entry;
1489 u32 sb_offset, pi_offset;
1491 if (IS_VF(p_hwfn->p_dev))
1492 return;/* @@@TBD MichalK- VF CAU... */
1494 sb_offset = igu_sb_id * PIS_PER_SB_E4;
1495 OSAL_MEMSET(&pi_entry, 0, sizeof(struct cau_pi_entry));
1497 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
1498 if (coalescing_fsm == ECORE_COAL_RX_STATE_MACHINE)
1499 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0);
1501 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1);
1503 pi_offset = sb_offset + pi_index;
1504 if (p_hwfn->hw_init_done) {
1505 ecore_wr(p_hwfn, p_ptt,
1506 CAU_REG_PI_MEMORY + pi_offset * sizeof(u32),
1507 *((u32 *)&(pi_entry)));
1509 STORE_RT_REG(p_hwfn,
1510 CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
1511 *((u32 *)&(pi_entry)));
1515 void ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
1516 struct ecore_ptt *p_ptt,
1517 struct ecore_sb_info *p_sb, u32 pi_index,
1518 enum ecore_coalescing_fsm coalescing_fsm,
1521 _ecore_int_cau_conf_pi(p_hwfn, p_ptt, p_sb->igu_sb_id,
1522 pi_index, coalescing_fsm, timeset);
1525 void ecore_int_cau_conf_sb(struct ecore_hwfn *p_hwfn,
1526 struct ecore_ptt *p_ptt,
1527 dma_addr_t sb_phys, u16 igu_sb_id,
1528 u16 vf_number, u8 vf_valid)
1530 struct cau_sb_entry sb_entry;
1532 ecore_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id,
1533 vf_number, vf_valid);
1535 if (p_hwfn->hw_init_done) {
1536 /* Wide-bus, initialize via DMAE */
1537 u64 phys_addr = (u64)sb_phys;
1539 ecore_dmae_host2grc(p_hwfn, p_ptt,
1540 (u64)(osal_uintptr_t)&phys_addr,
1541 CAU_REG_SB_ADDR_MEMORY +
1542 igu_sb_id * sizeof(u64), 2, 0);
1543 ecore_dmae_host2grc(p_hwfn, p_ptt,
1544 (u64)(osal_uintptr_t)&sb_entry,
1545 CAU_REG_SB_VAR_MEMORY +
1546 igu_sb_id * sizeof(u64), 2, 0);
1548 /* Initialize Status Block Address */
1549 STORE_RT_REG_AGG(p_hwfn,
1550 CAU_REG_SB_ADDR_MEMORY_RT_OFFSET +
1551 igu_sb_id * 2, sb_phys);
1553 STORE_RT_REG_AGG(p_hwfn,
1554 CAU_REG_SB_VAR_MEMORY_RT_OFFSET +
1555 igu_sb_id * 2, sb_entry);
1558 /* Configure pi coalescing if set */
1559 if (p_hwfn->p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
1560 /* eth will open queues for all tcs, so configure all of them
1561 * properly, rather than just the active ones
1563 u8 num_tc = p_hwfn->hw_info.num_hw_tc;
1565 u8 timeset, timer_res;
1568 /* timeset = (coalesce >> timer-res), timeset is 7bit wide */
1569 if (p_hwfn->p_dev->rx_coalesce_usecs <= 0x7F)
1571 else if (p_hwfn->p_dev->rx_coalesce_usecs <= 0xFF)
1575 timeset = (u8)(p_hwfn->p_dev->rx_coalesce_usecs >> timer_res);
1576 _ecore_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
1577 ECORE_COAL_RX_STATE_MACHINE,
1580 if (p_hwfn->p_dev->tx_coalesce_usecs <= 0x7F)
1582 else if (p_hwfn->p_dev->tx_coalesce_usecs <= 0xFF)
1586 timeset = (u8)(p_hwfn->p_dev->tx_coalesce_usecs >> timer_res);
1587 for (i = 0; i < num_tc; i++) {
1588 _ecore_int_cau_conf_pi(p_hwfn, p_ptt,
1589 igu_sb_id, TX_PI(i),
1590 ECORE_COAL_TX_STATE_MACHINE,
1596 void ecore_int_sb_setup(struct ecore_hwfn *p_hwfn,
1597 struct ecore_ptt *p_ptt, struct ecore_sb_info *sb_info)
1599 /* zero status block and ack counter */
1600 sb_info->sb_ack = 0;
1601 OSAL_MEMSET(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1603 if (IS_PF(p_hwfn->p_dev))
1604 ecore_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,
1605 sb_info->igu_sb_id, 0, 0);
1608 struct ecore_igu_block *
1609 ecore_get_igu_free_sb(struct ecore_hwfn *p_hwfn, bool b_is_pf)
1611 struct ecore_igu_block *p_block;
1614 for (igu_id = 0; igu_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
1616 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1618 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
1619 !(p_block->status & ECORE_IGU_STATUS_FREE))
1622 if (!!(p_block->status & ECORE_IGU_STATUS_PF) ==
1630 static u16 ecore_get_pf_igu_sb_id(struct ecore_hwfn *p_hwfn,
1633 struct ecore_igu_block *p_block;
1636 for (igu_id = 0; igu_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
1638 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1640 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
1642 p_block->vector_number != vector_id)
1648 return ECORE_SB_INVALID_IDX;
1651 u16 ecore_get_igu_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id)
1655 /* Assuming continuous set of IGU SBs dedicated for given PF */
1656 if (sb_id == ECORE_SP_SB_ID)
1657 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
1658 else if (IS_PF(p_hwfn->p_dev))
1659 igu_sb_id = ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1);
1661 igu_sb_id = ecore_vf_get_igu_sb_id(p_hwfn, sb_id);
1663 if (igu_sb_id == ECORE_SB_INVALID_IDX)
1664 DP_NOTICE(p_hwfn, true,
1665 "Slowpath SB vector %04x doesn't exist\n",
1667 else if (sb_id == ECORE_SP_SB_ID)
1668 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1669 "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id);
1671 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1672 "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id);
1677 enum _ecore_status_t ecore_int_sb_init(struct ecore_hwfn *p_hwfn,
1678 struct ecore_ptt *p_ptt,
1679 struct ecore_sb_info *sb_info,
1681 dma_addr_t sb_phy_addr, u16 sb_id)
1683 sb_info->sb_virt = sb_virt_addr;
1684 sb_info->sb_phys = sb_phy_addr;
1686 sb_info->igu_sb_id = ecore_get_igu_sb_id(p_hwfn, sb_id);
1688 if (sb_info->igu_sb_id == ECORE_SB_INVALID_IDX)
1691 /* Let the igu info reference the client's SB info */
1692 if (sb_id != ECORE_SP_SB_ID) {
1693 if (IS_PF(p_hwfn->p_dev)) {
1694 struct ecore_igu_info *p_info;
1695 struct ecore_igu_block *p_block;
1697 p_info = p_hwfn->hw_info.p_igu_info;
1698 p_block = &p_info->entry[sb_info->igu_sb_id];
1700 p_block->sb_info = sb_info;
1701 p_block->status &= ~ECORE_IGU_STATUS_FREE;
1702 p_info->usage.free_cnt--;
1704 ecore_vf_set_sb_info(p_hwfn, sb_id, sb_info);
1707 #ifdef ECORE_CONFIG_DIRECT_HWFN
1708 sb_info->p_hwfn = p_hwfn;
1710 sb_info->p_dev = p_hwfn->p_dev;
1712 /* The igu address will hold the absolute address that needs to be
1713 * written to for a specific status block
1715 if (IS_PF(p_hwfn->p_dev)) {
1716 sb_info->igu_addr = (u8 OSAL_IOMEM *)p_hwfn->regview +
1717 GTT_BAR0_MAP_REG_IGU_CMD + (sb_info->igu_sb_id << 3);
1721 (u8 OSAL_IOMEM *)p_hwfn->regview +
1722 PXP_VF_BAR0_START_IGU +
1723 ((IGU_CMD_INT_ACK_BASE + sb_info->igu_sb_id) << 3);
1726 sb_info->flags |= ECORE_SB_INFO_INIT;
1728 ecore_int_sb_setup(p_hwfn, p_ptt, sb_info);
1730 return ECORE_SUCCESS;
1733 enum _ecore_status_t ecore_int_sb_release(struct ecore_hwfn *p_hwfn,
1734 struct ecore_sb_info *sb_info,
1737 struct ecore_igu_info *p_info;
1738 struct ecore_igu_block *p_block;
1740 if (sb_info == OSAL_NULL)
1741 return ECORE_SUCCESS;
1743 /* zero status block and ack counter */
1744 sb_info->sb_ack = 0;
1745 OSAL_MEMSET(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1747 if (IS_VF(p_hwfn->p_dev)) {
1748 ecore_vf_set_sb_info(p_hwfn, sb_id, OSAL_NULL);
1749 return ECORE_SUCCESS;
1752 p_info = p_hwfn->hw_info.p_igu_info;
1753 p_block = &p_info->entry[sb_info->igu_sb_id];
1755 /* Vector 0 is reserved to Default SB */
1756 if (p_block->vector_number == 0) {
1757 DP_ERR(p_hwfn, "Do Not free sp sb using this function");
1761 /* Lose reference to client's SB info, and fix counters */
1762 p_block->sb_info = OSAL_NULL;
1763 p_block->status |= ECORE_IGU_STATUS_FREE;
1764 p_info->usage.free_cnt++;
1766 return ECORE_SUCCESS;
1769 static void ecore_int_sp_sb_free(struct ecore_hwfn *p_hwfn)
1771 struct ecore_sb_sp_info *p_sb = p_hwfn->p_sp_sb;
1776 if (p_sb->sb_info.sb_virt) {
1777 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
1778 p_sb->sb_info.sb_virt,
1779 p_sb->sb_info.sb_phys,
1780 SB_ALIGNED_SIZE(p_hwfn));
1783 OSAL_FREE(p_hwfn->p_dev, p_sb);
1786 static enum _ecore_status_t ecore_int_sp_sb_alloc(struct ecore_hwfn *p_hwfn,
1787 struct ecore_ptt *p_ptt)
1789 struct ecore_sb_sp_info *p_sb;
1790 dma_addr_t p_phys = 0;
1795 OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL,
1798 DP_NOTICE(p_hwfn, true,
1799 "Failed to allocate `struct ecore_sb_info'\n");
1804 p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
1805 &p_phys, SB_ALIGNED_SIZE(p_hwfn));
1807 DP_NOTICE(p_hwfn, true, "Failed to allocate status block\n");
1808 OSAL_FREE(p_hwfn->p_dev, p_sb);
1812 /* Status Block setup */
1813 p_hwfn->p_sp_sb = p_sb;
1814 ecore_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info,
1815 p_virt, p_phys, ECORE_SP_SB_ID);
1817 OSAL_MEMSET(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr));
1819 return ECORE_SUCCESS;
1822 enum _ecore_status_t ecore_int_register_cb(struct ecore_hwfn *p_hwfn,
1823 ecore_int_comp_cb_t comp_cb,
1825 u8 *sb_idx, __le16 **p_fw_cons)
1827 struct ecore_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1828 enum _ecore_status_t rc = ECORE_NOMEM;
1831 /* Look for a free index */
1832 for (pi = 0; pi < OSAL_ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) {
1833 if (p_sp_sb->pi_info_arr[pi].comp_cb != OSAL_NULL)
1836 p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
1837 p_sp_sb->pi_info_arr[pi].cookie = cookie;
1839 *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi];
1847 enum _ecore_status_t ecore_int_unregister_cb(struct ecore_hwfn *p_hwfn, u8 pi)
1849 struct ecore_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1851 if (p_sp_sb->pi_info_arr[pi].comp_cb == OSAL_NULL)
1854 p_sp_sb->pi_info_arr[pi].comp_cb = OSAL_NULL;
1855 p_sp_sb->pi_info_arr[pi].cookie = OSAL_NULL;
1856 return ECORE_SUCCESS;
1859 u16 ecore_int_get_sp_sb_id(struct ecore_hwfn *p_hwfn)
1861 return p_hwfn->p_sp_sb->sb_info.igu_sb_id;
1864 void ecore_int_igu_enable_int(struct ecore_hwfn *p_hwfn,
1865 struct ecore_ptt *p_ptt,
1866 enum ecore_int_mode int_mode)
1868 u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN;
1871 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1872 DP_INFO(p_hwfn, "FPGA - don't enable ATTN generation in IGU\n");
1873 igu_pf_conf &= ~IGU_PF_CONF_ATTN_BIT_EN;
1877 p_hwfn->p_dev->int_mode = int_mode;
1878 switch (p_hwfn->p_dev->int_mode) {
1879 case ECORE_INT_MODE_INTA:
1880 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN;
1881 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1884 case ECORE_INT_MODE_MSI:
1885 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1886 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1889 case ECORE_INT_MODE_MSIX:
1890 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1892 case ECORE_INT_MODE_POLL:
1896 ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);
1899 static void ecore_int_igu_enable_attn(struct ecore_hwfn *p_hwfn,
1900 struct ecore_ptt *p_ptt)
1903 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1905 "FPGA - Don't enable Attentions in IGU and MISC\n");
1910 /* Configure AEU signal change to produce attentions */
1911 ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0);
1912 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);
1913 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);
1914 ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff);
1916 /* Flush the writes to IGU */
1917 OSAL_MMIOWB(p_hwfn->p_dev);
1919 /* Unmask AEU signals toward IGU */
1920 ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);
1923 enum _ecore_status_t
1924 ecore_int_igu_enable(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1925 enum ecore_int_mode int_mode)
1927 enum _ecore_status_t rc = ECORE_SUCCESS;
1929 ecore_int_igu_enable_attn(p_hwfn, p_ptt);
1931 if ((int_mode != ECORE_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {
1932 rc = OSAL_SLOWPATH_IRQ_REQ(p_hwfn);
1933 if (rc != ECORE_SUCCESS) {
1934 DP_NOTICE(p_hwfn, true,
1935 "Slowpath IRQ request failed\n");
1936 return ECORE_NORESOURCES;
1938 p_hwfn->b_int_requested = true;
1941 /* Enable interrupt Generation */
1942 ecore_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
1944 p_hwfn->b_int_enabled = 1;
1949 void ecore_int_igu_disable_int(struct ecore_hwfn *p_hwfn,
1950 struct ecore_ptt *p_ptt)
1952 p_hwfn->b_int_enabled = 0;
1954 if (IS_VF(p_hwfn->p_dev))
1957 ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
1960 #define IGU_CLEANUP_SLEEP_LENGTH (1000)
1961 static void ecore_int_igu_cleanup_sb(struct ecore_hwfn *p_hwfn,
1962 struct ecore_ptt *p_ptt,
1967 u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0;
1968 u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id;
1969 u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH;
1970 u8 type = 0; /* FIXME MichalS type??? */
1972 OSAL_BUILD_BUG_ON((IGU_REG_CLEANUP_STATUS_4 -
1973 IGU_REG_CLEANUP_STATUS_0) != 0x200);
1975 /* USE Control Command Register to perform cleanup. There is an
1976 * option to do this using IGU bar, but then it can't be used for VFs.
1979 /* Set the data field */
1980 SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0);
1981 SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, type);
1982 SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET);
1984 /* Set the control register */
1985 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr);
1986 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid);
1987 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR);
1989 ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);
1991 OSAL_BARRIER(p_hwfn->p_dev);
1993 ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);
1995 /* Flush the write to IGU */
1996 OSAL_MMIOWB(p_hwfn->p_dev);
1998 /* calculate where to read the status bit from */
1999 sb_bit = 1 << (igu_sb_id % 32);
2000 sb_bit_addr = igu_sb_id / 32 * sizeof(u32);
2002 sb_bit_addr += IGU_REG_CLEANUP_STATUS_0 + (0x80 * type);
2004 /* Now wait for the command to complete */
2005 while (--sleep_cnt) {
2006 val = ecore_rd(p_hwfn, p_ptt, sb_bit_addr);
2007 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0))
2013 DP_NOTICE(p_hwfn, true,
2014 "Timeout waiting for clear status 0x%08x [for sb %d]\n",
2018 void ecore_int_igu_init_pure_rt_single(struct ecore_hwfn *p_hwfn,
2019 struct ecore_ptt *p_ptt,
2020 u16 igu_sb_id, u16 opaque, bool b_set)
2022 struct ecore_igu_block *p_block;
2025 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
2026 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2027 "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n",
2028 igu_sb_id, p_block->function_id, p_block->is_pf,
2029 p_block->vector_number);
2033 ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque);
2036 ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque);
2038 /* Wait for the IGU SB to cleanup */
2039 for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) {
2042 val = ecore_rd(p_hwfn, p_ptt,
2043 IGU_REG_WRITE_DONE_PENDING +
2044 ((igu_sb_id / 32) * 4));
2045 if (val & (1 << (igu_sb_id % 32)))
2050 if (i == IGU_CLEANUP_SLEEP_LENGTH)
2051 DP_NOTICE(p_hwfn, true,
2052 "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n",
2055 /* Clear the CAU for the SB */
2056 for (pi = 0; pi < 12; pi++)
2057 ecore_wr(p_hwfn, p_ptt,
2058 CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0);
2061 void ecore_int_igu_init_pure_rt(struct ecore_hwfn *p_hwfn,
2062 struct ecore_ptt *p_ptt,
2063 bool b_set, bool b_slowpath)
2065 struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2066 struct ecore_igu_block *p_block;
2070 /* @@@TBD MichalK temporary... should be moved to init-tool... */
2071 val = ecore_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
2072 val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN;
2073 val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN;
2074 ecore_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);
2078 igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2080 p_block = &p_info->entry[igu_sb_id];
2082 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
2084 (p_block->status & ECORE_IGU_STATUS_DSB))
2087 ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id,
2088 p_hwfn->hw_info.opaque_fid,
2093 ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt,
2095 p_hwfn->hw_info.opaque_fid,
2099 int ecore_int_igu_reset_cam(struct ecore_hwfn *p_hwfn,
2100 struct ecore_ptt *p_ptt)
2102 struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2103 struct ecore_igu_block *p_block;
2108 if (!RESC_NUM(p_hwfn, ECORE_SB)) {
2109 /* We're using an old MFW - have to prevent any switching
2110 * of SBs between PF and VFs as later driver wouldn't be
2111 * able to tell which belongs to which.
2113 p_info->b_allow_pf_vf_change = false;
2115 /* Use the numbers the MFW have provided -
2116 * don't forget MFW accounts for the default SB as well.
2118 p_info->b_allow_pf_vf_change = true;
2120 if (p_info->usage.cnt != RESC_NUM(p_hwfn, ECORE_SB) - 1) {
2122 "MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n",
2123 RESC_NUM(p_hwfn, ECORE_SB) - 1,
2125 p_info->usage.cnt = RESC_NUM(p_hwfn, ECORE_SB) - 1;
2128 /* TODO - how do we learn about VF SBs from MFW? */
2129 if (IS_PF_SRIOV(p_hwfn)) {
2130 u16 vfs = p_hwfn->p_dev->p_iov_info->total_vfs;
2132 if (vfs != p_info->usage.iov_cnt)
2133 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2134 "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n",
2135 p_info->usage.iov_cnt, vfs);
2137 /* At this point we know how many SBs we have totally
2138 * in IGU + number of PF SBs. So we can validate that
2139 * we'd have sufficient for VF.
2141 if (vfs > p_info->usage.free_cnt +
2142 p_info->usage.free_cnt_iov -
2143 p_info->usage.cnt) {
2144 DP_NOTICE(p_hwfn, true,
2145 "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n",
2146 p_info->usage.free_cnt +
2147 p_info->usage.free_cnt_iov,
2148 p_info->usage.cnt, vfs);
2154 /* Cap the number of VFs SBs by the number of VFs */
2155 if (IS_PF_SRIOV(p_hwfn))
2156 p_info->usage.iov_cnt = p_hwfn->p_dev->p_iov_info->total_vfs;
2158 /* Mark all SBs as free, now in the right PF/VFs division */
2159 p_info->usage.free_cnt = p_info->usage.cnt;
2160 p_info->usage.free_cnt_iov = p_info->usage.iov_cnt;
2161 p_info->usage.orig = p_info->usage.cnt;
2162 p_info->usage.iov_orig = p_info->usage.iov_cnt;
2164 /* We now proceed to re-configure the IGU cam to reflect the initial
2165 * configuration. We can start with the Default SB.
2167 pf_sbs = p_info->usage.cnt;
2168 vf_sbs = p_info->usage.iov_cnt;
2170 for (igu_sb_id = p_info->igu_dsb_id;
2171 igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2173 p_block = &p_info->entry[igu_sb_id];
2176 if (!(p_block->status & ECORE_IGU_STATUS_VALID))
2179 if (p_block->status & ECORE_IGU_STATUS_DSB) {
2180 p_block->function_id = p_hwfn->rel_pf_id;
2182 p_block->vector_number = 0;
2183 p_block->status = ECORE_IGU_STATUS_VALID |
2184 ECORE_IGU_STATUS_PF |
2185 ECORE_IGU_STATUS_DSB;
2186 } else if (pf_sbs) {
2188 p_block->function_id = p_hwfn->rel_pf_id;
2190 p_block->vector_number = p_info->usage.cnt - pf_sbs;
2191 p_block->status = ECORE_IGU_STATUS_VALID |
2192 ECORE_IGU_STATUS_PF |
2193 ECORE_IGU_STATUS_FREE;
2194 } else if (vf_sbs) {
2195 p_block->function_id =
2196 p_hwfn->p_dev->p_iov_info->first_vf_in_pf +
2197 p_info->usage.iov_cnt - vf_sbs;
2199 p_block->vector_number = 0;
2200 p_block->status = ECORE_IGU_STATUS_VALID |
2201 ECORE_IGU_STATUS_FREE;
2204 p_block->function_id = 0;
2206 p_block->vector_number = 0;
2209 SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER,
2210 p_block->function_id);
2211 SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf);
2212 SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER,
2213 p_block->vector_number);
2215 /* VF entries would be enabled when VF is initializaed */
2216 SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf);
2218 rval = ecore_rd(p_hwfn, p_ptt,
2219 IGU_REG_MAPPING_MEMORY +
2220 sizeof(u32) * igu_sb_id);
2223 ecore_wr(p_hwfn, p_ptt,
2224 IGU_REG_MAPPING_MEMORY +
2225 sizeof(u32) * igu_sb_id,
2228 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2229 "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n",
2230 igu_sb_id, p_block->function_id,
2231 p_block->is_pf, p_block->vector_number,
2239 int ecore_int_igu_reset_cam_default(struct ecore_hwfn *p_hwfn,
2240 struct ecore_ptt *p_ptt)
2242 struct ecore_sb_cnt_info *p_cnt = &p_hwfn->hw_info.p_igu_info->usage;
2244 /* Return all the usage indications to default prior to the reset;
2245 * The reset expects the !orig to reflect the initial status of the
2246 * SBs, and would re-calculate the originals based on those.
2248 p_cnt->cnt = p_cnt->orig;
2249 p_cnt->free_cnt = p_cnt->orig;
2250 p_cnt->iov_cnt = p_cnt->iov_orig;
2251 p_cnt->free_cnt_iov = p_cnt->iov_orig;
2253 p_cnt->iov_orig = 0;
2255 /* TODO - we probably need to re-configure the CAU as well... */
2256 return ecore_int_igu_reset_cam(p_hwfn, p_ptt);
2259 static void ecore_int_igu_read_cam_block(struct ecore_hwfn *p_hwfn,
2260 struct ecore_ptt *p_ptt,
2263 u32 val = ecore_rd(p_hwfn, p_ptt,
2264 IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id);
2265 struct ecore_igu_block *p_block;
2267 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
2269 /* Fill the block information */
2270 p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER);
2271 p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
2272 p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER);
2274 p_block->igu_sb_id = igu_sb_id;
2277 enum _ecore_status_t ecore_int_igu_read_cam(struct ecore_hwfn *p_hwfn,
2278 struct ecore_ptt *p_ptt)
2280 struct ecore_igu_info *p_igu_info;
2281 struct ecore_igu_block *p_block;
2282 u32 min_vf = 0, max_vf = 0;
2285 p_hwfn->hw_info.p_igu_info = OSAL_ZALLOC(p_hwfn->p_dev,
2287 sizeof(*p_igu_info));
2288 if (!p_hwfn->hw_info.p_igu_info)
2290 p_igu_info = p_hwfn->hw_info.p_igu_info;
2292 /* Distinguish between existent and onn-existent default SB */
2293 p_igu_info->igu_dsb_id = ECORE_SB_INVALID_IDX;
2295 /* Find the range of VF ids whose SB belong to this PF */
2296 if (p_hwfn->p_dev->p_iov_info) {
2297 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
2299 min_vf = p_iov->first_vf_in_pf;
2300 max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs;
2304 igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2306 /* Read current entry; Notice it might not belong to this PF */
2307 ecore_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id);
2308 p_block = &p_igu_info->entry[igu_sb_id];
2310 if ((p_block->is_pf) &&
2311 (p_block->function_id == p_hwfn->rel_pf_id)) {
2312 p_block->status = ECORE_IGU_STATUS_PF |
2313 ECORE_IGU_STATUS_VALID |
2314 ECORE_IGU_STATUS_FREE;
2316 if (p_igu_info->igu_dsb_id != ECORE_SB_INVALID_IDX)
2317 p_igu_info->usage.cnt++;
2318 } else if (!(p_block->is_pf) &&
2319 (p_block->function_id >= min_vf) &&
2320 (p_block->function_id < max_vf)) {
2321 /* Available for VFs of this PF */
2322 p_block->status = ECORE_IGU_STATUS_VALID |
2323 ECORE_IGU_STATUS_FREE;
2325 if (p_igu_info->igu_dsb_id != ECORE_SB_INVALID_IDX)
2326 p_igu_info->usage.iov_cnt++;
2329 /* Mark the First entry belonging to the PF or its VFs
2330 * as the default SB [we'll reset IGU prior to first usage].
2332 if ((p_block->status & ECORE_IGU_STATUS_VALID) &&
2333 (p_igu_info->igu_dsb_id == ECORE_SB_INVALID_IDX)) {
2334 p_igu_info->igu_dsb_id = igu_sb_id;
2335 p_block->status |= ECORE_IGU_STATUS_DSB;
2338 /* While this isn't suitable for all clients, limit number
2339 * of prints by having each PF print only its entries with the
2340 * exception of PF0 which would print everything.
2342 if ((p_block->status & ECORE_IGU_STATUS_VALID) ||
2343 (p_hwfn->abs_pf_id == 0))
2344 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2345 "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n",
2346 igu_sb_id, p_block->function_id,
2347 p_block->is_pf, p_block->vector_number);
2350 if (p_igu_info->igu_dsb_id == ECORE_SB_INVALID_IDX) {
2351 DP_NOTICE(p_hwfn, true,
2352 "IGU CAM returned invalid values igu_dsb_id=0x%x\n",
2353 p_igu_info->igu_dsb_id);
2357 /* All non default SB are considered free at this point */
2358 p_igu_info->usage.free_cnt = p_igu_info->usage.cnt;
2359 p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt;
2361 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2362 "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n",
2363 p_igu_info->igu_dsb_id, p_igu_info->usage.cnt,
2364 p_igu_info->usage.iov_cnt);
2366 return ECORE_SUCCESS;
2369 enum _ecore_status_t
2370 ecore_int_igu_relocate_sb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2371 u16 sb_id, bool b_to_vf)
2373 struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2374 struct ecore_igu_block *p_block = OSAL_NULL;
2375 u16 igu_sb_id = 0, vf_num = 0;
2378 if (IS_VF(p_hwfn->p_dev) || !IS_PF_SRIOV(p_hwfn))
2381 if (sb_id == ECORE_SP_SB_ID)
2384 if (!p_info->b_allow_pf_vf_change) {
2385 DP_INFO(p_hwfn, "Can't relocate SBs as MFW is too old.\n");
2389 /* If we're moving a SB from PF to VF, the client had to specify
2390 * which vector it wants to move.
2393 igu_sb_id = ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1);
2394 if (igu_sb_id == ECORE_SB_INVALID_IDX)
2398 /* If we're moving a SB from VF to PF, need to validate there isn't
2399 * already a line configured for that vector.
2402 if (ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1) !=
2403 ECORE_SB_INVALID_IDX)
2407 /* We need to validate that the SB can actually be relocated.
2408 * This would also handle the previous case where we've explicitly
2409 * stated which IGU SB needs to move.
2411 for (; igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2413 p_block = &p_info->entry[igu_sb_id];
2415 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
2416 !(p_block->status & ECORE_IGU_STATUS_FREE) ||
2417 (!!(p_block->status & ECORE_IGU_STATUS_PF) != b_to_vf)) {
2427 if (igu_sb_id == ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev)) {
2428 DP_VERBOSE(p_hwfn, (ECORE_MSG_INTR | ECORE_MSG_IOV),
2429 "Failed to find a free SB to move\n");
2433 /* At this point, p_block points to the SB we want to relocate */
2435 p_block->status &= ~ECORE_IGU_STATUS_PF;
2437 /* It doesn't matter which VF number we choose, since we're
2438 * going to disable the line; But let's keep it in range.
2440 vf_num = (u16)p_hwfn->p_dev->p_iov_info->first_vf_in_pf;
2442 p_block->function_id = (u8)vf_num;
2444 p_block->vector_number = 0;
2446 p_info->usage.cnt--;
2447 p_info->usage.free_cnt--;
2448 p_info->usage.iov_cnt++;
2449 p_info->usage.free_cnt_iov++;
2451 /* TODO - if SBs aren't really the limiting factor,
2452 * then it might not be accurate [in the since that
2453 * we might not need decrement the feature].
2455 p_hwfn->hw_info.feat_num[ECORE_PF_L2_QUE]--;
2456 p_hwfn->hw_info.feat_num[ECORE_VF_L2_QUE]++;
2458 p_block->status |= ECORE_IGU_STATUS_PF;
2459 p_block->function_id = p_hwfn->rel_pf_id;
2461 p_block->vector_number = sb_id + 1;
2463 p_info->usage.cnt++;
2464 p_info->usage.free_cnt++;
2465 p_info->usage.iov_cnt--;
2466 p_info->usage.free_cnt_iov--;
2468 p_hwfn->hw_info.feat_num[ECORE_PF_L2_QUE]++;
2469 p_hwfn->hw_info.feat_num[ECORE_VF_L2_QUE]--;
2472 /* Update the IGU and CAU with the new configuration */
2473 SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER,
2474 p_block->function_id);
2475 SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf);
2476 SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf);
2477 SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER,
2478 p_block->vector_number);
2480 ecore_wr(p_hwfn, p_ptt,
2481 IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id,
2484 ecore_int_cau_conf_sb(p_hwfn, p_ptt, 0,
2486 p_block->is_pf ? 0 : 1);
2488 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2489 "Relocation: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n",
2490 igu_sb_id, p_block->function_id,
2491 p_block->is_pf, p_block->vector_number);
2493 return ECORE_SUCCESS;
2497 * @brief Initialize igu runtime registers
2501 void ecore_int_igu_init_rt(struct ecore_hwfn *p_hwfn)
2503 u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN;
2505 STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);
2508 #define LSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - \
2509 IGU_CMD_INT_ACK_BASE)
2510 #define MSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - \
2511 IGU_CMD_INT_ACK_BASE)
2512 u64 ecore_int_igu_read_sisr_reg(struct ecore_hwfn *p_hwfn)
2514 u32 intr_status_hi = 0, intr_status_lo = 0;
2515 u64 intr_status = 0;
2517 intr_status_lo = REG_RD(p_hwfn,
2518 GTT_BAR0_MAP_REG_IGU_CMD +
2519 LSB_IGU_CMD_ADDR * 8);
2520 intr_status_hi = REG_RD(p_hwfn,
2521 GTT_BAR0_MAP_REG_IGU_CMD +
2522 MSB_IGU_CMD_ADDR * 8);
2523 intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo;
2528 static void ecore_int_sp_dpc_setup(struct ecore_hwfn *p_hwfn)
2530 OSAL_DPC_INIT(p_hwfn->sp_dpc, p_hwfn);
2531 p_hwfn->b_sp_dpc_enabled = true;
2534 static enum _ecore_status_t ecore_int_sp_dpc_alloc(struct ecore_hwfn *p_hwfn)
2536 p_hwfn->sp_dpc = OSAL_DPC_ALLOC(p_hwfn);
2537 if (!p_hwfn->sp_dpc)
2540 return ECORE_SUCCESS;
2543 static void ecore_int_sp_dpc_free(struct ecore_hwfn *p_hwfn)
2545 OSAL_FREE(p_hwfn->p_dev, p_hwfn->sp_dpc);
2548 enum _ecore_status_t ecore_int_alloc(struct ecore_hwfn *p_hwfn,
2549 struct ecore_ptt *p_ptt)
2551 enum _ecore_status_t rc = ECORE_SUCCESS;
2553 rc = ecore_int_sp_dpc_alloc(p_hwfn);
2554 if (rc != ECORE_SUCCESS) {
2555 DP_ERR(p_hwfn->p_dev, "Failed to allocate sp dpc mem\n");
2559 rc = ecore_int_sp_sb_alloc(p_hwfn, p_ptt);
2560 if (rc != ECORE_SUCCESS) {
2561 DP_ERR(p_hwfn->p_dev, "Failed to allocate sp sb mem\n");
2565 rc = ecore_int_sb_attn_alloc(p_hwfn, p_ptt);
2566 if (rc != ECORE_SUCCESS)
2567 DP_ERR(p_hwfn->p_dev, "Failed to allocate sb attn mem\n");
2572 void ecore_int_free(struct ecore_hwfn *p_hwfn)
2574 ecore_int_sp_sb_free(p_hwfn);
2575 ecore_int_sb_attn_free(p_hwfn);
2576 ecore_int_sp_dpc_free(p_hwfn);
2579 void ecore_int_setup(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
2581 if (!p_hwfn || !p_hwfn->p_sp_sb || !p_hwfn->p_sb_attn)
2584 ecore_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);
2585 ecore_int_sb_attn_setup(p_hwfn, p_ptt);
2586 ecore_int_sp_dpc_setup(p_hwfn);
2589 void ecore_int_get_num_sbs(struct ecore_hwfn *p_hwfn,
2590 struct ecore_sb_cnt_info *p_sb_cnt_info)
2592 struct ecore_igu_info *p_igu_info = p_hwfn->hw_info.p_igu_info;
2594 if (!p_igu_info || !p_sb_cnt_info)
2597 OSAL_MEMCPY(p_sb_cnt_info, &p_igu_info->usage,
2598 sizeof(*p_sb_cnt_info));
2601 void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev)
2605 for_each_hwfn(p_dev, i)
2606 p_dev->hwfns[i].b_int_requested = false;
2609 void ecore_int_attn_clr_enable(struct ecore_dev *p_dev, bool clr_enable)
2611 p_dev->attn_clr_en = clr_enable;
2614 enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,
2615 struct ecore_ptt *p_ptt,
2616 u8 timer_res, u16 sb_id, bool tx)
2618 struct cau_sb_entry sb_entry;
2619 enum _ecore_status_t rc;
2621 if (!p_hwfn->hw_init_done) {
2622 DP_ERR(p_hwfn, "hardware not initialized yet\n");
2626 rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2627 sb_id * sizeof(u64),
2628 (u64)(osal_uintptr_t)&sb_entry, 2, 0);
2629 if (rc != ECORE_SUCCESS) {
2630 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2635 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
2637 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
2639 rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
2640 (u64)(osal_uintptr_t)&sb_entry,
2641 CAU_REG_SB_VAR_MEMORY +
2642 sb_id * sizeof(u64), 2, 0);
2643 if (rc != ECORE_SUCCESS) {
2644 DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc);
2651 enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,
2652 struct ecore_ptt *p_ptt,
2653 struct ecore_sb_info *p_sb,
2654 struct ecore_sb_info_dbg *p_info)
2656 u16 sbid = p_sb->igu_sb_id;
2659 if (IS_VF(p_hwfn->p_dev))
2662 if (sbid > NUM_OF_SBS(p_hwfn->p_dev))
2665 p_info->igu_prod = ecore_rd(p_hwfn, p_ptt,
2666 IGU_REG_PRODUCER_MEMORY + sbid * 4);
2667 p_info->igu_cons = ecore_rd(p_hwfn, p_ptt,
2668 IGU_REG_CONSUMER_MEM + sbid * 4);
2670 for (i = 0; i < PIS_PER_SB_E4; i++)
2671 p_info->pi[i] = (u16)ecore_rd(p_hwfn, p_ptt,
2673 sbid * 4 * PIS_PER_SB_E4 +
2676 return ECORE_SUCCESS;