2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_spq.h"
13 #include "ecore_gtt_reg_addr.h"
14 #include "ecore_init_ops.h"
15 #include "ecore_rt_defs.h"
16 #include "ecore_int.h"
19 #include "ecore_sriov.h"
21 #include "ecore_hw_defs.h"
22 #include "ecore_hsi_common.h"
23 #include "ecore_mcp.h"
25 struct ecore_pi_info {
26 ecore_int_comp_cb_t comp_cb;
27 void *cookie; /* Will be sent to the compl cb function */
30 struct ecore_sb_sp_info {
31 struct ecore_sb_info sb_info;
32 /* per protocol index data */
33 struct ecore_pi_info pi_info_arr[PIS_PER_SB];
36 enum ecore_attention_type {
38 ECORE_ATTN_TYPE_PARITY,
41 #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
42 ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
44 struct aeu_invert_reg_bit {
47 #define ATTENTION_PARITY (1 << 0)
49 #define ATTENTION_LENGTH_MASK (0x00000ff0)
50 #define ATTENTION_LENGTH_SHIFT (4)
51 #define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \
52 ATTENTION_LENGTH_SHIFT)
53 #define ATTENTION_SINGLE (1 << ATTENTION_LENGTH_SHIFT)
54 #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY)
55 #define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \
58 /* Multiple bits start with this offset */
59 #define ATTENTION_OFFSET_MASK (0x000ff000)
60 #define ATTENTION_OFFSET_SHIFT (12)
62 #define ATTENTION_CLEAR_ENABLE (1 << 28)
65 /* Callback to call if attention will be triggered */
66 enum _ecore_status_t (*cb)(struct ecore_hwfn *p_hwfn);
68 enum block_id block_index;
71 struct aeu_invert_reg {
72 struct aeu_invert_reg_bit bits[32];
75 #define MAX_ATTN_GRPS (8)
76 #define NUM_ATTN_REGS (9)
78 static enum _ecore_status_t ecore_mcp_attn_cb(struct ecore_hwfn *p_hwfn)
80 u32 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE);
82 DP_INFO(p_hwfn->p_dev, "MCP_REG_CPU_STATE: %08x - Masking...\n", tmp);
83 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 0xffffffff);
88 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK (0x3c000)
89 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT (14)
90 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK (0x03fc0)
91 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT (6)
92 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK (0x00020)
93 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT (5)
94 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK (0x0001e)
95 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT (1)
96 #define ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK (0x1)
97 #define ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT (0)
98 #define ECORE_PSWHST_ATTENTION_VF_DISABLED (0x1)
99 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1)
100 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1)
101 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0)
102 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0x1e)
103 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1)
104 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x20)
105 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5)
106 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0x3fc0)
107 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6)
108 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0x3c000)
109 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14)
110 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0x3fc0000)
111 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18)
112 static enum _ecore_status_t ecore_pswhst_attn_cb(struct ecore_hwfn *p_hwfn)
115 ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
116 PSWHST_REG_VF_DISABLED_ERROR_VALID);
118 /* Disabled VF access */
119 if (tmp & ECORE_PSWHST_ATTENTION_VF_DISABLED) {
122 addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
123 PSWHST_REG_VF_DISABLED_ERROR_ADDRESS);
124 data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
125 PSWHST_REG_VF_DISABLED_ERROR_DATA);
126 DP_INFO(p_hwfn->p_dev,
127 "PF[0x%02x] VF [0x%02x] [Valid 0x%02x] Client [0x%02x]"
128 " Write [0x%02x] Addr [0x%08x]\n",
129 (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK)
130 >> ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT),
131 (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK)
132 >> ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT),
134 ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK) >>
135 ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT),
137 ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK) >>
138 ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT),
140 ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK) >>
141 ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT),
145 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
146 PSWHST_REG_INCORRECT_ACCESS_VALID);
147 if (tmp & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS) {
148 u32 addr, data, length;
150 addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
151 PSWHST_REG_INCORRECT_ACCESS_ADDRESS);
152 data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
153 PSWHST_REG_INCORRECT_ACCESS_DATA);
154 length = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
155 PSWHST_REG_INCORRECT_ACCESS_LENGTH);
157 DP_INFO(p_hwfn->p_dev,
158 "Incorrect access to %08x of length %08x - PF [%02x]"
159 " VF [%04x] [valid %02x] client [%02x] write [%02x]"
160 " Byte-Enable [%04x] [%08x]\n",
163 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK) >>
164 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT),
166 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK) >>
167 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT),
169 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK) >>
170 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT),
172 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK) >>
173 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT),
175 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK) >>
176 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT),
178 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK) >>
179 ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT),
183 /* TODO - We know 'some' of these are legal due to virtualization,
184 * but is it true for all of them?
186 return ECORE_SUCCESS;
189 #define ECORE_GRC_ATTENTION_VALID_BIT (1 << 0)
190 #define ECORE_GRC_ATTENTION_ADDRESS_MASK (0x7fffff << 0)
191 #define ECORE_GRC_ATTENTION_RDWR_BIT (1 << 23)
192 #define ECORE_GRC_ATTENTION_MASTER_MASK (0xf << 24)
193 #define ECORE_GRC_ATTENTION_MASTER_SHIFT (24)
194 #define ECORE_GRC_ATTENTION_PF_MASK (0xf)
195 #define ECORE_GRC_ATTENTION_VF_MASK (0xff << 4)
196 #define ECORE_GRC_ATTENTION_VF_SHIFT (4)
197 #define ECORE_GRC_ATTENTION_PRIV_MASK (0x3 << 14)
198 #define ECORE_GRC_ATTENTION_PRIV_SHIFT (14)
199 #define ECORE_GRC_ATTENTION_PRIV_VF (0)
200 static const char *grc_timeout_attn_master_to_str(u8 master)
228 static enum _ecore_status_t ecore_grc_attn_cb(struct ecore_hwfn *p_hwfn)
232 /* We've already cleared the timeout interrupt register, so we learn
233 * of interrupts via the validity register
235 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
236 GRC_REG_TIMEOUT_ATTN_ACCESS_VALID);
237 if (!(tmp & ECORE_GRC_ATTENTION_VALID_BIT))
240 /* Read the GRC timeout information */
241 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
242 GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0);
243 tmp2 = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
244 GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1);
246 DP_INFO(p_hwfn->p_dev,
247 "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s]"
248 " [PF: %02x %s %02x]\n",
250 (tmp & ECORE_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from",
251 (tmp & ECORE_GRC_ATTENTION_ADDRESS_MASK) << 2,
252 grc_timeout_attn_master_to_str((tmp &
253 ECORE_GRC_ATTENTION_MASTER_MASK) >>
254 ECORE_GRC_ATTENTION_MASTER_SHIFT),
255 (tmp2 & ECORE_GRC_ATTENTION_PF_MASK),
256 (((tmp2 & ECORE_GRC_ATTENTION_PRIV_MASK) >>
257 ECORE_GRC_ATTENTION_PRIV_SHIFT) ==
258 ECORE_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant:)",
259 (tmp2 & ECORE_GRC_ATTENTION_VF_MASK) >>
260 ECORE_GRC_ATTENTION_VF_SHIFT);
263 /* Regardles of anything else, clean the validity bit */
264 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
265 GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0);
266 return ECORE_SUCCESS;
269 #define ECORE_PGLUE_ATTENTION_VALID (1 << 29)
270 #define ECORE_PGLUE_ATTENTION_RD_VALID (1 << 26)
271 #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf << 20)
272 #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20)
273 #define ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID (1 << 19)
274 #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff << 24)
275 #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24)
276 #define ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR (1 << 21)
277 #define ECORE_PGLUE_ATTENTION_DETAILS2_BME (1 << 22)
278 #define ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN (1 << 23)
279 #define ECORE_PGLUE_ATTENTION_ICPL_VALID (1 << 23)
280 #define ECORE_PGLUE_ATTENTION_ZLR_VALID (1 << 25)
281 #define ECORE_PGLUE_ATTENTION_ILT_VALID (1 << 23)
282 static enum _ecore_status_t ecore_pglub_rbc_attn_cb(struct ecore_hwfn *p_hwfn)
286 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
287 PGLUE_B_REG_TX_ERR_WR_DETAILS2);
288 if (tmp & ECORE_PGLUE_ATTENTION_VALID) {
289 u32 addr_lo, addr_hi, details;
291 addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
292 PGLUE_B_REG_TX_ERR_WR_ADD_31_0);
293 addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
294 PGLUE_B_REG_TX_ERR_WR_ADD_63_32);
295 details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
296 PGLUE_B_REG_TX_ERR_WR_DETAILS);
299 "Illegal write by chip to [%08x:%08x] blocked."
300 "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]"
301 " Details2 %08x [Was_error %02x BME deassert %02x"
302 " FID_enable deassert %02x]\n",
303 addr_hi, addr_lo, details,
305 ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>
306 ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
308 ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >>
309 ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
310 (u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID)
312 (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1
314 (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ? 1 :
316 (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1
320 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
321 PGLUE_B_REG_TX_ERR_RD_DETAILS2);
322 if (tmp & ECORE_PGLUE_ATTENTION_RD_VALID) {
323 u32 addr_lo, addr_hi, details;
325 addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
326 PGLUE_B_REG_TX_ERR_RD_ADD_31_0);
327 addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
328 PGLUE_B_REG_TX_ERR_RD_ADD_63_32);
329 details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
330 PGLUE_B_REG_TX_ERR_RD_DETAILS);
333 "Illegal read by chip from [%08x:%08x] blocked."
334 " Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]"
335 " Details2 %08x [Was_error %02x BME deassert %02x"
336 " FID_enable deassert %02x]\n",
337 addr_hi, addr_lo, details,
339 ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>
340 ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
342 ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >>
343 ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
344 (u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID)
346 (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1
348 (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ? 1 :
350 (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1
354 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
355 PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL);
356 if (tmp & ECORE_PGLUE_ATTENTION_ICPL_VALID)
357 DP_INFO(p_hwfn, "ICPL error - %08x\n", tmp);
359 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
360 PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS);
361 if (tmp & ECORE_PGLUE_ATTENTION_ZLR_VALID) {
362 u32 addr_hi, addr_lo;
364 addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
365 PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0);
366 addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
367 PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32);
369 DP_INFO(p_hwfn, "ICPL error - %08x [Address %08x:%08x]\n",
370 tmp, addr_hi, addr_lo);
373 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
374 PGLUE_B_REG_VF_ILT_ERR_DETAILS2);
375 if (tmp & ECORE_PGLUE_ATTENTION_ILT_VALID) {
376 u32 addr_hi, addr_lo, details;
378 addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
379 PGLUE_B_REG_VF_ILT_ERR_ADD_31_0);
380 addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
381 PGLUE_B_REG_VF_ILT_ERR_ADD_63_32);
382 details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
383 PGLUE_B_REG_VF_ILT_ERR_DETAILS);
386 "ILT error - Details %08x Details2 %08x"
387 " [Address %08x:%08x]\n",
388 details, tmp, addr_hi, addr_lo);
391 /* Clear the indications */
392 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
393 PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2));
395 return ECORE_SUCCESS;
398 static enum _ecore_status_t ecore_fw_assertion(struct ecore_hwfn *p_hwfn)
400 DP_NOTICE(p_hwfn, false, "FW assertion!\n");
402 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FW_ASSERT);
407 static enum _ecore_status_t
408 ecore_general_attention_35(struct ecore_hwfn *p_hwfn)
410 DP_INFO(p_hwfn, "General attention 35!\n");
412 return ECORE_SUCCESS;
415 #define ECORE_DORQ_ATTENTION_REASON_MASK (0xfffff)
416 #define ECORE_DORQ_ATTENTION_OPAQUE_MASK (0xffff)
417 #define ECORE_DORQ_ATTENTION_SIZE_MASK (0x7f)
418 #define ECORE_DORQ_ATTENTION_SIZE_SHIFT (16)
420 static enum _ecore_status_t ecore_dorq_attn_cb(struct ecore_hwfn *p_hwfn)
424 reason = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, DORQ_REG_DB_DROP_REASON) &
425 ECORE_DORQ_ATTENTION_REASON_MASK;
427 u32 details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
428 DORQ_REG_DB_DROP_DETAILS);
430 DP_INFO(p_hwfn->p_dev,
431 "DORQ db_drop: address 0x%08x Opaque FID 0x%04x"
432 " Size [bytes] 0x%08x Reason: 0x%08x\n",
433 ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
434 DORQ_REG_DB_DROP_DETAILS_ADDRESS),
435 (u16)(details & ECORE_DORQ_ATTENTION_OPAQUE_MASK),
436 ((details & ECORE_DORQ_ATTENTION_SIZE_MASK) >>
437 ECORE_DORQ_ATTENTION_SIZE_SHIFT) * 4, reason);
443 static enum _ecore_status_t ecore_tm_attn_cb(struct ecore_hwfn *p_hwfn)
446 if (CHIP_REV_IS_EMUL_B0(p_hwfn->p_dev)) {
447 u32 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
450 if (val & ~(TM_REG_INT_STS_1_PEND_TASK_SCAN |
451 TM_REG_INT_STS_1_PEND_CONN_SCAN))
454 if (val & (TM_REG_INT_STS_1_PEND_TASK_SCAN |
455 TM_REG_INT_STS_1_PEND_CONN_SCAN))
457 "TM attention on emulation - most likely"
458 " results of clock-ratios\n");
459 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1);
460 val |= TM_REG_INT_MASK_1_PEND_CONN_SCAN |
461 TM_REG_INT_MASK_1_PEND_TASK_SCAN;
462 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1, val);
464 return ECORE_SUCCESS;
471 /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */
472 static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = {
474 { /* After Invert 1 */
475 {"GPIO0 function%d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
481 { /* After Invert 2 */
482 {"PGLUE config_space", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
483 {"PGLUE misc_flr", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
484 {"PGLUE B RBC", ATTENTION_PAR_INT, ecore_pglub_rbc_attn_cb,
486 {"PGLUE misc_mctp", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
487 {"Flash event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
488 {"SMB event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
489 {"Main Power", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
491 (8 << ATTENTION_LENGTH_SHIFT) | (1 << ATTENTION_OFFSET_SHIFT),
492 OSAL_NULL, MAX_BLOCK_ID},
493 {"PCIE glue/PXP VPD %d", (16 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
499 { /* After Invert 3 */
500 {"General Attention %d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
506 { /* After Invert 4 */
507 {"General Attention 32", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE,
508 ecore_fw_assertion, MAX_BLOCK_ID},
509 {"General Attention %d",
510 (2 << ATTENTION_LENGTH_SHIFT) | (33 << ATTENTION_OFFSET_SHIFT),
511 OSAL_NULL, MAX_BLOCK_ID},
512 {"General Attention 35", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE,
513 ecore_general_attention_35, MAX_BLOCK_ID},
514 {"CNIG port %d", (4 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
516 {"MCP CPU", ATTENTION_SINGLE, ecore_mcp_attn_cb, MAX_BLOCK_ID},
517 {"MCP Watchdog timer", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
518 {"MCP M2P", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
519 {"AVS stop status ready", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
520 {"MSTAT", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
521 {"MSTAT per-path", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
522 {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
524 {"NIG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NIG},
525 {"BMB/OPTE/MCP", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BMB},
526 {"BTB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BTB},
527 {"BRB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BRB},
528 {"PRS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRS},
533 { /* After Invert 5 */
534 {"SRC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_SRC},
535 {"PB Client1", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB1},
536 {"PB Client2", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB2},
537 {"RPB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RPB},
538 {"PBF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF},
539 {"QM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_QM},
540 {"TM", ATTENTION_PAR_INT, ecore_tm_attn_cb, BLOCK_TM},
541 {"MCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MCM},
542 {"MSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSDM},
543 {"MSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSEM},
544 {"PCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PCM},
545 {"PSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSDM},
546 {"PSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSEM},
547 {"TCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCM},
548 {"TSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSDM},
549 {"TSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSEM},
554 { /* After Invert 6 */
555 {"UCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_UCM},
556 {"USDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USDM},
557 {"USEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USEM},
558 {"XCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XCM},
559 {"XSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSDM},
560 {"XSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSEM},
561 {"YCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YCM},
562 {"YSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSDM},
563 {"YSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSEM},
564 {"XYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XYLD},
565 {"TMLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TMLD},
566 {"MYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MULD},
567 {"YULD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YULD},
568 {"DORQ", ATTENTION_PAR_INT, ecore_dorq_attn_cb, BLOCK_DORQ},
569 {"DBG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DBG},
570 {"IPC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IPC},
575 { /* After Invert 7 */
576 {"CCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CCFC},
577 {"CDU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CDU},
578 {"DMAE", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DMAE},
579 {"IGU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IGU},
580 {"ATC", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
581 {"CAU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CAU},
582 {"PTU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PTU},
583 {"PRM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRM},
584 {"TCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCFC},
585 {"RDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RDIF},
586 {"TDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TDIF},
587 {"RSS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RSS},
588 {"MISC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISC},
589 {"MISCS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISCS},
590 {"PCIE", ATTENTION_PAR, OSAL_NULL, BLOCK_PCIE},
591 {"Vaux PCI core", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
592 {"PSWRQ", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ},
597 { /* After Invert 8 */
598 {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ2},
599 {"PSWWR", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR},
600 {"PSWWR (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR2},
601 {"PSWRD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD},
602 {"PSWRD (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD2},
603 {"PSWHST", ATTENTION_PAR_INT, ecore_pswhst_attn_cb, BLOCK_PSWHST},
604 {"PSWHST (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWHST2},
605 {"GRC", ATTENTION_PAR_INT, ecore_grc_attn_cb, BLOCK_GRC},
606 {"CPMU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CPMU},
607 {"NCSI", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NCSI},
608 {"MSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
609 {"PSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
610 {"TSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
611 {"USEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
612 {"XSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
613 {"YSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
614 {"pxp_misc_mps", ATTENTION_PAR, OSAL_NULL, BLOCK_PGLCS},
615 {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
616 {"PERST_B assertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
617 {"PERST_B deassertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
618 {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
624 { /* After Invert 9 */
625 {"MCP Latched memory", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
626 {"MCP Latched scratchpad cache", ATTENTION_SINGLE, OSAL_NULL,
628 {"MCP Latched ump_tx", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
629 {"MCP Latched scratchpad", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
630 {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
637 #define ATTN_STATE_BITS (0xfff)
638 #define ATTN_BITS_MASKABLE (0x3ff)
639 struct ecore_sb_attn_info {
640 /* Virtual & Physical address of the SB */
641 struct atten_status_block *sb_attn;
644 /* Last seen running index */
647 /* A mask of the AEU bits resulting in a parity error */
648 u32 parity_mask[NUM_ATTN_REGS];
650 /* A pointer to the attention description structure */
651 struct aeu_invert_reg *p_aeu_desc;
653 /* Previously asserted attentions, which are still unasserted */
656 /* Cleanup address for the link's general hw attention */
660 static u16 ecore_attn_update_idx(struct ecore_hwfn *p_hwfn,
661 struct ecore_sb_attn_info *p_sb_desc)
665 OSAL_MMIOWB(p_hwfn->p_dev);
667 index = OSAL_LE16_TO_CPU(p_sb_desc->sb_attn->sb_index);
668 if (p_sb_desc->index != index) {
669 p_sb_desc->index = index;
670 rc = ECORE_SB_ATT_IDX;
673 OSAL_MMIOWB(p_hwfn->p_dev);
679 * @brief ecore_int_assertion - handles asserted attention bits
682 * @param asserted_bits newly asserted bits
683 * @return enum _ecore_status_t
685 static enum _ecore_status_t ecore_int_assertion(struct ecore_hwfn *p_hwfn,
688 struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
691 /* Mask the source of the attention in the IGU */
692 igu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
693 IGU_REG_ATTENTION_ENABLE);
694 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n",
695 igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE));
696 igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE);
697 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);
699 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
700 "inner known ATTN state: 0x%04x --> 0x%04x\n",
701 sb_attn_sw->known_attn,
702 sb_attn_sw->known_attn | asserted_bits);
703 sb_attn_sw->known_attn |= asserted_bits;
705 /* Handle MCP events */
706 if (asserted_bits & 0x100) {
707 ecore_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt);
708 /* Clean the MCP attention */
709 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
710 sb_attn_sw->mfw_attn_addr, 0);
713 /* FIXME - this will change once we'll have GOOD gtt definitions */
714 DIRECT_REG_WR(p_hwfn,
715 (u8 OSAL_IOMEM *) p_hwfn->regview +
716 GTT_BAR0_MAP_REG_IGU_CMD +
717 ((IGU_CMD_ATTN_BIT_SET_UPPER -
718 IGU_CMD_INT_ACK_BASE) << 3), (u32)asserted_bits);
720 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "set cmd IGU: 0x%04x\n",
723 return ECORE_SUCCESS;
726 static void ecore_int_attn_print(struct ecore_hwfn *p_hwfn,
727 enum block_id id, enum dbg_attn_type type,
731 DP_NOTICE(p_hwfn->p_dev, false, "[block_id %d type %d]\n", id, type);
735 * @brief ecore_int_deassertion_aeu_bit - handles the effects of a single
736 * cause of the attention
739 * @param p_aeu - descriptor of an AEU bit which caused the attention
740 * @param aeu_en_reg - register offset of the AEU enable reg. which configured
741 * this bit to this group.
742 * @param bit_index - index of this bit in the aeu_en_reg
744 * @return enum _ecore_status_t
746 static enum _ecore_status_t
747 ecore_int_deassertion_aeu_bit(struct ecore_hwfn *p_hwfn,
748 struct aeu_invert_reg_bit *p_aeu,
750 const char *p_bit_name,
753 enum _ecore_status_t rc = ECORE_INVAL;
754 bool b_fatal = false;
756 DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n",
757 p_bit_name, bitmask);
759 /* Call callback before clearing the interrupt status */
761 DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n",
763 rc = p_aeu->cb(p_hwfn);
766 if (rc != ECORE_SUCCESS)
769 /* Print HW block interrupt registers */
770 if (p_aeu->block_index != MAX_BLOCK_ID) {
771 ecore_int_attn_print(p_hwfn, p_aeu->block_index,
772 ATTN_TYPE_INTERRUPT, !b_fatal);
775 /* Reach assertion if attention is fatal */
777 DP_NOTICE(p_hwfn, true, "`%s': Fatal attention\n",
780 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
783 /* Prevent this Attention from being asserted in the future */
784 if (p_aeu->flags & ATTENTION_CLEAR_ENABLE ||
785 p_hwfn->p_dev->attn_clr_en) {
788 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
789 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & mask));
790 DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n",
798 * @brief ecore_int_deassertion_parity - handle a single parity AEU source
801 * @param p_aeu - descriptor of an AEU bit which caused the
805 static void ecore_int_deassertion_parity(struct ecore_hwfn *p_hwfn,
806 struct aeu_invert_reg_bit *p_aeu,
809 u32 block_id = p_aeu->block_index;
811 DP_INFO(p_hwfn->p_dev, "%s[%d] parity attention is set\n",
812 p_aeu->bit_name, bit_index);
814 if (block_id == MAX_BLOCK_ID)
817 ecore_int_attn_print(p_hwfn, block_id,
818 ATTN_TYPE_PARITY, false);
820 /* In A0, there's a single parity bit for several blocks */
821 if (block_id == BLOCK_BTB) {
822 ecore_int_attn_print(p_hwfn, BLOCK_OPTE,
823 ATTN_TYPE_PARITY, false);
824 ecore_int_attn_print(p_hwfn, BLOCK_MCP,
825 ATTN_TYPE_PARITY, false);
830 * @brief - handles deassertion of previously asserted attentions.
833 * @param deasserted_bits - newly deasserted bits
834 * @return enum _ecore_status_t
837 static enum _ecore_status_t ecore_int_deassertion(struct ecore_hwfn *p_hwfn,
840 struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
841 u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask;
842 bool b_parity = false;
844 enum _ecore_status_t rc = ECORE_SUCCESS;
846 /* Read the attention registers in the AEU */
847 for (i = 0; i < NUM_ATTN_REGS; i++) {
848 aeu_inv_arr[i] = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
849 MISC_REG_AEU_AFTER_INVERT_1_IGU +
851 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
852 "Deasserted bits [%d]: %08x\n", i, aeu_inv_arr[i]);
855 /* Handle parity attentions first */
856 for (i = 0; i < NUM_ATTN_REGS; i++) {
857 struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i];
858 u32 en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
859 MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
862 u32 parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en;
864 /* Skip register in which no parity bit is currently set */
868 for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
869 struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j];
871 if ((p_bit->flags & ATTENTION_PARITY) &&
872 !!(parities & (1 << bit_idx))) {
873 ecore_int_deassertion_parity(p_hwfn, p_bit,
878 bit_idx += ATTENTION_LENGTH(p_bit->flags);
882 /* Find non-parity cause for attention and act */
883 for (k = 0; k < MAX_ATTN_GRPS; k++) {
884 struct aeu_invert_reg_bit *p_aeu;
886 /* Handle only groups whose attention is currently deasserted */
887 if (!(deasserted_bits & (1 << k)))
890 for (i = 0; i < NUM_ATTN_REGS; i++) {
891 u32 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
892 i * sizeof(u32) + k * sizeof(u32) * NUM_ATTN_REGS;
893 u32 en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
894 u32 bits = aeu_inv_arr[i] & en;
896 /* Skip if no bit from this group is currently set */
900 /* Find all set bits from current register which belong
901 * to current group, making them responsible for the
902 * previous assertion.
904 for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
905 unsigned long int bitmask;
908 p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j];
910 /* No need to handle attention-only bits */
911 if (p_aeu->flags == ATTENTION_PAR)
915 bit_len = ATTENTION_LENGTH(p_aeu->flags);
916 if (p_aeu->flags & ATTENTION_PAR) {
922 /* Find the bits relating to HW-block, then
923 * shift so they'll become LSB.
925 bitmask = bits & (((1 << bit_len) - 1) << bit);
929 u32 flags = p_aeu->flags;
933 num = (u8)OSAL_FIND_FIRST_BIT(&bitmask,
936 /* Some bits represent more than a
937 * a single interrupt. Correctly print
940 if (ATTENTION_LENGTH(flags) > 2 ||
941 ((flags & ATTENTION_PAR_INT) &&
942 ATTENTION_LENGTH(flags) > 1))
943 OSAL_SNPRINTF(bit_name, 30,
947 OSAL_STRNCPY(bit_name,
951 /* We now need to pass bitmask in its
956 /* Handle source of the attention */
957 ecore_int_deassertion_aeu_bit(p_hwfn,
964 bit_idx += ATTENTION_LENGTH(p_aeu->flags);
969 /* Clear IGU indication for the deasserted bits */
970 /* FIXME - this will change once we'll have GOOD gtt definitions */
971 DIRECT_REG_WR(p_hwfn,
972 (u8 OSAL_IOMEM *) p_hwfn->regview +
973 GTT_BAR0_MAP_REG_IGU_CMD +
974 ((IGU_CMD_ATTN_BIT_CLR_UPPER -
975 IGU_CMD_INT_ACK_BASE) << 3), ~((u32)deasserted_bits));
977 /* Unmask deasserted attentions in IGU */
978 aeu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
979 IGU_REG_ATTENTION_ENABLE);
980 aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE);
981 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);
983 /* Clear deassertion from inner state */
984 sb_attn_sw->known_attn &= ~deasserted_bits;
989 static enum _ecore_status_t ecore_int_attentions(struct ecore_hwfn *p_hwfn)
991 struct ecore_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn;
992 struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn;
993 u16 index = 0, asserted_bits, deasserted_bits;
994 u32 attn_bits = 0, attn_acks = 0;
995 enum _ecore_status_t rc = ECORE_SUCCESS;
997 /* Read current attention bits/acks - safeguard against attentions
998 * by guaranting work on a synchronized timeframe
1001 index = OSAL_LE16_TO_CPU(p_sb_attn->sb_index);
1002 attn_bits = OSAL_LE32_TO_CPU(p_sb_attn->atten_bits);
1003 attn_acks = OSAL_LE32_TO_CPU(p_sb_attn->atten_ack);
1004 } while (index != OSAL_LE16_TO_CPU(p_sb_attn->sb_index));
1005 p_sb_attn->sb_index = index;
1007 /* Attention / Deassertion are meaningful (and in correct state)
1008 * only when they differ and consistent with known state - deassertion
1009 * when previous attention & current ack, and assertion when current
1010 * attention with no previous attention
1012 asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) &
1013 ~p_sb_attn_sw->known_attn;
1014 deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) &
1015 p_sb_attn_sw->known_attn;
1017 if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100))
1019 "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n",
1020 index, attn_bits, attn_acks, asserted_bits,
1021 deasserted_bits, p_sb_attn_sw->known_attn);
1022 else if (asserted_bits == 0x100)
1023 DP_INFO(p_hwfn, "MFW indication via attention\n");
1025 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1026 "MFW indication [deassertion]\n");
1028 if (asserted_bits) {
1029 rc = ecore_int_assertion(p_hwfn, asserted_bits);
1034 if (deasserted_bits)
1035 rc = ecore_int_deassertion(p_hwfn, deasserted_bits);
1040 static void ecore_sb_ack_attn(struct ecore_hwfn *p_hwfn,
1041 void OSAL_IOMEM *igu_addr, u32 ack_cons)
1043 struct igu_prod_cons_update igu_ack = { 0 };
1045 igu_ack.sb_id_and_flags =
1046 ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1047 (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1048 (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1049 (IGU_SEG_ACCESS_ATTN <<
1050 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1052 DIRECT_REG_WR(p_hwfn, igu_addr, igu_ack.sb_id_and_flags);
1054 /* Both segments (interrupts & acks) are written to same place address;
1055 * Need to guarantee all commands will be received (in-order) by HW.
1057 OSAL_MMIOWB(p_hwfn->p_dev);
1058 OSAL_BARRIER(p_hwfn->p_dev);
1061 void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie)
1063 struct ecore_hwfn *p_hwfn = (struct ecore_hwfn *)hwfn_cookie;
1064 struct ecore_pi_info *pi_info = OSAL_NULL;
1065 struct ecore_sb_attn_info *sb_attn;
1066 struct ecore_sb_info *sb_info;
1073 if (!p_hwfn->p_sp_sb) {
1074 DP_ERR(p_hwfn->p_dev, "DPC called - no p_sp_sb\n");
1078 sb_info = &p_hwfn->p_sp_sb->sb_info;
1079 arr_size = OSAL_ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr);
1081 DP_ERR(p_hwfn->p_dev,
1082 "Status block is NULL - cannot ack interrupts\n");
1086 if (!p_hwfn->p_sb_attn) {
1087 DP_ERR(p_hwfn->p_dev, "DPC called - no p_sb_attn");
1090 sb_attn = p_hwfn->p_sb_attn;
1092 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "DPC Called! (hwfn %p %d)\n",
1093 p_hwfn, p_hwfn->my_id);
1095 /* Disable ack for def status block. Required both for msix +
1096 * inta in non-mask mode, in inta does no harm.
1098 ecore_sb_ack(sb_info, IGU_INT_DISABLE, 0);
1100 /* Gather Interrupts/Attentions information */
1101 if (!sb_info->sb_virt) {
1102 DP_ERR(p_hwfn->p_dev,
1103 "Interrupt Status block is NULL -"
1104 " cannot check for new interrupts!\n");
1106 u32 tmp_index = sb_info->sb_ack;
1107 rc = ecore_sb_update_sb_idx(sb_info);
1108 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR,
1109 "Interrupt indices: 0x%08x --> 0x%08x\n",
1110 tmp_index, sb_info->sb_ack);
1113 if (!sb_attn || !sb_attn->sb_attn) {
1114 DP_ERR(p_hwfn->p_dev,
1115 "Attentions Status block is NULL -"
1116 " cannot check for new attentions!\n");
1118 u16 tmp_index = sb_attn->index;
1120 rc |= ecore_attn_update_idx(p_hwfn, sb_attn);
1121 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR,
1122 "Attention indices: 0x%08x --> 0x%08x\n",
1123 tmp_index, sb_attn->index);
1126 /* Check if we expect interrupts at this time. if not just ack them */
1127 if (!(rc & ECORE_SB_EVENT_MASK)) {
1128 ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1132 /* Check the validity of the DPC ptt. If not ack interrupts and fail */
1134 if (!p_hwfn->p_dpc_ptt) {
1135 DP_NOTICE(p_hwfn->p_dev, true, "Failed to allocate PTT\n");
1136 ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1140 if (rc & ECORE_SB_ATT_IDX)
1141 ecore_int_attentions(p_hwfn);
1143 if (rc & ECORE_SB_IDX) {
1146 /* Since we only looked at the SB index, it's possible more
1147 * than a single protocol-index on the SB incremented.
1148 * Iterate over all configured protocol indices and check
1149 * whether something happened for each.
1151 for (pi = 0; pi < arr_size; pi++) {
1152 pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi];
1153 if (pi_info->comp_cb != OSAL_NULL)
1154 pi_info->comp_cb(p_hwfn, pi_info->cookie);
1158 if (sb_attn && (rc & ECORE_SB_ATT_IDX)) {
1159 /* This should be done before the interrupts are enabled,
1160 * since otherwise a new attention will be generated.
1162 ecore_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index);
1165 ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1168 static void ecore_int_sb_attn_free(struct ecore_hwfn *p_hwfn)
1170 struct ecore_sb_attn_info *p_sb = p_hwfn->p_sb_attn;
1175 if (p_sb->sb_attn) {
1176 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, p_sb->sb_attn,
1178 SB_ATTN_ALIGNED_SIZE(p_hwfn));
1180 OSAL_FREE(p_hwfn->p_dev, p_sb);
1183 static void ecore_int_sb_attn_setup(struct ecore_hwfn *p_hwfn,
1184 struct ecore_ptt *p_ptt)
1186 struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1188 OSAL_MEMSET(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn));
1191 sb_info->known_attn = 0;
1193 /* Configure Attention Status Block in IGU */
1194 ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,
1195 DMA_LO(p_hwfn->p_sb_attn->sb_phys));
1196 ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,
1197 DMA_HI(p_hwfn->p_sb_attn->sb_phys));
1200 static void ecore_int_sb_attn_init(struct ecore_hwfn *p_hwfn,
1201 struct ecore_ptt *p_ptt,
1202 void *sb_virt_addr, dma_addr_t sb_phy_addr)
1204 struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1207 sb_info->sb_attn = sb_virt_addr;
1208 sb_info->sb_phys = sb_phy_addr;
1210 /* Set the pointer to the AEU descriptors */
1211 sb_info->p_aeu_desc = aeu_descs;
1213 /* Calculate Parity Masks */
1214 OSAL_MEMSET(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS);
1215 for (i = 0; i < NUM_ATTN_REGS; i++) {
1216 /* j is array index, k is bit index */
1217 for (j = 0, k = 0; k < 32; j++) {
1218 unsigned int flags = aeu_descs[i].bits[j].flags;
1220 if (flags & ATTENTION_PARITY)
1221 sb_info->parity_mask[i] |= 1 << k;
1223 k += ATTENTION_LENGTH(flags);
1225 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1226 "Attn Mask [Reg %d]: 0x%08x\n",
1227 i, sb_info->parity_mask[i]);
1230 /* Set the address of cleanup for the mcp attention */
1231 sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) +
1232 MISC_REG_AEU_GENERAL_ATTN_0;
1234 ecore_int_sb_attn_setup(p_hwfn, p_ptt);
1237 static enum _ecore_status_t ecore_int_sb_attn_alloc(struct ecore_hwfn *p_hwfn,
1238 struct ecore_ptt *p_ptt)
1240 struct ecore_dev *p_dev = p_hwfn->p_dev;
1241 struct ecore_sb_attn_info *p_sb;
1242 dma_addr_t p_phys = 0;
1246 p_sb = OSAL_ALLOC(p_dev, GFP_KERNEL, sizeof(*p_sb));
1248 DP_NOTICE(p_dev, true,
1249 "Failed to allocate `struct ecore_sb_attn_info'\n");
1254 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
1255 SB_ATTN_ALIGNED_SIZE(p_hwfn));
1257 DP_NOTICE(p_dev, true,
1258 "Failed to allocate status block (attentions)\n");
1259 OSAL_FREE(p_dev, p_sb);
1263 /* Attention setup */
1264 p_hwfn->p_sb_attn = p_sb;
1265 ecore_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys);
1267 return ECORE_SUCCESS;
1270 /* coalescing timeout = timeset << (timer_res + 1) */
1271 #define ECORE_CAU_DEF_RX_USECS 24
1272 #define ECORE_CAU_DEF_TX_USECS 48
1274 void ecore_init_cau_sb_entry(struct ecore_hwfn *p_hwfn,
1275 struct cau_sb_entry *p_sb_entry,
1276 u8 pf_id, u16 vf_number, u8 vf_valid)
1278 struct ecore_dev *p_dev = p_hwfn->p_dev;
1282 OSAL_MEMSET(p_sb_entry, 0, sizeof(*p_sb_entry));
1284 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id);
1285 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number);
1286 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid);
1287 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F);
1288 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F);
1290 cau_state = CAU_HC_DISABLE_STATE;
1292 if (p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
1293 cau_state = CAU_HC_ENABLE_STATE;
1294 if (!p_dev->rx_coalesce_usecs)
1295 p_dev->rx_coalesce_usecs = ECORE_CAU_DEF_RX_USECS;
1296 if (!p_dev->tx_coalesce_usecs)
1297 p_dev->tx_coalesce_usecs = ECORE_CAU_DEF_TX_USECS;
1300 /* Coalesce = (timeset << timer-res), timeset is 7bit wide */
1301 if (p_dev->rx_coalesce_usecs <= 0x7F)
1303 else if (p_dev->rx_coalesce_usecs <= 0xFF)
1307 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
1309 if (p_dev->tx_coalesce_usecs <= 0x7F)
1311 else if (p_dev->tx_coalesce_usecs <= 0xFF)
1315 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
1317 SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state);
1318 SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
1321 void ecore_int_cau_conf_sb(struct ecore_hwfn *p_hwfn,
1322 struct ecore_ptt *p_ptt,
1323 dma_addr_t sb_phys, u16 igu_sb_id,
1324 u16 vf_number, u8 vf_valid)
1326 struct cau_sb_entry sb_entry;
1328 ecore_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id,
1329 vf_number, vf_valid);
1331 if (p_hwfn->hw_init_done) {
1332 /* Wide-bus, initialize via DMAE */
1333 u64 phys_addr = (u64)sb_phys;
1335 ecore_dmae_host2grc(p_hwfn, p_ptt,
1336 (u64)(osal_uintptr_t)&phys_addr,
1337 CAU_REG_SB_ADDR_MEMORY +
1338 igu_sb_id * sizeof(u64), 2, 0);
1339 ecore_dmae_host2grc(p_hwfn, p_ptt,
1340 (u64)(osal_uintptr_t)&sb_entry,
1341 CAU_REG_SB_VAR_MEMORY +
1342 igu_sb_id * sizeof(u64), 2, 0);
1344 /* Initialize Status Block Address */
1345 STORE_RT_REG_AGG(p_hwfn,
1346 CAU_REG_SB_ADDR_MEMORY_RT_OFFSET +
1347 igu_sb_id * 2, sb_phys);
1349 STORE_RT_REG_AGG(p_hwfn,
1350 CAU_REG_SB_VAR_MEMORY_RT_OFFSET +
1351 igu_sb_id * 2, sb_entry);
1354 /* Configure pi coalescing if set */
1355 if (p_hwfn->p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
1356 /* eth will open queues for all tcs, so configure all of them
1357 * properly, rather than just the active ones
1359 u8 num_tc = p_hwfn->hw_info.num_hw_tc;
1361 u8 timeset, timer_res;
1364 /* timeset = (coalesce >> timer-res), timeset is 7bit wide */
1365 if (p_hwfn->p_dev->rx_coalesce_usecs <= 0x7F)
1367 else if (p_hwfn->p_dev->rx_coalesce_usecs <= 0xFF)
1371 timeset = (u8)(p_hwfn->p_dev->rx_coalesce_usecs >> timer_res);
1372 ecore_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
1373 ECORE_COAL_RX_STATE_MACHINE, timeset);
1375 if (p_hwfn->p_dev->tx_coalesce_usecs <= 0x7F)
1377 else if (p_hwfn->p_dev->tx_coalesce_usecs <= 0xFF)
1381 timeset = (u8)(p_hwfn->p_dev->tx_coalesce_usecs >> timer_res);
1382 for (i = 0; i < num_tc; i++) {
1383 ecore_int_cau_conf_pi(p_hwfn, p_ptt,
1384 igu_sb_id, TX_PI(i),
1385 ECORE_COAL_TX_STATE_MACHINE,
1391 void ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
1392 struct ecore_ptt *p_ptt,
1393 u16 igu_sb_id, u32 pi_index,
1394 enum ecore_coalescing_fsm coalescing_fsm, u8 timeset)
1396 struct cau_pi_entry pi_entry;
1397 u32 sb_offset, pi_offset;
1399 if (IS_VF(p_hwfn->p_dev))
1400 return; /* @@@TBD MichalK- VF CAU... */
1402 sb_offset = igu_sb_id * PIS_PER_SB;
1403 OSAL_MEMSET(&pi_entry, 0, sizeof(struct cau_pi_entry));
1405 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
1406 if (coalescing_fsm == ECORE_COAL_RX_STATE_MACHINE)
1407 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0);
1409 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1);
1411 pi_offset = sb_offset + pi_index;
1412 if (p_hwfn->hw_init_done) {
1413 ecore_wr(p_hwfn, p_ptt,
1414 CAU_REG_PI_MEMORY + pi_offset * sizeof(u32),
1415 *((u32 *)&(pi_entry)));
1417 STORE_RT_REG(p_hwfn,
1418 CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
1419 *((u32 *)&(pi_entry)));
1423 void ecore_int_sb_setup(struct ecore_hwfn *p_hwfn,
1424 struct ecore_ptt *p_ptt, struct ecore_sb_info *sb_info)
1426 /* zero status block and ack counter */
1427 sb_info->sb_ack = 0;
1428 OSAL_MEMSET(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1430 if (IS_PF(p_hwfn->p_dev))
1431 ecore_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,
1432 sb_info->igu_sb_id, 0, 0);
1436 * @brief ecore_get_igu_sb_id - given a sw sb_id return the
1444 static u16 ecore_get_igu_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id)
1448 /* Assuming continuous set of IGU SBs dedicated for given PF */
1449 if (sb_id == ECORE_SP_SB_ID)
1450 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
1451 else if (IS_PF(p_hwfn->p_dev))
1452 igu_sb_id = sb_id + p_hwfn->hw_info.p_igu_info->igu_base_sb;
1454 igu_sb_id = ecore_vf_get_igu_sb_id(p_hwfn, sb_id);
1456 if (sb_id == ECORE_SP_SB_ID)
1457 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1458 "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id);
1460 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1461 "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id);
1466 enum _ecore_status_t ecore_int_sb_init(struct ecore_hwfn *p_hwfn,
1467 struct ecore_ptt *p_ptt,
1468 struct ecore_sb_info *sb_info,
1470 dma_addr_t sb_phy_addr, u16 sb_id)
1472 sb_info->sb_virt = sb_virt_addr;
1473 sb_info->sb_phys = sb_phy_addr;
1475 sb_info->igu_sb_id = ecore_get_igu_sb_id(p_hwfn, sb_id);
1477 if (sb_id != ECORE_SP_SB_ID) {
1478 p_hwfn->sbs_info[sb_id] = sb_info;
1481 #ifdef ECORE_CONFIG_DIRECT_HWFN
1482 sb_info->p_hwfn = p_hwfn;
1484 sb_info->p_dev = p_hwfn->p_dev;
1486 /* The igu address will hold the absolute address that needs to be
1487 * written to for a specific status block
1489 if (IS_PF(p_hwfn->p_dev)) {
1490 sb_info->igu_addr = (u8 OSAL_IOMEM *)p_hwfn->regview +
1491 GTT_BAR0_MAP_REG_IGU_CMD + (sb_info->igu_sb_id << 3);
1495 (u8 OSAL_IOMEM *)p_hwfn->regview +
1496 PXP_VF_BAR0_START_IGU +
1497 ((IGU_CMD_INT_ACK_BASE + sb_info->igu_sb_id) << 3);
1500 sb_info->flags |= ECORE_SB_INFO_INIT;
1502 ecore_int_sb_setup(p_hwfn, p_ptt, sb_info);
1504 return ECORE_SUCCESS;
1507 enum _ecore_status_t ecore_int_sb_release(struct ecore_hwfn *p_hwfn,
1508 struct ecore_sb_info *sb_info,
1511 if (sb_id == ECORE_SP_SB_ID) {
1512 DP_ERR(p_hwfn, "Do Not free sp sb using this function");
1516 /* zero status block and ack counter */
1517 sb_info->sb_ack = 0;
1518 OSAL_MEMSET(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1520 if (p_hwfn->sbs_info[sb_id] != OSAL_NULL) {
1521 p_hwfn->sbs_info[sb_id] = OSAL_NULL;
1525 return ECORE_SUCCESS;
1528 static void ecore_int_sp_sb_free(struct ecore_hwfn *p_hwfn)
1530 struct ecore_sb_sp_info *p_sb = p_hwfn->p_sp_sb;
1535 if (p_sb->sb_info.sb_virt) {
1536 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
1537 p_sb->sb_info.sb_virt,
1538 p_sb->sb_info.sb_phys,
1539 SB_ALIGNED_SIZE(p_hwfn));
1542 OSAL_FREE(p_hwfn->p_dev, p_sb);
1545 static enum _ecore_status_t ecore_int_sp_sb_alloc(struct ecore_hwfn *p_hwfn,
1546 struct ecore_ptt *p_ptt)
1548 struct ecore_sb_sp_info *p_sb;
1549 dma_addr_t p_phys = 0;
1554 OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL,
1557 DP_NOTICE(p_hwfn, true,
1558 "Failed to allocate `struct ecore_sb_info'\n");
1563 p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
1564 &p_phys, SB_ALIGNED_SIZE(p_hwfn));
1566 DP_NOTICE(p_hwfn, true, "Failed to allocate status block\n");
1567 OSAL_FREE(p_hwfn->p_dev, p_sb);
1571 /* Status Block setup */
1572 p_hwfn->p_sp_sb = p_sb;
1573 ecore_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info,
1574 p_virt, p_phys, ECORE_SP_SB_ID);
1576 OSAL_MEMSET(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr));
1578 return ECORE_SUCCESS;
1581 enum _ecore_status_t ecore_int_register_cb(struct ecore_hwfn *p_hwfn,
1582 ecore_int_comp_cb_t comp_cb,
1584 u8 *sb_idx, __le16 **p_fw_cons)
1586 struct ecore_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1587 enum _ecore_status_t rc = ECORE_NOMEM;
1590 /* Look for a free index */
1591 for (pi = 0; pi < OSAL_ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) {
1592 if (p_sp_sb->pi_info_arr[pi].comp_cb != OSAL_NULL)
1595 p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
1596 p_sp_sb->pi_info_arr[pi].cookie = cookie;
1598 *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi];
1606 enum _ecore_status_t ecore_int_unregister_cb(struct ecore_hwfn *p_hwfn, u8 pi)
1608 struct ecore_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1610 if (p_sp_sb->pi_info_arr[pi].comp_cb == OSAL_NULL)
1613 p_sp_sb->pi_info_arr[pi].comp_cb = OSAL_NULL;
1614 p_sp_sb->pi_info_arr[pi].cookie = OSAL_NULL;
1615 return ECORE_SUCCESS;
1618 u16 ecore_int_get_sp_sb_id(struct ecore_hwfn *p_hwfn)
1620 return p_hwfn->p_sp_sb->sb_info.igu_sb_id;
1623 void ecore_int_igu_enable_int(struct ecore_hwfn *p_hwfn,
1624 struct ecore_ptt *p_ptt,
1625 enum ecore_int_mode int_mode)
1627 u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN;
1630 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1631 DP_INFO(p_hwfn, "FPGA - don't enable ATTN generation in IGU\n");
1632 igu_pf_conf &= ~IGU_PF_CONF_ATTN_BIT_EN;
1636 p_hwfn->p_dev->int_mode = int_mode;
1637 switch (p_hwfn->p_dev->int_mode) {
1638 case ECORE_INT_MODE_INTA:
1639 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN;
1640 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1643 case ECORE_INT_MODE_MSI:
1644 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1645 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1648 case ECORE_INT_MODE_MSIX:
1649 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1651 case ECORE_INT_MODE_POLL:
1655 ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);
1658 static void ecore_int_igu_enable_attn(struct ecore_hwfn *p_hwfn,
1659 struct ecore_ptt *p_ptt)
1662 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1664 "FPGA - Don't enable Attentions in IGU and MISC\n");
1669 /* Configure AEU signal change to produce attentions */
1670 ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0);
1671 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);
1672 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);
1673 ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff);
1675 /* Flush the writes to IGU */
1676 OSAL_MMIOWB(p_hwfn->p_dev);
1678 /* Unmask AEU signals toward IGU */
1679 ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);
1682 enum _ecore_status_t
1683 ecore_int_igu_enable(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1684 enum ecore_int_mode int_mode)
1686 enum _ecore_status_t rc = ECORE_SUCCESS;
1689 /* @@@tmp - Starting with MFW 8.2.1.0 we've started hitting AVS stop
1690 * attentions. Since we're waiting for BRCM answer regarding this
1691 * attention, in the meanwhile we simply mask it.
1693 tmp = ecore_rd(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0);
1695 ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0, tmp);
1697 ecore_int_igu_enable_attn(p_hwfn, p_ptt);
1699 if ((int_mode != ECORE_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {
1700 rc = OSAL_SLOWPATH_IRQ_REQ(p_hwfn);
1701 if (rc != ECORE_SUCCESS) {
1702 DP_NOTICE(p_hwfn, true,
1703 "Slowpath IRQ request failed\n");
1704 return ECORE_NORESOURCES;
1706 p_hwfn->b_int_requested = true;
1709 /* Enable interrupt Generation */
1710 ecore_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
1712 p_hwfn->b_int_enabled = 1;
1717 void ecore_int_igu_disable_int(struct ecore_hwfn *p_hwfn,
1718 struct ecore_ptt *p_ptt)
1720 p_hwfn->b_int_enabled = 0;
1722 if (IS_VF(p_hwfn->p_dev))
1725 ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
1728 #define IGU_CLEANUP_SLEEP_LENGTH (1000)
1729 static void ecore_int_igu_cleanup_sb(struct ecore_hwfn *p_hwfn,
1730 struct ecore_ptt *p_ptt,
1731 u32 sb_id, bool cleanup_set, u16 opaque_fid)
1733 u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0;
1734 u32 pxp_addr = IGU_CMD_INT_ACK_BASE + sb_id;
1735 u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH;
1736 u8 type = 0; /* FIXME MichalS type??? */
1738 OSAL_BUILD_BUG_ON((IGU_REG_CLEANUP_STATUS_4 -
1739 IGU_REG_CLEANUP_STATUS_0) != 0x200);
1741 /* USE Control Command Register to perform cleanup. There is an
1742 * option to do this using IGU bar, but then it can't be used for VFs.
1745 /* Set the data field */
1746 SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0);
1747 SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, type);
1748 SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET);
1750 /* Set the control register */
1751 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr);
1752 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid);
1753 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR);
1755 ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);
1757 OSAL_BARRIER(p_hwfn->p_dev);
1759 ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);
1761 /* Flush the write to IGU */
1762 OSAL_MMIOWB(p_hwfn->p_dev);
1764 /* calculate where to read the status bit from */
1765 sb_bit = 1 << (sb_id % 32);
1766 sb_bit_addr = sb_id / 32 * sizeof(u32);
1768 sb_bit_addr += IGU_REG_CLEANUP_STATUS_0 + (0x80 * type);
1770 /* Now wait for the command to complete */
1771 while (--sleep_cnt) {
1772 val = ecore_rd(p_hwfn, p_ptt, sb_bit_addr);
1773 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0))
1779 DP_NOTICE(p_hwfn, true,
1780 "Timeout waiting for clear status 0x%08x [for sb %d]\n",
1784 void ecore_int_igu_init_pure_rt_single(struct ecore_hwfn *p_hwfn,
1785 struct ecore_ptt *p_ptt,
1786 u32 sb_id, u16 opaque, bool b_set)
1792 ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 1, opaque);
1795 ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 0, opaque);
1797 /* Wait for the IGU SB to cleanup */
1798 for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) {
1801 val = ecore_rd(p_hwfn, p_ptt,
1802 IGU_REG_WRITE_DONE_PENDING +
1803 ((sb_id / 32) * 4));
1804 if (val & (1 << (sb_id % 32)))
1809 if (i == IGU_CLEANUP_SLEEP_LENGTH)
1810 DP_NOTICE(p_hwfn, true,
1811 "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n",
1814 /* Clear the CAU for the SB */
1815 for (pi = 0; pi < 12; pi++)
1816 ecore_wr(p_hwfn, p_ptt,
1817 CAU_REG_PI_MEMORY + (sb_id * 12 + pi) * 4, 0);
1820 void ecore_int_igu_init_pure_rt(struct ecore_hwfn *p_hwfn,
1821 struct ecore_ptt *p_ptt,
1822 bool b_set, bool b_slowpath)
1824 u32 igu_base_sb = p_hwfn->hw_info.p_igu_info->igu_base_sb;
1825 u32 igu_sb_cnt = p_hwfn->hw_info.p_igu_info->igu_sb_cnt;
1826 u32 sb_id = 0, val = 0;
1828 /* @@@TBD MichalK temporary... should be moved to init-tool... */
1829 val = ecore_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
1830 val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN;
1831 val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN;
1832 ecore_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);
1835 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1836 "IGU cleaning SBs [%d,...,%d]\n",
1837 igu_base_sb, igu_base_sb + igu_sb_cnt - 1);
1839 for (sb_id = igu_base_sb; sb_id < igu_base_sb + igu_sb_cnt; sb_id++)
1840 ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id,
1841 p_hwfn->hw_info.opaque_fid,
1847 sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
1848 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1849 "IGU cleaning slowpath SB [%d]\n", sb_id);
1850 ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id,
1851 p_hwfn->hw_info.opaque_fid, b_set);
1854 static u32 ecore_int_igu_read_cam_block(struct ecore_hwfn *p_hwfn,
1855 struct ecore_ptt *p_ptt, u16 sb_id)
1857 u32 val = ecore_rd(p_hwfn, p_ptt,
1858 IGU_REG_MAPPING_MEMORY + sizeof(u32) * sb_id);
1859 struct ecore_igu_block *p_block;
1861 p_block = &p_hwfn->hw_info.p_igu_info->igu_map.igu_blocks[sb_id];
1863 /* stop scanning when hit first invalid PF entry */
1864 if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) &&
1865 GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID))
1868 /* Fill the block information */
1869 p_block->status = ECORE_IGU_STATUS_VALID;
1870 p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER);
1871 p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
1872 p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER);
1874 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1875 "IGU_BLOCK: [SB 0x%04x, Value in CAM 0x%08x] func_id = %d"
1876 " is_pf = %d vector_num = 0x%x\n",
1877 sb_id, val, p_block->function_id, p_block->is_pf,
1878 p_block->vector_number);
1884 enum _ecore_status_t ecore_int_igu_read_cam(struct ecore_hwfn *p_hwfn,
1885 struct ecore_ptt *p_ptt)
1887 struct ecore_igu_info *p_igu_info;
1888 struct ecore_igu_block *p_block;
1889 u32 min_vf = 0, max_vf = 0, val;
1890 u16 sb_id, last_iov_sb_id = 0;
1891 u16 prev_sb_id = 0xFF;
1893 p_hwfn->hw_info.p_igu_info = OSAL_ALLOC(p_hwfn->p_dev,
1895 sizeof(*p_igu_info));
1896 if (!p_hwfn->hw_info.p_igu_info)
1899 OSAL_MEMSET(p_hwfn->hw_info.p_igu_info, 0, sizeof(*p_igu_info));
1901 p_igu_info = p_hwfn->hw_info.p_igu_info;
1903 /* Initialize base sb / sb cnt for PFs and VFs */
1904 p_igu_info->igu_base_sb = 0xffff;
1905 p_igu_info->igu_sb_cnt = 0;
1906 p_igu_info->igu_dsb_id = 0xffff;
1907 p_igu_info->igu_base_sb_iov = 0xffff;
1909 if (p_hwfn->p_dev->p_iov_info) {
1910 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
1912 min_vf = p_iov->first_vf_in_pf;
1913 max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs;
1916 sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
1918 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
1919 val = ecore_int_igu_read_cam_block(p_hwfn, p_ptt, sb_id);
1920 if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) &&
1921 GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID))
1924 if (p_block->is_pf) {
1925 if (p_block->function_id == p_hwfn->rel_pf_id) {
1926 p_block->status |= ECORE_IGU_STATUS_PF;
1928 if (p_block->vector_number == 0) {
1929 if (p_igu_info->igu_dsb_id == 0xffff)
1930 p_igu_info->igu_dsb_id = sb_id;
1932 if (p_igu_info->igu_base_sb == 0xffff) {
1933 p_igu_info->igu_base_sb = sb_id;
1934 } else if (prev_sb_id != sb_id - 1) {
1935 DP_NOTICE(p_hwfn->p_dev, false,
1943 /* we don't count the default */
1944 (p_igu_info->igu_sb_cnt)++;
1948 if ((p_block->function_id >= min_vf) &&
1949 (p_block->function_id < max_vf)) {
1950 /* Available for VFs of this PF */
1951 if (p_igu_info->igu_base_sb_iov == 0xffff) {
1952 p_igu_info->igu_base_sb_iov = sb_id;
1953 } else if (last_iov_sb_id != sb_id - 1) {
1955 DP_VERBOSE(p_hwfn->p_dev,
1957 "First uninited IGU"
1962 DP_NOTICE(p_hwfn->p_dev, false,
1973 p_block->status |= ECORE_IGU_STATUS_FREE;
1974 p_hwfn->hw_info.p_igu_info->free_blks++;
1975 last_iov_sb_id = sb_id;
1980 /* There's a possibility the igu_sb_cnt_iov doesn't properly reflect
1981 * the number of VF SBs [especially for first VF on engine, as we can't
1982 * diffrentiate between empty entries and its entries].
1983 * Since we don't really support more SBs than VFs today, prevent any
1984 * such configuration by sanitizing the number of SBs to equal the
1987 if (IS_PF_SRIOV(p_hwfn)) {
1988 u16 total_vfs = p_hwfn->p_dev->p_iov_info->total_vfs;
1990 if (total_vfs < p_igu_info->free_blks) {
1991 DP_VERBOSE(p_hwfn, (ECORE_MSG_INTR | ECORE_MSG_IOV),
1992 "Limiting number of SBs for IOV - %04x --> %04x\n",
1993 p_igu_info->free_blks,
1994 p_hwfn->p_dev->p_iov_info->total_vfs);
1995 p_igu_info->free_blks = total_vfs;
1996 } else if (total_vfs > p_igu_info->free_blks) {
1997 DP_NOTICE(p_hwfn, true,
1998 "IGU has only %04x SBs for VFs while the device has %04x VFs\n",
1999 p_igu_info->free_blks, total_vfs);
2004 p_igu_info->igu_sb_cnt_iov = p_igu_info->free_blks;
2006 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2007 "IGU igu_base_sb=0x%x [IOV 0x%x] igu_sb_cnt=%d [IOV 0x%x] "
2008 "igu_dsb_id=0x%x\n",
2009 p_igu_info->igu_base_sb, p_igu_info->igu_base_sb_iov,
2010 p_igu_info->igu_sb_cnt, p_igu_info->igu_sb_cnt_iov,
2011 p_igu_info->igu_dsb_id);
2013 if (p_igu_info->igu_base_sb == 0xffff ||
2014 p_igu_info->igu_dsb_id == 0xffff || p_igu_info->igu_sb_cnt == 0) {
2015 DP_NOTICE(p_hwfn, true,
2016 "IGU CAM returned invalid values igu_base_sb=0x%x "
2017 "igu_sb_cnt=%d igu_dsb_id=0x%x\n",
2018 p_igu_info->igu_base_sb, p_igu_info->igu_sb_cnt,
2019 p_igu_info->igu_dsb_id);
2023 return ECORE_SUCCESS;
2027 * @brief Initialize igu runtime registers
2031 void ecore_int_igu_init_rt(struct ecore_hwfn *p_hwfn)
2033 u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN;
2035 STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);
2038 #define LSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - \
2039 IGU_CMD_INT_ACK_BASE)
2040 #define MSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - \
2041 IGU_CMD_INT_ACK_BASE)
2042 u64 ecore_int_igu_read_sisr_reg(struct ecore_hwfn *p_hwfn)
2044 u32 intr_status_hi = 0, intr_status_lo = 0;
2045 u64 intr_status = 0;
2047 intr_status_lo = REG_RD(p_hwfn,
2048 GTT_BAR0_MAP_REG_IGU_CMD +
2049 LSB_IGU_CMD_ADDR * 8);
2050 intr_status_hi = REG_RD(p_hwfn,
2051 GTT_BAR0_MAP_REG_IGU_CMD +
2052 MSB_IGU_CMD_ADDR * 8);
2053 intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo;
2058 static void ecore_int_sp_dpc_setup(struct ecore_hwfn *p_hwfn)
2060 OSAL_DPC_INIT(p_hwfn->sp_dpc, p_hwfn);
2061 p_hwfn->b_sp_dpc_enabled = true;
2064 static enum _ecore_status_t ecore_int_sp_dpc_alloc(struct ecore_hwfn *p_hwfn)
2066 p_hwfn->sp_dpc = OSAL_DPC_ALLOC(p_hwfn);
2067 if (!p_hwfn->sp_dpc)
2070 return ECORE_SUCCESS;
2073 static void ecore_int_sp_dpc_free(struct ecore_hwfn *p_hwfn)
2075 OSAL_FREE(p_hwfn->p_dev, p_hwfn->sp_dpc);
2078 enum _ecore_status_t ecore_int_alloc(struct ecore_hwfn *p_hwfn,
2079 struct ecore_ptt *p_ptt)
2081 enum _ecore_status_t rc = ECORE_SUCCESS;
2083 rc = ecore_int_sp_dpc_alloc(p_hwfn);
2084 if (rc != ECORE_SUCCESS) {
2085 DP_ERR(p_hwfn->p_dev, "Failed to allocate sp dpc mem\n");
2089 rc = ecore_int_sp_sb_alloc(p_hwfn, p_ptt);
2090 if (rc != ECORE_SUCCESS) {
2091 DP_ERR(p_hwfn->p_dev, "Failed to allocate sp sb mem\n");
2095 rc = ecore_int_sb_attn_alloc(p_hwfn, p_ptt);
2096 if (rc != ECORE_SUCCESS)
2097 DP_ERR(p_hwfn->p_dev, "Failed to allocate sb attn mem\n");
2102 void ecore_int_free(struct ecore_hwfn *p_hwfn)
2104 ecore_int_sp_sb_free(p_hwfn);
2105 ecore_int_sb_attn_free(p_hwfn);
2106 ecore_int_sp_dpc_free(p_hwfn);
2109 void ecore_int_setup(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
2111 if (!p_hwfn || !p_hwfn->p_sp_sb || !p_hwfn->p_sb_attn)
2114 ecore_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);
2115 ecore_int_sb_attn_setup(p_hwfn, p_ptt);
2116 ecore_int_sp_dpc_setup(p_hwfn);
2119 void ecore_int_get_num_sbs(struct ecore_hwfn *p_hwfn,
2120 struct ecore_sb_cnt_info *p_sb_cnt_info)
2122 struct ecore_igu_info *info = p_hwfn->hw_info.p_igu_info;
2124 if (!info || !p_sb_cnt_info)
2127 p_sb_cnt_info->sb_cnt = info->igu_sb_cnt;
2128 p_sb_cnt_info->sb_iov_cnt = info->igu_sb_cnt_iov;
2129 p_sb_cnt_info->sb_free_blk = info->free_blks;
2132 u16 ecore_int_queue_id_from_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id)
2134 struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2136 /* Determine origin of SB id */
2137 if ((sb_id >= p_info->igu_base_sb) &&
2138 (sb_id < p_info->igu_base_sb + p_info->igu_sb_cnt)) {
2139 return sb_id - p_info->igu_base_sb;
2140 } else if ((sb_id >= p_info->igu_base_sb_iov) &&
2141 (sb_id < p_info->igu_base_sb_iov +
2142 p_info->igu_sb_cnt_iov)) {
2143 /* We want the first VF queue to be adjacent to the
2144 * last PF queue. Since L2 queues can be partial to
2145 * SBs, we'll use the feature instead.
2147 return sb_id - p_info->igu_base_sb_iov +
2148 FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE);
2150 DP_NOTICE(p_hwfn, true, "SB %d not in range for function\n",
2156 void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev)
2160 for_each_hwfn(p_dev, i)
2161 p_dev->hwfns[i].b_int_requested = false;
2164 void ecore_int_attn_clr_enable(struct ecore_dev *p_dev, bool clr_enable)
2166 p_dev->attn_clr_en = clr_enable;
2169 enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,
2170 struct ecore_ptt *p_ptt,
2171 u8 timer_res, u16 sb_id, bool tx)
2173 struct cau_sb_entry sb_entry;
2174 enum _ecore_status_t rc;
2176 if (!p_hwfn->hw_init_done) {
2177 DP_ERR(p_hwfn, "hardware not initialized yet\n");
2181 rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2182 sb_id * sizeof(u64),
2183 (u64)(osal_uintptr_t)&sb_entry, 2, 0);
2184 if (rc != ECORE_SUCCESS) {
2185 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2190 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
2192 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
2194 rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
2195 (u64)(osal_uintptr_t)&sb_entry,
2196 CAU_REG_SB_VAR_MEMORY +
2197 sb_id * sizeof(u64), 2, 0);
2198 if (rc != ECORE_SUCCESS) {
2199 DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc);