1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
7 #ifndef __ECORE_INT_API_H__
8 #define __ECORE_INT_API_H__
10 #ifndef __EXTRACT__LINUX__
11 #define ECORE_SB_IDX 0x0002
14 #define TX_PI(tc) (RX_PI + 1 + tc)
16 #ifndef ECORE_INT_MODE
17 #define ECORE_INT_MODE
26 struct ecore_sb_info {
27 struct status_block *sb_virt;
29 u32 sb_ack; /* Last given ack */
31 void OSAL_IOMEM *igu_addr;
33 #define ECORE_SB_INFO_INIT 0x1
34 #define ECORE_SB_INFO_SETUP 0x2
36 #ifdef ECORE_CONFIG_DIRECT_HWFN
37 struct ecore_hwfn *p_hwfn;
39 struct ecore_dev *p_dev;
42 struct ecore_sb_info_dbg {
45 u16 pi[MAX_PIS_PER_SB];
48 struct ecore_sb_cnt_info {
49 /* Original, current, and free SBs for PF */
54 /* Original, current and free SBS for child VFs */
60 static OSAL_INLINE u16 ecore_sb_update_sb_idx(struct ecore_sb_info *sb_info)
65 /* barrier(); status block is written to by the chip */
66 /* FIXME: need some sort of barrier. */
67 prod = OSAL_LE32_TO_CPU(sb_info->sb_virt->prod_index) &
68 STATUS_BLOCK_PROD_INDEX_MASK;
69 if (sb_info->sb_ack != prod) {
70 sb_info->sb_ack = prod;
74 OSAL_MMIOWB(sb_info->p_dev);
80 * @brief This function creates an update command for interrupts that is
83 * @param sb_info - This is the structure allocated and
84 * initialized per status block. Assumption is
85 * that it was initialized using ecore_sb_init
86 * @param int_cmd - Enable/Disable/Nop
87 * @param upd_flg - whether igu consumer should be
90 * @return OSAL_INLINE void
92 static OSAL_INLINE void ecore_sb_ack(struct ecore_sb_info *sb_info,
93 enum igu_int_cmd int_cmd, u8 upd_flg)
95 struct igu_prod_cons_update igu_ack;
97 OSAL_MEMSET(&igu_ack, 0, sizeof(struct igu_prod_cons_update));
98 igu_ack.sb_id_and_flags =
99 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
100 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
101 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
102 (IGU_SEG_ACCESS_REG << IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
104 #ifdef ECORE_CONFIG_DIRECT_HWFN
105 DIRECT_REG_WR(sb_info->p_hwfn, sb_info->igu_addr,
106 igu_ack.sb_id_and_flags);
108 DIRECT_REG_WR(OSAL_NULL, sb_info->igu_addr, igu_ack.sb_id_and_flags);
110 /* Both segments (interrupts & acks) are written to same place address;
111 * Need to guarantee all commands will be received (in-order) by HW.
113 OSAL_MMIOWB(sb_info->p_dev);
114 OSAL_BARRIER(sb_info->p_dev);
117 #ifdef ECORE_CONFIG_DIRECT_HWFN
118 static OSAL_INLINE void __internal_ram_wr(struct ecore_hwfn *p_hwfn,
119 void OSAL_IOMEM *addr,
122 static OSAL_INLINE void __internal_ram_wr(__rte_unused void *p_hwfn,
123 void OSAL_IOMEM *addr,
129 for (i = 0; i < size / sizeof(*data); i++)
130 DIRECT_REG_WR(p_hwfn, &((u32 OSAL_IOMEM *)addr)[i], data[i]);
133 #ifdef ECORE_CONFIG_DIRECT_HWFN
134 static OSAL_INLINE void __internal_ram_wr_relaxed(struct ecore_hwfn *p_hwfn,
135 void OSAL_IOMEM * addr,
138 static OSAL_INLINE void __internal_ram_wr_relaxed(__rte_unused void *p_hwfn,
139 void OSAL_IOMEM * addr,
145 for (i = 0; i < size / sizeof(*data); i++)
146 DIRECT_REG_WR_RELAXED(p_hwfn, &((u32 OSAL_IOMEM *)addr)[i],
150 #ifdef ECORE_CONFIG_DIRECT_HWFN
151 static OSAL_INLINE void internal_ram_wr(struct ecore_hwfn *p_hwfn,
152 void OSAL_IOMEM * addr,
155 __internal_ram_wr_relaxed(p_hwfn, addr, size, data);
158 static OSAL_INLINE void internal_ram_wr(void OSAL_IOMEM *addr,
161 __internal_ram_wr_relaxed(OSAL_NULL, addr, size, data);
170 enum ecore_coalescing_fsm {
171 ECORE_COAL_RX_STATE_MACHINE,
172 ECORE_COAL_TX_STATE_MACHINE
176 * @brief ecore_int_cau_conf_pi - configure cau for a given
186 void ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
187 struct ecore_ptt *p_ptt,
188 struct ecore_sb_info *p_sb,
190 enum ecore_coalescing_fsm coalescing_fsm,
195 * @brief ecore_int_igu_enable_int - enable device interrupts
199 * @param int_mode - interrupt mode to use
201 void ecore_int_igu_enable_int(struct ecore_hwfn *p_hwfn,
202 struct ecore_ptt *p_ptt,
203 enum ecore_int_mode int_mode);
207 * @brief ecore_int_igu_disable_int - disable device interrupts
212 void ecore_int_igu_disable_int(struct ecore_hwfn *p_hwfn,
213 struct ecore_ptt *p_ptt);
217 * @brief ecore_int_igu_read_sisr_reg - Reads the single isr multiple dpc
224 u64 ecore_int_igu_read_sisr_reg(struct ecore_hwfn *p_hwfn);
226 #define ECORE_SP_SB_ID 0xffff
229 * @brief ecore_int_sb_init - Initializes the sb_info structure.
231 * once the structure is initialized it can be passed to sb related functions.
235 * @param sb_info points to an uninitialized (but
236 * allocated) sb_info structure
237 * @param sb_virt_addr
239 * @param sb_id the sb_id to be used (zero based in driver)
240 * should use ECORE_SP_SB_ID for SP Status block
242 * @return enum _ecore_status_t
244 enum _ecore_status_t ecore_int_sb_init(struct ecore_hwfn *p_hwfn,
245 struct ecore_ptt *p_ptt,
246 struct ecore_sb_info *sb_info,
248 dma_addr_t sb_phy_addr, u16 sb_id);
250 * @brief ecore_int_sb_setup - Setup the sb.
254 * @param sb_info initialized sb_info structure
256 void ecore_int_sb_setup(struct ecore_hwfn *p_hwfn,
257 struct ecore_ptt *p_ptt, struct ecore_sb_info *sb_info);
260 * @brief ecore_int_sb_release - releases the sb_info structure.
262 * once the structure is released, it's memory can be freed
265 * @param sb_info points to an allocated sb_info structure
266 * @param sb_id the sb_id to be used (zero based in driver)
267 * should never be equal to ECORE_SP_SB_ID
270 * @return enum _ecore_status_t
272 enum _ecore_status_t ecore_int_sb_release(struct ecore_hwfn *p_hwfn,
273 struct ecore_sb_info *sb_info,
277 * @brief ecore_int_sp_dpc - To be called when an interrupt is received on the
278 * default status block.
280 * @param p_hwfn - pointer to hwfn
283 void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie);
286 * @brief ecore_int_get_num_sbs - get the number of status
287 * blocks configured for this funciton in the igu.
290 * @param p_sb_cnt_info
294 void ecore_int_get_num_sbs(struct ecore_hwfn *p_hwfn,
295 struct ecore_sb_cnt_info *p_sb_cnt_info);
298 * @brief ecore_int_disable_post_isr_release - performs the cleanup post ISR
299 * release. The API need to be called after releasing all slowpath IRQs
305 void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev);
308 * @brief ecore_int_attn_clr_enable - sets whether the general behavior is
309 * preventing attentions from being reasserted, or following the
310 * attributes of the specific attention.
316 void ecore_int_attn_clr_enable(struct ecore_dev *p_dev, bool clr_enable);
319 * @brief Read debug information regarding a given SB.
323 * @param p_sb - point to Status block for which we want to get info.
324 * @param p_info - pointer to struct to fill with information regarding SB.
326 * @return ECORE_SUCCESS if pointer is filled; failure otherwise.
328 enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,
329 struct ecore_ptt *p_ptt,
330 struct ecore_sb_info *p_sb,
331 struct ecore_sb_info_dbg *p_info);
334 * @brief - Move a free Status block between PF and child VF
338 * @param sb_id - The PF fastpath vector to be moved [re-assigned if claiming
339 * from VF, given-up if moving to VF]
340 * @param b_to_vf - PF->VF == true, VF->PF == false
342 * @return ECORE_SUCCESS if SB successfully moved.
345 ecore_int_igu_relocate_sb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
346 u16 sb_id, bool b_to_vf);
349 * @brief - Doorbell Recovery handler.
350 * Run DB_REAL_DEAL doorbell recovery in case of PF overflow
351 * (and flush DORQ if needed), otherwise run DB_REC_ONCE.
356 enum _ecore_status_t ecore_db_rec_handler(struct ecore_hwfn *p_hwfn,
357 struct ecore_ptt *p_ptt);