2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #ifndef __ECORE_INT_API_H__
10 #define __ECORE_INT_API_H__
12 #ifndef __EXTRACT__LINUX__
13 #define ECORE_SB_IDX 0x0002
16 #define TX_PI(tc) (RX_PI + 1 + tc)
18 #ifndef ECORE_INT_MODE
19 #define ECORE_INT_MODE
28 struct ecore_sb_info {
29 struct status_block *sb_virt;
31 u32 sb_ack; /* Last given ack */
33 void OSAL_IOMEM *igu_addr;
35 #define ECORE_SB_INFO_INIT 0x1
36 #define ECORE_SB_INFO_SETUP 0x2
38 #ifdef ECORE_CONFIG_DIRECT_HWFN
39 struct ecore_hwfn *p_hwfn;
41 struct ecore_dev *p_dev;
44 struct ecore_sb_info_dbg {
50 struct ecore_sb_cnt_info {
51 /* Original, current, and free SBs for PF */
56 /* Original, current and free SBS for child VFs */
62 static OSAL_INLINE u16 ecore_sb_update_sb_idx(struct ecore_sb_info *sb_info)
67 /* barrier(); status block is written to by the chip */
68 /* FIXME: need some sort of barrier. */
69 prod = OSAL_LE32_TO_CPU(sb_info->sb_virt->prod_index) &
70 STATUS_BLOCK_PROD_INDEX_MASK;
71 if (sb_info->sb_ack != prod) {
72 sb_info->sb_ack = prod;
76 OSAL_MMIOWB(sb_info->p_dev);
82 * @brief This function creates an update command for interrupts that is
85 * @param sb_info - This is the structure allocated and
86 * initialized per status block. Assumption is
87 * that it was initialized using ecore_sb_init
88 * @param int_cmd - Enable/Disable/Nop
89 * @param upd_flg - whether igu consumer should be
92 * @return OSAL_INLINE void
94 static OSAL_INLINE void ecore_sb_ack(struct ecore_sb_info *sb_info,
95 enum igu_int_cmd int_cmd, u8 upd_flg)
97 struct igu_prod_cons_update igu_ack = { 0 };
99 igu_ack.sb_id_and_flags =
100 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
101 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
102 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
103 (IGU_SEG_ACCESS_REG << IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
105 #ifdef ECORE_CONFIG_DIRECT_HWFN
106 DIRECT_REG_WR(sb_info->p_hwfn, sb_info->igu_addr,
107 igu_ack.sb_id_and_flags);
109 DIRECT_REG_WR(OSAL_NULL, sb_info->igu_addr, igu_ack.sb_id_and_flags);
111 /* Both segments (interrupts & acks) are written to same place address;
112 * Need to guarantee all commands will be received (in-order) by HW.
114 OSAL_MMIOWB(sb_info->p_dev);
115 OSAL_BARRIER(sb_info->p_dev);
118 #ifdef ECORE_CONFIG_DIRECT_HWFN
119 static OSAL_INLINE void __internal_ram_wr(struct ecore_hwfn *p_hwfn,
120 void OSAL_IOMEM *addr,
123 static OSAL_INLINE void __internal_ram_wr(__rte_unused void *p_hwfn,
124 void OSAL_IOMEM *addr,
130 for (i = 0; i < size / sizeof(*data); i++)
131 DIRECT_REG_WR(p_hwfn, &((u32 OSAL_IOMEM *)addr)[i], data[i]);
134 #ifdef ECORE_CONFIG_DIRECT_HWFN
135 static OSAL_INLINE void __internal_ram_wr_relaxed(struct ecore_hwfn *p_hwfn,
136 void OSAL_IOMEM * addr,
139 static OSAL_INLINE void __internal_ram_wr_relaxed(__rte_unused void *p_hwfn,
140 void OSAL_IOMEM * addr,
146 for (i = 0; i < size / sizeof(*data); i++)
147 DIRECT_REG_WR_RELAXED(p_hwfn, &((u32 OSAL_IOMEM *)addr)[i],
151 #ifdef ECORE_CONFIG_DIRECT_HWFN
152 static OSAL_INLINE void internal_ram_wr(struct ecore_hwfn *p_hwfn,
153 void OSAL_IOMEM * addr,
156 __internal_ram_wr_relaxed(p_hwfn, addr, size, data);
159 static OSAL_INLINE void internal_ram_wr(void OSAL_IOMEM *addr,
162 __internal_ram_wr_relaxed(OSAL_NULL, addr, size, data);
171 enum ecore_coalescing_fsm {
172 ECORE_COAL_RX_STATE_MACHINE,
173 ECORE_COAL_TX_STATE_MACHINE
177 * @brief ecore_int_cau_conf_pi - configure cau for a given
187 void ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
188 struct ecore_ptt *p_ptt,
189 struct ecore_sb_info *p_sb,
191 enum ecore_coalescing_fsm coalescing_fsm,
196 * @brief ecore_int_igu_enable_int - enable device interrupts
200 * @param int_mode - interrupt mode to use
202 void ecore_int_igu_enable_int(struct ecore_hwfn *p_hwfn,
203 struct ecore_ptt *p_ptt,
204 enum ecore_int_mode int_mode);
208 * @brief ecore_int_igu_disable_int - disable device interrupts
213 void ecore_int_igu_disable_int(struct ecore_hwfn *p_hwfn,
214 struct ecore_ptt *p_ptt);
218 * @brief ecore_int_igu_read_sisr_reg - Reads the single isr multiple dpc
225 u64 ecore_int_igu_read_sisr_reg(struct ecore_hwfn *p_hwfn);
227 #define ECORE_SP_SB_ID 0xffff
230 * @brief ecore_int_sb_init - Initializes the sb_info structure.
232 * once the structure is initialized it can be passed to sb related functions.
236 * @param sb_info points to an uninitialized (but
237 * allocated) sb_info structure
238 * @param sb_virt_addr
240 * @param sb_id the sb_id to be used (zero based in driver)
241 * should use ECORE_SP_SB_ID for SP Status block
243 * @return enum _ecore_status_t
245 enum _ecore_status_t ecore_int_sb_init(struct ecore_hwfn *p_hwfn,
246 struct ecore_ptt *p_ptt,
247 struct ecore_sb_info *sb_info,
249 dma_addr_t sb_phy_addr, u16 sb_id);
251 * @brief ecore_int_sb_setup - Setup the sb.
255 * @param sb_info initialized sb_info structure
257 void ecore_int_sb_setup(struct ecore_hwfn *p_hwfn,
258 struct ecore_ptt *p_ptt, struct ecore_sb_info *sb_info);
261 * @brief ecore_int_sb_release - releases the sb_info structure.
263 * once the structure is released, it's memory can be freed
266 * @param sb_info points to an allocated sb_info structure
267 * @param sb_id the sb_id to be used (zero based in driver)
268 * should never be equal to ECORE_SP_SB_ID
271 * @return enum _ecore_status_t
273 enum _ecore_status_t ecore_int_sb_release(struct ecore_hwfn *p_hwfn,
274 struct ecore_sb_info *sb_info,
278 * @brief ecore_int_sp_dpc - To be called when an interrupt is received on the
279 * default status block.
281 * @param p_hwfn - pointer to hwfn
284 void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie);
287 * @brief ecore_int_get_num_sbs - get the number of status
288 * blocks configured for this funciton in the igu.
291 * @param p_sb_cnt_info
295 void ecore_int_get_num_sbs(struct ecore_hwfn *p_hwfn,
296 struct ecore_sb_cnt_info *p_sb_cnt_info);
299 * @brief ecore_int_disable_post_isr_release - performs the cleanup post ISR
300 * release. The API need to be called after releasing all slowpath IRQs
306 void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev);
309 * @brief ecore_int_attn_clr_enable - sets whether the general behavior is
310 * preventing attentions from being reasserted, or following the
311 * attributes of the specific attention.
317 void ecore_int_attn_clr_enable(struct ecore_dev *p_dev, bool clr_enable);
320 * @brief Read debug information regarding a given SB.
324 * @param p_sb - point to Status block for which we want to get info.
325 * @param p_info - pointer to struct to fill with information regarding SB.
327 * @return ECORE_SUCCESS if pointer is filled; failure otherwise.
329 enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,
330 struct ecore_ptt *p_ptt,
331 struct ecore_sb_info *p_sb,
332 struct ecore_sb_info_dbg *p_info);
335 * @brief - Move a free Status block between PF and child VF
339 * @param sb_id - The PF fastpath vector to be moved [re-assigned if claiming
340 * from VF, given-up if moving to VF]
341 * @param b_to_vf - PF->VF == true, VF->PF == false
343 * @return ECORE_SUCCESS if SB successfully moved.
346 ecore_int_igu_relocate_sb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
347 u16 sb_id, bool b_to_vf);