drivers/net/qede/base/ecore_l2.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10
  11 #include "ecore.h"
  12 #include "ecore_status.h"
  13 #include "ecore_hsi_eth.h"
  14 #include "ecore_chain.h"
  15 #include "ecore_spq.h"
  16 #include "ecore_init_fw_funcs.h"
  17 #include "ecore_cxt.h"
  18 #include "ecore_l2.h"
  19 #include "ecore_sp_commands.h"
  20 #include "ecore_gtt_reg_addr.h"
  21 #include "ecore_iro.h"
  22 #include "reg_addr.h"
  23 #include "ecore_int.h"
  24 #include "ecore_hw.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_sriov.h"
  27 #include "ecore_mcp.h"
  28
  29 #define ECORE_MAX_SGES_NUM 16
  30 #define CRC32_POLY 0x1edc6f41
  31
  32 enum _ecore_status_t
  33 ecore_sp_eth_vport_start(struct ecore_hwfn *p_hwfn,
  34                          struct ecore_sp_vport_start_params *p_params)
  35 {
  36         struct vport_start_ramrod_data *p_ramrod = OSAL_NULL;
  37         struct ecore_spq_entry *p_ent = OSAL_NULL;
  38         struct ecore_sp_init_data init_data;
  39         u16 rx_mode = 0, tx_err = 0;
  40         u8 abs_vport_id = 0;
  41         enum _ecore_status_t rc = ECORE_NOTIMPL;
  42
  43         rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
  44         if (rc != ECORE_SUCCESS)
  45                 return rc;
  46
  47         /* Get SPQ entry */
  48         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
  49         init_data.cid = ecore_spq_get_cid(p_hwfn);
  50         init_data.opaque_fid = p_params->opaque_fid;
  51         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
  52
  53         rc = ecore_sp_init_request(p_hwfn, &p_ent,
  54                                    ETH_RAMROD_VPORT_START,
  55                                    PROTOCOLID_ETH, &init_data);
  56         if (rc != ECORE_SUCCESS)
  57                 return rc;
  58
  59         p_ramrod = &p_ent->ramrod.vport_start;
  60         p_ramrod->vport_id = abs_vport_id;
  61
  62         p_ramrod->mtu = OSAL_CPU_TO_LE16(p_params->mtu);
  63         p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
  64         p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts;
  65         p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
  66         p_ramrod->untagged = p_params->only_untagged;
  67         p_ramrod->zero_placement_offset = p_params->zero_placement_offset;
  68
  69         SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
  70         SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
  71
  72         p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(rx_mode);
  73
  74         /* Handle requests for strict behavior on transmission errors */
  75         SET_FIELD(tx_err, ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE,
  76                   p_params->b_err_illegal_vlan_mode ?
  77                   ETH_TX_ERR_ASSERT_MALICIOUS : 0);
  78         SET_FIELD(tx_err, ETH_TX_ERR_VALS_PACKET_TOO_SMALL,
  79                   p_params->b_err_small_pkt ?
  80                   ETH_TX_ERR_ASSERT_MALICIOUS : 0);
  81         SET_FIELD(tx_err, ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR,
  82                   p_params->b_err_anti_spoof ?
  83                   ETH_TX_ERR_ASSERT_MALICIOUS : 0);
  84         SET_FIELD(tx_err, ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS,
  85                   p_params->b_err_illegal_inband_mode ?
  86                   ETH_TX_ERR_ASSERT_MALICIOUS : 0);
  87         SET_FIELD(tx_err, ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG,
  88                   p_params->b_err_vlan_insert_with_inband ?
  89                   ETH_TX_ERR_ASSERT_MALICIOUS : 0);
  90         SET_FIELD(tx_err, ETH_TX_ERR_VALS_MTU_VIOLATION,
  91                   p_params->b_err_big_pkt ?
  92                   ETH_TX_ERR_ASSERT_MALICIOUS : 0);
  93         SET_FIELD(tx_err, ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME,
  94                   p_params->b_err_ctrl_frame ?
  95                   ETH_TX_ERR_ASSERT_MALICIOUS : 0);
  96         p_ramrod->tx_err_behav.values = OSAL_CPU_TO_LE16(tx_err);
  97
  98         /* TPA related fields */
  99         OSAL_MEMSET(&p_ramrod->tpa_param, 0,
 100                     sizeof(struct eth_vport_tpa_param));
 101         p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
 102
 103         switch (p_params->tpa_mode) {
 104         case ECORE_TPA_MODE_GRO:
 105                 p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 106                 p_ramrod->tpa_param.tpa_max_size = (u16)-1;
 107                 p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
 108                 p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
 109                 p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
 110                 p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
 111                 p_ramrod->tpa_param.tpa_ipv4_tunn_en_flg = 1;
 112                 p_ramrod->tpa_param.tpa_ipv6_tunn_en_flg = 1;
 113                 p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
 114                 p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
 115                 break;
 116         default:
 117                 break;
 118         }
 119
 120         p_ramrod->tx_switching_en = p_params->tx_switching;
 121 #ifndef ASIC_ONLY
 122         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
 123                 p_ramrod->tx_switching_en = 0;
 124 #endif
 125
 126         p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac;
 127         p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype;
 128
 129         /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
 130         p_ramrod->sw_fid = ecore_concrete_to_sw_fid(p_hwfn->p_dev,
 131                                                     p_params->concrete_fid);
 132
 133         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 134 }
 135
 136 enum _ecore_status_t
 137 ecore_sp_vport_start(struct ecore_hwfn *p_hwfn,
 138                      struct ecore_sp_vport_start_params *p_params)
 139 {
 140         if (IS_VF(p_hwfn->p_dev))
 141                 return ecore_vf_pf_vport_start(p_hwfn, p_params->vport_id,
 142                                                p_params->mtu,
 143                                                p_params->remove_inner_vlan,
 144                                                p_params->tpa_mode,
 145                                                p_params->max_buffers_per_cqe,
 146                                                p_params->only_untagged);
 147
 148         return ecore_sp_eth_vport_start(p_hwfn, p_params);
 149 }
 150
 151 static enum _ecore_status_t
 152 ecore_sp_vport_update_rss(struct ecore_hwfn *p_hwfn,
 153                           struct vport_update_ramrod_data *p_ramrod,
 154                           struct ecore_rss_params *p_rss)
 155 {
 156         enum _ecore_status_t rc = ECORE_SUCCESS;
 157         struct eth_vport_rss_config *p_config;
 158         u16 abs_l2_queue = 0;
 159         int i;
 160
 161         if (!p_rss) {
 162                 p_ramrod->common.update_rss_flg = 0;
 163                 return rc;
 164         }
 165         p_config = &p_ramrod->rss_config;
 166
 167         OSAL_BUILD_BUG_ON(ECORE_RSS_IND_TABLE_SIZE !=
 168                           ETH_RSS_IND_TABLE_ENTRIES_NUM);
 169
 170         rc = ecore_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
 171         if (rc != ECORE_SUCCESS)
 172                 return rc;
 173
 174         p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
 175         p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
 176         p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
 177         p_config->update_rss_key = p_rss->update_rss_key;
 178
 179         p_config->rss_mode = p_rss->rss_enable ?
 180             ETH_VPORT_RSS_MODE_REGULAR : ETH_VPORT_RSS_MODE_DISABLED;
 181
 182         p_config->capabilities = 0;
 183
 184         SET_FIELD(p_config->capabilities,
 185                   ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
 186                   !!(p_rss->rss_caps & ECORE_RSS_IPV4));
 187         SET_FIELD(p_config->capabilities,
 188                   ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
 189                   !!(p_rss->rss_caps & ECORE_RSS_IPV6));
 190         SET_FIELD(p_config->capabilities,
 191                   ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
 192                   !!(p_rss->rss_caps & ECORE_RSS_IPV4_TCP));
 193         SET_FIELD(p_config->capabilities,
 194                   ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
 195                   !!(p_rss->rss_caps & ECORE_RSS_IPV6_TCP));
 196         SET_FIELD(p_config->capabilities,
 197                   ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
 198                   !!(p_rss->rss_caps & ECORE_RSS_IPV4_UDP));
 199         SET_FIELD(p_config->capabilities,
 200                   ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
 201                   !!(p_rss->rss_caps & ECORE_RSS_IPV6_UDP));
 202         p_config->tbl_size = p_rss->rss_table_size_log;
 203         p_config->capabilities = OSAL_CPU_TO_LE16(p_config->capabilities);
 204
 205         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
 206                    "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
 207                    p_ramrod->common.update_rss_flg,
 208                    p_config->rss_mode,
 209                    p_config->update_rss_capabilities,
 210                    p_config->capabilities,
 211                    p_config->update_rss_ind_table, p_config->update_rss_key);
 212
 213         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
 214                 rc = ecore_fw_l2_queue(p_hwfn,
 215                                        (u8)p_rss->rss_ind_table[i],
 216                                        &abs_l2_queue);
 217                 if (rc != ECORE_SUCCESS)
 218                         return rc;
 219
 220                 p_config->indirection_table[i] = OSAL_CPU_TO_LE16(abs_l2_queue);
 221                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP, "i= %d, queue = %d\n",
 222                            i, p_config->indirection_table[i]);
 223         }
 224
 225         for (i = 0; i < 10; i++)
 226                 p_config->rss_key[i] = OSAL_CPU_TO_LE32(p_rss->rss_key[i]);
 227
 228         return rc;
 229 }
 230
 231 static void
 232 ecore_sp_update_accept_mode(struct ecore_hwfn *p_hwfn,
 233                             struct vport_update_ramrod_data *p_ramrod,
 234                             struct ecore_filter_accept_flags accept_flags)
 235 {
 236         p_ramrod->common.update_rx_mode_flg =
 237                                         accept_flags.update_rx_mode_config;
 238         p_ramrod->common.update_tx_mode_flg =
 239                                         accept_flags.update_tx_mode_config;
 240
 241 #ifndef ASIC_ONLY
 242         /* On B0 emulation we cannot enable Tx, since this would cause writes
 243          * to PVFC HW block which isn't implemented in emulation.
 244          */
 245         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 246                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 247                            "Non-Asic - prevent Tx mode in vport update\n");
 248                 p_ramrod->common.update_tx_mode_flg = 0;
 249         }
 250 #endif
 251
 252         /* Set Rx mode accept flags */
 253         if (p_ramrod->common.update_rx_mode_flg) {
 254                 u8 accept_filter = accept_flags.rx_accept_filter;
 255                 u16 state = 0;
 256
 257                 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
 258                           !(!!(accept_filter & ECORE_ACCEPT_UCAST_MATCHED) ||
 259                            !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)));
 260
 261                 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
 262                           !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED));
 263
 264                 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
 265                           !(!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) ||
 266                             !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
 267
 268                 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
 269                           (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
 270                            !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
 271
 272                 SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
 273                           !!(accept_filter & ECORE_ACCEPT_BCAST));
 274
 275                 p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(state);
 276                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 277                            "p_ramrod->rx_mode.state = 0x%x\n",
 278                            state);
 279         }
 280
 281         /* Set Tx mode accept flags */
 282         if (p_ramrod->common.update_tx_mode_flg) {
 283                 u8 accept_filter = accept_flags.tx_accept_filter;
 284                 u16 state = 0;
 285
 286                 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
 287                           !!(accept_filter & ECORE_ACCEPT_NONE));
 288
 289                 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
 290                           !!(accept_filter & ECORE_ACCEPT_NONE));
 291
 292                 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
 293                           (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
 294                            !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
 295
 296                 SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
 297                           !!(accept_filter & ECORE_ACCEPT_BCAST));
 298
 299                 p_ramrod->tx_mode.state = OSAL_CPU_TO_LE16(state);
 300                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 301                            "p_ramrod->tx_mode.state = 0x%x\n",
 302                            state);
 303         }
 304 }
 305
 306 static void
 307 ecore_sp_vport_update_sge_tpa(struct ecore_hwfn *p_hwfn,
 308                               struct vport_update_ramrod_data *p_ramrod,
 309                               struct ecore_sge_tpa_params *p_params)
 310 {
 311         struct eth_vport_tpa_param *p_tpa;
 312
 313         if (!p_params) {
 314                 p_ramrod->common.update_tpa_param_flg = 0;
 315                 p_ramrod->common.update_tpa_en_flg = 0;
 316                 p_ramrod->common.update_tpa_param_flg = 0;
 317                 return;
 318         }
 319
 320         p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
 321         p_tpa = &p_ramrod->tpa_param;
 322         p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
 323         p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
 324         p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
 325         p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
 326
 327         p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
 328         p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
 329         p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
 330         p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
 331         p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
 332         p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
 333         p_tpa->tpa_max_size = p_params->tpa_max_size;
 334         p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
 335         p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
 336 }
 337
 338 static void
 339 ecore_sp_update_mcast_bin(struct ecore_hwfn *p_hwfn,
 340                           struct vport_update_ramrod_data *p_ramrod,
 341                           struct ecore_sp_vport_update_params *p_params)
 342 {
 343         int i;
 344
 345         OSAL_MEMSET(&p_ramrod->approx_mcast.bins, 0,
 346                     sizeof(p_ramrod->approx_mcast.bins));
 347
 348         if (!p_params->update_approx_mcast_flg)
 349                 return;
 350
 351         p_ramrod->common.update_approx_mcast_flg = 1;
 352         for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
 353                 u32 *p_bins = (u32 *)p_params->bins;
 354
 355                 p_ramrod->approx_mcast.bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
 356         }
 357 }
 358
 359 enum _ecore_status_t
 360 ecore_sp_vport_update(struct ecore_hwfn *p_hwfn,
 361                       struct ecore_sp_vport_update_params *p_params,
 362                       enum spq_mode comp_mode,
 363                       struct ecore_spq_comp_cb *p_comp_data)
 364 {
 365         struct ecore_rss_params *p_rss_params = p_params->rss_params;
 366         struct vport_update_ramrod_data_cmn *p_cmn;
 367         struct ecore_sp_init_data init_data;
 368         struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
 369         struct ecore_spq_entry *p_ent = OSAL_NULL;
 370         u8 abs_vport_id = 0, val;
 371         enum _ecore_status_t rc = ECORE_NOTIMPL;
 372
 373         if (IS_VF(p_hwfn->p_dev)) {
 374                 rc = ecore_vf_pf_vport_update(p_hwfn, p_params);
 375                 return rc;
 376         }
 377
 378         rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
 379         if (rc != ECORE_SUCCESS)
 380                 return rc;
 381
 382         /* Get SPQ entry */
 383         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 384         init_data.cid = ecore_spq_get_cid(p_hwfn);
 385         init_data.opaque_fid = p_params->opaque_fid;
 386         init_data.comp_mode = comp_mode;
 387         init_data.p_comp_data = p_comp_data;
 388
 389         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 390                                    ETH_RAMROD_VPORT_UPDATE,
 391                                    PROTOCOLID_ETH, &init_data);
 392         if (rc != ECORE_SUCCESS)
 393                 return rc;
 394
 395         /* Copy input params to ramrod according to FW struct */
 396         p_ramrod = &p_ent->ramrod.vport_update;
 397         p_cmn = &p_ramrod->common;
 398
 399         p_cmn->vport_id = abs_vport_id;
 400
 401         p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
 402         p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
 403         p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
 404         p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
 405
 406         p_cmn->accept_any_vlan = p_params->accept_any_vlan;
 407         val = p_params->update_accept_any_vlan_flg;
 408         p_cmn->update_accept_any_vlan_flg = val;
 409
 410         p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
 411         val = p_params->update_inner_vlan_removal_flg;
 412         p_cmn->update_inner_vlan_removal_en_flg = val;
 413
 414         p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
 415         val = p_params->update_default_vlan_enable_flg;
 416         p_cmn->update_default_vlan_en_flg = val;
 417
 418         p_cmn->default_vlan = OSAL_CPU_TO_LE16(p_params->default_vlan);
 419         p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
 420
 421         p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
 422
 423         p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
 424
 425 #ifndef ASIC_ONLY
 426         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
 427                 if (p_ramrod->common.tx_switching_en ||
 428                     p_ramrod->common.update_tx_switching_en_flg) {
 429                         DP_NOTICE(p_hwfn, false,
 430                                   "FPGA - why are we seeing tx-switching? Overriding it\n");
 431                         p_ramrod->common.tx_switching_en = 0;
 432                         p_ramrod->common.update_tx_switching_en_flg = 1;
 433                 }
 434 #endif
 435         p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
 436
 437         p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
 438         val = p_params->update_anti_spoofing_en_flg;
 439         p_ramrod->common.update_anti_spoofing_en_flg = val;
 440
 441         rc = ecore_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
 442         if (rc != ECORE_SUCCESS) {
 443                 /* Return spq entry which is taken in ecore_sp_init_request()*/
 444                 ecore_spq_return_entry(p_hwfn, p_ent);
 445                 return rc;
 446         }
 447
 448         /* Update mcast bins for VFs, PF doesn't use this functionality */
 449         ecore_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
 450
 451         ecore_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
 452         ecore_sp_vport_update_sge_tpa(p_hwfn, p_ramrod,
 453                                       p_params->sge_tpa_params);
 454         if (p_params->mtu) {
 455                 p_ramrod->common.update_mtu_flg = 1;
 456                 p_ramrod->common.mtu = OSAL_CPU_TO_LE16(p_params->mtu);
 457         }
 458
 459         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 460 }
 461
 462 enum _ecore_status_t ecore_sp_vport_stop(struct ecore_hwfn *p_hwfn,
 463                                          u16 opaque_fid, u8 vport_id)
 464 {
 465         struct vport_stop_ramrod_data *p_ramrod;
 466         struct ecore_sp_init_data init_data;
 467         struct ecore_spq_entry *p_ent;
 468         u8 abs_vport_id = 0;
 469         enum _ecore_status_t rc;
 470
 471         if (IS_VF(p_hwfn->p_dev))
 472                 return ecore_vf_pf_vport_stop(p_hwfn);
 473
 474         rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
 475         if (rc != ECORE_SUCCESS)
 476                 return rc;
 477
 478         /* Get SPQ entry */
 479         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 480         init_data.cid = ecore_spq_get_cid(p_hwfn);
 481         init_data.opaque_fid = opaque_fid;
 482         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 483
 484         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 485                                    ETH_RAMROD_VPORT_STOP,
 486                                    PROTOCOLID_ETH, &init_data);
 487         if (rc != ECORE_SUCCESS)
 488                 return rc;
 489
 490         p_ramrod = &p_ent->ramrod.vport_stop;
 491         p_ramrod->vport_id = abs_vport_id;
 492
 493         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 494 }
 495
 496 static enum _ecore_status_t
 497 ecore_vf_pf_accept_flags(struct ecore_hwfn *p_hwfn,
 498                          struct ecore_filter_accept_flags *p_accept_flags)
 499 {
 500         struct ecore_sp_vport_update_params s_params;
 501
 502         OSAL_MEMSET(&s_params, 0, sizeof(s_params));
 503         OSAL_MEMCPY(&s_params.accept_flags, p_accept_flags,
 504                     sizeof(struct ecore_filter_accept_flags));
 505
 506         return ecore_vf_pf_vport_update(p_hwfn, &s_params);
 507 }
 508
 509 enum _ecore_status_t
 510 ecore_filter_accept_cmd(struct ecore_dev *p_dev,
 511                         u8 vport,
 512                         struct ecore_filter_accept_flags accept_flags,
 513                         u8 update_accept_any_vlan,
 514                         u8 accept_any_vlan,
 515                         enum spq_mode comp_mode,
 516                         struct ecore_spq_comp_cb *p_comp_data)
 517 {
 518         struct ecore_sp_vport_update_params vport_update_params;
 519         int i, rc;
 520
 521         /* Prepare and send the vport rx_mode change */
 522         OSAL_MEMSET(&vport_update_params, 0, sizeof(vport_update_params));
 523         vport_update_params.vport_id = vport;
 524         vport_update_params.accept_flags = accept_flags;
 525         vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
 526         vport_update_params.accept_any_vlan = accept_any_vlan;
 527
 528         for_each_hwfn(p_dev, i) {
 529                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 530
 531                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 532
 533                 if (IS_VF(p_dev)) {
 534                         rc = ecore_vf_pf_accept_flags(p_hwfn, &accept_flags);
 535                         if (rc != ECORE_SUCCESS)
 536                                 return rc;
 537                         continue;
 538                 }
 539
 540                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
 541                                            comp_mode, p_comp_data);
 542                 if (rc != ECORE_SUCCESS) {
 543                         DP_ERR(p_dev, "Update rx_mode failed %d\n", rc);
 544                         return rc;
 545                 }
 546
 547                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 548                            "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
 549                            accept_flags.rx_accept_filter,
 550                            accept_flags.tx_accept_filter);
 551
 552                 if (update_accept_any_vlan)
 553                         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 554                                    "accept_any_vlan=%d configured\n",
 555                                    accept_any_vlan);
 556         }
 557
 558         return 0;
 559 }
 560
 561 static void ecore_sp_release_queue_cid(struct ecore_hwfn *p_hwfn,
 562                                        struct ecore_hw_cid_data *p_cid_data)
 563 {
 564         if (!p_cid_data->b_cid_allocated)
 565                 return;
 566
 567         ecore_cxt_release_cid(p_hwfn, p_cid_data->cid);
 568         p_cid_data->b_cid_allocated = false;
 569 }
 570
 571 enum _ecore_status_t
 572 ecore_sp_eth_rxq_start_ramrod(struct ecore_hwfn *p_hwfn,
 573                               u16 opaque_fid,
 574                               u32 cid,
 575                               struct ecore_queue_start_common_params *p_params,
 576                               u16 bd_max_bytes,
 577                               dma_addr_t bd_chain_phys_addr,
 578                               dma_addr_t cqe_pbl_addr,
 579                               u16 cqe_pbl_size, bool b_use_zone_a_prod)
 580 {
 581         struct rx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
 582         struct ecore_spq_entry *p_ent = OSAL_NULL;
 583         struct ecore_sp_init_data init_data;
 584         struct ecore_hw_cid_data *p_rx_cid;
 585         u16 abs_rx_q_id = 0;
 586         u8 abs_vport_id = 0;
 587         enum _ecore_status_t rc = ECORE_NOTIMPL;
 588
 589         /* Store information for the stop */
 590         p_rx_cid = &p_hwfn->p_rx_cids[p_params->queue_id];
 591         p_rx_cid->cid = cid;
 592         p_rx_cid->opaque_fid = opaque_fid;
 593         p_rx_cid->vport_id = p_params->vport_id;
 594
 595         rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
 596         if (rc != ECORE_SUCCESS)
 597                 return rc;
 598
 599         rc = ecore_fw_l2_queue(p_hwfn, p_params->queue_id, &abs_rx_q_id);
 600         if (rc != ECORE_SUCCESS)
 601                 return rc;
 602
 603         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 604                    "opaque_fid=0x%x, cid=0x%x, rx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
 605                    opaque_fid, cid, p_params->queue_id,
 606                    p_params->vport_id, p_params->sb);
 607
 608         /* Get SPQ entry */
 609         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 610         init_data.cid = cid;
 611         init_data.opaque_fid = opaque_fid;
 612         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 613
 614         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 615                                    ETH_RAMROD_RX_QUEUE_START,
 616                                    PROTOCOLID_ETH, &init_data);
 617         if (rc != ECORE_SUCCESS)
 618                 return rc;
 619
 620         p_ramrod = &p_ent->ramrod.rx_queue_start;
 621
 622         p_ramrod->sb_id = OSAL_CPU_TO_LE16(p_params->sb);
 623         p_ramrod->sb_index = (u8)p_params->sb_idx;
 624         p_ramrod->vport_id = abs_vport_id;
 625         p_ramrod->stats_counter_id = p_params->stats_id;
 626         p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
 627         p_ramrod->complete_cqe_flg = 0;
 628         p_ramrod->complete_event_flg = 1;
 629
 630         p_ramrod->bd_max_bytes = OSAL_CPU_TO_LE16(bd_max_bytes);
 631         DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
 632
 633         p_ramrod->num_of_pbl_pages = OSAL_CPU_TO_LE16(cqe_pbl_size);
 634         DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
 635
 636         if (p_params->vf_qid || b_use_zone_a_prod) {
 637                 p_ramrod->vf_rx_prod_index = (u8)p_params->vf_qid;
 638                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 639                            "Queue%s is meant for VF rxq[%02x]\n",
 640                            b_use_zone_a_prod ? " [legacy]" : "",
 641                            p_params->vf_qid);
 642                 p_ramrod->vf_rx_prod_use_zone_a = b_use_zone_a_prod;
 643         }
 644
 645         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 646 }
 647
 648 enum _ecore_status_t
 649 ecore_sp_eth_rx_queue_start(struct ecore_hwfn *p_hwfn,
 650                             u16 opaque_fid,
 651                             struct ecore_queue_start_common_params *p_params,
 652                             u16 bd_max_bytes,
 653                             dma_addr_t bd_chain_phys_addr,
 654                             dma_addr_t cqe_pbl_addr,
 655                             u16 cqe_pbl_size,
 656                             void OSAL_IOMEM * *pp_prod)
 657 {
 658         struct ecore_hw_cid_data *p_rx_cid;
 659         u32 init_prod_val = 0;
 660         u16 abs_l2_queue = 0;
 661         u8 abs_stats_id = 0;
 662         enum _ecore_status_t rc;
 663
 664         if (IS_VF(p_hwfn->p_dev)) {
 665                 return ecore_vf_pf_rxq_start(p_hwfn,
 666                                              (u8)p_params->queue_id,
 667                                              p_params->sb,
 668                                              (u8)p_params->sb_idx,
 669                                              bd_max_bytes,
 670                                              bd_chain_phys_addr,
 671                                              cqe_pbl_addr,
 672                                              cqe_pbl_size, pp_prod);
 673         }
 674
 675         rc = ecore_fw_l2_queue(p_hwfn, p_params->queue_id, &abs_l2_queue);
 676         if (rc != ECORE_SUCCESS)
 677                 return rc;
 678
 679         rc = ecore_fw_vport(p_hwfn, p_params->stats_id, &abs_stats_id);
 680         if (rc != ECORE_SUCCESS)
 681                 return rc;
 682
 683         *pp_prod = (u8 OSAL_IOMEM *)p_hwfn->regview +
 684             GTT_BAR0_MAP_REG_MSDM_RAM +
 685             MSTORM_ETH_PF_PRODS_OFFSET(abs_l2_queue);
 686
 687         /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
 688         __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
 689                           (u32 *)(&init_prod_val));
 690
 691         /* Allocate a CID for the queue */
 692         p_rx_cid = &p_hwfn->p_rx_cids[p_params->queue_id];
 693         rc = ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
 694                                    &p_rx_cid->cid);
 695         if (rc != ECORE_SUCCESS) {
 696                 DP_NOTICE(p_hwfn, true, "Failed to acquire cid\n");
 697                 return rc;
 698         }
 699         p_rx_cid->b_cid_allocated = true;
 700         p_params->stats_id = abs_stats_id;
 701         p_params->vf_qid = 0;
 702
 703         rc = ecore_sp_eth_rxq_start_ramrod(p_hwfn,
 704                                            opaque_fid,
 705                                            p_rx_cid->cid,
 706                                            p_params,
 707                                            bd_max_bytes,
 708                                            bd_chain_phys_addr,
 709                                            cqe_pbl_addr,
 710                                            cqe_pbl_size,
 711                                            false);
 712
 713         if (rc != ECORE_SUCCESS)
 714                 ecore_sp_release_queue_cid(p_hwfn, p_rx_cid);
 715
 716         return rc;
 717 }
 718
 719 enum _ecore_status_t
 720 ecore_sp_eth_rx_queues_update(struct ecore_hwfn *p_hwfn,
 721                               u16 rx_queue_id,
 722                               u8 num_rxqs,
 723                               u8 complete_cqe_flg,
 724                               u8 complete_event_flg,
 725                               enum spq_mode comp_mode,
 726                               struct ecore_spq_comp_cb *p_comp_data)
 727 {
 728         struct rx_queue_update_ramrod_data *p_ramrod = OSAL_NULL;
 729         struct ecore_spq_entry *p_ent = OSAL_NULL;
 730         struct ecore_sp_init_data init_data;
 731         struct ecore_hw_cid_data *p_rx_cid;
 732         u16 qid, abs_rx_q_id = 0;
 733         enum _ecore_status_t rc = ECORE_NOTIMPL;
 734         u8 i;
 735
 736         if (IS_VF(p_hwfn->p_dev))
 737                 return ecore_vf_pf_rxqs_update(p_hwfn,
 738                                                rx_queue_id,
 739                                                num_rxqs,
 740                                                complete_cqe_flg,
 741                                                complete_event_flg);
 742
 743         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 744         init_data.comp_mode = comp_mode;
 745         init_data.p_comp_data = p_comp_data;
 746
 747         for (i = 0; i < num_rxqs; i++) {
 748                 qid = rx_queue_id + i;
 749                 p_rx_cid = &p_hwfn->p_rx_cids[qid];
 750
 751                 /* Get SPQ entry */
 752                 init_data.cid = p_rx_cid->cid;
 753                 init_data.opaque_fid = p_rx_cid->opaque_fid;
 754
 755                 rc = ecore_sp_init_request(p_hwfn, &p_ent,
 756                                            ETH_RAMROD_RX_QUEUE_UPDATE,
 757                                            PROTOCOLID_ETH, &init_data);
 758                 if (rc != ECORE_SUCCESS)
 759                         return rc;
 760
 761                 p_ramrod = &p_ent->ramrod.rx_queue_update;
 762
 763                 ecore_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
 764                 ecore_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
 765                 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
 766                 p_ramrod->complete_cqe_flg = complete_cqe_flg;
 767                 p_ramrod->complete_event_flg = complete_event_flg;
 768
 769                 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 770                 if (rc)
 771                         return rc;
 772         }
 773
 774         return rc;
 775 }
 776
 777 enum _ecore_status_t
 778 ecore_sp_eth_rx_queue_stop(struct ecore_hwfn *p_hwfn,
 779                            u16 rx_queue_id,
 780                            bool eq_completion_only, bool cqe_completion)
 781 {
 782         struct ecore_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
 783         struct rx_queue_stop_ramrod_data *p_ramrod = OSAL_NULL;
 784         struct ecore_spq_entry *p_ent = OSAL_NULL;
 785         struct ecore_sp_init_data init_data;
 786         u16 abs_rx_q_id = 0;
 787         enum _ecore_status_t rc = ECORE_NOTIMPL;
 788
 789         if (IS_VF(p_hwfn->p_dev))
 790                 return ecore_vf_pf_rxq_stop(p_hwfn, rx_queue_id,
 791                                             cqe_completion);
 792
 793         /* Get SPQ entry */
 794         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 795         init_data.cid = p_rx_cid->cid;
 796         init_data.opaque_fid = p_rx_cid->opaque_fid;
 797         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 798
 799         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 800                                    ETH_RAMROD_RX_QUEUE_STOP,
 801                                    PROTOCOLID_ETH, &init_data);
 802         if (rc != ECORE_SUCCESS)
 803                 return rc;
 804
 805         p_ramrod = &p_ent->ramrod.rx_queue_stop;
 806
 807         ecore_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
 808         ecore_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
 809         p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
 810
 811         /* Cleaning the queue requires the completion to arrive there.
 812          * In addition, VFs require the answer to come as eqe to PF.
 813          */
 814         p_ramrod->complete_cqe_flg = (!!(p_rx_cid->opaque_fid ==
 815                                          p_hwfn->hw_info.opaque_fid) &&
 816                                       !eq_completion_only) || cqe_completion;
 817         p_ramrod->complete_event_flg = !(p_rx_cid->opaque_fid ==
 818                                          p_hwfn->hw_info.opaque_fid) ||
 819             eq_completion_only;
 820
 821         rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 822         if (rc != ECORE_SUCCESS)
 823                 return rc;
 824
 825         ecore_sp_release_queue_cid(p_hwfn, p_rx_cid);
 826
 827         return rc;
 828 }
 829
 830 enum _ecore_status_t
 831 ecore_sp_eth_txq_start_ramrod(struct ecore_hwfn *p_hwfn,
 832                               u16 opaque_fid,
 833                               u32 cid,
 834                               struct ecore_queue_start_common_params *p_params,
 835                               dma_addr_t pbl_addr,
 836                               u16 pbl_size,
 837                               union ecore_qm_pq_params *p_pq_params)
 838 {
 839         struct tx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
 840         struct ecore_spq_entry *p_ent = OSAL_NULL;
 841         struct ecore_sp_init_data init_data;
 842         struct ecore_hw_cid_data *p_tx_cid;
 843         u16 pq_id, abs_tx_qzone_id = 0;
 844         enum _ecore_status_t rc = ECORE_NOTIMPL;
 845         u8 abs_vport_id;
 846
 847         /* Store information for the stop */
 848         p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id];
 849         p_tx_cid->cid = cid;
 850         p_tx_cid->opaque_fid = opaque_fid;
 851
 852         rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
 853         if (rc != ECORE_SUCCESS)
 854                 return rc;
 855
 856         rc = ecore_fw_l2_queue(p_hwfn, p_params->qzone_id, &abs_tx_qzone_id);
 857         if (rc != ECORE_SUCCESS)
 858                 return rc;
 859
 860         /* Get SPQ entry */
 861         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 862         init_data.cid = cid;
 863         init_data.opaque_fid = opaque_fid;
 864         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 865
 866         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 867                                    ETH_RAMROD_TX_QUEUE_START,
 868                                    PROTOCOLID_ETH, &init_data);
 869         if (rc != ECORE_SUCCESS)
 870                 return rc;
 871
 872         p_ramrod = &p_ent->ramrod.tx_queue_start;
 873         p_ramrod->vport_id = abs_vport_id;
 874
 875         p_ramrod->sb_id = OSAL_CPU_TO_LE16(p_params->sb);
 876         p_ramrod->sb_index = (u8)p_params->sb_idx;
 877         p_ramrod->stats_counter_id = p_params->stats_id;
 878
 879         p_ramrod->queue_zone_id = OSAL_CPU_TO_LE16(abs_tx_qzone_id);
 880         p_ramrod->same_as_last_id = OSAL_CPU_TO_LE16(abs_tx_qzone_id);
 881
 882         p_ramrod->pbl_size = OSAL_CPU_TO_LE16(pbl_size);
 883         DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
 884
 885         pq_id = ecore_get_qm_pq(p_hwfn, PROTOCOLID_ETH, p_pq_params);
 886         p_ramrod->qm_pq_id = OSAL_CPU_TO_LE16(pq_id);
 887
 888         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 889 }
 890
 891 enum _ecore_status_t
 892 ecore_sp_eth_tx_queue_start(struct ecore_hwfn *p_hwfn,
 893                             u16 opaque_fid,
 894                             struct ecore_queue_start_common_params *p_params,
 895                             u8 tc,
 896                             dma_addr_t pbl_addr,
 897                             u16 pbl_size,
 898                             void OSAL_IOMEM * *pp_doorbell)
 899 {
 900         struct ecore_hw_cid_data *p_tx_cid;
 901         union ecore_qm_pq_params pq_params;
 902         u8 abs_stats_id = 0;
 903         enum _ecore_status_t rc;
 904
 905         if (IS_VF(p_hwfn->p_dev)) {
 906                 return ecore_vf_pf_txq_start(p_hwfn,
 907                                              p_params->queue_id,
 908                                              p_params->sb,
 909                                              (u8)p_params->sb_idx,
 910                                              pbl_addr,
 911                                              pbl_size,
 912                                              pp_doorbell);
 913         }
 914
 915         rc = ecore_fw_vport(p_hwfn, p_params->stats_id, &abs_stats_id);
 916         if (rc != ECORE_SUCCESS)
 917                 return rc;
 918
 919         p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id];
 920         OSAL_MEMSET(p_tx_cid, 0, sizeof(*p_tx_cid));
 921         OSAL_MEMSET(&pq_params, 0, sizeof(pq_params));
 922
 923         pq_params.eth.tc = tc;
 924
 925         /* Allocate a CID for the queue */
 926         rc = ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &p_tx_cid->cid);
 927         if (rc != ECORE_SUCCESS) {
 928                 DP_NOTICE(p_hwfn, true, "Failed to acquire cid\n");
 929                 return rc;
 930         }
 931         p_tx_cid->b_cid_allocated = true;
 932
 933         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 934                    "opaque_fid=0x%x, cid=0x%x, tx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
 935                     opaque_fid, p_tx_cid->cid, p_params->queue_id,
 936                     p_params->vport_id, p_params->sb);
 937
 938         p_params->stats_id = abs_stats_id;
 939
 940         /* TODO - set tc in the pq_params for multi-cos */
 941         rc = ecore_sp_eth_txq_start_ramrod(p_hwfn,
 942                                            opaque_fid,
 943                                            p_tx_cid->cid,
 944                                            p_params,
 945                                            pbl_addr,
 946                                            pbl_size,
 947                                            &pq_params);
 948
 949         *pp_doorbell = (u8 OSAL_IOMEM *)p_hwfn->doorbells +
 950             DB_ADDR(p_tx_cid->cid, DQ_DEMS_LEGACY);
 951
 952         if (rc != ECORE_SUCCESS)
 953                 ecore_sp_release_queue_cid(p_hwfn, p_tx_cid);
 954
 955         return rc;
 956 }
 957
 958 enum _ecore_status_t ecore_sp_eth_tx_queue_update(struct ecore_hwfn *p_hwfn)
 959 {
 960         return ECORE_NOTIMPL;
 961 }
 962
 963 enum _ecore_status_t ecore_sp_eth_tx_queue_stop(struct ecore_hwfn *p_hwfn,
 964                                                 u16 tx_queue_id)
 965 {
 966         struct ecore_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
 967         struct ecore_spq_entry *p_ent = OSAL_NULL;
 968         struct ecore_sp_init_data init_data;
 969         enum _ecore_status_t rc = ECORE_NOTIMPL;
 970
 971         if (IS_VF(p_hwfn->p_dev))
 972                 return ecore_vf_pf_txq_stop(p_hwfn, tx_queue_id);
 973
 974         /* Get SPQ entry */
 975         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 976         init_data.cid = p_tx_cid->cid;
 977         init_data.opaque_fid = p_tx_cid->opaque_fid;
 978         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 979
 980         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 981                                    ETH_RAMROD_TX_QUEUE_STOP,
 982                                    PROTOCOLID_ETH, &init_data);
 983         if (rc != ECORE_SUCCESS)
 984                 return rc;
 985
 986         rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 987         if (rc != ECORE_SUCCESS)
 988                 return rc;
 989
 990         ecore_sp_release_queue_cid(p_hwfn, p_tx_cid);
 991         return rc;
 992 }
 993
 994 static enum eth_filter_action
 995 ecore_filter_action(enum ecore_filter_opcode opcode)
 996 {
 997         enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
 998
 999         switch (opcode) {
1000         case ECORE_FILTER_ADD:
1001                 action = ETH_FILTER_ACTION_ADD;
1002                 break;
1003         case ECORE_FILTER_REMOVE:
1004                 action = ETH_FILTER_ACTION_REMOVE;
1005                 break;
1006         case ECORE_FILTER_FLUSH:
1007                 action = ETH_FILTER_ACTION_REMOVE_ALL;
1008                 break;
1009         default:
1010                 action = MAX_ETH_FILTER_ACTION;
1011         }
1012
1013         return action;
1014 }
1015
1016 static enum _ecore_status_t
1017 ecore_filter_ucast_common(struct ecore_hwfn *p_hwfn,
1018                           u16 opaque_fid,
1019                           struct ecore_filter_ucast *p_filter_cmd,
1020                           struct vport_filter_update_ramrod_data **pp_ramrod,
1021                           struct ecore_spq_entry **pp_ent,
1022                           enum spq_mode comp_mode,
1023                           struct ecore_spq_comp_cb *p_comp_data)
1024 {
1025         u8 vport_to_add_to = 0, vport_to_remove_from = 0;
1026         struct vport_filter_update_ramrod_data *p_ramrod;
1027         struct eth_filter_cmd *p_first_filter;
1028         struct eth_filter_cmd *p_second_filter;
1029         struct ecore_sp_init_data init_data;
1030         enum eth_filter_action action;
1031         enum _ecore_status_t rc;
1032
1033         rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1034                             &vport_to_remove_from);
1035         if (rc != ECORE_SUCCESS)
1036                 return rc;
1037
1038         rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1039                             &vport_to_add_to);
1040         if (rc != ECORE_SUCCESS)
1041                 return rc;
1042
1043         /* Get SPQ entry */
1044         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1045         init_data.cid = ecore_spq_get_cid(p_hwfn);
1046         init_data.opaque_fid = opaque_fid;
1047         init_data.comp_mode = comp_mode;
1048         init_data.p_comp_data = p_comp_data;
1049
1050         rc = ecore_sp_init_request(p_hwfn, pp_ent,
1051                                    ETH_RAMROD_FILTERS_UPDATE,
1052                                    PROTOCOLID_ETH, &init_data);
1053         if (rc != ECORE_SUCCESS)
1054                 return rc;
1055
1056         *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
1057         p_ramrod = *pp_ramrod;
1058         p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
1059         p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
1060
1061 #ifndef ASIC_ONLY
1062         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1063                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1064                            "Non-Asic - prevent Tx filters\n");
1065                 p_ramrod->filter_cmd_hdr.tx = 0;
1066         }
1067 #endif
1068
1069         switch (p_filter_cmd->opcode) {
1070         case ECORE_FILTER_REPLACE:
1071         case ECORE_FILTER_MOVE:
1072                 p_ramrod->filter_cmd_hdr.cmd_cnt = 2;
1073                 break;
1074         default:
1075                 p_ramrod->filter_cmd_hdr.cmd_cnt = 1;
1076                 break;
1077         }
1078
1079         p_first_filter = &p_ramrod->filter_cmds[0];
1080         p_second_filter = &p_ramrod->filter_cmds[1];
1081
1082         switch (p_filter_cmd->type) {
1083         case ECORE_FILTER_MAC:
1084                 p_first_filter->type = ETH_FILTER_TYPE_MAC;
1085                 break;
1086         case ECORE_FILTER_VLAN:
1087                 p_first_filter->type = ETH_FILTER_TYPE_VLAN;
1088                 break;
1089         case ECORE_FILTER_MAC_VLAN:
1090                 p_first_filter->type = ETH_FILTER_TYPE_PAIR;
1091                 break;
1092         case ECORE_FILTER_INNER_MAC:
1093                 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC;
1094                 break;
1095         case ECORE_FILTER_INNER_VLAN:
1096                 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN;
1097                 break;
1098         case ECORE_FILTER_INNER_PAIR:
1099                 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR;
1100                 break;
1101         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
1102                 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
1103                 break;
1104         case ECORE_FILTER_MAC_VNI_PAIR:
1105                 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR;
1106                 break;
1107         case ECORE_FILTER_VNI:
1108                 p_first_filter->type = ETH_FILTER_TYPE_VNI;
1109                 break;
1110         case ECORE_FILTER_UNUSED: /* @DPDK */
1111                 p_first_filter->type = MAX_ETH_FILTER_TYPE;
1112                 break;
1113         }
1114
1115         if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1116             (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1117             (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1118             (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1119             (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1120             (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR))
1121                 ecore_set_fw_mac_addr(&p_first_filter->mac_msb,
1122                                       &p_first_filter->mac_mid,
1123                                       &p_first_filter->mac_lsb,
1124                                       (u8 *)p_filter_cmd->mac);
1125
1126         if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1127             (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1128             (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1129             (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1130                 p_first_filter->vlan_id = OSAL_CPU_TO_LE16(p_filter_cmd->vlan);
1131
1132         if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1133             (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1134             (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1135                 p_first_filter->vni = OSAL_CPU_TO_LE32(p_filter_cmd->vni);
1136
1137         if (p_filter_cmd->opcode == ECORE_FILTER_MOVE) {
1138                 p_second_filter->type = p_first_filter->type;
1139                 p_second_filter->mac_msb = p_first_filter->mac_msb;
1140                 p_second_filter->mac_mid = p_first_filter->mac_mid;
1141                 p_second_filter->mac_lsb = p_first_filter->mac_lsb;
1142                 p_second_filter->vlan_id = p_first_filter->vlan_id;
1143                 p_second_filter->vni = p_first_filter->vni;
1144
1145                 p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1146
1147                 p_first_filter->vport_id = vport_to_remove_from;
1148
1149                 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1150                 p_second_filter->vport_id = vport_to_add_to;
1151         } else if (p_filter_cmd->opcode == ECORE_FILTER_REPLACE) {
1152                 p_first_filter->vport_id = vport_to_add_to;
1153                 OSAL_MEMCPY(p_second_filter, p_first_filter,
1154                             sizeof(*p_second_filter));
1155                 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
1156                 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1157         } else {
1158                 action = ecore_filter_action(p_filter_cmd->opcode);
1159
1160                 if (action == MAX_ETH_FILTER_ACTION) {
1161                         DP_NOTICE(p_hwfn, true,
1162                                   "%d is not supported yet\n",
1163                                   p_filter_cmd->opcode);
1164                         return ECORE_NOTIMPL;
1165                 }
1166
1167                 p_first_filter->action = action;
1168                 p_first_filter->vport_id =
1169                     (p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1170                     vport_to_remove_from : vport_to_add_to;
1171         }
1172
1173         return ECORE_SUCCESS;
1174 }
1175
1176 enum _ecore_status_t
1177 ecore_sp_eth_filter_ucast(struct ecore_hwfn *p_hwfn,
1178                           u16 opaque_fid,
1179                           struct ecore_filter_ucast *p_filter_cmd,
1180                           enum spq_mode comp_mode,
1181                           struct ecore_spq_comp_cb *p_comp_data)
1182 {
1183         struct vport_filter_update_ramrod_data *p_ramrod = OSAL_NULL;
1184         struct ecore_spq_entry *p_ent = OSAL_NULL;
1185         struct eth_filter_cmd_header *p_header;
1186         enum _ecore_status_t rc;
1187
1188         rc = ecore_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1189                                        &p_ramrod, &p_ent,
1190                                        comp_mode, p_comp_data);
1191         if (rc != ECORE_SUCCESS) {
1192                 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1193                 return rc;
1194         }
1195         p_header = &p_ramrod->filter_cmd_hdr;
1196         p_header->assert_on_error = p_filter_cmd->assert_on_error;
1197
1198         rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1199         if (rc != ECORE_SUCCESS) {
1200                 DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
1201                 return rc;
1202         }
1203
1204         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1205                    "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1206                    (p_filter_cmd->opcode == ECORE_FILTER_ADD) ? "ADD" :
1207                    ((p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1208                     "REMOVE" :
1209                     ((p_filter_cmd->opcode == ECORE_FILTER_MOVE) ?
1210                      "MOVE" : "REPLACE")),
1211                    (p_filter_cmd->type == ECORE_FILTER_MAC) ? "MAC" :
1212                    ((p_filter_cmd->type == ECORE_FILTER_VLAN) ?
1213                     "VLAN" : "MAC & VLAN"),
1214                    p_ramrod->filter_cmd_hdr.cmd_cnt,
1215                    p_filter_cmd->is_rx_filter, p_filter_cmd->is_tx_filter);
1216         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1217                    "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1218                    p_filter_cmd->vport_to_add_to,
1219                    p_filter_cmd->vport_to_remove_from,
1220                    p_filter_cmd->mac[0], p_filter_cmd->mac[1],
1221                    p_filter_cmd->mac[2], p_filter_cmd->mac[3],
1222                    p_filter_cmd->mac[4], p_filter_cmd->mac[5],
1223                    p_filter_cmd->vlan);
1224
1225         return ECORE_SUCCESS;
1226 }
1227
1228 /*******************************************************************************
1229  * Description:
1230  *         Calculates crc 32 on a buffer
1231  *         Note: crc32_length MUST be aligned to 8
1232  * Return:
1233  ******************************************************************************/
1234 static u32 ecore_calc_crc32c(u8 *crc32_packet,
1235                              u32 crc32_length, u32 crc32_seed, u8 complement)
1236 {
1237         u32 byte = 0, bit = 0, crc32_result = crc32_seed;
1238         u8 msb = 0, current_byte = 0;
1239
1240         if ((crc32_packet == OSAL_NULL) ||
1241             (crc32_length == 0) || ((crc32_length % 8) != 0)) {
1242                 return crc32_result;
1243         }
1244
1245         for (byte = 0; byte < crc32_length; byte++) {
1246                 current_byte = crc32_packet[byte];
1247                 for (bit = 0; bit < 8; bit++) {
1248                         msb = (u8)(crc32_result >> 31);
1249                         crc32_result = crc32_result << 1;
1250                         if (msb != (0x1 & (current_byte >> bit))) {
1251                                 crc32_result = crc32_result ^ CRC32_POLY;
1252                                 crc32_result |= 1;
1253                         }
1254                 }
1255         }
1256
1257         return crc32_result;
1258 }
1259
1260 static u32 ecore_crc32c_le(u32 seed, u8 *mac, u32 len)
1261 {
1262         u32 packet_buf[2] = { 0 };
1263
1264         OSAL_MEMCPY((u8 *)(&packet_buf[0]), &mac[0], 6);
1265         return ecore_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1266 }
1267
1268 u8 ecore_mcast_bin_from_mac(u8 *mac)
1269 {
1270         u32 crc = ecore_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1271                                   mac, ETH_ALEN);
1272
1273         return crc & 0xff;
1274 }
1275
1276 static enum _ecore_status_t
1277 ecore_sp_eth_filter_mcast(struct ecore_hwfn *p_hwfn,
1278                           u16 opaque_fid,
1279                           struct ecore_filter_mcast *p_filter_cmd,
1280                           enum spq_mode comp_mode,
1281                           struct ecore_spq_comp_cb *p_comp_data)
1282 {
1283         unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1284         struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
1285         struct ecore_spq_entry *p_ent = OSAL_NULL;
1286         struct ecore_sp_init_data init_data;
1287         u8 abs_vport_id = 0;
1288         enum _ecore_status_t rc;
1289         int i;
1290
1291         if (p_filter_cmd->opcode == ECORE_FILTER_ADD)
1292                 rc = ecore_fw_vport(p_hwfn,
1293                                     p_filter_cmd->vport_to_add_to,
1294                                     &abs_vport_id);
1295         else
1296                 rc = ecore_fw_vport(p_hwfn,
1297                                     p_filter_cmd->vport_to_remove_from,
1298                                     &abs_vport_id);
1299         if (rc != ECORE_SUCCESS)
1300                 return rc;
1301
1302         /* Get SPQ entry */
1303         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1304         init_data.cid = ecore_spq_get_cid(p_hwfn);
1305         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1306         init_data.comp_mode = comp_mode;
1307         init_data.p_comp_data = p_comp_data;
1308
1309         rc = ecore_sp_init_request(p_hwfn, &p_ent,
1310                                    ETH_RAMROD_VPORT_UPDATE,
1311                                    PROTOCOLID_ETH, &init_data);
1312         if (rc != ECORE_SUCCESS) {
1313                 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1314                 return rc;
1315         }
1316
1317         p_ramrod = &p_ent->ramrod.vport_update;
1318         p_ramrod->common.update_approx_mcast_flg = 1;
1319
1320         /* explicitly clear out the entire vector */
1321         OSAL_MEMSET(&p_ramrod->approx_mcast.bins,
1322                     0, sizeof(p_ramrod->approx_mcast.bins));
1323         OSAL_MEMSET(bins, 0, sizeof(unsigned long) *
1324                     ETH_MULTICAST_MAC_BINS_IN_REGS);
1325         /* filter ADD op is explicit set op and it removes
1326         *  any existing filters for the vport.
1327         */
1328         if (p_filter_cmd->opcode == ECORE_FILTER_ADD) {
1329                 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1330                         u32 bit;
1331
1332                         bit = ecore_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1333                         OSAL_SET_BIT(bit, bins);
1334                 }
1335
1336                 /* Convert to correct endianity */
1337                 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
1338                         struct vport_update_ramrod_mcast *p_ramrod_bins;
1339                         u32 *p_bins = (u32 *)bins;
1340
1341                         p_ramrod_bins = &p_ramrod->approx_mcast;
1342                         p_ramrod_bins->bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
1343                 }
1344         }
1345
1346         p_ramrod->common.vport_id = abs_vport_id;
1347
1348         rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1349         if (rc != ECORE_SUCCESS)
1350                 DP_ERR(p_hwfn, "Multicast filter command failed %d\n", rc);
1351
1352         return rc;
1353 }
1354
1355 enum _ecore_status_t
1356 ecore_filter_mcast_cmd(struct ecore_dev *p_dev,
1357                        struct ecore_filter_mcast *p_filter_cmd,
1358                        enum spq_mode comp_mode,
1359                        struct ecore_spq_comp_cb *p_comp_data)
1360 {
1361         enum _ecore_status_t rc = ECORE_SUCCESS;
1362         int i;
1363
1364         /* only ADD and REMOVE operations are supported for multi-cast */
1365         if ((p_filter_cmd->opcode != ECORE_FILTER_ADD &&
1366              (p_filter_cmd->opcode != ECORE_FILTER_REMOVE)) ||
1367             (p_filter_cmd->num_mc_addrs > ECORE_MAX_MC_ADDRS)) {
1368                 return ECORE_INVAL;
1369         }
1370
1371         for_each_hwfn(p_dev, i) {
1372                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1373                 u16 opaque_fid;
1374
1375                 if (IS_VF(p_dev)) {
1376                         ecore_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1377                         continue;
1378                 }
1379
1380                 opaque_fid = p_hwfn->hw_info.opaque_fid;
1381                 rc = ecore_sp_eth_filter_mcast(p_hwfn,
1382                                                opaque_fid,
1383                                                p_filter_cmd,
1384                                                comp_mode, p_comp_data);
1385                 if (rc != ECORE_SUCCESS)
1386                         break;
1387         }
1388
1389         return rc;
1390 }
1391
1392 enum _ecore_status_t
1393 ecore_filter_ucast_cmd(struct ecore_dev *p_dev,
1394                        struct ecore_filter_ucast *p_filter_cmd,
1395                        enum spq_mode comp_mode,
1396                        struct ecore_spq_comp_cb *p_comp_data)
1397 {
1398         enum _ecore_status_t rc = ECORE_SUCCESS;
1399         int i;
1400
1401         for_each_hwfn(p_dev, i) {
1402                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1403                 u16 opaque_fid;
1404
1405                 if (IS_VF(p_dev)) {
1406                         rc = ecore_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1407                         continue;
1408                 }
1409
1410                 opaque_fid = p_hwfn->hw_info.opaque_fid;
1411                 rc = ecore_sp_eth_filter_ucast(p_hwfn,
1412                                                opaque_fid,
1413                                                p_filter_cmd,
1414                                                comp_mode, p_comp_data);
1415                 if (rc != ECORE_SUCCESS)
1416                         break;
1417         }
1418
1419         return rc;
1420 }
1421
1422 /* Statistics related code */
1423 static void __ecore_get_vport_pstats_addrlen(struct ecore_hwfn *p_hwfn,
1424                                              u32 *p_addr, u32 *p_len,
1425                                              u16 statistics_bin)
1426 {
1427         if (IS_PF(p_hwfn->p_dev)) {
1428                 *p_addr = BAR0_MAP_REG_PSDM_RAM +
1429                     PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1430                 *p_len = sizeof(struct eth_pstorm_per_queue_stat);
1431         } else {
1432                 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1433                 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1434
1435                 *p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1436                 *p_len = p_resp->pfdev_info.stats_info.pstats.len;
1437         }
1438 }
1439
1440 static void __ecore_get_vport_pstats(struct ecore_hwfn *p_hwfn,
1441                                      struct ecore_ptt *p_ptt,
1442                                      struct ecore_eth_stats *p_stats,
1443                                      u16 statistics_bin)
1444 {
1445         struct eth_pstorm_per_queue_stat pstats;
1446         u32 pstats_addr = 0, pstats_len = 0;
1447
1448         __ecore_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
1449                                          statistics_bin);
1450
1451         OSAL_MEMSET(&pstats, 0, sizeof(pstats));
1452         ecore_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
1453
1454         p_stats->tx_ucast_bytes += HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1455         p_stats->tx_mcast_bytes += HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1456         p_stats->tx_bcast_bytes += HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1457         p_stats->tx_ucast_pkts += HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1458         p_stats->tx_mcast_pkts += HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1459         p_stats->tx_bcast_pkts += HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1460         p_stats->tx_err_drop_pkts += HILO_64_REGPAIR(pstats.error_drop_pkts);
1461 }
1462
1463 static void __ecore_get_vport_tstats(struct ecore_hwfn *p_hwfn,
1464                                      struct ecore_ptt *p_ptt,
1465                                      struct ecore_eth_stats *p_stats,
1466                                      u16 statistics_bin)
1467 {
1468         struct tstorm_per_port_stat tstats;
1469         u32 tstats_addr, tstats_len;
1470
1471         if (IS_PF(p_hwfn->p_dev)) {
1472                 tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1473                     TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1474                 tstats_len = sizeof(struct tstorm_per_port_stat);
1475         } else {
1476                 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1477                 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1478
1479                 tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1480                 tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1481         }
1482
1483         OSAL_MEMSET(&tstats, 0, sizeof(tstats));
1484         ecore_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
1485
1486         p_stats->mftag_filter_discards +=
1487             HILO_64_REGPAIR(tstats.mftag_filter_discard);
1488         p_stats->mac_filter_discards +=
1489             HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
1490 }
1491
1492 static void __ecore_get_vport_ustats_addrlen(struct ecore_hwfn *p_hwfn,
1493                                              u32 *p_addr, u32 *p_len,
1494                                              u16 statistics_bin)
1495 {
1496         if (IS_PF(p_hwfn->p_dev)) {
1497                 *p_addr = BAR0_MAP_REG_USDM_RAM +
1498                     USTORM_QUEUE_STAT_OFFSET(statistics_bin);
1499                 *p_len = sizeof(struct eth_ustorm_per_queue_stat);
1500         } else {
1501                 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1502                 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1503
1504                 *p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1505                 *p_len = p_resp->pfdev_info.stats_info.ustats.len;
1506         }
1507 }
1508
1509 static void __ecore_get_vport_ustats(struct ecore_hwfn *p_hwfn,
1510                                      struct ecore_ptt *p_ptt,
1511                                      struct ecore_eth_stats *p_stats,
1512                                      u16 statistics_bin)
1513 {
1514         struct eth_ustorm_per_queue_stat ustats;
1515         u32 ustats_addr = 0, ustats_len = 0;
1516
1517         __ecore_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
1518                                          statistics_bin);
1519
1520         OSAL_MEMSET(&ustats, 0, sizeof(ustats));
1521         ecore_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
1522
1523         p_stats->rx_ucast_bytes += HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1524         p_stats->rx_mcast_bytes += HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1525         p_stats->rx_bcast_bytes += HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1526         p_stats->rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1527         p_stats->rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1528         p_stats->rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
1529 }
1530
1531 static void __ecore_get_vport_mstats_addrlen(struct ecore_hwfn *p_hwfn,
1532                                              u32 *p_addr, u32 *p_len,
1533                                              u16 statistics_bin)
1534 {
1535         if (IS_PF(p_hwfn->p_dev)) {
1536                 *p_addr = BAR0_MAP_REG_MSDM_RAM +
1537                     MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1538                 *p_len = sizeof(struct eth_mstorm_per_queue_stat);
1539         } else {
1540                 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1541                 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1542
1543                 *p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1544                 *p_len = p_resp->pfdev_info.stats_info.mstats.len;
1545         }
1546 }
1547
1548 static void __ecore_get_vport_mstats(struct ecore_hwfn *p_hwfn,
1549                                      struct ecore_ptt *p_ptt,
1550                                      struct ecore_eth_stats *p_stats,
1551                                      u16 statistics_bin)
1552 {
1553         struct eth_mstorm_per_queue_stat mstats;
1554         u32 mstats_addr = 0, mstats_len = 0;
1555
1556         __ecore_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
1557                                          statistics_bin);
1558
1559         OSAL_MEMSET(&mstats, 0, sizeof(mstats));
1560         ecore_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
1561
1562         p_stats->no_buff_discards += HILO_64_REGPAIR(mstats.no_buff_discard);
1563         p_stats->packet_too_big_discard +=
1564             HILO_64_REGPAIR(mstats.packet_too_big_discard);
1565         p_stats->ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
1566         p_stats->tpa_coalesced_pkts +=
1567             HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
1568         p_stats->tpa_coalesced_events +=
1569             HILO_64_REGPAIR(mstats.tpa_coalesced_events);
1570         p_stats->tpa_aborts_num += HILO_64_REGPAIR(mstats.tpa_aborts_num);
1571         p_stats->tpa_coalesced_bytes +=
1572             HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
1573 }
1574
1575 static void __ecore_get_vport_port_stats(struct ecore_hwfn *p_hwfn,
1576                                          struct ecore_ptt *p_ptt,
1577                                          struct ecore_eth_stats *p_stats)
1578 {
1579         struct port_stats port_stats;
1580         int j;
1581
1582         OSAL_MEMSET(&port_stats, 0, sizeof(port_stats));
1583
1584         ecore_memcpy_from(p_hwfn, p_ptt, &port_stats,
1585                           p_hwfn->mcp_info->port_addr +
1586                           OFFSETOF(struct public_port, stats),
1587                           sizeof(port_stats));
1588
1589         p_stats->rx_64_byte_packets += port_stats.eth.r64;
1590         p_stats->rx_65_to_127_byte_packets += port_stats.eth.r127;
1591         p_stats->rx_128_to_255_byte_packets += port_stats.eth.r255;
1592         p_stats->rx_256_to_511_byte_packets += port_stats.eth.r511;
1593         p_stats->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
1594         p_stats->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
1595         p_stats->rx_1519_to_1522_byte_packets += port_stats.eth.r1522;
1596         p_stats->rx_1519_to_2047_byte_packets += port_stats.eth.r2047;
1597         p_stats->rx_2048_to_4095_byte_packets += port_stats.eth.r4095;
1598         p_stats->rx_4096_to_9216_byte_packets += port_stats.eth.r9216;
1599         p_stats->rx_9217_to_16383_byte_packets += port_stats.eth.r16383;
1600         p_stats->rx_crc_errors += port_stats.eth.rfcs;
1601         p_stats->rx_mac_crtl_frames += port_stats.eth.rxcf;
1602         p_stats->rx_pause_frames += port_stats.eth.rxpf;
1603         p_stats->rx_pfc_frames += port_stats.eth.rxpp;
1604         p_stats->rx_align_errors += port_stats.eth.raln;
1605         p_stats->rx_carrier_errors += port_stats.eth.rfcr;
1606         p_stats->rx_oversize_packets += port_stats.eth.rovr;
1607         p_stats->rx_jabbers += port_stats.eth.rjbr;
1608         p_stats->rx_undersize_packets += port_stats.eth.rund;
1609         p_stats->rx_fragments += port_stats.eth.rfrg;
1610         p_stats->tx_64_byte_packets += port_stats.eth.t64;
1611         p_stats->tx_65_to_127_byte_packets += port_stats.eth.t127;
1612         p_stats->tx_128_to_255_byte_packets += port_stats.eth.t255;
1613         p_stats->tx_256_to_511_byte_packets += port_stats.eth.t511;
1614         p_stats->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
1615         p_stats->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
1616         p_stats->tx_1519_to_2047_byte_packets += port_stats.eth.t2047;
1617         p_stats->tx_2048_to_4095_byte_packets += port_stats.eth.t4095;
1618         p_stats->tx_4096_to_9216_byte_packets += port_stats.eth.t9216;
1619         p_stats->tx_9217_to_16383_byte_packets += port_stats.eth.t16383;
1620         p_stats->tx_pause_frames += port_stats.eth.txpf;
1621         p_stats->tx_pfc_frames += port_stats.eth.txpp;
1622         p_stats->tx_lpi_entry_count += port_stats.eth.tlpiec;
1623         p_stats->tx_total_collisions += port_stats.eth.tncl;
1624         p_stats->rx_mac_bytes += port_stats.eth.rbyte;
1625         p_stats->rx_mac_uc_packets += port_stats.eth.rxuca;
1626         p_stats->rx_mac_mc_packets += port_stats.eth.rxmca;
1627         p_stats->rx_mac_bc_packets += port_stats.eth.rxbca;
1628         p_stats->rx_mac_frames_ok += port_stats.eth.rxpok;
1629         p_stats->tx_mac_bytes += port_stats.eth.tbyte;
1630         p_stats->tx_mac_uc_packets += port_stats.eth.txuca;
1631         p_stats->tx_mac_mc_packets += port_stats.eth.txmca;
1632         p_stats->tx_mac_bc_packets += port_stats.eth.txbca;
1633         p_stats->tx_mac_ctrl_frames += port_stats.eth.txcf;
1634         for (j = 0; j < 8; j++) {
1635                 p_stats->brb_truncates += port_stats.brb.brb_truncate[j];
1636                 p_stats->brb_discards += port_stats.brb.brb_discard[j];
1637         }
1638 }
1639
1640 void __ecore_get_vport_stats(struct ecore_hwfn *p_hwfn,
1641                              struct ecore_ptt *p_ptt,
1642                              struct ecore_eth_stats *stats,
1643                              u16 statistics_bin, bool b_get_port_stats)
1644 {
1645         __ecore_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
1646         __ecore_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
1647         __ecore_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
1648         __ecore_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
1649
1650 #ifndef ASIC_ONLY
1651         /* Avoid getting PORT stats for emulation. */
1652         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1653                 return;
1654 #endif
1655
1656         if (b_get_port_stats && p_hwfn->mcp_info)
1657                 __ecore_get_vport_port_stats(p_hwfn, p_ptt, stats);
1658 }
1659
1660 static void _ecore_get_vport_stats(struct ecore_dev *p_dev,
1661                                    struct ecore_eth_stats *stats)
1662 {
1663         u8 fw_vport = 0;
1664         int i;
1665
1666         OSAL_MEMSET(stats, 0, sizeof(*stats));
1667
1668         for_each_hwfn(p_dev, i) {
1669                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1670                 struct ecore_ptt *p_ptt = IS_PF(p_dev) ?
1671                     ecore_ptt_acquire(p_hwfn) : OSAL_NULL;
1672
1673                 if (IS_PF(p_dev)) {
1674                         /* The main vport index is relative first */
1675                         if (ecore_fw_vport(p_hwfn, 0, &fw_vport)) {
1676                                 DP_ERR(p_hwfn, "No vport available!\n");
1677                                 goto out;
1678                         }
1679                 }
1680
1681                 if (IS_PF(p_dev) && !p_ptt) {
1682                         DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1683                         continue;
1684                 }
1685
1686                 __ecore_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1687                                         IS_PF(p_dev) ? true : false);
1688
1689 out:
1690                 if (IS_PF(p_dev) && p_ptt)
1691                         ecore_ptt_release(p_hwfn, p_ptt);
1692         }
1693 }
1694
1695 void ecore_get_vport_stats(struct ecore_dev *p_dev,
1696                            struct ecore_eth_stats *stats)
1697 {
1698         u32 i;
1699
1700         if (!p_dev) {
1701                 OSAL_MEMSET(stats, 0, sizeof(*stats));
1702                 return;
1703         }
1704
1705         _ecore_get_vport_stats(p_dev, stats);
1706
1707         if (!p_dev->reset_stats)
1708                 return;
1709
1710         /* Reduce the statistics baseline */
1711         for (i = 0; i < sizeof(struct ecore_eth_stats) / sizeof(u64); i++)
1712                 ((u64 *)stats)[i] -= ((u64 *)p_dev->reset_stats)[i];
1713 }
1714
1715 /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
1716 void ecore_reset_vport_stats(struct ecore_dev *p_dev)
1717 {
1718         int i;
1719
1720         for_each_hwfn(p_dev, i) {
1721                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1722                 struct eth_mstorm_per_queue_stat mstats;
1723                 struct eth_ustorm_per_queue_stat ustats;
1724                 struct eth_pstorm_per_queue_stat pstats;
1725                 struct ecore_ptt *p_ptt = IS_PF(p_dev) ?
1726                     ecore_ptt_acquire(p_hwfn) : OSAL_NULL;
1727                 u32 addr = 0, len = 0;
1728
1729                 if (IS_PF(p_dev) && !p_ptt) {
1730                         DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1731                         continue;
1732                 }
1733
1734                 OSAL_MEMSET(&mstats, 0, sizeof(mstats));
1735                 __ecore_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
1736                 ecore_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
1737
1738                 OSAL_MEMSET(&ustats, 0, sizeof(ustats));
1739                 __ecore_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
1740                 ecore_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
1741
1742                 OSAL_MEMSET(&pstats, 0, sizeof(pstats));
1743                 __ecore_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
1744                 ecore_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
1745
1746                 if (IS_PF(p_dev))
1747                         ecore_ptt_release(p_hwfn, p_ptt);
1748         }
1749
1750         /* PORT statistics are not necessarily reset, so we need to
1751          * read and create a baseline for future statistics.
1752          */
1753         if (!p_dev->reset_stats)
1754                 DP_INFO(p_dev, "Reset stats not allocated\n");
1755         else
1756                 _ecore_get_vport_stats(p_dev, p_dev->reset_stats);
1757 }