drivers/net/qede/base/ecore_l2.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10
  11 #include "ecore.h"
  12 #include "ecore_status.h"
  13 #include "ecore_hsi_eth.h"
  14 #include "ecore_chain.h"
  15 #include "ecore_spq.h"
  16 #include "ecore_init_fw_funcs.h"
  17 #include "ecore_cxt.h"
  18 #include "ecore_l2.h"
  19 #include "ecore_sp_commands.h"
  20 #include "ecore_gtt_reg_addr.h"
  21 #include "ecore_iro.h"
  22 #include "reg_addr.h"
  23 #include "ecore_int.h"
  24 #include "ecore_hw.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_sriov.h"
  27 #include "ecore_mcp.h"
  28
  29 #define ECORE_MAX_SGES_NUM 16
  30 #define CRC32_POLY 0x1edc6f41
  31
  32 enum _ecore_status_t
  33 ecore_sp_eth_vport_start(struct ecore_hwfn *p_hwfn,
  34                          struct ecore_sp_vport_start_params *p_params)
  35 {
  36         struct vport_start_ramrod_data *p_ramrod = OSAL_NULL;
  37         struct ecore_spq_entry *p_ent = OSAL_NULL;
  38         struct ecore_sp_init_data init_data;
  39         u8 abs_vport_id = 0;
  40         enum _ecore_status_t rc = ECORE_NOTIMPL;
  41         u16 rx_mode = 0;
  42
  43         rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
  44         if (rc != ECORE_SUCCESS)
  45                 return rc;
  46
  47         /* Get SPQ entry */
  48         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
  49         init_data.cid = ecore_spq_get_cid(p_hwfn);
  50         init_data.opaque_fid = p_params->opaque_fid;
  51         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
  52
  53         rc = ecore_sp_init_request(p_hwfn, &p_ent,
  54                                    ETH_RAMROD_VPORT_START,
  55                                    PROTOCOLID_ETH, &init_data);
  56         if (rc != ECORE_SUCCESS)
  57                 return rc;
  58
  59         p_ramrod = &p_ent->ramrod.vport_start;
  60         p_ramrod->vport_id = abs_vport_id;
  61
  62         p_ramrod->mtu = OSAL_CPU_TO_LE16(p_params->mtu);
  63         p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
  64         p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts;
  65         p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
  66         p_ramrod->untagged = p_params->only_untagged;
  67         p_ramrod->zero_placement_offset = p_params->zero_placement_offset;
  68
  69         SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
  70         SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
  71
  72         p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(rx_mode);
  73
  74         /* TPA related fields */
  75         OSAL_MEMSET(&p_ramrod->tpa_param, 0,
  76                     sizeof(struct eth_vport_tpa_param));
  77         p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
  78
  79         switch (p_params->tpa_mode) {
  80         case ECORE_TPA_MODE_GRO:
  81                 p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
  82                 p_ramrod->tpa_param.tpa_max_size = (u16)-1;
  83                 p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
  84                 p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
  85                 p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
  86                 p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
  87                 p_ramrod->tpa_param.tpa_ipv4_tunn_en_flg = 1;
  88                 p_ramrod->tpa_param.tpa_ipv6_tunn_en_flg = 1;
  89                 p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
  90                 p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
  91                 break;
  92         default:
  93                 break;
  94         }
  95
  96         p_ramrod->tx_switching_en = p_params->tx_switching;
  97 #ifndef ASIC_ONLY
  98         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
  99                 p_ramrod->tx_switching_en = 0;
 100 #endif
 101
 102         p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac;
 103         p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype;
 104
 105         /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
 106         p_ramrod->sw_fid = ecore_concrete_to_sw_fid(p_hwfn->p_dev,
 107                                                     p_params->concrete_fid);
 108
 109         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 110 }
 111
 112 enum _ecore_status_t
 113 ecore_sp_vport_start(struct ecore_hwfn *p_hwfn,
 114                      struct ecore_sp_vport_start_params *p_params)
 115 {
 116         if (IS_VF(p_hwfn->p_dev))
 117                 return ecore_vf_pf_vport_start(p_hwfn, p_params->vport_id,
 118                                                p_params->mtu,
 119                                                p_params->remove_inner_vlan,
 120                                                p_params->tpa_mode,
 121                                                p_params->max_buffers_per_cqe,
 122                                                p_params->only_untagged);
 123
 124         return ecore_sp_eth_vport_start(p_hwfn, p_params);
 125 }
 126
 127 static enum _ecore_status_t
 128 ecore_sp_vport_update_rss(struct ecore_hwfn *p_hwfn,
 129                           struct vport_update_ramrod_data *p_ramrod,
 130                           struct ecore_rss_params *p_rss)
 131 {
 132         enum _ecore_status_t rc = ECORE_SUCCESS;
 133         struct eth_vport_rss_config *p_config;
 134         u16 abs_l2_queue = 0;
 135         int i;
 136
 137         if (!p_rss) {
 138                 p_ramrod->common.update_rss_flg = 0;
 139                 return rc;
 140         }
 141         p_config = &p_ramrod->rss_config;
 142
 143         OSAL_BUILD_BUG_ON(ECORE_RSS_IND_TABLE_SIZE !=
 144                           ETH_RSS_IND_TABLE_ENTRIES_NUM);
 145
 146         rc = ecore_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
 147         if (rc != ECORE_SUCCESS)
 148                 return rc;
 149
 150         p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
 151         p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
 152         p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
 153         p_config->update_rss_key = p_rss->update_rss_key;
 154
 155         p_config->rss_mode = p_rss->rss_enable ?
 156             ETH_VPORT_RSS_MODE_REGULAR : ETH_VPORT_RSS_MODE_DISABLED;
 157
 158         p_config->capabilities = 0;
 159
 160         SET_FIELD(p_config->capabilities,
 161                   ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
 162                   !!(p_rss->rss_caps & ECORE_RSS_IPV4));
 163         SET_FIELD(p_config->capabilities,
 164                   ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
 165                   !!(p_rss->rss_caps & ECORE_RSS_IPV6));
 166         SET_FIELD(p_config->capabilities,
 167                   ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
 168                   !!(p_rss->rss_caps & ECORE_RSS_IPV4_TCP));
 169         SET_FIELD(p_config->capabilities,
 170                   ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
 171                   !!(p_rss->rss_caps & ECORE_RSS_IPV6_TCP));
 172         SET_FIELD(p_config->capabilities,
 173                   ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
 174                   !!(p_rss->rss_caps & ECORE_RSS_IPV4_UDP));
 175         SET_FIELD(p_config->capabilities,
 176                   ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
 177                   !!(p_rss->rss_caps & ECORE_RSS_IPV6_UDP));
 178         p_config->tbl_size = p_rss->rss_table_size_log;
 179         p_config->capabilities = OSAL_CPU_TO_LE16(p_config->capabilities);
 180
 181         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
 182                    "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
 183                    p_ramrod->common.update_rss_flg,
 184                    p_config->rss_mode,
 185                    p_config->update_rss_capabilities,
 186                    p_config->capabilities,
 187                    p_config->update_rss_ind_table, p_config->update_rss_key);
 188
 189         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
 190                 rc = ecore_fw_l2_queue(p_hwfn,
 191                                        (u8)p_rss->rss_ind_table[i],
 192                                        &abs_l2_queue);
 193                 if (rc != ECORE_SUCCESS)
 194                         return rc;
 195
 196                 p_config->indirection_table[i] = OSAL_CPU_TO_LE16(abs_l2_queue);
 197                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP, "i= %d, queue = %d\n",
 198                            i, p_config->indirection_table[i]);
 199         }
 200
 201         for (i = 0; i < 10; i++)
 202                 p_config->rss_key[i] = OSAL_CPU_TO_LE32(p_rss->rss_key[i]);
 203
 204         return rc;
 205 }
 206
 207 static void
 208 ecore_sp_update_accept_mode(struct ecore_hwfn *p_hwfn,
 209                             struct vport_update_ramrod_data *p_ramrod,
 210                             struct ecore_filter_accept_flags accept_flags)
 211 {
 212         p_ramrod->common.update_rx_mode_flg =
 213                                         accept_flags.update_rx_mode_config;
 214         p_ramrod->common.update_tx_mode_flg =
 215                                         accept_flags.update_tx_mode_config;
 216
 217 #ifndef ASIC_ONLY
 218         /* On B0 emulation we cannot enable Tx, since this would cause writes
 219          * to PVFC HW block which isn't implemented in emulation.
 220          */
 221         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 222                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 223                            "Non-Asic - prevent Tx mode in vport update\n");
 224                 p_ramrod->common.update_tx_mode_flg = 0;
 225         }
 226 #endif
 227
 228         /* Set Rx mode accept flags */
 229         if (p_ramrod->common.update_rx_mode_flg) {
 230                 u8 accept_filter = accept_flags.rx_accept_filter;
 231                 u16 state = 0;
 232
 233                 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
 234                           !(!!(accept_filter & ECORE_ACCEPT_UCAST_MATCHED) ||
 235                            !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)));
 236
 237                 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
 238                           !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED));
 239
 240                 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
 241                           !(!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) ||
 242                             !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
 243
 244                 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
 245                           (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
 246                            !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
 247
 248                 SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
 249                           !!(accept_filter & ECORE_ACCEPT_BCAST));
 250
 251                 p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(state);
 252                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 253                            "p_ramrod->rx_mode.state = 0x%x\n",
 254                            state);
 255         }
 256
 257         /* Set Tx mode accept flags */
 258         if (p_ramrod->common.update_tx_mode_flg) {
 259                 u8 accept_filter = accept_flags.tx_accept_filter;
 260                 u16 state = 0;
 261
 262                 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
 263                           !!(accept_filter & ECORE_ACCEPT_NONE));
 264
 265                 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
 266                           !!(accept_filter & ECORE_ACCEPT_NONE));
 267
 268                 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
 269                           (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
 270                            !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
 271
 272                 SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
 273                           !!(accept_filter & ECORE_ACCEPT_BCAST));
 274
 275                 p_ramrod->tx_mode.state = OSAL_CPU_TO_LE16(state);
 276                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 277                            "p_ramrod->tx_mode.state = 0x%x\n",
 278                            state);
 279         }
 280 }
 281
 282 static void
 283 ecore_sp_vport_update_sge_tpa(struct ecore_hwfn *p_hwfn,
 284                               struct vport_update_ramrod_data *p_ramrod,
 285                               struct ecore_sge_tpa_params *p_params)
 286 {
 287         struct eth_vport_tpa_param *p_tpa;
 288
 289         if (!p_params) {
 290                 p_ramrod->common.update_tpa_param_flg = 0;
 291                 p_ramrod->common.update_tpa_en_flg = 0;
 292                 p_ramrod->common.update_tpa_param_flg = 0;
 293                 return;
 294         }
 295
 296         p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
 297         p_tpa = &p_ramrod->tpa_param;
 298         p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
 299         p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
 300         p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
 301         p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
 302
 303         p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
 304         p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
 305         p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
 306         p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
 307         p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
 308         p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
 309         p_tpa->tpa_max_size = p_params->tpa_max_size;
 310         p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
 311         p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
 312 }
 313
 314 static void
 315 ecore_sp_update_mcast_bin(struct ecore_hwfn *p_hwfn,
 316                           struct vport_update_ramrod_data *p_ramrod,
 317                           struct ecore_sp_vport_update_params *p_params)
 318 {
 319         int i;
 320
 321         OSAL_MEMSET(&p_ramrod->approx_mcast.bins, 0,
 322                     sizeof(p_ramrod->approx_mcast.bins));
 323
 324         if (!p_params->update_approx_mcast_flg)
 325                 return;
 326
 327         p_ramrod->common.update_approx_mcast_flg = 1;
 328         for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
 329                 u32 *p_bins = (u32 *)p_params->bins;
 330
 331                 p_ramrod->approx_mcast.bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
 332         }
 333 }
 334
 335 enum _ecore_status_t
 336 ecore_sp_vport_update(struct ecore_hwfn *p_hwfn,
 337                       struct ecore_sp_vport_update_params *p_params,
 338                       enum spq_mode comp_mode,
 339                       struct ecore_spq_comp_cb *p_comp_data)
 340 {
 341         struct ecore_rss_params *p_rss_params = p_params->rss_params;
 342         struct vport_update_ramrod_data_cmn *p_cmn;
 343         struct ecore_sp_init_data init_data;
 344         struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
 345         struct ecore_spq_entry *p_ent = OSAL_NULL;
 346         u8 abs_vport_id = 0, val;
 347         enum _ecore_status_t rc = ECORE_NOTIMPL;
 348
 349         if (IS_VF(p_hwfn->p_dev)) {
 350                 rc = ecore_vf_pf_vport_update(p_hwfn, p_params);
 351                 return rc;
 352         }
 353
 354         rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
 355         if (rc != ECORE_SUCCESS)
 356                 return rc;
 357
 358         /* Get SPQ entry */
 359         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 360         init_data.cid = ecore_spq_get_cid(p_hwfn);
 361         init_data.opaque_fid = p_params->opaque_fid;
 362         init_data.comp_mode = comp_mode;
 363         init_data.p_comp_data = p_comp_data;
 364
 365         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 366                                    ETH_RAMROD_VPORT_UPDATE,
 367                                    PROTOCOLID_ETH, &init_data);
 368         if (rc != ECORE_SUCCESS)
 369                 return rc;
 370
 371         /* Copy input params to ramrod according to FW struct */
 372         p_ramrod = &p_ent->ramrod.vport_update;
 373         p_cmn = &p_ramrod->common;
 374
 375         p_cmn->vport_id = abs_vport_id;
 376
 377         p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
 378         p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
 379         p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
 380         p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
 381
 382         p_cmn->accept_any_vlan = p_params->accept_any_vlan;
 383         val = p_params->update_accept_any_vlan_flg;
 384         p_cmn->update_accept_any_vlan_flg = val;
 385
 386         p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
 387         val = p_params->update_inner_vlan_removal_flg;
 388         p_cmn->update_inner_vlan_removal_en_flg = val;
 389
 390         p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
 391         val = p_params->update_default_vlan_enable_flg;
 392         p_cmn->update_default_vlan_en_flg = val;
 393
 394         p_cmn->default_vlan = OSAL_CPU_TO_LE16(p_params->default_vlan);
 395         p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
 396
 397         p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
 398
 399         p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
 400
 401 #ifndef ASIC_ONLY
 402         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
 403                 if (p_ramrod->common.tx_switching_en ||
 404                     p_ramrod->common.update_tx_switching_en_flg) {
 405                         DP_NOTICE(p_hwfn, false,
 406                                   "FPGA - why are we seeing tx-switching? Overriding it\n");
 407                         p_ramrod->common.tx_switching_en = 0;
 408                         p_ramrod->common.update_tx_switching_en_flg = 1;
 409                 }
 410 #endif
 411         p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
 412
 413         p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
 414         val = p_params->update_anti_spoofing_en_flg;
 415         p_ramrod->common.update_anti_spoofing_en_flg = val;
 416
 417         rc = ecore_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
 418         if (rc != ECORE_SUCCESS) {
 419                 /* Return spq entry which is taken in ecore_sp_init_request()*/
 420                 ecore_spq_return_entry(p_hwfn, p_ent);
 421                 return rc;
 422         }
 423
 424         /* Update mcast bins for VFs, PF doesn't use this functionality */
 425         ecore_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
 426
 427         ecore_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
 428         ecore_sp_vport_update_sge_tpa(p_hwfn, p_ramrod,
 429                                       p_params->sge_tpa_params);
 430         if (p_params->mtu) {
 431                 p_ramrod->common.update_mtu_flg = 1;
 432                 p_ramrod->common.mtu = OSAL_CPU_TO_LE16(p_params->mtu);
 433         }
 434
 435         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 436 }
 437
 438 enum _ecore_status_t ecore_sp_vport_stop(struct ecore_hwfn *p_hwfn,
 439                                          u16 opaque_fid, u8 vport_id)
 440 {
 441         struct vport_stop_ramrod_data *p_ramrod;
 442         struct ecore_sp_init_data init_data;
 443         struct ecore_spq_entry *p_ent;
 444         u8 abs_vport_id = 0;
 445         enum _ecore_status_t rc;
 446
 447         if (IS_VF(p_hwfn->p_dev))
 448                 return ecore_vf_pf_vport_stop(p_hwfn);
 449
 450         rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
 451         if (rc != ECORE_SUCCESS)
 452                 return rc;
 453
 454         /* Get SPQ entry */
 455         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 456         init_data.cid = ecore_spq_get_cid(p_hwfn);
 457         init_data.opaque_fid = opaque_fid;
 458         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 459
 460         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 461                                    ETH_RAMROD_VPORT_STOP,
 462                                    PROTOCOLID_ETH, &init_data);
 463         if (rc != ECORE_SUCCESS)
 464                 return rc;
 465
 466         p_ramrod = &p_ent->ramrod.vport_stop;
 467         p_ramrod->vport_id = abs_vport_id;
 468
 469         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 470 }
 471
 472 static enum _ecore_status_t
 473 ecore_vf_pf_accept_flags(struct ecore_hwfn *p_hwfn,
 474                          struct ecore_filter_accept_flags *p_accept_flags)
 475 {
 476         struct ecore_sp_vport_update_params s_params;
 477
 478         OSAL_MEMSET(&s_params, 0, sizeof(s_params));
 479         OSAL_MEMCPY(&s_params.accept_flags, p_accept_flags,
 480                     sizeof(struct ecore_filter_accept_flags));
 481
 482         return ecore_vf_pf_vport_update(p_hwfn, &s_params);
 483 }
 484
 485 enum _ecore_status_t
 486 ecore_filter_accept_cmd(struct ecore_dev *p_dev,
 487                         u8 vport,
 488                         struct ecore_filter_accept_flags accept_flags,
 489                         u8 update_accept_any_vlan,
 490                         u8 accept_any_vlan,
 491                         enum spq_mode comp_mode,
 492                         struct ecore_spq_comp_cb *p_comp_data)
 493 {
 494         struct ecore_sp_vport_update_params vport_update_params;
 495         int i, rc;
 496
 497         /* Prepare and send the vport rx_mode change */
 498         OSAL_MEMSET(&vport_update_params, 0, sizeof(vport_update_params));
 499         vport_update_params.vport_id = vport;
 500         vport_update_params.accept_flags = accept_flags;
 501         vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
 502         vport_update_params.accept_any_vlan = accept_any_vlan;
 503
 504         for_each_hwfn(p_dev, i) {
 505                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 506
 507                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 508
 509                 if (IS_VF(p_dev)) {
 510                         rc = ecore_vf_pf_accept_flags(p_hwfn, &accept_flags);
 511                         if (rc != ECORE_SUCCESS)
 512                                 return rc;
 513                         continue;
 514                 }
 515
 516                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
 517                                            comp_mode, p_comp_data);
 518                 if (rc != ECORE_SUCCESS) {
 519                         DP_ERR(p_dev, "Update rx_mode failed %d\n", rc);
 520                         return rc;
 521                 }
 522
 523                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 524                            "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
 525                            accept_flags.rx_accept_filter,
 526                            accept_flags.tx_accept_filter);
 527
 528                 if (update_accept_any_vlan)
 529                         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 530                                    "accept_any_vlan=%d configured\n",
 531                                    accept_any_vlan);
 532         }
 533
 534         return 0;
 535 }
 536
 537 static void ecore_sp_release_queue_cid(struct ecore_hwfn *p_hwfn,
 538                                        struct ecore_hw_cid_data *p_cid_data)
 539 {
 540         if (!p_cid_data->b_cid_allocated)
 541                 return;
 542
 543         ecore_cxt_release_cid(p_hwfn, p_cid_data->cid);
 544         p_cid_data->b_cid_allocated = false;
 545 }
 546
 547 enum _ecore_status_t
 548 ecore_sp_eth_rxq_start_ramrod(struct ecore_hwfn *p_hwfn,
 549                               u16 opaque_fid,
 550                               u32 cid,
 551                               u16 rx_queue_id,
 552                               u8 vf_rx_queue_id,
 553                               u8 vport_id,
 554                               u8 stats_id,
 555                               u16 sb,
 556                               u8 sb_index,
 557                               u16 bd_max_bytes,
 558                               dma_addr_t bd_chain_phys_addr,
 559                               dma_addr_t cqe_pbl_addr,
 560                               u16 cqe_pbl_size, bool b_use_zone_a_prod)
 561 {
 562         struct rx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
 563         struct ecore_spq_entry *p_ent = OSAL_NULL;
 564         struct ecore_sp_init_data init_data;
 565         struct ecore_hw_cid_data *p_rx_cid;
 566         u16 abs_rx_q_id = 0;
 567         u8 abs_vport_id = 0;
 568         enum _ecore_status_t rc = ECORE_NOTIMPL;
 569
 570         /* Store information for the stop */
 571         p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
 572         p_rx_cid->cid = cid;
 573         p_rx_cid->opaque_fid = opaque_fid;
 574         p_rx_cid->vport_id = vport_id;
 575
 576         rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
 577         if (rc != ECORE_SUCCESS)
 578                 return rc;
 579
 580         rc = ecore_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
 581         if (rc != ECORE_SUCCESS)
 582                 return rc;
 583
 584         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 585                    "opaque_fid=0x%x, cid=0x%x, rx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
 586                    opaque_fid, cid, rx_queue_id, vport_id, sb);
 587
 588         /* Get SPQ entry */
 589         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 590         init_data.cid = cid;
 591         init_data.opaque_fid = opaque_fid;
 592         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 593
 594         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 595                                    ETH_RAMROD_RX_QUEUE_START,
 596                                    PROTOCOLID_ETH, &init_data);
 597         if (rc != ECORE_SUCCESS)
 598                 return rc;
 599
 600         p_ramrod = &p_ent->ramrod.rx_queue_start;
 601
 602         p_ramrod->sb_id = OSAL_CPU_TO_LE16(sb);
 603         p_ramrod->sb_index = sb_index;
 604         p_ramrod->vport_id = abs_vport_id;
 605         p_ramrod->stats_counter_id = stats_id;
 606         p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
 607         p_ramrod->complete_cqe_flg = 0;
 608         p_ramrod->complete_event_flg = 1;
 609
 610         p_ramrod->bd_max_bytes = OSAL_CPU_TO_LE16(bd_max_bytes);
 611         DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
 612
 613         p_ramrod->num_of_pbl_pages = OSAL_CPU_TO_LE16(cqe_pbl_size);
 614         DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
 615
 616         if (vf_rx_queue_id || b_use_zone_a_prod) {
 617                 p_ramrod->vf_rx_prod_index = vf_rx_queue_id;
 618                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 619                            "Queue%s is meant for VF rxq[%02x]\n",
 620                            b_use_zone_a_prod ? " [legacy]" : "",
 621                            vf_rx_queue_id);
 622                 p_ramrod->vf_rx_prod_use_zone_a = b_use_zone_a_prod;
 623         }
 624
 625         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 626 }
 627
 628 enum _ecore_status_t ecore_sp_eth_rx_queue_start(struct ecore_hwfn *p_hwfn,
 629                                                  u16 opaque_fid,
 630                                                  u8 rx_queue_id,
 631                                                  u8 vport_id,
 632                                                  u8 stats_id,
 633                                                  u16 sb,
 634                                                  u8 sb_index,
 635                                                  u16 bd_max_bytes,
 636                                                  dma_addr_t bd_chain_phys_addr,
 637                                                  dma_addr_t cqe_pbl_addr,
 638                                                  u16 cqe_pbl_size,
 639                                                  void OSAL_IOMEM **pp_prod)
 640 {
 641         struct ecore_hw_cid_data *p_rx_cid;
 642         u32 init_prod_val = 0;
 643         u16 abs_l2_queue = 0;
 644         u8 abs_stats_id = 0;
 645         enum _ecore_status_t rc;
 646
 647         if (IS_VF(p_hwfn->p_dev)) {
 648                 return ecore_vf_pf_rxq_start(p_hwfn,
 649                                              rx_queue_id,
 650                                              sb,
 651                                              sb_index,
 652                                              bd_max_bytes,
 653                                              bd_chain_phys_addr,
 654                                              cqe_pbl_addr,
 655                                              cqe_pbl_size, pp_prod);
 656         }
 657
 658         rc = ecore_fw_l2_queue(p_hwfn, rx_queue_id, &abs_l2_queue);
 659         if (rc != ECORE_SUCCESS)
 660                 return rc;
 661
 662         rc = ecore_fw_vport(p_hwfn, stats_id, &abs_stats_id);
 663         if (rc != ECORE_SUCCESS)
 664                 return rc;
 665
 666         *pp_prod = (u8 OSAL_IOMEM *)p_hwfn->regview +
 667             GTT_BAR0_MAP_REG_MSDM_RAM +
 668             MSTORM_ETH_PF_PRODS_OFFSET(abs_l2_queue);
 669
 670         /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
 671         __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
 672                           (u32 *)(&init_prod_val));
 673
 674         /* Allocate a CID for the queue */
 675         p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
 676         rc = ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
 677                                    &p_rx_cid->cid);
 678         if (rc != ECORE_SUCCESS) {
 679                 DP_NOTICE(p_hwfn, true, "Failed to acquire cid\n");
 680                 return rc;
 681         }
 682         p_rx_cid->b_cid_allocated = true;
 683
 684         rc = ecore_sp_eth_rxq_start_ramrod(p_hwfn,
 685                                            opaque_fid,
 686                                            p_rx_cid->cid,
 687                                            rx_queue_id,
 688                                            0,
 689                                            vport_id,
 690                                            abs_stats_id,
 691                                            sb,
 692                                            sb_index,
 693                                            bd_max_bytes,
 694                                            bd_chain_phys_addr,
 695                                            cqe_pbl_addr,
 696                                            cqe_pbl_size,
 697                                            false);
 698
 699         if (rc != ECORE_SUCCESS)
 700                 ecore_sp_release_queue_cid(p_hwfn, p_rx_cid);
 701
 702         return rc;
 703 }
 704
 705 enum _ecore_status_t
 706 ecore_sp_eth_rx_queues_update(struct ecore_hwfn *p_hwfn,
 707                               u16 rx_queue_id,
 708                               u8 num_rxqs,
 709                               u8 complete_cqe_flg,
 710                               u8 complete_event_flg,
 711                               enum spq_mode comp_mode,
 712                               struct ecore_spq_comp_cb *p_comp_data)
 713 {
 714         struct rx_queue_update_ramrod_data *p_ramrod = OSAL_NULL;
 715         struct ecore_spq_entry *p_ent = OSAL_NULL;
 716         struct ecore_sp_init_data init_data;
 717         struct ecore_hw_cid_data *p_rx_cid;
 718         u16 qid, abs_rx_q_id = 0;
 719         enum _ecore_status_t rc = ECORE_NOTIMPL;
 720         u8 i;
 721
 722         if (IS_VF(p_hwfn->p_dev))
 723                 return ecore_vf_pf_rxqs_update(p_hwfn,
 724                                                rx_queue_id,
 725                                                num_rxqs,
 726                                                complete_cqe_flg,
 727                                                complete_event_flg);
 728
 729         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 730         init_data.comp_mode = comp_mode;
 731         init_data.p_comp_data = p_comp_data;
 732
 733         for (i = 0; i < num_rxqs; i++) {
 734                 qid = rx_queue_id + i;
 735                 p_rx_cid = &p_hwfn->p_rx_cids[qid];
 736
 737                 /* Get SPQ entry */
 738                 init_data.cid = p_rx_cid->cid;
 739                 init_data.opaque_fid = p_rx_cid->opaque_fid;
 740
 741                 rc = ecore_sp_init_request(p_hwfn, &p_ent,
 742                                            ETH_RAMROD_RX_QUEUE_UPDATE,
 743                                            PROTOCOLID_ETH, &init_data);
 744                 if (rc != ECORE_SUCCESS)
 745                         return rc;
 746
 747                 p_ramrod = &p_ent->ramrod.rx_queue_update;
 748
 749                 ecore_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
 750                 ecore_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
 751                 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
 752                 p_ramrod->complete_cqe_flg = complete_cqe_flg;
 753                 p_ramrod->complete_event_flg = complete_event_flg;
 754
 755                 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 756                 if (rc)
 757                         return rc;
 758         }
 759
 760         return rc;
 761 }
 762
 763 enum _ecore_status_t
 764 ecore_sp_eth_rx_queue_stop(struct ecore_hwfn *p_hwfn,
 765                            u16 rx_queue_id,
 766                            bool eq_completion_only, bool cqe_completion)
 767 {
 768         struct ecore_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
 769         struct rx_queue_stop_ramrod_data *p_ramrod = OSAL_NULL;
 770         struct ecore_spq_entry *p_ent = OSAL_NULL;
 771         struct ecore_sp_init_data init_data;
 772         u16 abs_rx_q_id = 0;
 773         enum _ecore_status_t rc = ECORE_NOTIMPL;
 774
 775         if (IS_VF(p_hwfn->p_dev))
 776                 return ecore_vf_pf_rxq_stop(p_hwfn, rx_queue_id,
 777                                             cqe_completion);
 778
 779         /* Get SPQ entry */
 780         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 781         init_data.cid = p_rx_cid->cid;
 782         init_data.opaque_fid = p_rx_cid->opaque_fid;
 783         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 784
 785         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 786                                    ETH_RAMROD_RX_QUEUE_STOP,
 787                                    PROTOCOLID_ETH, &init_data);
 788         if (rc != ECORE_SUCCESS)
 789                 return rc;
 790
 791         p_ramrod = &p_ent->ramrod.rx_queue_stop;
 792
 793         ecore_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
 794         ecore_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
 795         p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
 796
 797         /* Cleaning the queue requires the completion to arrive there.
 798          * In addition, VFs require the answer to come as eqe to PF.
 799          */
 800         p_ramrod->complete_cqe_flg = (!!(p_rx_cid->opaque_fid ==
 801                                          p_hwfn->hw_info.opaque_fid) &&
 802                                       !eq_completion_only) || cqe_completion;
 803         p_ramrod->complete_event_flg = !(p_rx_cid->opaque_fid ==
 804                                          p_hwfn->hw_info.opaque_fid) ||
 805             eq_completion_only;
 806
 807         rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 808         if (rc != ECORE_SUCCESS)
 809                 return rc;
 810
 811         ecore_sp_release_queue_cid(p_hwfn, p_rx_cid);
 812
 813         return rc;
 814 }
 815
 816 enum _ecore_status_t
 817 ecore_sp_eth_txq_start_ramrod(struct ecore_hwfn *p_hwfn,
 818                               u16 opaque_fid,
 819                               u16 tx_queue_id,
 820                               u32 cid,
 821                               u8 vport_id,
 822                               u8 stats_id,
 823                               u16 sb,
 824                               u8 sb_index,
 825                               dma_addr_t pbl_addr,
 826                               u16 pbl_size,
 827                               union ecore_qm_pq_params *p_pq_params)
 828 {
 829         struct tx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
 830         struct ecore_spq_entry *p_ent = OSAL_NULL;
 831         struct ecore_sp_init_data init_data;
 832         struct ecore_hw_cid_data *p_tx_cid;
 833         u16 pq_id, abs_tx_q_id = 0;
 834         u8 abs_vport_id;
 835         enum _ecore_status_t rc = ECORE_NOTIMPL;
 836
 837         /* Store information for the stop */
 838         p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
 839         p_tx_cid->cid = cid;
 840         p_tx_cid->opaque_fid = opaque_fid;
 841
 842         rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
 843         if (rc != ECORE_SUCCESS)
 844                 return rc;
 845
 846         rc = ecore_fw_l2_queue(p_hwfn, tx_queue_id, &abs_tx_q_id);
 847         if (rc != ECORE_SUCCESS)
 848                 return rc;
 849
 850         /* Get SPQ entry */
 851         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 852         init_data.cid = cid;
 853         init_data.opaque_fid = opaque_fid;
 854         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 855
 856         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 857                                    ETH_RAMROD_TX_QUEUE_START,
 858                                    PROTOCOLID_ETH, &init_data);
 859         if (rc != ECORE_SUCCESS)
 860                 return rc;
 861
 862         p_ramrod = &p_ent->ramrod.tx_queue_start;
 863         p_ramrod->vport_id = abs_vport_id;
 864
 865         p_ramrod->sb_id = OSAL_CPU_TO_LE16(sb);
 866         p_ramrod->sb_index = sb_index;
 867         p_ramrod->stats_counter_id = stats_id;
 868
 869         p_ramrod->queue_zone_id = OSAL_CPU_TO_LE16(abs_tx_q_id);
 870
 871         p_ramrod->pbl_size = OSAL_CPU_TO_LE16(pbl_size);
 872         DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
 873
 874         pq_id = ecore_get_qm_pq(p_hwfn, PROTOCOLID_ETH, p_pq_params);
 875         p_ramrod->qm_pq_id = OSAL_CPU_TO_LE16(pq_id);
 876
 877         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 878 }
 879
 880 enum _ecore_status_t ecore_sp_eth_tx_queue_start(struct ecore_hwfn *p_hwfn,
 881                                                  u16 opaque_fid,
 882                                                  u16 tx_queue_id,
 883                                                  u8 vport_id,
 884                                                  u8 stats_id,
 885                                                  u16 sb,
 886                                                  u8 sb_index,
 887                                                  u8 tc,
 888                                                  dma_addr_t pbl_addr,
 889                                                  u16 pbl_size,
 890                                                  void OSAL_IOMEM **pp_doorbell)
 891 {
 892         struct ecore_hw_cid_data *p_tx_cid;
 893         union ecore_qm_pq_params pq_params;
 894         u8 abs_stats_id = 0;
 895         enum _ecore_status_t rc;
 896
 897         if (IS_VF(p_hwfn->p_dev)) {
 898                 return ecore_vf_pf_txq_start(p_hwfn,
 899                                              tx_queue_id,
 900                                              sb,
 901                                              sb_index,
 902                                              pbl_addr,
 903                                              pbl_size,
 904                                              pp_doorbell);
 905         }
 906
 907         rc = ecore_fw_vport(p_hwfn, stats_id, &abs_stats_id);
 908         if (rc != ECORE_SUCCESS)
 909                 return rc;
 910
 911         p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
 912         OSAL_MEMSET(p_tx_cid, 0, sizeof(*p_tx_cid));
 913         OSAL_MEMSET(&pq_params, 0, sizeof(pq_params));
 914
 915         pq_params.eth.tc = tc;
 916
 917         /* Allocate a CID for the queue */
 918         rc = ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &p_tx_cid->cid);
 919         if (rc != ECORE_SUCCESS) {
 920                 DP_NOTICE(p_hwfn, true, "Failed to acquire cid\n");
 921                 return rc;
 922         }
 923         p_tx_cid->b_cid_allocated = true;
 924
 925         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 926                    "opaque_fid=0x%x, cid=0x%x, tx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
 927                     opaque_fid, p_tx_cid->cid, tx_queue_id,
 928                     vport_id, sb);
 929
 930         /* TODO - set tc in the pq_params for multi-cos */
 931         rc = ecore_sp_eth_txq_start_ramrod(p_hwfn,
 932                                            opaque_fid,
 933                                            tx_queue_id,
 934                                            p_tx_cid->cid,
 935                                            vport_id,
 936                                            abs_stats_id,
 937                                            sb,
 938                                            sb_index,
 939                                            pbl_addr,
 940                                            pbl_size,
 941                                            &pq_params);
 942
 943         *pp_doorbell = (u8 OSAL_IOMEM *)p_hwfn->doorbells +
 944             DB_ADDR(p_tx_cid->cid, DQ_DEMS_LEGACY);
 945
 946         if (rc != ECORE_SUCCESS)
 947                 ecore_sp_release_queue_cid(p_hwfn, p_tx_cid);
 948
 949         return rc;
 950 }
 951
 952 enum _ecore_status_t ecore_sp_eth_tx_queue_update(struct ecore_hwfn *p_hwfn)
 953 {
 954         return ECORE_NOTIMPL;
 955 }
 956
 957 enum _ecore_status_t ecore_sp_eth_tx_queue_stop(struct ecore_hwfn *p_hwfn,
 958                                                 u16 tx_queue_id)
 959 {
 960         struct ecore_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
 961         struct ecore_spq_entry *p_ent = OSAL_NULL;
 962         struct ecore_sp_init_data init_data;
 963         enum _ecore_status_t rc = ECORE_NOTIMPL;
 964
 965         if (IS_VF(p_hwfn->p_dev))
 966                 return ecore_vf_pf_txq_stop(p_hwfn, tx_queue_id);
 967
 968         /* Get SPQ entry */
 969         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 970         init_data.cid = p_tx_cid->cid;
 971         init_data.opaque_fid = p_tx_cid->opaque_fid;
 972         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 973
 974         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 975                                    ETH_RAMROD_TX_QUEUE_STOP,
 976                                    PROTOCOLID_ETH, &init_data);
 977         if (rc != ECORE_SUCCESS)
 978                 return rc;
 979
 980         rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 981         if (rc != ECORE_SUCCESS)
 982                 return rc;
 983
 984         ecore_sp_release_queue_cid(p_hwfn, p_tx_cid);
 985         return rc;
 986 }
 987
 988 static enum eth_filter_action
 989 ecore_filter_action(enum ecore_filter_opcode opcode)
 990 {
 991         enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
 992
 993         switch (opcode) {
 994         case ECORE_FILTER_ADD:
 995                 action = ETH_FILTER_ACTION_ADD;
 996                 break;
 997         case ECORE_FILTER_REMOVE:
 998                 action = ETH_FILTER_ACTION_REMOVE;
 999                 break;
1000         case ECORE_FILTER_FLUSH:
1001                 action = ETH_FILTER_ACTION_REMOVE_ALL;
1002                 break;
1003         default:
1004                 action = MAX_ETH_FILTER_ACTION;
1005         }
1006
1007         return action;
1008 }
1009
1010 static void ecore_set_fw_mac_addr(__le16 *fw_msb,
1011                                   __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
1012 {
1013         ((u8 *)fw_msb)[0] = mac[1];
1014         ((u8 *)fw_msb)[1] = mac[0];
1015         ((u8 *)fw_mid)[0] = mac[3];
1016         ((u8 *)fw_mid)[1] = mac[2];
1017         ((u8 *)fw_lsb)[0] = mac[5];
1018         ((u8 *)fw_lsb)[1] = mac[4];
1019 }
1020
1021 static enum _ecore_status_t
1022 ecore_filter_ucast_common(struct ecore_hwfn *p_hwfn,
1023                           u16 opaque_fid,
1024                           struct ecore_filter_ucast *p_filter_cmd,
1025                           struct vport_filter_update_ramrod_data **pp_ramrod,
1026                           struct ecore_spq_entry **pp_ent,
1027                           enum spq_mode comp_mode,
1028                           struct ecore_spq_comp_cb *p_comp_data)
1029 {
1030         u8 vport_to_add_to = 0, vport_to_remove_from = 0;
1031         struct vport_filter_update_ramrod_data *p_ramrod;
1032         struct eth_filter_cmd *p_first_filter;
1033         struct eth_filter_cmd *p_second_filter;
1034         struct ecore_sp_init_data init_data;
1035         enum eth_filter_action action;
1036         enum _ecore_status_t rc;
1037
1038         rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1039                             &vport_to_remove_from);
1040         if (rc != ECORE_SUCCESS)
1041                 return rc;
1042
1043         rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1044                             &vport_to_add_to);
1045         if (rc != ECORE_SUCCESS)
1046                 return rc;
1047
1048         /* Get SPQ entry */
1049         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1050         init_data.cid = ecore_spq_get_cid(p_hwfn);
1051         init_data.opaque_fid = opaque_fid;
1052         init_data.comp_mode = comp_mode;
1053         init_data.p_comp_data = p_comp_data;
1054
1055         rc = ecore_sp_init_request(p_hwfn, pp_ent,
1056                                    ETH_RAMROD_FILTERS_UPDATE,
1057                                    PROTOCOLID_ETH, &init_data);
1058         if (rc != ECORE_SUCCESS)
1059                 return rc;
1060
1061         *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
1062         p_ramrod = *pp_ramrod;
1063         p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
1064         p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
1065
1066 #ifndef ASIC_ONLY
1067         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1068                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1069                            "Non-Asic - prevent Tx filters\n");
1070                 p_ramrod->filter_cmd_hdr.tx = 0;
1071         }
1072 #endif
1073
1074         switch (p_filter_cmd->opcode) {
1075         case ECORE_FILTER_REPLACE:
1076         case ECORE_FILTER_MOVE:
1077                 p_ramrod->filter_cmd_hdr.cmd_cnt = 2;
1078                 break;
1079         default:
1080                 p_ramrod->filter_cmd_hdr.cmd_cnt = 1;
1081                 break;
1082         }
1083
1084         p_first_filter = &p_ramrod->filter_cmds[0];
1085         p_second_filter = &p_ramrod->filter_cmds[1];
1086
1087         switch (p_filter_cmd->type) {
1088         case ECORE_FILTER_MAC:
1089                 p_first_filter->type = ETH_FILTER_TYPE_MAC;
1090                 break;
1091         case ECORE_FILTER_VLAN:
1092                 p_first_filter->type = ETH_FILTER_TYPE_VLAN;
1093                 break;
1094         case ECORE_FILTER_MAC_VLAN:
1095                 p_first_filter->type = ETH_FILTER_TYPE_PAIR;
1096                 break;
1097         case ECORE_FILTER_INNER_MAC:
1098                 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC;
1099                 break;
1100         case ECORE_FILTER_INNER_VLAN:
1101                 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN;
1102                 break;
1103         case ECORE_FILTER_INNER_PAIR:
1104                 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR;
1105                 break;
1106         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
1107                 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
1108                 break;
1109         case ECORE_FILTER_MAC_VNI_PAIR:
1110                 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR;
1111                 break;
1112         case ECORE_FILTER_VNI:
1113                 p_first_filter->type = ETH_FILTER_TYPE_VNI;
1114                 break;
1115         }
1116
1117         if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1118             (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1119             (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1120             (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1121             (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1122             (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR))
1123                 ecore_set_fw_mac_addr(&p_first_filter->mac_msb,
1124                                       &p_first_filter->mac_mid,
1125                                       &p_first_filter->mac_lsb,
1126                                       (u8 *)p_filter_cmd->mac);
1127
1128         if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1129             (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1130             (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1131             (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1132                 p_first_filter->vlan_id = OSAL_CPU_TO_LE16(p_filter_cmd->vlan);
1133
1134         if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1135             (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1136             (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1137                 p_first_filter->vni = OSAL_CPU_TO_LE32(p_filter_cmd->vni);
1138
1139         if (p_filter_cmd->opcode == ECORE_FILTER_MOVE) {
1140                 p_second_filter->type = p_first_filter->type;
1141                 p_second_filter->mac_msb = p_first_filter->mac_msb;
1142                 p_second_filter->mac_mid = p_first_filter->mac_mid;
1143                 p_second_filter->mac_lsb = p_first_filter->mac_lsb;
1144                 p_second_filter->vlan_id = p_first_filter->vlan_id;
1145                 p_second_filter->vni = p_first_filter->vni;
1146
1147                 p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1148
1149                 p_first_filter->vport_id = vport_to_remove_from;
1150
1151                 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1152                 p_second_filter->vport_id = vport_to_add_to;
1153         } else if (p_filter_cmd->opcode == ECORE_FILTER_REPLACE) {
1154                 p_first_filter->vport_id = vport_to_add_to;
1155                 OSAL_MEMCPY(p_second_filter, p_first_filter,
1156                             sizeof(*p_second_filter));
1157                 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
1158                 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1159         } else {
1160                 action = ecore_filter_action(p_filter_cmd->opcode);
1161
1162                 if (action == MAX_ETH_FILTER_ACTION) {
1163                         DP_NOTICE(p_hwfn, true,
1164                                   "%d is not supported yet\n",
1165                                   p_filter_cmd->opcode);
1166                         return ECORE_NOTIMPL;
1167                 }
1168
1169                 p_first_filter->action = action;
1170                 p_first_filter->vport_id =
1171                     (p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1172                     vport_to_remove_from : vport_to_add_to;
1173         }
1174
1175         return ECORE_SUCCESS;
1176 }
1177
1178 enum _ecore_status_t
1179 ecore_sp_eth_filter_ucast(struct ecore_hwfn *p_hwfn,
1180                           u16 opaque_fid,
1181                           struct ecore_filter_ucast *p_filter_cmd,
1182                           enum spq_mode comp_mode,
1183                           struct ecore_spq_comp_cb *p_comp_data)
1184 {
1185         struct vport_filter_update_ramrod_data *p_ramrod = OSAL_NULL;
1186         struct ecore_spq_entry *p_ent = OSAL_NULL;
1187         struct eth_filter_cmd_header *p_header;
1188         enum _ecore_status_t rc;
1189
1190         rc = ecore_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1191                                        &p_ramrod, &p_ent,
1192                                        comp_mode, p_comp_data);
1193         if (rc != ECORE_SUCCESS) {
1194                 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1195                 return rc;
1196         }
1197         p_header = &p_ramrod->filter_cmd_hdr;
1198         p_header->assert_on_error = p_filter_cmd->assert_on_error;
1199
1200         rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1201         if (rc != ECORE_SUCCESS) {
1202                 DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
1203                 return rc;
1204         }
1205
1206         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1207                    "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1208                    (p_filter_cmd->opcode == ECORE_FILTER_ADD) ? "ADD" :
1209                    ((p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1210                     "REMOVE" :
1211                     ((p_filter_cmd->opcode == ECORE_FILTER_MOVE) ?
1212                      "MOVE" : "REPLACE")),
1213                    (p_filter_cmd->type == ECORE_FILTER_MAC) ? "MAC" :
1214                    ((p_filter_cmd->type == ECORE_FILTER_VLAN) ?
1215                     "VLAN" : "MAC & VLAN"),
1216                    p_ramrod->filter_cmd_hdr.cmd_cnt,
1217                    p_filter_cmd->is_rx_filter, p_filter_cmd->is_tx_filter);
1218         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1219                    "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1220                    p_filter_cmd->vport_to_add_to,
1221                    p_filter_cmd->vport_to_remove_from,
1222                    p_filter_cmd->mac[0], p_filter_cmd->mac[1],
1223                    p_filter_cmd->mac[2], p_filter_cmd->mac[3],
1224                    p_filter_cmd->mac[4], p_filter_cmd->mac[5],
1225                    p_filter_cmd->vlan);
1226
1227         return ECORE_SUCCESS;
1228 }
1229
1230 /*******************************************************************************
1231  * Description:
1232  *         Calculates crc 32 on a buffer
1233  *         Note: crc32_length MUST be aligned to 8
1234  * Return:
1235  ******************************************************************************/
1236 static u32 ecore_calc_crc32c(u8 *crc32_packet,
1237                              u32 crc32_length, u32 crc32_seed, u8 complement)
1238 {
1239         u32 byte = 0, bit = 0, crc32_result = crc32_seed;
1240         u8 msb = 0, current_byte = 0;
1241
1242         if ((crc32_packet == OSAL_NULL) ||
1243             (crc32_length == 0) || ((crc32_length % 8) != 0)) {
1244                 return crc32_result;
1245         }
1246
1247         for (byte = 0; byte < crc32_length; byte++) {
1248                 current_byte = crc32_packet[byte];
1249                 for (bit = 0; bit < 8; bit++) {
1250                         msb = (u8)(crc32_result >> 31);
1251                         crc32_result = crc32_result << 1;
1252                         if (msb != (0x1 & (current_byte >> bit))) {
1253                                 crc32_result = crc32_result ^ CRC32_POLY;
1254                                 crc32_result |= 1;
1255                         }
1256                 }
1257         }
1258
1259         return crc32_result;
1260 }
1261
1262 static u32 ecore_crc32c_le(u32 seed, u8 *mac, u32 len)
1263 {
1264         u32 packet_buf[2] = { 0 };
1265
1266         OSAL_MEMCPY((u8 *)(&packet_buf[0]), &mac[0], 6);
1267         return ecore_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1268 }
1269
1270 u8 ecore_mcast_bin_from_mac(u8 *mac)
1271 {
1272         u32 crc = ecore_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1273                                   mac, ETH_ALEN);
1274
1275         return crc & 0xff;
1276 }
1277
1278 static enum _ecore_status_t
1279 ecore_sp_eth_filter_mcast(struct ecore_hwfn *p_hwfn,
1280                           u16 opaque_fid,
1281                           struct ecore_filter_mcast *p_filter_cmd,
1282                           enum spq_mode comp_mode,
1283                           struct ecore_spq_comp_cb *p_comp_data)
1284 {
1285         unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1286         struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
1287         struct ecore_spq_entry *p_ent = OSAL_NULL;
1288         struct ecore_sp_init_data init_data;
1289         u8 abs_vport_id = 0;
1290         enum _ecore_status_t rc;
1291         int i;
1292
1293         if (p_filter_cmd->opcode == ECORE_FILTER_ADD)
1294                 rc = ecore_fw_vport(p_hwfn,
1295                                     p_filter_cmd->vport_to_add_to,
1296                                     &abs_vport_id);
1297         else
1298                 rc = ecore_fw_vport(p_hwfn,
1299                                     p_filter_cmd->vport_to_remove_from,
1300                                     &abs_vport_id);
1301         if (rc != ECORE_SUCCESS)
1302                 return rc;
1303
1304         /* Get SPQ entry */
1305         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1306         init_data.cid = ecore_spq_get_cid(p_hwfn);
1307         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1308         init_data.comp_mode = comp_mode;
1309         init_data.p_comp_data = p_comp_data;
1310
1311         rc = ecore_sp_init_request(p_hwfn, &p_ent,
1312                                    ETH_RAMROD_VPORT_UPDATE,
1313                                    PROTOCOLID_ETH, &init_data);
1314         if (rc != ECORE_SUCCESS) {
1315                 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1316                 return rc;
1317         }
1318
1319         p_ramrod = &p_ent->ramrod.vport_update;
1320         p_ramrod->common.update_approx_mcast_flg = 1;
1321
1322         /* explicitly clear out the entire vector */
1323         OSAL_MEMSET(&p_ramrod->approx_mcast.bins,
1324                     0, sizeof(p_ramrod->approx_mcast.bins));
1325         OSAL_MEMSET(bins, 0, sizeof(unsigned long) *
1326                     ETH_MULTICAST_MAC_BINS_IN_REGS);
1327         /* filter ADD op is explicit set op and it removes
1328         *  any existing filters for the vport.
1329         */
1330         if (p_filter_cmd->opcode == ECORE_FILTER_ADD) {
1331                 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1332                         u32 bit;
1333
1334                         bit = ecore_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1335                         OSAL_SET_BIT(bit, bins);
1336                 }
1337
1338                 /* Convert to correct endianity */
1339                 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
1340                         struct vport_update_ramrod_mcast *p_ramrod_bins;
1341                         u32 *p_bins = (u32 *)bins;
1342
1343                         p_ramrod_bins = &p_ramrod->approx_mcast;
1344                         p_ramrod_bins->bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
1345                 }
1346         }
1347
1348         p_ramrod->common.vport_id = abs_vport_id;
1349
1350         rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1351         if (rc != ECORE_SUCCESS)
1352                 DP_ERR(p_hwfn, "Multicast filter command failed %d\n", rc);
1353
1354         return rc;
1355 }
1356
1357 enum _ecore_status_t
1358 ecore_filter_mcast_cmd(struct ecore_dev *p_dev,
1359                        struct ecore_filter_mcast *p_filter_cmd,
1360                        enum spq_mode comp_mode,
1361                        struct ecore_spq_comp_cb *p_comp_data)
1362 {
1363         enum _ecore_status_t rc = ECORE_SUCCESS;
1364         int i;
1365
1366         /* only ADD and REMOVE operations are supported for multi-cast */
1367         if ((p_filter_cmd->opcode != ECORE_FILTER_ADD &&
1368              (p_filter_cmd->opcode != ECORE_FILTER_REMOVE)) ||
1369             (p_filter_cmd->num_mc_addrs > ECORE_MAX_MC_ADDRS)) {
1370                 return ECORE_INVAL;
1371         }
1372
1373         for_each_hwfn(p_dev, i) {
1374                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1375                 u16 opaque_fid;
1376
1377                 if (IS_VF(p_dev)) {
1378                         ecore_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1379                         continue;
1380                 }
1381
1382                 opaque_fid = p_hwfn->hw_info.opaque_fid;
1383                 rc = ecore_sp_eth_filter_mcast(p_hwfn,
1384                                                opaque_fid,
1385                                                p_filter_cmd,
1386                                                comp_mode, p_comp_data);
1387                 if (rc != ECORE_SUCCESS)
1388                         break;
1389         }
1390
1391         return rc;
1392 }
1393
1394 enum _ecore_status_t
1395 ecore_filter_ucast_cmd(struct ecore_dev *p_dev,
1396                        struct ecore_filter_ucast *p_filter_cmd,
1397                        enum spq_mode comp_mode,
1398                        struct ecore_spq_comp_cb *p_comp_data)
1399 {
1400         enum _ecore_status_t rc = ECORE_SUCCESS;
1401         int i;
1402
1403         for_each_hwfn(p_dev, i) {
1404                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1405                 u16 opaque_fid;
1406
1407                 if (IS_VF(p_dev)) {
1408                         rc = ecore_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1409                         continue;
1410                 }
1411
1412                 opaque_fid = p_hwfn->hw_info.opaque_fid;
1413                 rc = ecore_sp_eth_filter_ucast(p_hwfn,
1414                                                opaque_fid,
1415                                                p_filter_cmd,
1416                                                comp_mode, p_comp_data);
1417                 if (rc != ECORE_SUCCESS)
1418                         break;
1419         }
1420
1421         return rc;
1422 }
1423
1424 /* Statistics related code */
1425 static void __ecore_get_vport_pstats_addrlen(struct ecore_hwfn *p_hwfn,
1426                                              u32 *p_addr, u32 *p_len,
1427                                              u16 statistics_bin)
1428 {
1429         if (IS_PF(p_hwfn->p_dev)) {
1430                 *p_addr = BAR0_MAP_REG_PSDM_RAM +
1431                     PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1432                 *p_len = sizeof(struct eth_pstorm_per_queue_stat);
1433         } else {
1434                 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1435                 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1436
1437                 *p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1438                 *p_len = p_resp->pfdev_info.stats_info.pstats.len;
1439         }
1440 }
1441
1442 static void __ecore_get_vport_pstats(struct ecore_hwfn *p_hwfn,
1443                                      struct ecore_ptt *p_ptt,
1444                                      struct ecore_eth_stats *p_stats,
1445                                      u16 statistics_bin)
1446 {
1447         struct eth_pstorm_per_queue_stat pstats;
1448         u32 pstats_addr = 0, pstats_len = 0;
1449
1450         __ecore_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
1451                                          statistics_bin);
1452
1453         OSAL_MEMSET(&pstats, 0, sizeof(pstats));
1454         ecore_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
1455
1456         p_stats->tx_ucast_bytes += HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1457         p_stats->tx_mcast_bytes += HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1458         p_stats->tx_bcast_bytes += HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1459         p_stats->tx_ucast_pkts += HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1460         p_stats->tx_mcast_pkts += HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1461         p_stats->tx_bcast_pkts += HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1462         p_stats->tx_err_drop_pkts += HILO_64_REGPAIR(pstats.error_drop_pkts);
1463 }
1464
1465 static void __ecore_get_vport_tstats(struct ecore_hwfn *p_hwfn,
1466                                      struct ecore_ptt *p_ptt,
1467                                      struct ecore_eth_stats *p_stats,
1468                                      u16 statistics_bin)
1469 {
1470         struct tstorm_per_port_stat tstats;
1471         u32 tstats_addr, tstats_len;
1472
1473         if (IS_PF(p_hwfn->p_dev)) {
1474                 tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1475                     TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1476                 tstats_len = sizeof(struct tstorm_per_port_stat);
1477         } else {
1478                 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1479                 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1480
1481                 tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1482                 tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1483         }
1484
1485         OSAL_MEMSET(&tstats, 0, sizeof(tstats));
1486         ecore_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
1487
1488         p_stats->mftag_filter_discards +=
1489             HILO_64_REGPAIR(tstats.mftag_filter_discard);
1490         p_stats->mac_filter_discards +=
1491             HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
1492 }
1493
1494 static void __ecore_get_vport_ustats_addrlen(struct ecore_hwfn *p_hwfn,
1495                                              u32 *p_addr, u32 *p_len,
1496                                              u16 statistics_bin)
1497 {
1498         if (IS_PF(p_hwfn->p_dev)) {
1499                 *p_addr = BAR0_MAP_REG_USDM_RAM +
1500                     USTORM_QUEUE_STAT_OFFSET(statistics_bin);
1501                 *p_len = sizeof(struct eth_ustorm_per_queue_stat);
1502         } else {
1503                 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1504                 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1505
1506                 *p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1507                 *p_len = p_resp->pfdev_info.stats_info.ustats.len;
1508         }
1509 }
1510
1511 static void __ecore_get_vport_ustats(struct ecore_hwfn *p_hwfn,
1512                                      struct ecore_ptt *p_ptt,
1513                                      struct ecore_eth_stats *p_stats,
1514                                      u16 statistics_bin)
1515 {
1516         struct eth_ustorm_per_queue_stat ustats;
1517         u32 ustats_addr = 0, ustats_len = 0;
1518
1519         __ecore_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
1520                                          statistics_bin);
1521
1522         OSAL_MEMSET(&ustats, 0, sizeof(ustats));
1523         ecore_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
1524
1525         p_stats->rx_ucast_bytes += HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1526         p_stats->rx_mcast_bytes += HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1527         p_stats->rx_bcast_bytes += HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1528         p_stats->rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1529         p_stats->rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1530         p_stats->rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
1531 }
1532
1533 static void __ecore_get_vport_mstats_addrlen(struct ecore_hwfn *p_hwfn,
1534                                              u32 *p_addr, u32 *p_len,
1535                                              u16 statistics_bin)
1536 {
1537         if (IS_PF(p_hwfn->p_dev)) {
1538                 *p_addr = BAR0_MAP_REG_MSDM_RAM +
1539                     MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1540                 *p_len = sizeof(struct eth_mstorm_per_queue_stat);
1541         } else {
1542                 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1543                 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1544
1545                 *p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1546                 *p_len = p_resp->pfdev_info.stats_info.mstats.len;
1547         }
1548 }
1549
1550 static void __ecore_get_vport_mstats(struct ecore_hwfn *p_hwfn,
1551                                      struct ecore_ptt *p_ptt,
1552                                      struct ecore_eth_stats *p_stats,
1553                                      u16 statistics_bin)
1554 {
1555         struct eth_mstorm_per_queue_stat mstats;
1556         u32 mstats_addr = 0, mstats_len = 0;
1557
1558         __ecore_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
1559                                          statistics_bin);
1560
1561         OSAL_MEMSET(&mstats, 0, sizeof(mstats));
1562         ecore_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
1563
1564         p_stats->no_buff_discards += HILO_64_REGPAIR(mstats.no_buff_discard);
1565         p_stats->packet_too_big_discard +=
1566             HILO_64_REGPAIR(mstats.packet_too_big_discard);
1567         p_stats->ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
1568         p_stats->tpa_coalesced_pkts +=
1569             HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
1570         p_stats->tpa_coalesced_events +=
1571             HILO_64_REGPAIR(mstats.tpa_coalesced_events);
1572         p_stats->tpa_aborts_num += HILO_64_REGPAIR(mstats.tpa_aborts_num);
1573         p_stats->tpa_coalesced_bytes +=
1574             HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
1575 }
1576
1577 static void __ecore_get_vport_port_stats(struct ecore_hwfn *p_hwfn,
1578                                          struct ecore_ptt *p_ptt,
1579                                          struct ecore_eth_stats *p_stats)
1580 {
1581         struct port_stats port_stats;
1582         int j;
1583
1584         OSAL_MEMSET(&port_stats, 0, sizeof(port_stats));
1585
1586         ecore_memcpy_from(p_hwfn, p_ptt, &port_stats,
1587                           p_hwfn->mcp_info->port_addr +
1588                           OFFSETOF(struct public_port, stats),
1589                           sizeof(port_stats));
1590
1591         p_stats->rx_64_byte_packets += port_stats.eth.r64;
1592         p_stats->rx_65_to_127_byte_packets += port_stats.eth.r127;
1593         p_stats->rx_128_to_255_byte_packets += port_stats.eth.r255;
1594         p_stats->rx_256_to_511_byte_packets += port_stats.eth.r511;
1595         p_stats->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
1596         p_stats->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
1597         p_stats->rx_1519_to_1522_byte_packets += port_stats.eth.r1522;
1598         p_stats->rx_1519_to_2047_byte_packets += port_stats.eth.r2047;
1599         p_stats->rx_2048_to_4095_byte_packets += port_stats.eth.r4095;
1600         p_stats->rx_4096_to_9216_byte_packets += port_stats.eth.r9216;
1601         p_stats->rx_9217_to_16383_byte_packets += port_stats.eth.r16383;
1602         p_stats->rx_crc_errors += port_stats.eth.rfcs;
1603         p_stats->rx_mac_crtl_frames += port_stats.eth.rxcf;
1604         p_stats->rx_pause_frames += port_stats.eth.rxpf;
1605         p_stats->rx_pfc_frames += port_stats.eth.rxpp;
1606         p_stats->rx_align_errors += port_stats.eth.raln;
1607         p_stats->rx_carrier_errors += port_stats.eth.rfcr;
1608         p_stats->rx_oversize_packets += port_stats.eth.rovr;
1609         p_stats->rx_jabbers += port_stats.eth.rjbr;
1610         p_stats->rx_undersize_packets += port_stats.eth.rund;
1611         p_stats->rx_fragments += port_stats.eth.rfrg;
1612         p_stats->tx_64_byte_packets += port_stats.eth.t64;
1613         p_stats->tx_65_to_127_byte_packets += port_stats.eth.t127;
1614         p_stats->tx_128_to_255_byte_packets += port_stats.eth.t255;
1615         p_stats->tx_256_to_511_byte_packets += port_stats.eth.t511;
1616         p_stats->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
1617         p_stats->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
1618         p_stats->tx_1519_to_2047_byte_packets += port_stats.eth.t2047;
1619         p_stats->tx_2048_to_4095_byte_packets += port_stats.eth.t4095;
1620         p_stats->tx_4096_to_9216_byte_packets += port_stats.eth.t9216;
1621         p_stats->tx_9217_to_16383_byte_packets += port_stats.eth.t16383;
1622         p_stats->tx_pause_frames += port_stats.eth.txpf;
1623         p_stats->tx_pfc_frames += port_stats.eth.txpp;
1624         p_stats->tx_lpi_entry_count += port_stats.eth.tlpiec;
1625         p_stats->tx_total_collisions += port_stats.eth.tncl;
1626         p_stats->rx_mac_bytes += port_stats.eth.rbyte;
1627         p_stats->rx_mac_uc_packets += port_stats.eth.rxuca;
1628         p_stats->rx_mac_mc_packets += port_stats.eth.rxmca;
1629         p_stats->rx_mac_bc_packets += port_stats.eth.rxbca;
1630         p_stats->rx_mac_frames_ok += port_stats.eth.rxpok;
1631         p_stats->tx_mac_bytes += port_stats.eth.tbyte;
1632         p_stats->tx_mac_uc_packets += port_stats.eth.txuca;
1633         p_stats->tx_mac_mc_packets += port_stats.eth.txmca;
1634         p_stats->tx_mac_bc_packets += port_stats.eth.txbca;
1635         p_stats->tx_mac_ctrl_frames += port_stats.eth.txcf;
1636         for (j = 0; j < 8; j++) {
1637                 p_stats->brb_truncates += port_stats.brb.brb_truncate[j];
1638                 p_stats->brb_discards += port_stats.brb.brb_discard[j];
1639         }
1640 }
1641
1642 void __ecore_get_vport_stats(struct ecore_hwfn *p_hwfn,
1643                              struct ecore_ptt *p_ptt,
1644                              struct ecore_eth_stats *stats,
1645                              u16 statistics_bin, bool b_get_port_stats)
1646 {
1647         __ecore_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
1648         __ecore_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
1649         __ecore_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
1650         __ecore_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
1651
1652 #ifndef ASIC_ONLY
1653         /* Avoid getting PORT stats for emulation. */
1654         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1655                 return;
1656 #endif
1657
1658         if (b_get_port_stats && p_hwfn->mcp_info)
1659                 __ecore_get_vport_port_stats(p_hwfn, p_ptt, stats);
1660 }
1661
1662 static void _ecore_get_vport_stats(struct ecore_dev *p_dev,
1663                                    struct ecore_eth_stats *stats)
1664 {
1665         u8 fw_vport = 0;
1666         int i;
1667
1668         OSAL_MEMSET(stats, 0, sizeof(*stats));
1669
1670         for_each_hwfn(p_dev, i) {
1671                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1672                 struct ecore_ptt *p_ptt = IS_PF(p_dev) ?
1673                     ecore_ptt_acquire(p_hwfn) : OSAL_NULL;
1674
1675                 if (IS_PF(p_dev)) {
1676                         /* The main vport index is relative first */
1677                         if (ecore_fw_vport(p_hwfn, 0, &fw_vport)) {
1678                                 DP_ERR(p_hwfn, "No vport available!\n");
1679                                 goto out;
1680                         }
1681                 }
1682
1683                 if (IS_PF(p_dev) && !p_ptt) {
1684                         DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1685                         continue;
1686                 }
1687
1688                 __ecore_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1689                                         IS_PF(p_dev) ? true : false);
1690
1691 out:
1692                 if (IS_PF(p_dev) && p_ptt)
1693                         ecore_ptt_release(p_hwfn, p_ptt);
1694         }
1695 }
1696
1697 void ecore_get_vport_stats(struct ecore_dev *p_dev,
1698                            struct ecore_eth_stats *stats)
1699 {
1700         u32 i;
1701
1702         if (!p_dev) {
1703                 OSAL_MEMSET(stats, 0, sizeof(*stats));
1704                 return;
1705         }
1706
1707         _ecore_get_vport_stats(p_dev, stats);
1708
1709         if (!p_dev->reset_stats)
1710                 return;
1711
1712         /* Reduce the statistics baseline */
1713         for (i = 0; i < sizeof(struct ecore_eth_stats) / sizeof(u64); i++)
1714                 ((u64 *)stats)[i] -= ((u64 *)p_dev->reset_stats)[i];
1715 }
1716
1717 /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
1718 void ecore_reset_vport_stats(struct ecore_dev *p_dev)
1719 {
1720         int i;
1721
1722         for_each_hwfn(p_dev, i) {
1723                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1724                 struct eth_mstorm_per_queue_stat mstats;
1725                 struct eth_ustorm_per_queue_stat ustats;
1726                 struct eth_pstorm_per_queue_stat pstats;
1727                 struct ecore_ptt *p_ptt = IS_PF(p_dev) ?
1728                     ecore_ptt_acquire(p_hwfn) : OSAL_NULL;
1729                 u32 addr = 0, len = 0;
1730
1731                 if (IS_PF(p_dev) && !p_ptt) {
1732                         DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1733                         continue;
1734                 }
1735
1736                 OSAL_MEMSET(&mstats, 0, sizeof(mstats));
1737                 __ecore_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
1738                 ecore_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
1739
1740                 OSAL_MEMSET(&ustats, 0, sizeof(ustats));
1741                 __ecore_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
1742                 ecore_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
1743
1744                 OSAL_MEMSET(&pstats, 0, sizeof(pstats));
1745                 __ecore_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
1746                 ecore_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
1747
1748                 if (IS_PF(p_dev))
1749                         ecore_ptt_release(p_hwfn, p_ptt);
1750         }
1751
1752         /* PORT statistics are not necessarily reset, so we need to
1753          * read and create a baseline for future statistics.
1754          */
1755         if (!p_dev->reset_stats)
1756                 DP_INFO(p_dev, "Reset stats not allocated\n");
1757         else
1758                 _ecore_get_vport_stats(p_dev, p_dev->reset_stats);
1759 }