2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
12 #include "ecore_status.h"
13 #include "ecore_hsi_eth.h"
14 #include "ecore_chain.h"
15 #include "ecore_spq.h"
16 #include "ecore_init_fw_funcs.h"
17 #include "ecore_cxt.h"
19 #include "ecore_sp_commands.h"
20 #include "ecore_gtt_reg_addr.h"
21 #include "ecore_iro.h"
23 #include "ecore_int.h"
26 #include "ecore_sriov.h"
27 #include "ecore_mcp.h"
29 #define ECORE_MAX_SGES_NUM 16
30 #define CRC32_POLY 0x1edc6f41
33 ecore_sp_eth_vport_start(struct ecore_hwfn *p_hwfn,
34 struct ecore_sp_vport_start_params *p_params)
36 struct vport_start_ramrod_data *p_ramrod = OSAL_NULL;
37 struct ecore_spq_entry *p_ent = OSAL_NULL;
38 struct ecore_sp_init_data init_data;
40 enum _ecore_status_t rc = ECORE_NOTIMPL;
43 rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
44 if (rc != ECORE_SUCCESS)
48 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
49 init_data.cid = ecore_spq_get_cid(p_hwfn);
50 init_data.opaque_fid = p_params->opaque_fid;
51 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
53 rc = ecore_sp_init_request(p_hwfn, &p_ent,
54 ETH_RAMROD_VPORT_START,
55 PROTOCOLID_ETH, &init_data);
56 if (rc != ECORE_SUCCESS)
59 p_ramrod = &p_ent->ramrod.vport_start;
60 p_ramrod->vport_id = abs_vport_id;
62 p_ramrod->mtu = OSAL_CPU_TO_LE16(p_params->mtu);
63 p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
64 p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts;
65 p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
66 p_ramrod->untagged = p_params->only_untagged;
67 p_ramrod->zero_placement_offset = p_params->zero_placement_offset;
69 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
70 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
72 p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(rx_mode);
74 /* TPA related fields */
75 OSAL_MEMSET(&p_ramrod->tpa_param, 0,
76 sizeof(struct eth_vport_tpa_param));
77 p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
79 switch (p_params->tpa_mode) {
80 case ECORE_TPA_MODE_GRO:
81 p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
82 p_ramrod->tpa_param.tpa_max_size = (u16)-1;
83 p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
84 p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
85 p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
86 p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
87 p_ramrod->tpa_param.tpa_ipv4_tunn_en_flg = 1;
88 p_ramrod->tpa_param.tpa_ipv6_tunn_en_flg = 1;
89 p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
90 p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
96 p_ramrod->tx_switching_en = p_params->tx_switching;
98 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
99 p_ramrod->tx_switching_en = 0;
102 p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac;
103 p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype;
105 /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
106 p_ramrod->sw_fid = ecore_concrete_to_sw_fid(p_hwfn->p_dev,
107 p_params->concrete_fid);
109 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
113 ecore_sp_vport_start(struct ecore_hwfn *p_hwfn,
114 struct ecore_sp_vport_start_params *p_params)
116 if (IS_VF(p_hwfn->p_dev))
117 return ecore_vf_pf_vport_start(p_hwfn, p_params->vport_id,
119 p_params->remove_inner_vlan,
121 p_params->max_buffers_per_cqe,
122 p_params->only_untagged);
124 return ecore_sp_eth_vport_start(p_hwfn, p_params);
127 static enum _ecore_status_t
128 ecore_sp_vport_update_rss(struct ecore_hwfn *p_hwfn,
129 struct vport_update_ramrod_data *p_ramrod,
130 struct ecore_rss_params *p_rss)
132 enum _ecore_status_t rc = ECORE_SUCCESS;
133 struct eth_vport_rss_config *p_config;
134 u16 abs_l2_queue = 0;
138 p_ramrod->common.update_rss_flg = 0;
141 p_config = &p_ramrod->rss_config;
143 OSAL_BUILD_BUG_ON(ECORE_RSS_IND_TABLE_SIZE !=
144 ETH_RSS_IND_TABLE_ENTRIES_NUM);
146 rc = ecore_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
147 if (rc != ECORE_SUCCESS)
150 p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
151 p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
152 p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
153 p_config->update_rss_key = p_rss->update_rss_key;
155 p_config->rss_mode = p_rss->rss_enable ?
156 ETH_VPORT_RSS_MODE_REGULAR : ETH_VPORT_RSS_MODE_DISABLED;
158 p_config->capabilities = 0;
160 SET_FIELD(p_config->capabilities,
161 ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
162 !!(p_rss->rss_caps & ECORE_RSS_IPV4));
163 SET_FIELD(p_config->capabilities,
164 ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
165 !!(p_rss->rss_caps & ECORE_RSS_IPV6));
166 SET_FIELD(p_config->capabilities,
167 ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
168 !!(p_rss->rss_caps & ECORE_RSS_IPV4_TCP));
169 SET_FIELD(p_config->capabilities,
170 ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
171 !!(p_rss->rss_caps & ECORE_RSS_IPV6_TCP));
172 SET_FIELD(p_config->capabilities,
173 ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
174 !!(p_rss->rss_caps & ECORE_RSS_IPV4_UDP));
175 SET_FIELD(p_config->capabilities,
176 ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
177 !!(p_rss->rss_caps & ECORE_RSS_IPV6_UDP));
178 p_config->tbl_size = p_rss->rss_table_size_log;
179 p_config->capabilities = OSAL_CPU_TO_LE16(p_config->capabilities);
181 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
182 "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
183 p_ramrod->common.update_rss_flg,
185 p_config->update_rss_capabilities,
186 p_config->capabilities,
187 p_config->update_rss_ind_table, p_config->update_rss_key);
189 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
190 rc = ecore_fw_l2_queue(p_hwfn,
191 (u8)p_rss->rss_ind_table[i],
193 if (rc != ECORE_SUCCESS)
196 p_config->indirection_table[i] = OSAL_CPU_TO_LE16(abs_l2_queue);
197 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP, "i= %d, queue = %d\n",
198 i, p_config->indirection_table[i]);
201 for (i = 0; i < 10; i++)
202 p_config->rss_key[i] = OSAL_CPU_TO_LE32(p_rss->rss_key[i]);
208 ecore_sp_update_accept_mode(struct ecore_hwfn *p_hwfn,
209 struct vport_update_ramrod_data *p_ramrod,
210 struct ecore_filter_accept_flags accept_flags)
212 p_ramrod->common.update_rx_mode_flg =
213 accept_flags.update_rx_mode_config;
214 p_ramrod->common.update_tx_mode_flg =
215 accept_flags.update_tx_mode_config;
218 /* On B0 emulation we cannot enable Tx, since this would cause writes
219 * to PVFC HW block which isn't implemented in emulation.
221 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
222 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
223 "Non-Asic - prevent Tx mode in vport update\n");
224 p_ramrod->common.update_tx_mode_flg = 0;
228 /* Set Rx mode accept flags */
229 if (p_ramrod->common.update_rx_mode_flg) {
230 u8 accept_filter = accept_flags.rx_accept_filter;
233 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
234 !(!!(accept_filter & ECORE_ACCEPT_UCAST_MATCHED) ||
235 !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)));
237 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
238 !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED));
240 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
241 !(!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) ||
242 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
244 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
245 (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
246 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
248 SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
249 !!(accept_filter & ECORE_ACCEPT_BCAST));
251 p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(state);
252 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
253 "p_ramrod->rx_mode.state = 0x%x\n",
257 /* Set Tx mode accept flags */
258 if (p_ramrod->common.update_tx_mode_flg) {
259 u8 accept_filter = accept_flags.tx_accept_filter;
262 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
263 !!(accept_filter & ECORE_ACCEPT_NONE));
265 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
266 !!(accept_filter & ECORE_ACCEPT_NONE));
268 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
269 (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
270 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
272 SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
273 !!(accept_filter & ECORE_ACCEPT_BCAST));
275 p_ramrod->tx_mode.state = OSAL_CPU_TO_LE16(state);
276 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
277 "p_ramrod->tx_mode.state = 0x%x\n",
283 ecore_sp_vport_update_sge_tpa(struct ecore_hwfn *p_hwfn,
284 struct vport_update_ramrod_data *p_ramrod,
285 struct ecore_sge_tpa_params *p_params)
287 struct eth_vport_tpa_param *p_tpa;
290 p_ramrod->common.update_tpa_param_flg = 0;
291 p_ramrod->common.update_tpa_en_flg = 0;
292 p_ramrod->common.update_tpa_param_flg = 0;
296 p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
297 p_tpa = &p_ramrod->tpa_param;
298 p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
299 p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
300 p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
301 p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
303 p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
304 p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
305 p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
306 p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
307 p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
308 p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
309 p_tpa->tpa_max_size = p_params->tpa_max_size;
310 p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
311 p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
315 ecore_sp_update_mcast_bin(struct ecore_hwfn *p_hwfn,
316 struct vport_update_ramrod_data *p_ramrod,
317 struct ecore_sp_vport_update_params *p_params)
321 OSAL_MEMSET(&p_ramrod->approx_mcast.bins, 0,
322 sizeof(p_ramrod->approx_mcast.bins));
324 if (!p_params->update_approx_mcast_flg)
327 p_ramrod->common.update_approx_mcast_flg = 1;
328 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
329 u32 *p_bins = (u32 *)p_params->bins;
331 p_ramrod->approx_mcast.bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
336 ecore_sp_vport_update(struct ecore_hwfn *p_hwfn,
337 struct ecore_sp_vport_update_params *p_params,
338 enum spq_mode comp_mode,
339 struct ecore_spq_comp_cb *p_comp_data)
341 struct ecore_rss_params *p_rss_params = p_params->rss_params;
342 struct vport_update_ramrod_data_cmn *p_cmn;
343 struct ecore_sp_init_data init_data;
344 struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
345 struct ecore_spq_entry *p_ent = OSAL_NULL;
346 u8 abs_vport_id = 0, val;
347 enum _ecore_status_t rc = ECORE_NOTIMPL;
349 if (IS_VF(p_hwfn->p_dev)) {
350 rc = ecore_vf_pf_vport_update(p_hwfn, p_params);
354 rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
355 if (rc != ECORE_SUCCESS)
359 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
360 init_data.cid = ecore_spq_get_cid(p_hwfn);
361 init_data.opaque_fid = p_params->opaque_fid;
362 init_data.comp_mode = comp_mode;
363 init_data.p_comp_data = p_comp_data;
365 rc = ecore_sp_init_request(p_hwfn, &p_ent,
366 ETH_RAMROD_VPORT_UPDATE,
367 PROTOCOLID_ETH, &init_data);
368 if (rc != ECORE_SUCCESS)
371 /* Copy input params to ramrod according to FW struct */
372 p_ramrod = &p_ent->ramrod.vport_update;
373 p_cmn = &p_ramrod->common;
375 p_cmn->vport_id = abs_vport_id;
377 p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
378 p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
379 p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
380 p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
382 p_cmn->accept_any_vlan = p_params->accept_any_vlan;
383 val = p_params->update_accept_any_vlan_flg;
384 p_cmn->update_accept_any_vlan_flg = val;
386 p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
387 val = p_params->update_inner_vlan_removal_flg;
388 p_cmn->update_inner_vlan_removal_en_flg = val;
390 p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
391 val = p_params->update_default_vlan_enable_flg;
392 p_cmn->update_default_vlan_en_flg = val;
394 p_cmn->default_vlan = OSAL_CPU_TO_LE16(p_params->default_vlan);
395 p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
397 p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
399 p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
402 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
403 if (p_ramrod->common.tx_switching_en ||
404 p_ramrod->common.update_tx_switching_en_flg) {
405 DP_NOTICE(p_hwfn, false,
406 "FPGA - why are we seeing tx-switching? Overriding it\n");
407 p_ramrod->common.tx_switching_en = 0;
408 p_ramrod->common.update_tx_switching_en_flg = 1;
411 p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
413 p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
414 val = p_params->update_anti_spoofing_en_flg;
415 p_ramrod->common.update_anti_spoofing_en_flg = val;
417 rc = ecore_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
418 if (rc != ECORE_SUCCESS) {
419 /* Return spq entry which is taken in ecore_sp_init_request()*/
420 ecore_spq_return_entry(p_hwfn, p_ent);
424 /* Update mcast bins for VFs, PF doesn't use this functionality */
425 ecore_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
427 ecore_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
428 ecore_sp_vport_update_sge_tpa(p_hwfn, p_ramrod,
429 p_params->sge_tpa_params);
431 p_ramrod->common.update_mtu_flg = 1;
432 p_ramrod->common.mtu = OSAL_CPU_TO_LE16(p_params->mtu);
435 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
438 enum _ecore_status_t ecore_sp_vport_stop(struct ecore_hwfn *p_hwfn,
439 u16 opaque_fid, u8 vport_id)
441 struct vport_stop_ramrod_data *p_ramrod;
442 struct ecore_sp_init_data init_data;
443 struct ecore_spq_entry *p_ent;
445 enum _ecore_status_t rc;
447 if (IS_VF(p_hwfn->p_dev))
448 return ecore_vf_pf_vport_stop(p_hwfn);
450 rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
451 if (rc != ECORE_SUCCESS)
455 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
456 init_data.cid = ecore_spq_get_cid(p_hwfn);
457 init_data.opaque_fid = opaque_fid;
458 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
460 rc = ecore_sp_init_request(p_hwfn, &p_ent,
461 ETH_RAMROD_VPORT_STOP,
462 PROTOCOLID_ETH, &init_data);
463 if (rc != ECORE_SUCCESS)
466 p_ramrod = &p_ent->ramrod.vport_stop;
467 p_ramrod->vport_id = abs_vport_id;
469 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
472 static enum _ecore_status_t
473 ecore_vf_pf_accept_flags(struct ecore_hwfn *p_hwfn,
474 struct ecore_filter_accept_flags *p_accept_flags)
476 struct ecore_sp_vport_update_params s_params;
478 OSAL_MEMSET(&s_params, 0, sizeof(s_params));
479 OSAL_MEMCPY(&s_params.accept_flags, p_accept_flags,
480 sizeof(struct ecore_filter_accept_flags));
482 return ecore_vf_pf_vport_update(p_hwfn, &s_params);
486 ecore_filter_accept_cmd(struct ecore_dev *p_dev,
488 struct ecore_filter_accept_flags accept_flags,
489 u8 update_accept_any_vlan,
491 enum spq_mode comp_mode,
492 struct ecore_spq_comp_cb *p_comp_data)
494 struct ecore_sp_vport_update_params vport_update_params;
497 /* Prepare and send the vport rx_mode change */
498 OSAL_MEMSET(&vport_update_params, 0, sizeof(vport_update_params));
499 vport_update_params.vport_id = vport;
500 vport_update_params.accept_flags = accept_flags;
501 vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
502 vport_update_params.accept_any_vlan = accept_any_vlan;
504 for_each_hwfn(p_dev, i) {
505 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
507 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
510 rc = ecore_vf_pf_accept_flags(p_hwfn, &accept_flags);
511 if (rc != ECORE_SUCCESS)
516 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
517 comp_mode, p_comp_data);
518 if (rc != ECORE_SUCCESS) {
519 DP_ERR(p_dev, "Update rx_mode failed %d\n", rc);
523 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
524 "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
525 accept_flags.rx_accept_filter,
526 accept_flags.tx_accept_filter);
528 if (update_accept_any_vlan)
529 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
530 "accept_any_vlan=%d configured\n",
537 static void ecore_sp_release_queue_cid(struct ecore_hwfn *p_hwfn,
538 struct ecore_hw_cid_data *p_cid_data)
540 if (!p_cid_data->b_cid_allocated)
543 ecore_cxt_release_cid(p_hwfn, p_cid_data->cid);
544 p_cid_data->b_cid_allocated = false;
548 ecore_sp_eth_rxq_start_ramrod(struct ecore_hwfn *p_hwfn,
558 dma_addr_t bd_chain_phys_addr,
559 dma_addr_t cqe_pbl_addr,
560 u16 cqe_pbl_size, bool b_use_zone_a_prod)
562 struct rx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
563 struct ecore_spq_entry *p_ent = OSAL_NULL;
564 struct ecore_sp_init_data init_data;
565 struct ecore_hw_cid_data *p_rx_cid;
568 enum _ecore_status_t rc = ECORE_NOTIMPL;
570 /* Store information for the stop */
571 p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
573 p_rx_cid->opaque_fid = opaque_fid;
574 p_rx_cid->vport_id = vport_id;
576 rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
577 if (rc != ECORE_SUCCESS)
580 rc = ecore_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
581 if (rc != ECORE_SUCCESS)
584 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
585 "opaque_fid=0x%x, cid=0x%x, rx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
586 opaque_fid, cid, rx_queue_id, vport_id, sb);
589 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
591 init_data.opaque_fid = opaque_fid;
592 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
594 rc = ecore_sp_init_request(p_hwfn, &p_ent,
595 ETH_RAMROD_RX_QUEUE_START,
596 PROTOCOLID_ETH, &init_data);
597 if (rc != ECORE_SUCCESS)
600 p_ramrod = &p_ent->ramrod.rx_queue_start;
602 p_ramrod->sb_id = OSAL_CPU_TO_LE16(sb);
603 p_ramrod->sb_index = sb_index;
604 p_ramrod->vport_id = abs_vport_id;
605 p_ramrod->stats_counter_id = stats_id;
606 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
607 p_ramrod->complete_cqe_flg = 0;
608 p_ramrod->complete_event_flg = 1;
610 p_ramrod->bd_max_bytes = OSAL_CPU_TO_LE16(bd_max_bytes);
611 DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
613 p_ramrod->num_of_pbl_pages = OSAL_CPU_TO_LE16(cqe_pbl_size);
614 DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
616 if (vf_rx_queue_id || b_use_zone_a_prod) {
617 p_ramrod->vf_rx_prod_index = vf_rx_queue_id;
618 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
619 "Queue%s is meant for VF rxq[%02x]\n",
620 b_use_zone_a_prod ? " [legacy]" : "",
622 p_ramrod->vf_rx_prod_use_zone_a = b_use_zone_a_prod;
625 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
628 enum _ecore_status_t ecore_sp_eth_rx_queue_start(struct ecore_hwfn *p_hwfn,
636 dma_addr_t bd_chain_phys_addr,
637 dma_addr_t cqe_pbl_addr,
639 void OSAL_IOMEM **pp_prod)
641 struct ecore_hw_cid_data *p_rx_cid;
642 u32 init_prod_val = 0;
643 u16 abs_l2_queue = 0;
645 enum _ecore_status_t rc;
647 if (IS_VF(p_hwfn->p_dev)) {
648 return ecore_vf_pf_rxq_start(p_hwfn,
655 cqe_pbl_size, pp_prod);
658 rc = ecore_fw_l2_queue(p_hwfn, rx_queue_id, &abs_l2_queue);
659 if (rc != ECORE_SUCCESS)
662 rc = ecore_fw_vport(p_hwfn, stats_id, &abs_stats_id);
663 if (rc != ECORE_SUCCESS)
666 *pp_prod = (u8 OSAL_IOMEM *)p_hwfn->regview +
667 GTT_BAR0_MAP_REG_MSDM_RAM +
668 MSTORM_ETH_PF_PRODS_OFFSET(abs_l2_queue);
670 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
671 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
672 (u32 *)(&init_prod_val));
674 /* Allocate a CID for the queue */
675 p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
676 rc = ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
678 if (rc != ECORE_SUCCESS) {
679 DP_NOTICE(p_hwfn, true, "Failed to acquire cid\n");
682 p_rx_cid->b_cid_allocated = true;
684 rc = ecore_sp_eth_rxq_start_ramrod(p_hwfn,
699 if (rc != ECORE_SUCCESS)
700 ecore_sp_release_queue_cid(p_hwfn, p_rx_cid);
706 ecore_sp_eth_rx_queues_update(struct ecore_hwfn *p_hwfn,
710 u8 complete_event_flg,
711 enum spq_mode comp_mode,
712 struct ecore_spq_comp_cb *p_comp_data)
714 struct rx_queue_update_ramrod_data *p_ramrod = OSAL_NULL;
715 struct ecore_spq_entry *p_ent = OSAL_NULL;
716 struct ecore_sp_init_data init_data;
717 struct ecore_hw_cid_data *p_rx_cid;
718 u16 qid, abs_rx_q_id = 0;
719 enum _ecore_status_t rc = ECORE_NOTIMPL;
722 if (IS_VF(p_hwfn->p_dev))
723 return ecore_vf_pf_rxqs_update(p_hwfn,
729 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
730 init_data.comp_mode = comp_mode;
731 init_data.p_comp_data = p_comp_data;
733 for (i = 0; i < num_rxqs; i++) {
734 qid = rx_queue_id + i;
735 p_rx_cid = &p_hwfn->p_rx_cids[qid];
738 init_data.cid = p_rx_cid->cid;
739 init_data.opaque_fid = p_rx_cid->opaque_fid;
741 rc = ecore_sp_init_request(p_hwfn, &p_ent,
742 ETH_RAMROD_RX_QUEUE_UPDATE,
743 PROTOCOLID_ETH, &init_data);
744 if (rc != ECORE_SUCCESS)
747 p_ramrod = &p_ent->ramrod.rx_queue_update;
749 ecore_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
750 ecore_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
751 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
752 p_ramrod->complete_cqe_flg = complete_cqe_flg;
753 p_ramrod->complete_event_flg = complete_event_flg;
755 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
764 ecore_sp_eth_rx_queue_stop(struct ecore_hwfn *p_hwfn,
766 bool eq_completion_only, bool cqe_completion)
768 struct ecore_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
769 struct rx_queue_stop_ramrod_data *p_ramrod = OSAL_NULL;
770 struct ecore_spq_entry *p_ent = OSAL_NULL;
771 struct ecore_sp_init_data init_data;
773 enum _ecore_status_t rc = ECORE_NOTIMPL;
775 if (IS_VF(p_hwfn->p_dev))
776 return ecore_vf_pf_rxq_stop(p_hwfn, rx_queue_id,
780 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
781 init_data.cid = p_rx_cid->cid;
782 init_data.opaque_fid = p_rx_cid->opaque_fid;
783 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
785 rc = ecore_sp_init_request(p_hwfn, &p_ent,
786 ETH_RAMROD_RX_QUEUE_STOP,
787 PROTOCOLID_ETH, &init_data);
788 if (rc != ECORE_SUCCESS)
791 p_ramrod = &p_ent->ramrod.rx_queue_stop;
793 ecore_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
794 ecore_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
795 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
797 /* Cleaning the queue requires the completion to arrive there.
798 * In addition, VFs require the answer to come as eqe to PF.
800 p_ramrod->complete_cqe_flg = (!!(p_rx_cid->opaque_fid ==
801 p_hwfn->hw_info.opaque_fid) &&
802 !eq_completion_only) || cqe_completion;
803 p_ramrod->complete_event_flg = !(p_rx_cid->opaque_fid ==
804 p_hwfn->hw_info.opaque_fid) ||
807 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
808 if (rc != ECORE_SUCCESS)
811 ecore_sp_release_queue_cid(p_hwfn, p_rx_cid);
817 ecore_sp_eth_txq_start_ramrod(struct ecore_hwfn *p_hwfn,
827 union ecore_qm_pq_params *p_pq_params)
829 struct tx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
830 struct ecore_spq_entry *p_ent = OSAL_NULL;
831 struct ecore_sp_init_data init_data;
832 struct ecore_hw_cid_data *p_tx_cid;
833 u16 pq_id, abs_tx_q_id = 0;
835 enum _ecore_status_t rc = ECORE_NOTIMPL;
837 /* Store information for the stop */
838 p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
840 p_tx_cid->opaque_fid = opaque_fid;
842 rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
843 if (rc != ECORE_SUCCESS)
846 rc = ecore_fw_l2_queue(p_hwfn, tx_queue_id, &abs_tx_q_id);
847 if (rc != ECORE_SUCCESS)
851 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
853 init_data.opaque_fid = opaque_fid;
854 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
856 rc = ecore_sp_init_request(p_hwfn, &p_ent,
857 ETH_RAMROD_TX_QUEUE_START,
858 PROTOCOLID_ETH, &init_data);
859 if (rc != ECORE_SUCCESS)
862 p_ramrod = &p_ent->ramrod.tx_queue_start;
863 p_ramrod->vport_id = abs_vport_id;
865 p_ramrod->sb_id = OSAL_CPU_TO_LE16(sb);
866 p_ramrod->sb_index = sb_index;
867 p_ramrod->stats_counter_id = stats_id;
869 p_ramrod->queue_zone_id = OSAL_CPU_TO_LE16(abs_tx_q_id);
871 p_ramrod->pbl_size = OSAL_CPU_TO_LE16(pbl_size);
872 DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
874 pq_id = ecore_get_qm_pq(p_hwfn, PROTOCOLID_ETH, p_pq_params);
875 p_ramrod->qm_pq_id = OSAL_CPU_TO_LE16(pq_id);
877 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
880 enum _ecore_status_t ecore_sp_eth_tx_queue_start(struct ecore_hwfn *p_hwfn,
890 void OSAL_IOMEM **pp_doorbell)
892 struct ecore_hw_cid_data *p_tx_cid;
893 union ecore_qm_pq_params pq_params;
895 enum _ecore_status_t rc;
897 if (IS_VF(p_hwfn->p_dev)) {
898 return ecore_vf_pf_txq_start(p_hwfn,
907 rc = ecore_fw_vport(p_hwfn, stats_id, &abs_stats_id);
908 if (rc != ECORE_SUCCESS)
911 p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
912 OSAL_MEMSET(p_tx_cid, 0, sizeof(*p_tx_cid));
913 OSAL_MEMSET(&pq_params, 0, sizeof(pq_params));
915 pq_params.eth.tc = tc;
917 /* Allocate a CID for the queue */
918 rc = ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &p_tx_cid->cid);
919 if (rc != ECORE_SUCCESS) {
920 DP_NOTICE(p_hwfn, true, "Failed to acquire cid\n");
923 p_tx_cid->b_cid_allocated = true;
925 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
926 "opaque_fid=0x%x, cid=0x%x, tx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
927 opaque_fid, p_tx_cid->cid, tx_queue_id,
930 /* TODO - set tc in the pq_params for multi-cos */
931 rc = ecore_sp_eth_txq_start_ramrod(p_hwfn,
943 *pp_doorbell = (u8 OSAL_IOMEM *)p_hwfn->doorbells +
944 DB_ADDR(p_tx_cid->cid, DQ_DEMS_LEGACY);
946 if (rc != ECORE_SUCCESS)
947 ecore_sp_release_queue_cid(p_hwfn, p_tx_cid);
952 enum _ecore_status_t ecore_sp_eth_tx_queue_update(struct ecore_hwfn *p_hwfn)
954 return ECORE_NOTIMPL;
957 enum _ecore_status_t ecore_sp_eth_tx_queue_stop(struct ecore_hwfn *p_hwfn,
960 struct ecore_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
961 struct ecore_spq_entry *p_ent = OSAL_NULL;
962 struct ecore_sp_init_data init_data;
963 enum _ecore_status_t rc = ECORE_NOTIMPL;
965 if (IS_VF(p_hwfn->p_dev))
966 return ecore_vf_pf_txq_stop(p_hwfn, tx_queue_id);
969 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
970 init_data.cid = p_tx_cid->cid;
971 init_data.opaque_fid = p_tx_cid->opaque_fid;
972 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
974 rc = ecore_sp_init_request(p_hwfn, &p_ent,
975 ETH_RAMROD_TX_QUEUE_STOP,
976 PROTOCOLID_ETH, &init_data);
977 if (rc != ECORE_SUCCESS)
980 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
981 if (rc != ECORE_SUCCESS)
984 ecore_sp_release_queue_cid(p_hwfn, p_tx_cid);
988 static enum eth_filter_action
989 ecore_filter_action(enum ecore_filter_opcode opcode)
991 enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
994 case ECORE_FILTER_ADD:
995 action = ETH_FILTER_ACTION_ADD;
997 case ECORE_FILTER_REMOVE:
998 action = ETH_FILTER_ACTION_REMOVE;
1000 case ECORE_FILTER_FLUSH:
1001 action = ETH_FILTER_ACTION_REMOVE_ALL;
1004 action = MAX_ETH_FILTER_ACTION;
1010 static void ecore_set_fw_mac_addr(__le16 *fw_msb,
1011 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
1013 ((u8 *)fw_msb)[0] = mac[1];
1014 ((u8 *)fw_msb)[1] = mac[0];
1015 ((u8 *)fw_mid)[0] = mac[3];
1016 ((u8 *)fw_mid)[1] = mac[2];
1017 ((u8 *)fw_lsb)[0] = mac[5];
1018 ((u8 *)fw_lsb)[1] = mac[4];
1021 static enum _ecore_status_t
1022 ecore_filter_ucast_common(struct ecore_hwfn *p_hwfn,
1024 struct ecore_filter_ucast *p_filter_cmd,
1025 struct vport_filter_update_ramrod_data **pp_ramrod,
1026 struct ecore_spq_entry **pp_ent,
1027 enum spq_mode comp_mode,
1028 struct ecore_spq_comp_cb *p_comp_data)
1030 u8 vport_to_add_to = 0, vport_to_remove_from = 0;
1031 struct vport_filter_update_ramrod_data *p_ramrod;
1032 struct eth_filter_cmd *p_first_filter;
1033 struct eth_filter_cmd *p_second_filter;
1034 struct ecore_sp_init_data init_data;
1035 enum eth_filter_action action;
1036 enum _ecore_status_t rc;
1038 rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1039 &vport_to_remove_from);
1040 if (rc != ECORE_SUCCESS)
1043 rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1045 if (rc != ECORE_SUCCESS)
1049 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1050 init_data.cid = ecore_spq_get_cid(p_hwfn);
1051 init_data.opaque_fid = opaque_fid;
1052 init_data.comp_mode = comp_mode;
1053 init_data.p_comp_data = p_comp_data;
1055 rc = ecore_sp_init_request(p_hwfn, pp_ent,
1056 ETH_RAMROD_FILTERS_UPDATE,
1057 PROTOCOLID_ETH, &init_data);
1058 if (rc != ECORE_SUCCESS)
1061 *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
1062 p_ramrod = *pp_ramrod;
1063 p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
1064 p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
1067 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1068 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1069 "Non-Asic - prevent Tx filters\n");
1070 p_ramrod->filter_cmd_hdr.tx = 0;
1074 switch (p_filter_cmd->opcode) {
1075 case ECORE_FILTER_REPLACE:
1076 case ECORE_FILTER_MOVE:
1077 p_ramrod->filter_cmd_hdr.cmd_cnt = 2;
1080 p_ramrod->filter_cmd_hdr.cmd_cnt = 1;
1084 p_first_filter = &p_ramrod->filter_cmds[0];
1085 p_second_filter = &p_ramrod->filter_cmds[1];
1087 switch (p_filter_cmd->type) {
1088 case ECORE_FILTER_MAC:
1089 p_first_filter->type = ETH_FILTER_TYPE_MAC;
1091 case ECORE_FILTER_VLAN:
1092 p_first_filter->type = ETH_FILTER_TYPE_VLAN;
1094 case ECORE_FILTER_MAC_VLAN:
1095 p_first_filter->type = ETH_FILTER_TYPE_PAIR;
1097 case ECORE_FILTER_INNER_MAC:
1098 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC;
1100 case ECORE_FILTER_INNER_VLAN:
1101 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN;
1103 case ECORE_FILTER_INNER_PAIR:
1104 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR;
1106 case ECORE_FILTER_INNER_MAC_VNI_PAIR:
1107 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
1109 case ECORE_FILTER_MAC_VNI_PAIR:
1110 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR;
1112 case ECORE_FILTER_VNI:
1113 p_first_filter->type = ETH_FILTER_TYPE_VNI;
1117 if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1118 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1119 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1120 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1121 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1122 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR))
1123 ecore_set_fw_mac_addr(&p_first_filter->mac_msb,
1124 &p_first_filter->mac_mid,
1125 &p_first_filter->mac_lsb,
1126 (u8 *)p_filter_cmd->mac);
1128 if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1129 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1130 (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1131 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1132 p_first_filter->vlan_id = OSAL_CPU_TO_LE16(p_filter_cmd->vlan);
1134 if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1135 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1136 (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1137 p_first_filter->vni = OSAL_CPU_TO_LE32(p_filter_cmd->vni);
1139 if (p_filter_cmd->opcode == ECORE_FILTER_MOVE) {
1140 p_second_filter->type = p_first_filter->type;
1141 p_second_filter->mac_msb = p_first_filter->mac_msb;
1142 p_second_filter->mac_mid = p_first_filter->mac_mid;
1143 p_second_filter->mac_lsb = p_first_filter->mac_lsb;
1144 p_second_filter->vlan_id = p_first_filter->vlan_id;
1145 p_second_filter->vni = p_first_filter->vni;
1147 p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1149 p_first_filter->vport_id = vport_to_remove_from;
1151 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1152 p_second_filter->vport_id = vport_to_add_to;
1153 } else if (p_filter_cmd->opcode == ECORE_FILTER_REPLACE) {
1154 p_first_filter->vport_id = vport_to_add_to;
1155 OSAL_MEMCPY(p_second_filter, p_first_filter,
1156 sizeof(*p_second_filter));
1157 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
1158 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1160 action = ecore_filter_action(p_filter_cmd->opcode);
1162 if (action == MAX_ETH_FILTER_ACTION) {
1163 DP_NOTICE(p_hwfn, true,
1164 "%d is not supported yet\n",
1165 p_filter_cmd->opcode);
1166 return ECORE_NOTIMPL;
1169 p_first_filter->action = action;
1170 p_first_filter->vport_id =
1171 (p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1172 vport_to_remove_from : vport_to_add_to;
1175 return ECORE_SUCCESS;
1178 enum _ecore_status_t
1179 ecore_sp_eth_filter_ucast(struct ecore_hwfn *p_hwfn,
1181 struct ecore_filter_ucast *p_filter_cmd,
1182 enum spq_mode comp_mode,
1183 struct ecore_spq_comp_cb *p_comp_data)
1185 struct vport_filter_update_ramrod_data *p_ramrod = OSAL_NULL;
1186 struct ecore_spq_entry *p_ent = OSAL_NULL;
1187 struct eth_filter_cmd_header *p_header;
1188 enum _ecore_status_t rc;
1190 rc = ecore_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1192 comp_mode, p_comp_data);
1193 if (rc != ECORE_SUCCESS) {
1194 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1197 p_header = &p_ramrod->filter_cmd_hdr;
1198 p_header->assert_on_error = p_filter_cmd->assert_on_error;
1200 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1201 if (rc != ECORE_SUCCESS) {
1202 DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
1206 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1207 "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1208 (p_filter_cmd->opcode == ECORE_FILTER_ADD) ? "ADD" :
1209 ((p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1211 ((p_filter_cmd->opcode == ECORE_FILTER_MOVE) ?
1212 "MOVE" : "REPLACE")),
1213 (p_filter_cmd->type == ECORE_FILTER_MAC) ? "MAC" :
1214 ((p_filter_cmd->type == ECORE_FILTER_VLAN) ?
1215 "VLAN" : "MAC & VLAN"),
1216 p_ramrod->filter_cmd_hdr.cmd_cnt,
1217 p_filter_cmd->is_rx_filter, p_filter_cmd->is_tx_filter);
1218 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1219 "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1220 p_filter_cmd->vport_to_add_to,
1221 p_filter_cmd->vport_to_remove_from,
1222 p_filter_cmd->mac[0], p_filter_cmd->mac[1],
1223 p_filter_cmd->mac[2], p_filter_cmd->mac[3],
1224 p_filter_cmd->mac[4], p_filter_cmd->mac[5],
1225 p_filter_cmd->vlan);
1227 return ECORE_SUCCESS;
1230 /*******************************************************************************
1232 * Calculates crc 32 on a buffer
1233 * Note: crc32_length MUST be aligned to 8
1235 ******************************************************************************/
1236 static u32 ecore_calc_crc32c(u8 *crc32_packet,
1237 u32 crc32_length, u32 crc32_seed, u8 complement)
1239 u32 byte = 0, bit = 0, crc32_result = crc32_seed;
1240 u8 msb = 0, current_byte = 0;
1242 if ((crc32_packet == OSAL_NULL) ||
1243 (crc32_length == 0) || ((crc32_length % 8) != 0)) {
1244 return crc32_result;
1247 for (byte = 0; byte < crc32_length; byte++) {
1248 current_byte = crc32_packet[byte];
1249 for (bit = 0; bit < 8; bit++) {
1250 msb = (u8)(crc32_result >> 31);
1251 crc32_result = crc32_result << 1;
1252 if (msb != (0x1 & (current_byte >> bit))) {
1253 crc32_result = crc32_result ^ CRC32_POLY;
1259 return crc32_result;
1262 static u32 ecore_crc32c_le(u32 seed, u8 *mac, u32 len)
1264 u32 packet_buf[2] = { 0 };
1266 OSAL_MEMCPY((u8 *)(&packet_buf[0]), &mac[0], 6);
1267 return ecore_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1270 u8 ecore_mcast_bin_from_mac(u8 *mac)
1272 u32 crc = ecore_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1278 static enum _ecore_status_t
1279 ecore_sp_eth_filter_mcast(struct ecore_hwfn *p_hwfn,
1281 struct ecore_filter_mcast *p_filter_cmd,
1282 enum spq_mode comp_mode,
1283 struct ecore_spq_comp_cb *p_comp_data)
1285 unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1286 struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
1287 struct ecore_spq_entry *p_ent = OSAL_NULL;
1288 struct ecore_sp_init_data init_data;
1289 u8 abs_vport_id = 0;
1290 enum _ecore_status_t rc;
1293 if (p_filter_cmd->opcode == ECORE_FILTER_ADD)
1294 rc = ecore_fw_vport(p_hwfn,
1295 p_filter_cmd->vport_to_add_to,
1298 rc = ecore_fw_vport(p_hwfn,
1299 p_filter_cmd->vport_to_remove_from,
1301 if (rc != ECORE_SUCCESS)
1305 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1306 init_data.cid = ecore_spq_get_cid(p_hwfn);
1307 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1308 init_data.comp_mode = comp_mode;
1309 init_data.p_comp_data = p_comp_data;
1311 rc = ecore_sp_init_request(p_hwfn, &p_ent,
1312 ETH_RAMROD_VPORT_UPDATE,
1313 PROTOCOLID_ETH, &init_data);
1314 if (rc != ECORE_SUCCESS) {
1315 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1319 p_ramrod = &p_ent->ramrod.vport_update;
1320 p_ramrod->common.update_approx_mcast_flg = 1;
1322 /* explicitly clear out the entire vector */
1323 OSAL_MEMSET(&p_ramrod->approx_mcast.bins,
1324 0, sizeof(p_ramrod->approx_mcast.bins));
1325 OSAL_MEMSET(bins, 0, sizeof(unsigned long) *
1326 ETH_MULTICAST_MAC_BINS_IN_REGS);
1327 /* filter ADD op is explicit set op and it removes
1328 * any existing filters for the vport.
1330 if (p_filter_cmd->opcode == ECORE_FILTER_ADD) {
1331 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1334 bit = ecore_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1335 OSAL_SET_BIT(bit, bins);
1338 /* Convert to correct endianity */
1339 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
1340 struct vport_update_ramrod_mcast *p_ramrod_bins;
1341 u32 *p_bins = (u32 *)bins;
1343 p_ramrod_bins = &p_ramrod->approx_mcast;
1344 p_ramrod_bins->bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
1348 p_ramrod->common.vport_id = abs_vport_id;
1350 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1351 if (rc != ECORE_SUCCESS)
1352 DP_ERR(p_hwfn, "Multicast filter command failed %d\n", rc);
1357 enum _ecore_status_t
1358 ecore_filter_mcast_cmd(struct ecore_dev *p_dev,
1359 struct ecore_filter_mcast *p_filter_cmd,
1360 enum spq_mode comp_mode,
1361 struct ecore_spq_comp_cb *p_comp_data)
1363 enum _ecore_status_t rc = ECORE_SUCCESS;
1366 /* only ADD and REMOVE operations are supported for multi-cast */
1367 if ((p_filter_cmd->opcode != ECORE_FILTER_ADD &&
1368 (p_filter_cmd->opcode != ECORE_FILTER_REMOVE)) ||
1369 (p_filter_cmd->num_mc_addrs > ECORE_MAX_MC_ADDRS)) {
1373 for_each_hwfn(p_dev, i) {
1374 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1378 ecore_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1382 opaque_fid = p_hwfn->hw_info.opaque_fid;
1383 rc = ecore_sp_eth_filter_mcast(p_hwfn,
1386 comp_mode, p_comp_data);
1387 if (rc != ECORE_SUCCESS)
1394 enum _ecore_status_t
1395 ecore_filter_ucast_cmd(struct ecore_dev *p_dev,
1396 struct ecore_filter_ucast *p_filter_cmd,
1397 enum spq_mode comp_mode,
1398 struct ecore_spq_comp_cb *p_comp_data)
1400 enum _ecore_status_t rc = ECORE_SUCCESS;
1403 for_each_hwfn(p_dev, i) {
1404 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1408 rc = ecore_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1412 opaque_fid = p_hwfn->hw_info.opaque_fid;
1413 rc = ecore_sp_eth_filter_ucast(p_hwfn,
1416 comp_mode, p_comp_data);
1417 if (rc != ECORE_SUCCESS)
1424 /* Statistics related code */
1425 static void __ecore_get_vport_pstats_addrlen(struct ecore_hwfn *p_hwfn,
1426 u32 *p_addr, u32 *p_len,
1429 if (IS_PF(p_hwfn->p_dev)) {
1430 *p_addr = BAR0_MAP_REG_PSDM_RAM +
1431 PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1432 *p_len = sizeof(struct eth_pstorm_per_queue_stat);
1434 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1435 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1437 *p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1438 *p_len = p_resp->pfdev_info.stats_info.pstats.len;
1442 static void __ecore_get_vport_pstats(struct ecore_hwfn *p_hwfn,
1443 struct ecore_ptt *p_ptt,
1444 struct ecore_eth_stats *p_stats,
1447 struct eth_pstorm_per_queue_stat pstats;
1448 u32 pstats_addr = 0, pstats_len = 0;
1450 __ecore_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
1453 OSAL_MEMSET(&pstats, 0, sizeof(pstats));
1454 ecore_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
1456 p_stats->tx_ucast_bytes += HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1457 p_stats->tx_mcast_bytes += HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1458 p_stats->tx_bcast_bytes += HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1459 p_stats->tx_ucast_pkts += HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1460 p_stats->tx_mcast_pkts += HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1461 p_stats->tx_bcast_pkts += HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1462 p_stats->tx_err_drop_pkts += HILO_64_REGPAIR(pstats.error_drop_pkts);
1465 static void __ecore_get_vport_tstats(struct ecore_hwfn *p_hwfn,
1466 struct ecore_ptt *p_ptt,
1467 struct ecore_eth_stats *p_stats,
1470 struct tstorm_per_port_stat tstats;
1471 u32 tstats_addr, tstats_len;
1473 if (IS_PF(p_hwfn->p_dev)) {
1474 tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1475 TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1476 tstats_len = sizeof(struct tstorm_per_port_stat);
1478 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1479 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1481 tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1482 tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1485 OSAL_MEMSET(&tstats, 0, sizeof(tstats));
1486 ecore_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
1488 p_stats->mftag_filter_discards +=
1489 HILO_64_REGPAIR(tstats.mftag_filter_discard);
1490 p_stats->mac_filter_discards +=
1491 HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
1494 static void __ecore_get_vport_ustats_addrlen(struct ecore_hwfn *p_hwfn,
1495 u32 *p_addr, u32 *p_len,
1498 if (IS_PF(p_hwfn->p_dev)) {
1499 *p_addr = BAR0_MAP_REG_USDM_RAM +
1500 USTORM_QUEUE_STAT_OFFSET(statistics_bin);
1501 *p_len = sizeof(struct eth_ustorm_per_queue_stat);
1503 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1504 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1506 *p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1507 *p_len = p_resp->pfdev_info.stats_info.ustats.len;
1511 static void __ecore_get_vport_ustats(struct ecore_hwfn *p_hwfn,
1512 struct ecore_ptt *p_ptt,
1513 struct ecore_eth_stats *p_stats,
1516 struct eth_ustorm_per_queue_stat ustats;
1517 u32 ustats_addr = 0, ustats_len = 0;
1519 __ecore_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
1522 OSAL_MEMSET(&ustats, 0, sizeof(ustats));
1523 ecore_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
1525 p_stats->rx_ucast_bytes += HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1526 p_stats->rx_mcast_bytes += HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1527 p_stats->rx_bcast_bytes += HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1528 p_stats->rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1529 p_stats->rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1530 p_stats->rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
1533 static void __ecore_get_vport_mstats_addrlen(struct ecore_hwfn *p_hwfn,
1534 u32 *p_addr, u32 *p_len,
1537 if (IS_PF(p_hwfn->p_dev)) {
1538 *p_addr = BAR0_MAP_REG_MSDM_RAM +
1539 MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1540 *p_len = sizeof(struct eth_mstorm_per_queue_stat);
1542 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1543 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1545 *p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1546 *p_len = p_resp->pfdev_info.stats_info.mstats.len;
1550 static void __ecore_get_vport_mstats(struct ecore_hwfn *p_hwfn,
1551 struct ecore_ptt *p_ptt,
1552 struct ecore_eth_stats *p_stats,
1555 struct eth_mstorm_per_queue_stat mstats;
1556 u32 mstats_addr = 0, mstats_len = 0;
1558 __ecore_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
1561 OSAL_MEMSET(&mstats, 0, sizeof(mstats));
1562 ecore_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
1564 p_stats->no_buff_discards += HILO_64_REGPAIR(mstats.no_buff_discard);
1565 p_stats->packet_too_big_discard +=
1566 HILO_64_REGPAIR(mstats.packet_too_big_discard);
1567 p_stats->ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
1568 p_stats->tpa_coalesced_pkts +=
1569 HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
1570 p_stats->tpa_coalesced_events +=
1571 HILO_64_REGPAIR(mstats.tpa_coalesced_events);
1572 p_stats->tpa_aborts_num += HILO_64_REGPAIR(mstats.tpa_aborts_num);
1573 p_stats->tpa_coalesced_bytes +=
1574 HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
1577 static void __ecore_get_vport_port_stats(struct ecore_hwfn *p_hwfn,
1578 struct ecore_ptt *p_ptt,
1579 struct ecore_eth_stats *p_stats)
1581 struct port_stats port_stats;
1584 OSAL_MEMSET(&port_stats, 0, sizeof(port_stats));
1586 ecore_memcpy_from(p_hwfn, p_ptt, &port_stats,
1587 p_hwfn->mcp_info->port_addr +
1588 OFFSETOF(struct public_port, stats),
1589 sizeof(port_stats));
1591 p_stats->rx_64_byte_packets += port_stats.eth.r64;
1592 p_stats->rx_65_to_127_byte_packets += port_stats.eth.r127;
1593 p_stats->rx_128_to_255_byte_packets += port_stats.eth.r255;
1594 p_stats->rx_256_to_511_byte_packets += port_stats.eth.r511;
1595 p_stats->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
1596 p_stats->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
1597 p_stats->rx_1519_to_1522_byte_packets += port_stats.eth.r1522;
1598 p_stats->rx_1519_to_2047_byte_packets += port_stats.eth.r2047;
1599 p_stats->rx_2048_to_4095_byte_packets += port_stats.eth.r4095;
1600 p_stats->rx_4096_to_9216_byte_packets += port_stats.eth.r9216;
1601 p_stats->rx_9217_to_16383_byte_packets += port_stats.eth.r16383;
1602 p_stats->rx_crc_errors += port_stats.eth.rfcs;
1603 p_stats->rx_mac_crtl_frames += port_stats.eth.rxcf;
1604 p_stats->rx_pause_frames += port_stats.eth.rxpf;
1605 p_stats->rx_pfc_frames += port_stats.eth.rxpp;
1606 p_stats->rx_align_errors += port_stats.eth.raln;
1607 p_stats->rx_carrier_errors += port_stats.eth.rfcr;
1608 p_stats->rx_oversize_packets += port_stats.eth.rovr;
1609 p_stats->rx_jabbers += port_stats.eth.rjbr;
1610 p_stats->rx_undersize_packets += port_stats.eth.rund;
1611 p_stats->rx_fragments += port_stats.eth.rfrg;
1612 p_stats->tx_64_byte_packets += port_stats.eth.t64;
1613 p_stats->tx_65_to_127_byte_packets += port_stats.eth.t127;
1614 p_stats->tx_128_to_255_byte_packets += port_stats.eth.t255;
1615 p_stats->tx_256_to_511_byte_packets += port_stats.eth.t511;
1616 p_stats->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
1617 p_stats->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
1618 p_stats->tx_1519_to_2047_byte_packets += port_stats.eth.t2047;
1619 p_stats->tx_2048_to_4095_byte_packets += port_stats.eth.t4095;
1620 p_stats->tx_4096_to_9216_byte_packets += port_stats.eth.t9216;
1621 p_stats->tx_9217_to_16383_byte_packets += port_stats.eth.t16383;
1622 p_stats->tx_pause_frames += port_stats.eth.txpf;
1623 p_stats->tx_pfc_frames += port_stats.eth.txpp;
1624 p_stats->tx_lpi_entry_count += port_stats.eth.tlpiec;
1625 p_stats->tx_total_collisions += port_stats.eth.tncl;
1626 p_stats->rx_mac_bytes += port_stats.eth.rbyte;
1627 p_stats->rx_mac_uc_packets += port_stats.eth.rxuca;
1628 p_stats->rx_mac_mc_packets += port_stats.eth.rxmca;
1629 p_stats->rx_mac_bc_packets += port_stats.eth.rxbca;
1630 p_stats->rx_mac_frames_ok += port_stats.eth.rxpok;
1631 p_stats->tx_mac_bytes += port_stats.eth.tbyte;
1632 p_stats->tx_mac_uc_packets += port_stats.eth.txuca;
1633 p_stats->tx_mac_mc_packets += port_stats.eth.txmca;
1634 p_stats->tx_mac_bc_packets += port_stats.eth.txbca;
1635 p_stats->tx_mac_ctrl_frames += port_stats.eth.txcf;
1636 for (j = 0; j < 8; j++) {
1637 p_stats->brb_truncates += port_stats.brb.brb_truncate[j];
1638 p_stats->brb_discards += port_stats.brb.brb_discard[j];
1642 void __ecore_get_vport_stats(struct ecore_hwfn *p_hwfn,
1643 struct ecore_ptt *p_ptt,
1644 struct ecore_eth_stats *stats,
1645 u16 statistics_bin, bool b_get_port_stats)
1647 __ecore_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
1648 __ecore_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
1649 __ecore_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
1650 __ecore_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
1653 /* Avoid getting PORT stats for emulation. */
1654 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1658 if (b_get_port_stats && p_hwfn->mcp_info)
1659 __ecore_get_vport_port_stats(p_hwfn, p_ptt, stats);
1662 static void _ecore_get_vport_stats(struct ecore_dev *p_dev,
1663 struct ecore_eth_stats *stats)
1668 OSAL_MEMSET(stats, 0, sizeof(*stats));
1670 for_each_hwfn(p_dev, i) {
1671 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1672 struct ecore_ptt *p_ptt = IS_PF(p_dev) ?
1673 ecore_ptt_acquire(p_hwfn) : OSAL_NULL;
1676 /* The main vport index is relative first */
1677 if (ecore_fw_vport(p_hwfn, 0, &fw_vport)) {
1678 DP_ERR(p_hwfn, "No vport available!\n");
1683 if (IS_PF(p_dev) && !p_ptt) {
1684 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1688 __ecore_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1689 IS_PF(p_dev) ? true : false);
1692 if (IS_PF(p_dev) && p_ptt)
1693 ecore_ptt_release(p_hwfn, p_ptt);
1697 void ecore_get_vport_stats(struct ecore_dev *p_dev,
1698 struct ecore_eth_stats *stats)
1703 OSAL_MEMSET(stats, 0, sizeof(*stats));
1707 _ecore_get_vport_stats(p_dev, stats);
1709 if (!p_dev->reset_stats)
1712 /* Reduce the statistics baseline */
1713 for (i = 0; i < sizeof(struct ecore_eth_stats) / sizeof(u64); i++)
1714 ((u64 *)stats)[i] -= ((u64 *)p_dev->reset_stats)[i];
1717 /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
1718 void ecore_reset_vport_stats(struct ecore_dev *p_dev)
1722 for_each_hwfn(p_dev, i) {
1723 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1724 struct eth_mstorm_per_queue_stat mstats;
1725 struct eth_ustorm_per_queue_stat ustats;
1726 struct eth_pstorm_per_queue_stat pstats;
1727 struct ecore_ptt *p_ptt = IS_PF(p_dev) ?
1728 ecore_ptt_acquire(p_hwfn) : OSAL_NULL;
1729 u32 addr = 0, len = 0;
1731 if (IS_PF(p_dev) && !p_ptt) {
1732 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1736 OSAL_MEMSET(&mstats, 0, sizeof(mstats));
1737 __ecore_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
1738 ecore_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
1740 OSAL_MEMSET(&ustats, 0, sizeof(ustats));
1741 __ecore_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
1742 ecore_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
1744 OSAL_MEMSET(&pstats, 0, sizeof(pstats));
1745 __ecore_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
1746 ecore_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
1749 ecore_ptt_release(p_hwfn, p_ptt);
1752 /* PORT statistics are not necessarily reset, so we need to
1753 * read and create a baseline for future statistics.
1755 if (!p_dev->reset_stats)
1756 DP_INFO(p_dev, "Reset stats not allocated\n");
1758 _ecore_get_vport_stats(p_dev, p_dev->reset_stats);